Semiconductor memory element

Abstract

To provide a semiconductor memory element with improved electrical characteristics. [Solution] A laminated structure comprising a plurality of layers stacked vertically on a substrate, the laminated structure comprising a first laminated structure formed on the substrate and a second laminated structure formed on the first laminated structure, and a bit line formed on one side of the laminated structure and extending vertically, wherein the plurality of layers comprises a semiconductor pattern, a gate electrode extending in a first horizontal direction on the semiconductor pattern, and an information storage element adjacent to the semiconductor pattern in a second horizontal direction intersecting the first horizontal direction, the semiconductor pattern comprising a first impurity region adjacent to the bit line, a second impurity region adjacent to the information storage element, and a channel region between the first impurity region and the second impurity region, the information storage element comprising a first electrode adjacent to the second impurity region, and either the first laminated structure or the second laminated structure comprising a metal silicide disposed between the second impurity region on one side of the semiconductor pattern and the first electrode.

Description

Technical Field

[0001] The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device capable of improving electrical characteristics.

Background Art

[0002] When the memory cells of a semiconductor memory device are arranged two-dimensionally or planar, the integration degree of the semiconductor memory device is determined by the area occupied by a unit memory cell, and thus is greatly affected by the level of the fine pattern formation technology.

[0003] However, for the miniaturization of patterns, very expensive equipment is required. Therefore, although the integration degree of the semiconductor memory device embodied two-dimensionally or planar has increased, it is still limited. Thereby, a semiconductor memory device including memory cells arranged three-dimensionally has been proposed, and improvement of its electrical characteristics and the like has become an issue every day.

Summary of the Invention

Problems to be Solved by the Invention

[0004] The present invention has been made in view of the problems in the above-described conventional semiconductor memory device, and an object of the present invention is to provide a semiconductor memory device with improved electrical characteristics.

Means for Solving the Problems

[0005] To achieve the above objective, the semiconductor memory element according to the present invention comprises a stacked structure including a plurality of layers stacked vertically on a substrate, wherein the stacked structure includes a first stacked structure formed on the substrate and a second stacked structure formed on the first stacked structure, and has a bit line formed on one side of the stacked structure and extending in the vertical direction, the plurality of layers include a semiconductor pattern, a gate electrode extending in a first horizontal direction on the semiconductor pattern, and an information storage element adjacent to the semiconductor pattern in a second horizontal direction intersecting the first horizontal direction, the semiconductor pattern includes a first impurity region adjacent to the bit line, a second impurity region adjacent to the information storage element, and a channel region between the first impurity region and the second impurity region, the information storage element includes a first electrode adjacent to the second impurity region, and either the first stacked structure or the second stacked structure includes a metal silicide disposed between the second impurity region and the first electrode on one side of the semiconductor pattern.

[0006] Furthermore, the semiconductor memory element according to the present invention, made to achieve the above objective, includes a stacked structure comprising a plurality of layers stacked vertically on a substrate, wherein the stacked structure comprises a first stacked structure formed on the substrate and a second stacked structure formed on the first stacked structure, and has a bit line formed on one side of the stacked structure and extending in the vertical direction, and the plurality of layers comprises a semiconductor pattern, a gate electrode extending in a first horizontal direction on the semiconductor pattern, and an information storage element adjacent to the semiconductor pattern in a second horizontal direction intersecting the first horizontal direction, and the semiconductor pattern The first stacked structure includes a first impurity region adjacent to the bit line, a second impurity region adjacent to the information storage element, and a channel region between the first impurity region and the second impurity region, wherein the information storage element includes a first electrode adjacent to the second impurity region, the first stacked structure is an active stacked structure including a metal silicide disposed between the second impurity region and the first electrode on one side of the semiconductor pattern, and the second stacked structure is a dummy stacked structure in which no metal silicide is disposed between the second impurity region and the first electrode on one side of the semiconductor pattern.

[0007] Furthermore, the semiconductor memory element according to the present invention, made to achieve the above objective, includes a stacked structure comprising a plurality of layers stacked vertically on a substrate, wherein the stacked structure comprises a first stacked structure formed on the substrate and a second stacked structure formed on the first stacked structure, and has a bit line formed on one side of the stacked structure and extending in the vertical direction, and the plurality of layers comprises a semiconductor pattern, a gate electrode extending in a first horizontal direction on the semiconductor pattern, and an information storage element adjacent to the semiconductor pattern in a second horizontal direction intersecting the first horizontal direction, and the semiconductor pattern The first stacked structure includes a first impurity region adjacent to the bit line, a second impurity region adjacent to the information storage element, and a channel region between the first impurity region and the second impurity region, wherein the information storage element includes a first electrode adjacent to the second impurity region, the first stacked structure is a dummy stacked structure in which no metal silicide is disposed between the second impurity region on one side of the semiconductor pattern and the first electrode, and the second stacked structure is an active stacked structure in which metal silicide is disposed between the second impurity region on one side of the semiconductor pattern and the first electrode. [Effects of the Invention]

[0008] According to the semiconductor memory element of the present invention, a metal silicide is not formed on one side of a portion of the semiconductor patterns in the upper or lower part of the semiconductor patterns constituting a stacked structure stacked vertically on a substrate. Furthermore, no metal silicide is formed between the second impurity region (second source / drain) formed on one side of the upper or lower semiconductor pattern within the semiconductor pattern constituting the stacked structure and the information storage element (capacitor). As a result, the semiconductor memory element of the present invention can improve its electrical characteristics by reducing variations in contact resistance between memory cells. [Brief explanation of the drawing]

[0009] [Figure 1] This is a circuit diagram showing a schematic configuration of a semiconductor memory element cell array according to an embodiment of the present invention. [Figure 2] This is a perspective view showing a schematic configuration of a subcell array of semiconductor memory elements according to an embodiment of the present invention. [Figure 3] This is a perspective view showing a schematic configuration of a subcell array of semiconductor memory elements according to an embodiment of the present invention. [Figure 4] This is a perspective view showing a schematic configuration of a subcell array of semiconductor memory elements according to an embodiment of the present invention. [Figure 5] This is a perspective view showing a schematic configuration of a subcell array of semiconductor memory elements according to an embodiment of the present invention. [Figure 6] This is a cross-sectional view showing a schematic configuration of a semiconductor memory element according to an embodiment of the present invention. [Figure 7] Figure 6 is an enlarged cross-sectional view of the CX1 region. [Figure 8] Figure 6 is an enlarged cross-sectional view of the CX2 region. [Figure 9] Figures 6 to 8 are cross-sectional views illustrating a method for manufacturing a semiconductor memory element according to embodiments of the present invention. [Figure 10] Figures 6 to 8 are cross-sectional views illustrating a method for manufacturing a semiconductor memory element according to embodiments of the present invention. [Figure 11] Figures 6 to 8 are cross-sectional views illustrating a method for manufacturing a semiconductor memory element according to embodiments of the present invention. [Figure 12] Figures 6 to 8 are cross-sectional views illustrating a method for manufacturing a semiconductor memory element according to embodiments of the present invention. [Figure 13] Figures 6 to 8 are cross-sectional views illustrating a method for manufacturing a semiconductor memory element according to embodiments of the present invention. [Figure 14] Figures 6 to 8 are cross-sectional views illustrating a method for manufacturing a semiconductor memory element according to embodiments of the present invention. [Figure 15] Figures 6 to 8 are cross-sectional views illustrating a method for manufacturing a semiconductor memory element according to embodiments of the present invention. [Figure 16] Figures 6 to 8 are cross-sectional views illustrating a method for manufacturing a semiconductor memory element according to embodiments of the present invention. [Figure 17] A cross-sectional view showing a schematic configuration of a semiconductor memory device according to another embodiment of the present invention. [Figure 18] A plan view of a memory module including a semiconductor memory device according to an embodiment of the present invention. [Figure 19] A block diagram showing a schematic configuration of a memory card including a semiconductor device according to an embodiment of the present invention. [Figure 20] A block diagram showing a schematic configuration of a system including a semiconductor memory device according to an embodiment of the present invention.

Embodiments for Carrying Out the Invention

[0010] Next, specific examples of embodiments for implementing the semiconductor memory device according to the present invention will be described with reference to the drawings.

[0011] Any one of the following embodiments of the present invention may be implemented alone, or one or more of the following embodiments may be combined and implemented. Therefore, the technical idea of the present invention should not be construed as being limited to one embodiment. In this specification, the singular form of a component may include the plural form unless otherwise clearly specified in the context. In this specification, the drawings are shown exaggerated for clearer explanation of the present invention. In this specification, the first, second, etc. are used to describe various elements and components, but these elements and components are not limited by these terms. These terms are merely used to distinguish one element or component from another. Therefore, it is needless to say that the first element or component mentioned below may be the second element or component within the technical idea of the present invention.

[0012] FIG. 1 is a circuit diagram showing a schematic configuration of a cell array of a semiconductor memory device according to an embodiment of the present invention. Specifically, the cell array CA of the semiconductor memory element according to the embodiment of the present invention includes a plurality of subcell arrays SCA. A semiconductor memory element cell array CA comprises memory cells MC arranged in three dimensions. The semiconductor memory element of the present invention is a three-dimensional semiconductor memory element.

[0013] The subcell array SCA is arranged along the second horizontal direction (Y direction). Each subcell array (SCA) includes multiple bit lines (BL), multiple word lines (WL), and multiple memory cell transistors (MCT). A memory cell transistor (MCT) is placed between one word line (WL) and one bit line (BL). A bit line BL is a conductive pattern (e.g., a metal wire) that extends perpendicularly from the substrate (vertical direction (Z direction)). Bit lines BL within a single subcell array SCA are arranged with spacing in the first horizontal direction (X direction). Adjacent bit lines BL are separated in the first horizontal direction (X direction). Word lines WL are conductive patterns (e.g., metal wires) that are stacked vertically (Z-direction) on the substrate. Each word line WL is extended in the first horizontal direction (X direction). Adjacent word lines WL are separated vertically (in the Z direction).

[0014] The gate electrode of the memory cell transistor (MCT) is connected to the word line WL, and the first source / drain of the memory cell transistor (MCT) is connected to the bit line BL via a direct contact (DC). The second source / drain of the memory cell transistor (MCT) is connected to the information storage element (DS) via a buried contact (BC). For example, the information storage element DS is a capacitor. The second source / drain of the memory cell transistor (MCT) is connected to the first electrode of the information storage element (DS), i.e., the capacitor. The bit line BL, word line WL, memory cell transistor MCT, and information storage element DS contained within each subcell array SCA constitute the memory cell MC.

[0015] Figures 2 to 5 are perspective views showing a schematic configuration of a subcell array of semiconductor memory elements according to an embodiment of the present invention. Referring to Figures 1 and 2, a peripheral circuit region PER is formed on the substrate SUB. The substrate SUB may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The peripheral circuit region PER includes peripheral transistors formed on the substrate SUB. The peripheral circuit region PER includes circuits for operating the cell array (CA in Figure 1) according to an embodiment of the present invention.

[0016] One of the multiple subcell arrays SCA described in Figure 1 is formed on the peripheral circuit region PER. Specifically, a laminated structure SS including the first to third layers (L1, L2, L3) is formed on the peripheral circuit region PER. The first to third layers (L1, L2, L3) of the laminated structure SS are stacked with a vertical direction (vertical direction (Z direction)) separating them from each other. Each of the first to third layers (L1, L2, and L3) includes multiple semiconductor patterns SP, multiple information storage elements DS, and a gate electrode GE.

[0017] The semiconductor pattern SP has a line-like or bar-like shape that extends in the second horizontal direction (Y direction). The semiconductor pattern SP may contain semiconductor materials such as silicon, germanium, or silicon-germanium. As an example, the semiconductor pattern SP includes polysilicon or single-crystal silicon. Each semiconductor pattern SP includes a channel region CH, a first impurity region SD1, and a second impurity region SD2. The channel region CH is located between the first impurity region SD1 and the second impurity region SD2. The channel region CH corresponds to the channel of the memory cell transistor MCT, as explained with reference to Figure 1.

[0018] The first impurity region SD1 and the second impurity region SD2 correspond to the first source / drain and second source / drain of the memory cell transistor MCT, respectively, as explained with reference to Figure 1. The first impurity region SD1 and the second impurity region SD2 are regions in the semiconductor pattern SP that are doped with impurities. The first impurity region SD1 and the second impurity region SD2 are regions doped with n-type or p-type conductivity impurities. The first impurity region SD1 is formed adjacent to the first end of the channel region CH, and the second impurity region SD2 is formed adjacent to the second end of the channel region CH. The second end faces the first end in the second horizontal direction (Y direction).

[0019] Information storage elements DS are connected to each semiconductor pattern SP. Specifically, information storage elements DS are connected to the second impurity region SD2 of the semiconductor pattern SP. The information storage element DS is a memory element that can store data. For example, the information storage element DS is a capacitor. The gate electrode GE has a line-like or bar-like shape that extends in the first horizontal direction (X direction). The gate electrodes (GEs) are stacked, spaced apart from each other along the vertical direction (Z direction). Each gate electrode GE extends in the first horizontal direction (X direction) across the semiconductor pattern SP within a single layer. In other words, the gate electrode GE may be the horizontal word line WL, as described with reference to Figure 1. The gate electrode (GE) contains a conductive material. As an example, a conductive material may be any one of the following: doped semiconductor materials (such as doped silicon or doped germanium), conductive metal nitrides (such as titanium nitride or tantalum nitride), metals (such as tungsten, titanium, or tantalum), or metal-semiconductor compounds (such as tungsten silicide, cobalt silicide, or titanium silicide).

[0020] Multiple bit lines BL are formed on the substrate SUB, extending in a vertical direction (vertical direction (Z direction)). Each bit line BL has a linear or columnar shape that extends vertically (in the Z direction). The bit lines BL are arranged along the first horizontal direction (X direction). Each bit line BL is electrically connected to the first impurity region SD1 of the vertically stacked semiconductor pattern SP. The bit wire BL contains a conductive material, which may be one of the following: a doped semiconductor material, a conductive metal nitride, a metal, or a metal-semiconductor compound. The bit line BL is the vertical bit line BL explained with reference to Figure 1.

[0021] Of the three layers (L1, L2, and L3), we will explain the first layer, L1, in detail. The semiconductor pattern SP of the first layer L1 is arranged in the first horizontal direction (X direction). The semiconductor patterns SP in the first layer L1 are located at the same level as each other. The gate electrode GE of the first layer L1 extends across the semiconductor pattern SP of the first layer L1 in the first horizontal direction (X direction). For example, the gate electrode GE of the first layer L1 is formed on the upper surface of the semiconductor pattern SP. A gate insulating film is interposed between the gate electrode GE and the channel region CH. The gate insulating film may include at least one of a high dielectric film, a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. As an example, the high dielectric film may contain at least one of the following: hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0022] Each bit line BL is connected to the first end of the semiconductor pattern SP of the first layer L1. For example, the bit line BL is directly connected to the first impurity region SD1. As another example, the bit line BL is electrically connected to the first impurity region SD1 via a metal silicide. The specific explanations for Layer 2 (L2) and Layer 3 (L3) are essentially the same as those for Layer 1 (L1) mentioned above. The empty spaces within the laminated structure SS are filled with insulating material. For example, the insulating material may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. A wiring layer electrically connected to the subcell array SCA is formed on the laminated structure SS. The wiring layer is electrically connected to the peripheral circuit region PER through through-contacts.

[0023] In the embodiments shown in Figures 3 to 5 below, detailed explanations of technical features that overlap with those described with reference to Figures 1 and 2 will be omitted, and the differences will be explained in detail. Referring to Figures 1 and 3, the gate electrode GE includes a first gate electrode GE1 on the upper surface of the semiconductor pattern SP and a second gate electrode GE2 on the bottom surface of the semiconductor pattern SP. In other words, the memory cell transistor according to this embodiment is a double-gate transistor in which the gate electrode GE is formed on both sides of the channel region CH.

[0024] Referring to Figures 1 and 4, the gate electrode GE surrounds the channel region CH of the semiconductor pattern SP. The gate electrode GE is formed on the top surface, bottom surface, and both side walls of the channel region CH. In other words, the memory cell transistor according to this embodiment is a gate-all-around transistor in which the gate electrode GE surrounds the channel region CH.

[0025] Referring to Figures 1 and 5, a subcell array SCA is formed on the substrate SUB. A peripheral circuit region PER is formed on the subcell array SCA. As mentioned above, the peripheral circuit region PER includes the circuitry for operating the subcell array SCA.

[0026] Figure 6 is a cross-sectional view showing a schematic configuration of a semiconductor memory element according to an embodiment of the present invention, and Figures 7 and 8 are enlarged cross-sectional views of the CX1 and CX2 regions of Figure 6, respectively. Specifically, the semiconductor memory element EX1 shown in Figure 6 includes a cross-sectional portion cut along the line A-A' in Figure 3. In Figures 6, 7, and 8, the same reference numerals as in Figures 1 and 3 indicate the same components. In Figures 6, 7, and 8, content identical to that in Figures 1 and 3 will be briefly explained or omitted.

[0027] Referring to Figures 3 and 6, a laminated structure SS is formed on the substrate SUB. For example, the laminated structure SS is arranged in the second horizontal direction (Y direction) together with the gate electrode GE. When multiple laminated structures SS are formed, the multiple laminated structures SS are arranged in the first horizontal direction (X direction). The laminated structure SS includes a first laminated structure SS1 formed on a substrate SUB and a second laminated structure SS2 formed on the first laminated structure SS1. The first stacked structure SS1 includes the first to the Nth layers (L1 to LN) (where N is a positive integer greater than or equal to 2) sequentially stacked on the substrate SUB. In one embodiment, N can range from several tens to several hundred. In one embodiment, N is between 10 and 500.

[0028] The first stacked structure SS1 is an active stacked structure that operates as a memory cell (MC in Figure 1). The first laminated structure SS1 is an active laminated structure in which metal silicide MS is arranged. The second laminated structure SS2 includes the (N+1)th and (N+2)th layers which are sequentially stacked on the first laminated structure SS1. The second stacked structure SS2 is a dummy stacked structure that does not function as a memory cell (MC in Figure 1). The second laminated structure SS2 is a dummy laminated structure in which the metal silicide MS2 is not placed. The (N+1)th and (N+2)th layers in this embodiment are illustrative, and an additional layer may be stacked on top of the (N+2)th layer.

[0029] Each of the first to (N+2) layers (L1 to L(N+2)) includes a first insulating film IL1, a semiconductor pattern SP, a gate electrode GE, a sidewall insulating pattern SWD, and a spacer SPC. The semiconductor pattern SP formed on the first stacked structure SS1 includes the first semiconductor pattern SP1. The semiconductor pattern SP formed on the second stacked structure SS2 includes the second semiconductor pattern SP2. The number of layers of the second semiconductor pattern SP2 formed on the second stacked structure SS2 is smaller than the number of layers of the first semiconductor pattern SP1 formed on the first stacked structure SS1. In one embodiment, the number of stacked layers of the first semiconductor pattern SP1 and the second semiconductor pattern SP2 is several tens to several hundred. In one embodiment, the number of layers of the second semiconductor pattern SP2 is 5% to 15% of the number of layers of the first semiconductor pattern SP1.

[0030] Each of the first to (N+2) layers (L1 to L(N+2)) may further include a semiconductor pattern SP, adjacent direct contact DC, and information storage element DS. The semiconductor pattern SP, gate electrode GE, and sidewall insulating pattern SWD are formed on the first insulating film IL1. The first insulating film IL1 separates the upper gate electrode GE and the lower gate electrode GE from each other in the vertical direction (Z direction). The gate electrode GE may include at least one of doped semiconductor materials, conductive metal nitrides, metals, and metal-semiconductor compounds. The semiconductor pattern SP may contain semiconductor materials such as silicon, germanium, or silicon-germanium. The first insulating film IL1 may include at least one of the following: silicon oxide film, silicon nitride film, silicon oxynitride film, carbon-containing silicon oxide film, carbon-containing silicon nitride film, and carbon-containing silicon oxynitride film.

[0031] The semiconductor pattern SP includes a channel region CH, a first impurity region SD1, and a second impurity region SD2. The channel region CH has a first end SPe1 and a second end SPe2 that is opposite the first end SPe1 in the second horizontal direction D2. The first impurity region SD1 is located on one side of the first end SPe1, and the second impurity region SD2 is located on one side of the second end SPe2. The first end SPe1 corresponds to the first end described in Figure 2. The second end SPe2 corresponds to the second end described in Figure 2. Specifically, the first impurity region SD1 is located between the channel region CH and the bit line BL. The second impurity region SD2 is located between the channel region CH and the information storage element DS. The channel region CH is located between the first impurity region SD1 and the second impurity region SD2.

[0032] For example, the channel region CH, the first impurity region SD1, and the second impurity region SD2 are configured as a single unit. In other words, no boundary is observed between the channel region CH and the first impurity region SD1, nor between the channel region CH and the second impurity region SD2. The first impurity region SD1 and the second impurity region SD2 are regions in the semiconductor pattern SP that are doped with impurities. As a result, the first impurity region SD1 and the second impurity region SD2 have n-type or p-type conductivity. The impurity doping concentration in the second impurity region, SD2, increases with increasing distance from the gate electrode GE in the second horizontal direction (Y direction). Conversely, the impurity doping concentration in the second impurity region SD2 decreases as you move towards the gate electrode GE in the opposite direction of the second horizontal direction (Y direction). This is due to the use of the GPD (Gas Phase Doping) process in forming the second impurity region, SD2. For example, the impurity doping concentration in the second impurity region SD2 increases either at a constant rate or exponentially with respect to the distance from the gate electrode GE in the second horizontal direction (Y direction). However, the concept of the present invention is not limited thereto, and the impurity doping concentration in the second impurity region SD2 may increase irregularly depending on the distance from the gate electrode GE in the second horizontal direction (Y direction).

[0033] Each of the first to (N+2) layers (L1 to L(N+2)) includes a first gate electrode GE1 on the first surface SPa of the semiconductor pattern SP, and a second gate electrode GE2 on the second surface SPb of the semiconductor pattern SP. The second face SPb is perpendicular to the first face SPa (in the Z direction). For example, the first surface SPa is the top surface of the semiconductor pattern SP, and the second surface SPb is the bottom surface of the semiconductor pattern SP. The first gate electrode GE1 and the second gate electrode GE2 are separated perpendicularly from each other, with the semiconductor pattern SP in between. In other words, the semiconductor pattern SP is sandwiched between the first gate electrode GE1 and the second gate electrode GE2, which are formed above and below it, respectively.

[0034] The first gate electrode GE1 and the second gate electrode GE2 extend parallel to each other in the first horizontal direction (X direction). As an example, each gate electrode GE in layers 1 to N (L1 to LN) constitutes a single word line WL (Figure 1). In this embodiment, the gate electrode GE continuously traverses semiconductor patterns SP arranged in a first horizontal direction (X direction) within a single layer. A gate isolation pattern GI is interposed between the first gate electrode GE1 and the second gate electrode GE2 and the semiconductor pattern SP. The gate insulation pattern GI may include a single film selected from high dielectric films, silicon oxide films, silicon nitride films, and silicon oxynitride films, or a combination thereof.

[0035] The memory cell transistor according to this embodiment has a double gate structure in which a first gate electrode GE1 and a second gate electrode GE2 are arranged above and below the semiconductor pattern SP, respectively. In other words, the memory cell transistor according to this embodiment is a double-gate transistor as described with reference to Figure 3. The memory cell transistor according to this embodiment has a double-gate structure, which improves the channel controllability of the gate electrode (GE). Each semiconductor pattern SP in the first to (N+2) layers (L1 to L(N+2)) is separated from each other by a vertical insulator and arranged in the first horizontal direction (X direction).

[0036] A bit line BL is formed that penetrates the laminated structure SS. The bit lines BL are separated from each other by vertical insulators. The bit lines BL are arranged in the first horizontal direction (X direction). Bit line BL corresponds to bit line BL explained with reference to Figures 1 and 3. The bit line BL is located on one side of the first end SPe1 of the channel region CH. The direct contact DC is located on one side of the first end SPe1 of the channel region CH. A direct contact DC is placed between the bit line BL and the first impurity region SD1. The bit line BL is connected to the direct contact DC. Bit line BL is electrically connected to the first impurity region SD1 via direct contact DC. Direct contacts (DC) are composed of metal silicide.

[0037] An insulating structure ISS is formed to cover the sidewall of the bit line BL. The insulating structure ISS extends in the first horizontal direction (X direction). The insulating structure ISS may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The sidewall insulation pattern SWD is placed between the bit line BL and the gate electrode GE. The sidewall insulation pattern SWD electrically isolates the bit wire BL from the gate electrode GE. The sidewall insulation pattern SWD is positioned on the upper and lower surfaces of the first impurity region SD1. The sidewall insulation pattern SWD is positioned on the upper and lower surfaces of the direct contact DC. The sidewall insulation pattern SWD is positioned on the upper and lower surfaces of the first insulating film IL1.

[0038] The information storage element DS is located on one side of the second end SPe2 of the channel region CH. The information storage element DS is electrically connected to the second impurity region SD2. Multiple information storage elements DS are formed. Each information storage element DS includes a first electrode EL1, a dielectric film DL, and a second electrode EL2. The information storage element DS shares one dielectric film DL and one second electrode EL2. In other words, multiple first electrodes EL1 are formed within the laminated structure SS, and a single dielectric film DL covers the surface of the first electrodes EL1.

[0039] One second electrode EL2 can be formed on one dielectric film DL. Each of the first electrodes EL1 has a cylindrical shape with a filled interior. The second electrode EL2 is formed on the outer surface of the cylinder of the first electrode EL1. The first electrode EL1 is connected to each semiconductor pattern SP within a single layer. Specifically, the first electrode EL1 is connected to the second impurity region SD2 within a single layer. The first electrodes EL1 within a single layer are arranged in the first horizontal direction (X direction). In the first stacked structure SS1, a metal silicide MS2 is placed between the first electrode EL1 and the second impurity region SD2. In the second layered structure SS2, no metal silicide MS2 is placed between the first electrode EL1 and the second impurity region SD2.

[0040] In one embodiment, the metal silicide MS2 can form titanium silicide, cobalt silicide, molybdenum silicide, or zirconium silicide. The second electrode EL2 may include at least one of the following: a metallic material (e.g., titanium, tantalum, tungsten, copper, or aluminum), a conductive metal nitride (e.g., titanium nitride or tantalum nitride), and a doped semiconductor material (e.g., doped silicon or doped germanium). The dielectric film DL may contain high dielectric constant materials (e.g., hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or combinations thereof). The spacer SPC is placed between the second electrode EL2 and the gate electrode GE. The spacer SPC is placed between the upper second impurity region SD2 and the lower second impurity region SD2. The spacer SPC separates the upper second impurity region SD2 and the lower second impurity region SD2 from each other in the vertical direction (Z direction).

[0041] Referring to Figure 3 and Figures 6 through 8 together, the outer wall SPCS of the spacer SPC is separated from the outer wall EL1S of the first electrode EL1. The outer wall SPCS of the spacer SPC is a side wall that is further away from the bit line BL among the side walls of the spacer SPC in the second horizontal direction (Y direction). Similarly, the outer wall EL1S of the first electrode EL1 is a side wall that is further away from the bit line BL among the side walls of the first electrode EL1 in the second horizontal direction (Y direction). The outer wall EL1S of the first electrode EL1 is further separated from the gate electrode GE in the second horizontal direction (Y direction) than the outer wall SPCS of the spacer SPC. Alternatively, the outer wall EL1S of the first electrode EL1 is further separated from the bit line BL in the second horizontal direction (Y direction) than the outer wall SPCS of the spacer SPC. In other words, the outer wall SPCS of the spacer SPC is further adjacent to the gate electrode GE in the second horizontal direction (Y direction) than the outer wall EL1S of the first electrode EL1. Alternatively, the outer wall SPCS of the spacer SPC is further adjacent to the bit line BL in the second horizontal direction (Y direction) than the outer wall EL1S of the first electrode EL1.

[0042] The outer wall SPCS of the spacer SPC is separated from the outer wall IL1S of the first insulating film IL1. The outer wall IL1S of the first insulating film IL1 is a side wall located further away from the bit line BL among the side walls of the first insulating film IL1 in the second horizontal direction (Y direction). The outer wall SPCS of the spacer SPC is further separated from the bit line BL in the second horizontal direction (Y direction) than the outer wall IL1S of the first insulating film IL1. The outer wall SPCS of the spacer SPC is further separated from the gate electrode GE in the second horizontal direction (Y direction) than the outer wall IL1S of the first insulating film IL1. In other words, the outer wall IL1S of the first insulating film IL1 is further adjacent to the bit line BL in the second horizontal direction (Y direction) than the outer wall SPCS of the spacer SPC.

[0043] Referring to Figure 7, in the first laminated structure SS1, the outer wall SPCS of the spacer SPC is aligned in a line with the outer wall MS2S of the metal silicide MS2. The outer wall SPCS of the spacer SPC is coplanar with the outer wall MS2S of the metal silicide MS2. The outer wall MS2S of the metal silicide MS2 is a side wall located further away from the bit line BL among the side walls of the metal silicide MS2 in the second horizontal direction (Y direction).

[0044] Referring to Figure 8, in the second laminated structure SS2, the outer wall SPCS of the spacer SPC is aligned in a line with the outer wall SD2S of the second impurity region SD2. The outer wall SPCS of spacer SPC is coplanar with the outer wall SD2S of the second impurity region SD2. The outer wall SD2S of the second impurity region SD2 is a side wall located further away from the bit line BL among the side walls of the second impurity region SD2 in the second horizontal direction (Y direction). The outer wall SPCS of the spacer SPC is separated from the outer wall GES of the gate electrode GE. The outer wall GES of the gate electrode GE is a side wall that is further away from the bit line BL among the side walls of the gate electrode GE in the second horizontal direction (Y direction). The outer wall SPCS of the spacer SPC is located further away from the bit line BL in the second horizontal direction (Y direction) than the outer wall GES of the gate electrode GE. In other words, the outer wall GES of the gate electrode GE is further adjacent to the bit line BL in the second horizontal direction (Y direction) than the outer wall SPCS of the spacer SPC.

[0045] The spacer SPC is separated from the second electrode EL2 in the second horizontal direction (Y direction) with the dielectric film DL in between. The outer wall SPCS of the spacer SPC is separated from the inner wall EL2IS of the second electrode EL2 by the dielectric film DL. The inner wall EL2IS of the second electrode EL2 is the side wall of the second electrode EL2 facing the second horizontal direction D2 that is closest to the gate electrode GE in the second horizontal direction (Y direction). The inner wall EL2IS of the second electrode EL2 is further adjacent to the gate electrode GE in the second horizontal direction (Y direction) than the outer wall EL1S of the first electrode EL1. As an example, the outer wall IL1S of the first insulating film IL1 is aligned in a line with the outer wall GES of the gate electrode GE. The outer wall IL1S of the first insulating film IL1 is coplane with the outer wall GES of the gate electrode GE.

[0046] As described above, in the semiconductor memory element EX1 of the present invention, the metal silicide MS2 is not formed on one side of the upper second semiconductor pattern SP2 among the semiconductor patterns SP that constitute the stacked structure SS stacked vertically on the substrate SUB. Furthermore, in the semiconductor memory element EX1 of the present invention, a metal silicide MS1 is formed on one side of the lower first semiconductor pattern SP1 of the semiconductor pattern SP that constitutes a stacked structure SS stacked vertically on a substrate SUB. In other words, in the semiconductor memory element EX1 of the present invention, no metal silicide MS2 is formed between the second impurity region SD2 (i.e., second source / drain) on one side of the upper second semiconductor pattern SP2 within the semiconductor pattern SP constituting the stacked structure SS and the information storage element DS (i.e., capacitor). Furthermore, in the semiconductor memory element EX1 of the present invention, a metal silicide MS2 is formed between the second impurity region SD2 (i.e., second source / drain) on one side of the lower first semiconductor pattern SP1 within the semiconductor pattern SP constituting the stacked structure SS and the information storage element DS (i.e., capacitor). The semiconductor memory element EX1 of the present invention reduces variations in contact resistance between the first semiconductor patterns SP1 in the vertical direction (Z direction) during the manufacturing process by forming a metal silicide MS2 only on one side of the lower first semiconductor pattern SP1 among the semiconductor patterns SP that constitute the stacked structure SS. As a result, the semiconductor memory element EX1 of the present invention can reduce variations in contact resistance between memory cells and improve its electrical characteristics.

[0047] Figures 9 to 16 are cross-sectional views illustrating the method for manufacturing a semiconductor memory element according to the embodiments of the present invention shown in Figures 6 to 8. Specifically, in Figures 9 to 16, the same reference numerals as in Figures 6 to 8 indicate the same components. In Figures 9 to 16, content identical to that in Figures 6 to 8 will be briefly explained or omitted.

[0048] Referring to Figure 9, a laminated structure SS is formed on the substrate SUB. Specifically, the laminated structure SS includes a first laminated structure SS1 and a second laminated structure SS2. The first laminated structure SS1 includes forming the first to Nth layers (L1 to LN) (where N is a positive integer of 2 or more) on the substrate SUB. The second laminated structure SS2 includes forming the (N+1)th layer and the (N+2)th layer on the first laminated structure SS1. The steps for forming the first to Nth layers (L1 to LN), the (N+1)th layer, and the (N+2)th layer, respectively, include the steps for forming the first insulating film IL1, forming the second insulating film IL2 on the first insulating film IL1, forming the semiconductor film SL on the second insulating film IL2, and forming the third insulating film IL3 on the semiconductor film SL. In other words, each of the first to Nth layers (L1 to LN), the (N+1)th layer, and the (N+2)th layer includes a sequentially stacked first insulating film IL1, a second insulating film IL2, a semiconductor film SL, and a third insulating film IL3.

[0049] The first insulating film IL1, the second insulating film IL2, and the third insulating film IL3 may include at least one of the following: silicon oxide film, silicon nitride film, silicon oxynitride film, carbon-containing silicon oxide film, carbon-containing silicon nitride film, and carbon-containing silicon oxynitride film. The second insulating film IL2 and the third insulating film IL3 contain the same material. The second insulating film IL2 and the third insulating film IL3 contain materials that are etching-selective with respect to the first insulating film IL1. As an example, the first insulating film IL1 includes a silicon oxide film, and the second insulating film IL2 and the third insulating film IL3 include silicon nitride films. The semiconductor film SL may contain semiconductor materials such as silicon, germanium, or silicon-germanium. Next, a first opening OP1 is formed that penetrates the laminated structure SS. The first opening OP exposes the top surface of the substrate SUB.

[0050] Referring to Figure 10, the second insulating film IL2 and the third insulating film IL3, exposed by the first opening OP1, are partially etched to form the first recess RS1. Specifically, a wet etching process is performed to selectively etch the second insulating film IL2 and the third insulating film IL3 through the first aperture OP1. During the wet etching process, the first insulating film IL1 and the semiconductor film SL remain intact. During the wet etching process, the second insulating film IL2 and the third insulating film IL3 are partially etched to form the first recess RS1. Each of the first recesses RS1 is located at the same vertical level as the second insulating film IL2 or the third insulating film IL3. The first recess RS1 exposes the sidewalls of the second insulating film IL2 and the third insulating film IL3. The first recess RS1 exposes a portion of the upper and lower surfaces of the semiconductor film SL. The first recess RS1 exposes a portion of the upper and lower surfaces of the first insulating film IL1.

[0051] Referring to Figure 11, the gate insulation pattern GI and the gate electrode GE are formed within the first recess RS1. Specifically, the steps of forming the gate insulating pattern GI and gate electrode GE within the first recess RS1 include the steps of forming a gate insulating material conformally covering the exposed upper surface, lower surface, and side walls of the semiconductor film SL, forming a gate electrode material film covering the surface of the gate insulating material film, and recessing the gate insulating material film and gate electrode material film through the first opening OP and the first recess RS1. The gate electrode GE includes a first gate electrode GE1 on the upper surface of the semiconductor film SL and a second gate electrode GE2 on the lower surface of the semiconductor film SL.

[0052] Referring to Figure 12, the first impurity region SD1, direct contact DC, bit line BL, and insulating structure ISS are formed. Specifically, the steps of forming the first impurity region SD1 and the direct contact DC include the steps of performing a GPD (Gas Phase Doping) process through the first opening OP and the first recess RS1, forming a portion of the sidewall insulation pattern SWD on one side of the gate electrode GE, silicide a portion of the semiconductor film SL, and forming the remaining portion of the sidewall insulation pattern SWD. The portion of the semiconductor film SL that overlaps the gate electrode GE perpendicularly (in the Z direction) is called the channel region CH. The GPD process refers to the doping of semiconductor materials with impurities using a gas phase. The GPD process uses gas as a doping agent, thus avoiding damage to the semiconductor material's lattice and shortening the process time. The GPD process has the advantage of being able to control the degree of diffusion by adjusting variables such as time.

[0053] A portion of the sidewall insulation pattern SWD is positioned on the upper and lower surfaces of the first impurity region SD1. The first impurity region, SD1, is formed by doping a portion of the semiconductor film SL with impurities. Direct contact (DC) includes a metal silicide formed by silicideizing a portion of the semiconductor film (SL). Direct contact (DC) is formed by depositing a metal layer onto the semiconductor film SL on one side of the first impurity region SD1, followed by annealing. Direct contact DC1 is formed by the reaction between a metal layer and a semiconductor film. The first impurity region SD1 and the direct contact DC are part of the semiconductor film SL, but the present invention is not limited thereto. Next, the first bit line BL is formed within the first aperture OP1. Next, an insulating structure ISS is formed on the side wall of the bit line BL.

[0054] Referring to Figure 13, a second opening OP2 and a second recess RS2 are formed. Specifically, a second opening OP2 is formed that penetrates the laminated structure SS. The second opening OP exposes the top surface of the substrate SUB. Next, the first insulating film IL1, the second insulating film IL2, and the third insulating film IL3 on one side of the gate electrode GE1 are etched to form the second recess RS2. The second recess RS2 is formed through a wet etching process that utilizes the etching selectivity between the first insulating film IL1, the second insulating film IL2, and the third insulating film IL3 and the semiconductor film SL. Through a wet etching process, a second recess RS2 is formed in the space where the removed first insulating film IL1, second insulating film IL2, and third insulating film IL3 were located. The second recess RS2 exposes a portion of the semiconductor film SL. The second recess RS2 exposes the upper semiconductor film SL and the lower semiconductor film SL. The second recess RS2 causes the semiconductor film SL to protrude in the second horizontal direction (Y direction) from the outer wall IL1S of the first insulating film IL1. The second recess RS2 makes it easier for the gaseous material to reach the exposed surface of the semiconductor film SL. The second recess RS2 aligns the outer wall IL1S of the first insulating film IL1 with the outer wall GES of the gate electrode GE.

[0055] Referring to Figure 14, a spacer SPC is formed within the second recess RS2. Specifically, a spacer SPC is formed between the upper semiconductor film SL and the lower semiconductor film SL. Spacer SPCs are formed above and below the semiconductor film SL in the second recess RS2. In one embodiment, the spacer SPC is formed from a silicon nitride film. The thickness of the spacer SPC in the second horizontal direction (Y direction) can be freely adjusted. The spacer SPC is in contact with one side of the gate electrode GE. The outer wall SPCS of the spacer SPC is separated from the outer wall GES of the gate electrode GE.

[0056] Referring to Figure 15, a cover insulating layer CRL is formed on one side of the spacer SPC. Specifically, a cover insulating layer CRL is formed on one side of the spacer SPC and on the semiconductor film SL. The cover insulating layer CRL is formed in contact with the outer wall SPCS of the spacer SPC. In one embodiment, the cover insulating layer CRL is formed from a spacer SPC and a material with an etching selectivity ratio. In one embodiment, the cover insulating layer CRL is formed of a silicon oxide film.

[0057] Referring to Figure 16, a third recess RE3, a second impurity region SD2, and a metal silicide MS2 are formed. Specifically, the semiconductor film (SL in Figure 15) between the cover insulating layers CRL arranged in the vertical direction (Z direction) is etched to form a third recess RS3 in the second horizontal direction (Y direction). The GPD process proceeds through the third recess RS3. In the GPD process, impurities are doped into the exposed portions of the semiconductor film SL. This creates a second impurity region, SD2, in the semiconductor film SL.

[0058] In this embodiment, the semiconductor film (SL in Figure 15) is etched to form a third recess RS3 in the second horizontal direction (Y direction), and then a second impurity region SD2 is formed. Alternatively, a second impurity region SD2 can be formed on the semiconductor film (SL in Figure 15) using the GPD process, followed by the formation of a spacer SPC, a cover insulating layer CRL, and a third recess RS3. Next, a metal silicide MS2 is formed on one side of the second impurity region SD2 of the first laminated structure SS1. In one embodiment, the metal silicide MS2 can form titanium silicide, cobalt silicide, molybdenum silicide, or zirconium silicide. Metal silicide MS2 is formed by depositing a metal layer onto the semiconductor film SL on one side of the second impurity region SD2, followed by annealing. The metal layer is formed by chemical vapor deposition or atomic layer deposition.

[0059] Metal silicide MS2 is not formed on one side of the second impurity region SD2 of the second layered structure SS2. The reason why metal silicide MS2 is not formed on one side of the second impurity region SD2 of the second layered structure SS2 is explained as follows. Specifically, when depositing the metal layer for the formation of metal silicide MS2, a metal precursor containing chlorine groups (Cl) is used. When a metal precursor contains chlorine groups (Cl), the deposition and etching of the metal precursor occur simultaneously during the deposition of the metal layer. As a result, the thickness of the metal layer is not uniform in the vertical direction (Z direction) along the second opening OP2. In other words, the thickness of the metal layer formed on one side of the second impurity region SD2 in the vertical direction (Z direction) is not uniform; for example, the metal layer is not formed on one side of the second impurity region SD2 of the second laminated structure SS2. In such cases, metal silicide MS2 is not formed on one side of the second impurity region SD2 of the second laminated structure SS2.

[0060] Next, as shown in Figure 9, the first electrode EL1 is formed within the third recess (RE3 in Figure 16). After removing the cover insulating layer CRL, a dielectric film DL is formed to conformally cover the exposed surface of the first electrode EL1. Then, by forming a second electrode EL2 that covers the dielectric film DL, the semiconductor memory element EX1 is completed.

[0061] Figure 17 is a cross-sectional view showing a schematic configuration of a semiconductor memory element according to another embodiment of the present invention. Specifically, the semiconductor memory element EX2 is identical to the semiconductor memory element EX1 shown in Figures 6 to 8, except that the metal silicide MS2 is not formed on the first stacked structure (SS1-1) at the bottom of the substrate SUB, but is formed on the second stacked structure (SS2-1). In Figure 17, the same reference numerals as in Figures 6 to 8 indicate the same components. In Figure 17, content identical to that in Figures 6-8 will be briefly explained or omitted.

[0062] The semiconductor memory element EX2 includes a stacked structure (SS-1) formed on a substrate SUB. The laminated structure SS includes a first laminated structure (SS1-1) formed on a substrate SUB and a second laminated structure (SS2-1) formed on the first laminated structure (SS1-1). The first stacked structure (SS1-1) includes the (N+1)th layer and the (N+2)th layer sequentially stacked on the substrate SUB. The first stacked structure (SS1-1) is a dummy stacked structure that does not function as a memory cell (MC in Figure 1). The first laminated structure (SS1-1) is a dummy laminated structure in which metal silicide MS2 is not placed. The (N+1)th and (N+2)th layers in this embodiment are illustrative, and additional layers may be stacked on top of the (N+2nd)th layer.

[0063] The second layered structure (SS2-1) includes the first to the Nth layers (L1 to LN) (where N is a positive integer greater than or equal to 2) that are sequentially stacked on the first layered structure (SS1-1). In one embodiment, N is several tens to several hundred. In one embodiment, N is between 10 and 500. The second stacked structure (SS2-1) is an active stacked structure that operates as a memory cell (MC in Figure 1). The second laminated structure (SS2-1) is an active laminated structure in which metal silicide MS2 is arranged. The (N+1)th layer, the (N+2)th layer, and the 1st to Nth layers (L1 to LN) each include a first insulating film IL1, a semiconductor pattern SP, a gate electrode GE, a sidewall insulating pattern SWD, and a spacer SPC.

[0064] The semiconductor pattern SP formed on the first stacked structure (SS1-1) includes the first semiconductor pattern (SP1-1). The semiconductor pattern SP formed on the second stacked structure (SS2-1) includes the second semiconductor pattern (SP2-1). The number of layers of the first semiconductor pattern (SP1-1) formed on the first stacked structure (SS1-1) is smaller than the number of layers of the second semiconductor pattern (SP2-1) formed on the second stacked structure (SS2-1). In one embodiment, the number of stacked layers of the first semiconductor pattern (SP1-1) and the second semiconductor pattern (SP2-1) is several tens to several hundred. In one embodiment, the number of layers of the first semiconductor pattern (SP1-1) is 5% to 15% of the number of layers of the second semiconductor pattern (SP2-2).

[0065] The (N+1)th layer, the (N+2)th layer, and the 1st to Nth layers (L1 to LN) may each further include a semiconductor pattern SP and adjacent direct contact DC and information storage element DS. The semiconductor pattern SP, gate electrode GE, and sidewall insulating pattern SWD are formed on the first insulating film IL1. The first insulating film IL1 separates the upper gate electrode GE and the lower gate electrode GE from each other in the vertical direction (Z direction). The semiconductor pattern SP includes a channel region CH, a first impurity region SD1, and a second impurity region SD2. The channel region CH has a first end SPe1 and a second end SPe2 that is opposite the first end SPe1 in the second horizontal direction D2. The first impurity region SD1 is located on one side of the first end SPe1, and the second impurity region SD2 is located on one side of the second end SPe2.

[0066] The semiconductor memory element EX2 includes a bit line BL that penetrates the stacked structure SS and an insulating structure ISS that covers the sidewall of the bit line BL. The bit line BL is connected to the direct contact DC. Bit line BL is electrically connected to the first impurity region SD1 via direct contact DC. The information storage element DS is located on one side of the second end SPe2 of the channel region CH. The information storage element DS is electrically connected to the second impurity region SD2. Each information storage element DS includes a first electrode EL1, a dielectric film DL, and a second electrode EL2. In the first layered structure (SS1-1), no metal silicide MS2 is placed between the first electrode EL1 and the second impurity region SD2. In the second layered structure (SS2-1), a metal silicide MS2 is positioned between the first electrode EL1 and the second impurity region SD2. In one embodiment, the metal silicide MS2 can form titanium silicide, cobalt silicide, molybdenum silicide, or zirconium silicide. The spacer SPC is placed between the second electrode EL2 and the gate electrode GE. The spacer SPC is placed between the upper second impurity region SD2 and the lower second impurity region SD2. The spacer SPC separates the upper second impurity region SD2 and the lower second impurity region SD2 from each other in the vertical direction (Z direction).

[0067] As described above, in the semiconductor memory element EX2 of the present invention, metal silicide MS2 is not formed on one side of the lower first semiconductor pattern (SP1-1) among the semiconductor patterns SP that constitute the stacked structure (SS-1) stacked vertically on the substrate SUB. Furthermore, in the semiconductor memory element EX2 of the present invention, a metal silicide MS2 is formed on one side of the upper second semiconductor pattern (SP2-2) among the semiconductor patterns SP that constitute a stacked structure (SS-1) stacked vertically on a substrate SUB. In other words, in the semiconductor memory element EX2 of the present invention, no metal silicide MS2 is formed between the second impurity region SD2 (i.e., second source / drain) on one side of the lower first semiconductor pattern (SP1-1) within the semiconductor pattern SP constituting the stacked structure (SS-1) and the information storage element DS (i.e., capacitor). Furthermore, in the semiconductor memory element EX2 of the present invention, a metal silicide MS2 is formed between a second impurity region SD2 (i.e., a second source / drain) on one side of the upper second semiconductor pattern SP2 within the semiconductor pattern SP constituting the stacked structure SS and an information storage element DS (i.e., a capacitor). The semiconductor memory element EX2 of the present invention reduces variations in contact resistance between the second semiconductor patterns (SP2-1) in the vertical direction (Z direction) during the manufacturing process by forming metal silicide MS2 only on one side of the upper second semiconductor pattern (SP2-1) among the semiconductor patterns SP that constitute the stacked structure (SS-1). As a result, the semiconductor memory element EX2 of the present invention can improve its electrical characteristics by reducing variations in contact resistance between memory cells.

[0068] Figure 18 is a plan view of a memory module including a semiconductor memory element according to an embodiment of the present invention. Specifically, the memory module 1000 includes a printed circuit board 1100 and a plurality of semiconductor packages 1200. Multiple semiconductor packages 1200 include semiconductor memory elements EX1 and EX2 according to embodiments of the present invention. The memory module 1000 is either a SIMM (single in-lined memory module) with multiple semiconductor packages 1200 mounted on only one side of a printed circuit board, or a DIMM (dual in-lined memory module) with multiple semiconductor packages 1200 arranged on both sides. Furthermore, the memory module 1000 may be an FBDIMM (fully buffered DIMM) having an AMB (advanced memory buffer) that forms external signals on each of the multiple semiconductor packages 1200.

[0069] Figure 19 is a block diagram showing a schematic configuration of a memory card including a semiconductor element according to an embodiment of the present invention. Specifically, the memory card 2000 is arranged so that the controller 2100 and the memory 2200 exchange electrical signals. For example, when a command is issued from the controller 2100, the memory 2200 transmits the data. The controller 2100 includes the semiconductor element of the present invention. The memory 2200 may include the semiconductor memory elements (EX1, EX2) of the present invention. Memory Card 2000 can comprise various types of memory cards, such as Memory Stick® cards, SmartMedia cards (SM), Secure Digital Cards (SD), Mini-Secure Digital Cards (MiniSD), and Multimedia Cards (MMC).

[0070] Figure 20 is a block diagram showing the schematic configuration of a system including semiconductor memory elements according to the present embodiment. Specifically, in system 3000, the processor 3100, memory 3200, and input / output device 3300 communicate with each other using bus 3400. The memory 3200 of system 3000 includes RAM (random access memory) and ROM (read-only memory). Furthermore, System 3000 includes peripheral devices 3500 such as a floppy disk drive and a CD (compact disk) ROM drive. The memory 3200 may include the semiconductor memory elements (EX11, EX2) of the present invention. Memory 3200 stores the code and data necessary for the operation of processor 3100. System 3000 can be used in mobile phones, MP3 players, navigation systems, portable multimedia players (PMPs), solid state disks (SSDs), or household appliances.

[0071] Furthermore, the present invention is not limited to the embodiments described above. It can be modified and implemented in various ways without departing from the technical scope of the present invention. [Explanation of symbols]

[0072] BC implantable contact lenses BL bit line CA Cell Array CH channel region DC Direct Contact DL Dielectric Film DS information storage element EL1, EL2 (1st, 2nd) electrodes EX1, EX2 Semiconductor Memory Devices GE Terminal GE1, GE2 (1st, 2nd) gate electrodes GI gate isolation pattern IL1, IL2 (first, second) insulating film ISS insulating structure MC memory cell MCT Memory Cell Transistor MS2 Metal Silicide PER peripheral circuit area SCA Subcell Array SD1, SD2 (1st, 2nd) impurity regions SP semiconductor pattern SP1, SP-1 First semiconductor pattern SP2, SP2-1 Second Semiconductor Pattern SPC Spacer SS, SS-1 laminated structure SS1, SS1-1 First Laminated Structure SS2, SS2-1 Second Laminated Structure SUB board SWD sidewall insulation pattern WL Word Line

Claims

1. A laminated structure comprising multiple layers stacked vertically on a substrate, Here, the laminated structure includes a first laminated structure formed on a substrate and a second laminated structure formed on the first laminated structure. The laminated structure has a bit line formed on one side and extending in the vertical direction, The aforementioned multiple layers are, Semiconductor patterns and, A gate electrode extending in a first horizontal direction on the semiconductor pattern, The semiconductor pattern and an adjacent information storage element are included in a second horizontal direction intersecting the first horizontal direction, The aforementioned semiconductor pattern is A first impurity region adjacent to the bit line, A second impurity region adjacent to the aforementioned information storage element, A channel region between the first impurity region and the second impurity region, including, The information storage element includes a first electrode adjacent to the second impurity region, A semiconductor memory element characterized in that either the first stacked structure or the second stacked structure includes a metal silicide disposed between the second impurity region on one side of the semiconductor pattern and the first electrode.

2. The laminated structure in which the metal silicide is arranged among the first laminated structure and the second laminated structure is an active laminated structure. The semiconductor memory element according to claim 1, characterized in that the stacked structure in which the metal silicide is not disposed among the first stacked structure and the second stacked structure is a dummy stacked structure.

3. The first stacked structure includes a first semiconductor pattern, The second layered structure includes a second semiconductor pattern, The semiconductor memory element according to claim 1, characterized in that the number of stacked second semiconductor patterns is smaller than the number of stacked first semiconductor patterns.

4. The first stacked structure includes a first semiconductor pattern, The second layered structure includes a second semiconductor pattern, The semiconductor memory element according to claim 1, characterized in that the number of stacked first semiconductor patterns is smaller than the number of stacked second semiconductor patterns.

5. The gate electrode and the second impurity region further have a spacer positioned in the second horizontal direction and extending in the first horizontal direction, The semiconductor memory element according to claim 1, characterized in that the outer wall of the metal silicide and the outer wall of the spacer are aligned in the vertical direction.

6. A laminated structure comprising multiple layers stacked vertically on a substrate, Here, the laminated structure includes a first laminated structure formed on a substrate and a second laminated structure formed on the first laminated structure. The laminated structure has a bit line formed on one side and extending in the vertical direction, The aforementioned multiple layers are, Semiconductor patterns and, A gate electrode extending in a first horizontal direction on the semiconductor pattern, The semiconductor pattern and an adjacent information storage element are included in a second horizontal direction intersecting the first horizontal direction, The aforementioned semiconductor pattern is A first impurity region adjacent to the bit line, A second impurity region adjacent to the aforementioned information storage element, A channel region between the first impurity region and the second impurity region, including, The information storage element includes a first electrode adjacent to the second impurity region, The first stacked structure is an active stacked structure that includes a metal silicide disposed between the second impurity region on one side of the semiconductor pattern and the first electrode, The semiconductor memory element is characterized in that the second stacked structure is a dummy stacked structure in which no metal silicide is disposed between the second impurity region on one side of the semiconductor pattern and the first electrode.

7. The first stacked structure includes a first semiconductor pattern, The second layered structure includes a second semiconductor pattern, The semiconductor memory element according to claim 6, characterized in that the number of stacked second semiconductor patterns is smaller than the number of stacked first semiconductor patterns.

8. The gate electrode and the second impurity region further have a spacer positioned in the second horizontal direction and extending in the first horizontal direction, The outer wall of the second impurity region of the second laminated structure and the outer wall of the spacer are aligned in the vertical direction. The semiconductor memory element according to claim 6, characterized in that the outer wall of the metal silicide of the first stacked structure and the outer wall of the spacer are aligned in the vertical direction.

9. A laminated structure comprising multiple layers stacked vertically on a substrate, Here, the laminated structure includes a first laminated structure formed on a substrate and a second laminated structure formed on the first laminated structure. The laminated structure has a bit line formed on one side and extending in the vertical direction, The aforementioned multiple layers are, Semiconductor patterns and, A gate electrode extending in a first horizontal direction on the semiconductor pattern, The semiconductor pattern and an adjacent information storage element are included in a second horizontal direction intersecting the first horizontal direction, The aforementioned semiconductor pattern is A first impurity region adjacent to the bit line, A second impurity region adjacent to the aforementioned information storage element, A channel region between the first impurity region and the second impurity region, including, The information storage element includes a first electrode adjacent to the second impurity region, The first stacked structure is a dummy stacked structure in which no metal silicide is disposed between the second impurity region on one side of the semiconductor pattern and the first electrode. The semiconductor memory element is characterized in that the second stacked structure is an active stacked structure that includes a metal silicide disposed between the second impurity region on one side of the semiconductor pattern and the first electrode.

10. The first stacked structure includes a first semiconductor pattern, The second layered structure includes a second semiconductor pattern, The semiconductor memory element according to claim 9, characterized in that the number of stacked first semiconductor patterns is smaller than the number of stacked second semiconductor patterns.

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