Dual-processor device and its control method and processor

Abstract

This invention provides a dual-processor device and a control method thereof. It solves the problem of data accuracy between the control processor and the arithmetic processor caused by the non-synchronization of the control processor and the arithmetic processor in conventional technology. [Solution] The dual processor includes a control processor and an arithmetic processor, and is implemented by the control processor, which, upon detecting the occurrence of an arc, sends a pre-turnoff output pre-shakehand to the arithmetic processor, causing the arithmetic processor to stop the relevant arithmetic operation, and the notification of the cessation of the arithmetic operation is issued after the arithmetic processor has received the pre-turnoff output pre-shakehand and completed the calculation of the received data, and the operation of a turnoff operation.

Description

Technical Field

[0001] The present invention relates to the technical field of device control, and specifically relates to dual-processor devices, their control methods, and processors.

Background Art

[0002] In the control mode of conventional dual-processor devices, Processor A is used to control the circuit and detect arcs, and Processor B performs PID calculations to provide control circuit operation parameters to Processor A. When Processor A detects an arc occurrence, it executes invalid control (DISABLE) to immediately disconnect the circuit or stop the signal output. However, since the PID calculation cannot be interrupted, when Processor A executes invalid control, Processor B continues the PID calculation and feeds back the control circuit operation parameters to Processor A. However, for Processor A, at this time, the calculation parameters fed back by Processor B are redundant, unnecessary, and errors. In addition, the invalid control of Processor A is sudden, and due to the operation parameters fed back by Processor B, Processor A may not be able to connect to subsequent monitoring data, and the entire control data group may become invalid.

[0003] Therefore, how to design a highly reliable and high-precision dual-processor device and its control method is a technical problem to be solved.

Summary of the Invention

Problems to be Solved by the Invention

[0004] Therefore, the technical problem to be solved by the present invention is that in the prior art, in dual-processor ​​​​​​​​​​​When PID control is performed between S and S, the control processor's control circuit immediately interrupts, but the calculations... The lossr continues PID calculations between the control processor and the arithmetic processor. The goal is to overcome the impact on data accuracy. Therefore, dual processors are necessary. The present invention provides a device, a method for controlling the same, and a processor. [Means for solving the problem]

[0005] To solve the above technical problems, the embodiments disclosed in the present invention are dual-processor machines The present invention provides at least a device, a method for controlling the same, and a processor.

[0006] According to the first aspect, the embodiments disclosed in the present invention relate to a dual-processor device control method. The dual processor includes a control processor and an arithmetic processor, and the The law is implemented by the control processor, When arc generation is detected, the arithmetic processor outputs a pre-turn-off pre-shake-handle By sending a signal, the arithmetic processor performs the pre-turn-off output pre-shakehand The steps include stopping the associated arithmetic operations based on the above, Receiving a calculation stop notification transmitted by the aforementioned calculation processor, A stop notification is issued when the arithmetic processor receives the pre-turn-off output pre-shakehand. Then, there is the step that is performed after the calculation of the received data has been completed, A dual processor characterized by including the step of performing a turn-off operation. A method for controlling equipment is provided.

[0007] Preferably, the above method is If the restart conditions are met, the restarted pre-shakehand is sent to the arithmetic processor. By doing so, the arithmetic processor performs based on the restarted pre-shakehand. Steps to restore financial reserves, After receiving the recovery confirmation message fed back by the aforementioned processing processor, To recover the acquisition of device operation data and transmit the device operation data to the processing processor. A step to recover, wherein the recovery confirmation message indicates that the arithmetic processor is performing calculations This further includes a step that is sent after the intention has been completed.

[0008] Preferably, before sending a restarted pre-shakehand to the arithmetic processor, The process further includes determining whether the arithmetic processor is in a sleep state, Sending a restarted pre-shakehand to the aforementioned arithmetic processor means that the arithmetic processor If the processor is in sleep mode, the restarted preshake function is sent to the arithmetic processor. It is about downloading.

[0009] Preferably, before sending a restarted pre-shakehand to the arithmetic processor, If the aforementioned processing processor is not in sleep mode, the device operation data is directly acquired, The further step includes transmitting the device operation data to the arithmetic processor.

[0010] Preferably, the restart condition is the length of the turn-off time that has been set in advance. This includes whether or not the condition is met, and / or whether or not restart instruction information is received.

[0011] Preferably, The process further includes a step of entering a sleep state after performing a turn-off operation.

[0012] Preferably, before entering sleep mode, the method freezes the equipment operation data for the arc generation period. further includes a step of binding.

[0013] According to a second aspect, an embodiment disclosed in the present invention is a control processor for a dual-processor device, when detecting arc generation, sends a pre-turn-off output pre-shake hand to an arithmetic processor, so that the arithmetic processor stops related arithmetic operations based on the pre-turn-off output pre-shake hand, a pre-turn-off instruction module; a pre-turn-off execution module for receiving an arithmetic stop notification sent by the arithmetic processor, where the arithmetic stop notification is sent after the arithmetic processor has received the pre-turn-off output pre-shake hand and completed the arithmetic of the received data, a pre-turn-off execution module; and a turn-off module for executing a turn-off operation, and provides a control processor for a dual-processor device.

[0014] According to a third aspect, an embodiment disclosed in the present invention is a method for controlling a dual-processor device, where the dual-processor includes a control processor and an arithmetic processor, and the method is implemented by the arithmetic processor, including the steps of receiving a pre-turn-off output pre-shake hand sent by the control processor, after completing the arithmetic of the received data, stopping related arithmetic operations, and sending an arithmetic stop notification to the control processor, so that after the control processor receives the arithmetic stop notification, it executes a turn-off operation, and provides a method for controlling a dual-processor device.

[0015] Preferably, The control processor receives the pre-shake hand that has been transmitted and restarted. Step and, Steps to complete preparation for recovery of operations based on the restarted pre-shakehand and, By sending a recovery confirmation message to the control processor, the control processor The steps include: recovering the acquisition of device operation data based on the recovery confirmation message, The steps include receiving the device operation data transmitted by the control processor, and It also includes.

[0016] Preferably, after sending a calculation stop notification to the control processor, the method enters a sleep state. This further includes the steps to enter the state.

[0017] Preferably, before entering the sleep state, the method is used for the operation of the equipment during the arc generation period. This further includes freezing the data.

[0018] According to a fourth aspect, the embodiments disclosed herein are for dual-processor devices. It is an arithmetic processor, The control processor received a pre-turn-off output pre-shakehand. The pre-turn-off instruction receiving module, After completing calculations on the received data, the calculation stop function is used to stop the associated calculation operations. Control module and By sending a calculation stop notification to the control processor, the control processor stops the calculation A stop notification module for performing a turn-off operation after receiving a stop notification, The present invention provides an arithmetic processor for a dual-processor device, characterized by including [a specific feature].

[0019] According to the fifth aspect, the embodiments disclosed in the present invention are dual-processor devices, Control processor for dual-processor device as described in the second aspect and as described in the fourth aspect A dual-processor device characterized by including an arithmetic processor for dual-processor equipment. We provide processing equipment.

[0020] According to the sixth aspect, the embodiments disclosed in the present invention relate to a dual-processor device control method. The dual-processor device comprises a control processor, an arithmetic processor, and a shared memory processor. The method includes a control This is made possible by the processor. Upon detecting the occurrence of an arc, the step of performing a turn-off operation, By setting the turn-off instruction identifier in the shared memory to the turn-off state The arithmetic processor generates first device operation data based on the state of the turn-off instruction identifier. A step of skipping the acquisition of the first device operation data, wherein the control process This includes a step which is equipment operation data acquired during the arc generation period by the system, and This invention provides a dual-processor device control method that features a distinctive design.

[0021] Preferably, before detecting the occurrence of an arc, the method is performed as follows: Steps include acquiring second device operation data, The second device operation data is transmitted to the arithmetic processor via the shared memory. It also includes the top.

[0022] Preferably, the second device operation data is sent to the arithmetic processor via the shared memory. The steps to believe are, In order for the arithmetic processor to acquire the second device operation data from the shared memory The procedure includes the step of storing the operation data of the second device in the shared memory.

[0023] Preferably, after performing a turn-off operation, the method includes a step of entering a sleep state. It also includes.

[0024] Preferably, the above method is If the restart conditions are met, the steps to restart are as follows: The steps include setting the turn-off instruction identifier in the shared memory to a normal state, A step to recover the acquisition of the second device operation data, To transmit the operation data of the second device to the processing processor via the shared memory. By recovering the state of the turn-off instruction identifier, the arithmetic processor will recover the state of the turn-off instruction identifier. The method further includes the step of obtaining the operation data of the second device from the shared memory.

[0025] Preferably, the restart conditions are: Whether the turn-off time satisfies the length of the predetermined turn-off time, and / or, This includes whether or not to receive restart instruction information.

[0026] Preferably, before entering sleep mode, the method freezes the equipment operation data for the arc generation period. This includes further steps to conclude the process.

[0027] According to the seventh aspect, the embodiments disclosed in the present invention are dual-processor devices, The dual-processor device includes a control processor, an arithmetic processor, and shared memory. The shared memory is set with a turn-off instruction identifier, and the control processor, When an arc is detected, the turn-off instruction module performs the turn-off operation. and, By setting the turn-off instruction identifier in the shared memory to the turn-off state The arithmetic processor generates first device operation data based on the state of the turn-off instruction identifier. A turn-off state setting module for skipping the acquisition of the first device operation The data is equipment operation data acquired by the control processor during the arc generation period. A dual-processor device characterized by including a turn-off state setting module. provide.

[0028] According to the eighth aspect, the embodiments disclosed in the present invention relate to a dual-processor device control method. The dual-processor device includes a control processor, an arithmetic processor, and a shared memory. The method includes a turn-off instruction identifier set in the shared memory, and the calculation process Realized by Rossessa, The steps include: obtaining the state of the turn-off instruction identifier in the shared memory; If the turn-off instruction identifier is in the turn-off state, the turn-off instruction identifier This involves skipping the acquisition of first device operation data based on the state, and the first device The operation data is equipment operation data acquired by the control processor during the arc generation period. The present invention provides a dual-processor device control method characterized by including the step of [step name].

[0029] Preferably, If the turn-off instruction identifier is in a normal state, the first device operation data is obtained from the shared memory. Steps to obtain data, The control parameters are calculated based on the operation data of the first device, The calculated control parameters are transmitted to the control processor via the shared memory. The steps include, and further include.

[0030] Preferably, when the turn-off indicator identifier is in the turn-off state, the system enters sleep mode. This further includes doing so.

[0031] Preferably, before obtaining the state of the turn-off instruction identifier in the shared memory, The notation method is, If the restart conditions are met, the process will further include a step to restart, The step of obtaining the state of the turn-off instruction identifier in the shared memory is shared The goal is to recover the state of the turn-off instruction identifier in memory.

[0032] Preferably, before entering sleep mode, the method freezes the equipment operation data for the arc generation period. This includes further steps to conclude the process.

[0033] According to the ninth aspect, the embodiments disclosed in the present invention are dual-processor devices, It includes a control processor, an arithmetic processor and a shared memory, and the shared memory has a turn-off An instruction identifier is set, and the arithmetic processor, Turnoff to obtain the state of the turnoff instruction identifier in the shared memory. Identifier acquisition module, If the turn-off instruction identifier is in the turn-off state, the turn-off instruction identifier Turn-off data processing mode to skip the acquisition of first device operation data based on the status. The first device operation data is in joules, and the arc generation period is determined by the control processor. This includes a turn-off data processing module, which is the equipment operation data acquired in between. It provides a dual-processor device that features this characteristic.

[0034] According to the tenth aspect, the embodiments disclosed in the present invention are dual-processor devices. , shared memory, control processor according to the 9th aspect, and arithmetic processor according to the 9th aspect The dual is characterized in that a turn-off instruction identifier is set in the shared memory. We provide processor equipment.

[0035] According to the eleventh aspect, the embodiments disclosed in the present invention are computer equipment, and The processor includes a processor, memory, and a bus, and the memory contains machine-readable data that the processor can execute. When the command is stored and the computer device is executed, the processor and the memory and The first communicates via the bus, and when the machine-readable instruction is executed by the processor, Dual processor equipment as described in any one of the following descriptions: 1st, 2nd, 3rd, 4th, or 8th description. The present invention provides a computer device characterized by its ability to execute a control method.

[0036] According to the twelfth aspect, the embodiments disclosed in the present invention are computer-readable storage media. Furthermore, a computer program is stored in the computer-readable storage medium, and the computer When the computer program is executed by the processor, the first, third, and sixth embodiments Or, to perform the dual processor device control method described in any one of the eighth aspects. The present invention provides a computer-readable storage medium characterized by the following:

[0037] (Effects of the invention) The technical method according to the embodiments of the present invention can have the following beneficial effects. Dualp In the control process based on the regulator, when the control processor detects the occurrence of an arc, the turn-off control is activated. The operation can be executed, and the acquisition of device operation data by the processor performing the calculations can be stopped. It is also possible to send a turn-off operation instruction to the arithmetic processor. The arithmetic processor then... Based on whether or not equipment operation data was acquired, or whether or not a turn-off calculation instruction was acquired. Based on this, it is decided whether or not to interrupt the calculation operation of the relevant control parameters, or if the calculation is completed. This determines whether or not to stop sending the related control parameters to the control processor. This ensures that the control processor obtains accurate control parameters and confirms arc generation. To maintain. When the control processor turns off the circuit, data between the dual processors The system can maintain good accuracy, stop PID calculations in a timely manner, and turn off OK. This avoids extending the John Point and reduces situations where data is discarded, and at one end When a circuit is turned off, the other end continues to operate, causing turbulent movement throughout the circuit. Unless the operation is avoided and the calculation of the entire PID has not started, the calculation may be interrupted or the calculation may be interrupted. It is not necessary to send completed operation parameters, and commands, shake hands, or data sharing are not required. When applied and turned off, the data is frozen between the control processor and the arithmetic processor. To ensure the stability and consistency of data transmission, when the control processor circuit is turned off, Disruption of the entire circuit due to the other end's processing unit still performing unnecessary calculations. To avoid this behavior, when an arc occurs, data is exchanged between the control processor and the arithmetic processor. To effectively ensure accuracy.

[0038] By referring to the following drawings, an exemplary embodiment of the present invention can be more fully understood. This is possible. The drawings are provided to further understand the embodiments of the present application. This specification, along with the examples, constitutes a part of the specification for explaining the present invention and constitutes a limitation of the present invention. That's not the case. In drawings, the same reference numeral usually represents the same part or step. [Brief explanation of the drawing]

[0039] [Figure 1] This is a flowchart of a dual-processor device control method according to an embodiment disclosed in the present invention. [Figure 2] This is a flowchart of another dual-processor device control method according to an embodiment disclosed in the present invention. [Figure 3] This is a schematic diagram of the interaction and timing between the control processor and the arithmetic processor according to an embodiment disclosed in the present invention. [Figure 4] This is a schematic diagram of the interaction and timing between the control processor and the arithmetic processor according to an embodiment disclosed in the present invention. [Figure 5] This is a schematic diagram of the interaction and timing between the control processor and the arithmetic processor according to an embodiment disclosed in the present invention. [Figure 6] This is a schematic diagram of the interaction and timing between the control processor and the arithmetic processor according to an embodiment disclosed in the present invention. [Figure 7] This is a flowchart of another dual-processor device control method according to an embodiment disclosed in the present invention. [Figure 8] This is a flowchart of another dual-processor device control method according to an embodiment disclosed in the present invention. [Figure 9] This is a schematic diagram of the structure of a control processor for a dual-processor device according to an embodiment disclosed in the present invention. [Figure 10] This is a schematic diagram of the structure of an arithmetic processor for a dual-processor device according to an embodiment disclosed in the present invention. [Figure 11] This is a schematic diagram of the structure of a dual-processor device according to an embodiment disclosed in the present invention. [Figure 12] This is a flowchart of a dual-processor device control method according to an embodiment disclosed in the present invention. [Figure 13] This is a flowchart of another dual-processor device control method according to an embodiment disclosed in the present invention. [Figure 14] This is a flowchart of another dual-processor device control method according to an embodiment disclosed in the present invention. [Figure 15] This is a flowchart of another dual-processor device control method according to an embodiment disclosed in the present invention. [Figure 16] This is a schematic diagram of the structure of a control processor in a dual-processor device according to an embodiment disclosed in the present invention. [Figure 17] This is a schematic diagram of the structure of the arithmetic processor in another dual-processor device according to an embodiment disclosed in the present invention. [Figure 18] This is a schematic diagram of a dual-processor device structure according to an embodiment disclosed in the present invention. [Figure 19] This is a timing relationship diagram of a dual-processor device control method according to an embodiment disclosed in the present invention. [Figure 20] This is a timing relationship diagram of a dual-processor device control method according to an embodiment disclosed in the present invention. [Figure 21] This is a timing relationship diagram of a dual-processor device control method according to an embodiment disclosed in the present invention. [Figure 22] This is a flowchart of another dual-processor device control method according to an embodiment disclosed in the present invention. [Figure 23] This is a flowchart of another dual-processor device control method according to an embodiment disclosed in the present invention. [Modes for carrying out the invention]

[0040] The exemplary embodiments of this disclosure will be described in more detail below with reference to the drawings. While exemplary embodiments of the present disclosure are shown, the present disclosure is not limited to the embodiments described herein. It should be understood that it should not be limited by this, but rather can be implemented in various forms. Conversely, providing these embodiments will lead to a better understanding of this disclosure and a full understanding of its scope. This is so that it can be communicated to those skilled in the art.

[0041] In the description of this invention, unless otherwise specifically defined or limited, the term "attachment" refers to: The terms "connection" and "linking" should be understood in a broad sense; for example, they could even refer to a fixed connection. The connection may be detachable or integral, and is a mechanical connection. This may also be an electrical connection, a direct connection, or an indirect connection via an intermediate medium. It may be a continuation, or it may be an internal connection of two elements. Those skilled in the art will know the specifics. Depending on the context, the specific meaning of the above terms in this invention can be specifically understood.

[0042] Furthermore, the technical features of different embodiments of the present invention described below are such that collisions occur between them. If they are not present, they can combine with each other.

[0043] (Example 1) As shown in Figure 1, a dual-processor device control method according to an embodiment disclosed in the present invention. This is a flowchart showing that a dual processor consists of a control processor and an arithmetic processor. The method, which is implemented by a control processor, includes the following:

[0044] S11: When arc generation is detected, the arithmetic processor outputs a pre-turn-off preshake. By sending a hand, the computing processor outputs a pre-turn-off output pre-shake hand. The associated calculation operations are stopped based on this.

[0045] S12: The calculation stop notification sent by the arithmetic processor is received, and the calculation stop notification is processed The arithmetic processor receives the pre-turn-off output pre-shakehand, and then receives the received data This is what is displayed after the calculation is completed.

[0046] S13: Perform the turn-off operation.

[0047] To make it easier to understand, in the technical proposal according to this embodiment, during the control process of a dual-processor device, When the control processor detects the occurrence of an arc, it sends a pre-turn-off output to the arithmetic processor. The shakehand signal is sent, and the processing unit outputs a pre-turn-off signal to the pre-shakehand. Based on this, the calculation of the received data is completed and the related calculation operations are stopped, and the control program After receiving a calculation stop notification sent by the processing unit, the cessator performs a turn-off operation. This is executed, and data transmission between the control processor and the arithmetic processor occurs through a shakehand. To ensure stability and consistency, when the control processor circuit is turned off, the other end of the arithmetic plane This avoids disruptive behavior of the entire circuit caused by the lossser still performing unnecessary calculations. Furthermore, when an arc occurs, it affects the data accuracy between the control processor and the arithmetic processor. Secure it as intended.

[0048] (Example 2) As an improvement to Example 1, as shown in Figure 2, another duplication according to the embodiment disclosed in the present invention This is a flowchart of the dual-processor device control method, and the dual-processor control process The method includes a separator and an arithmetic processor, and is implemented by a control processor, and the following This includes.

[0049] S21: If the restart conditions are met, the control processor will enter a sleep state while the arithmetic processor is in sleep mode. It determines whether or not it is in sleep mode, and if the arithmetic processor is in sleep mode, it executes S22. If the computing processor is not in sleep mode, execute S24.

[0050] S22: The control processor sends a restarted pre-shakehand to the arithmetic processor. By doing so, the computing processor prepares for calculation based on the restarted pre-shakehand. To recover.

[0051] S23: The control processor receives the recovery confirmation message fed back by the arithmetic processor. Upon receiving the message, execution of S24 is restored, and a recovery confirmation message is sent, indicating that the arithmetic processor is performing calculations. This should be sent after all preparations are complete.

[0052] S24: The control processor acquires equipment operation data and sends it to the arithmetic processor. Send the tag.

[0053] S25: When arc generation is detected, the control processor pre-turns on the arithmetic processor. By sending a pre-shakehand output, the arithmetic processor pre-turns off the output. The associated operations are stopped based on the reshakehand.

[0054] S26: The control processor receives the calculation stop notification sent by the arithmetic processor. The calculation stop notification is issued when the calculation processor receives a pre-turn-off output pre-shakehand. It is output after the calculations on the received data have been completed.

[0055] S27: The control processor performs the turn-off operation.

[0056] S28: The control processor freezes the equipment operation data for the arc generation period.

[0057] S29: The control processor enters sleep mode.

[0058] In some selective embodiments, the restart condition is a turn-off time that is set to a preset time. This includes whether the length of the shutdown period is met and / or whether restart instruction information is received. .

[0059] Furthermore, the data will be frozen, and CPUB alone or CPUA and CPUB simultaneously. It can enter a sleep state if it has a certain degree of sleep.

[0060] It should be explained that the embodiments described in this specific model are specific examples under the concept of the present invention. This is merely an illustrative description of typical embodiments, and the execution of the steps in each embodiment The order is not limited to the examples provided herein, and in carrying out specific steps, those skilled in the art will know The execution order of each step can be adjusted based on the actual situation, for example, S21 and S 27 has no necessary cause-and-effect relationship or sequence of events; the restart operation in S21 is the turn of S27. It may be written after the OFF operation.

[0061] To facilitate the reader's understanding, Figures 3, 4, 5, and 6 below will be combined to represent CPUA. The control processor is and the CPUB is used as the arithmetic processor in the embodiment of the present invention. This document provides a detailed explanation of the interaction process and timing relationships of the processor device control method. To clarify, at the first timing, CPUA transmits the data necessary for PID calculation to CPUB. The data is sent, CPUB acquires the data and performs PID calculations, and CPUA detects the arc. After sending a pre-shakehand with a pre-turn-off output, CPUB completes the PID operation. Accurate data is obtained and sent back to CPUA, and CPUB responds according to the shake-hand The stopped timing PID calculation preparation is fed back to CPUA, and CPUA then C The PUB receives feedback and performs a turn-off output, and the CPUA does this at this timing. Discard the PID data that was fed back to the system.

[0062] At the Nth timing, if N is an integer > 1, CUPB sleeps and CUPB This can be divided into two cases: 1. When CPUB is not sleeping. CPUA restarts the control circuit and outputs power, and CPUA is necessary for PID calculations. The data is transmitted to the CPUB, which retrieves the data and performs PID calculations.

[0063] 2. If CPUB goes to sleep, CPUA will exit the restarted pre-shakehand. CPUB then gives feedback that CPUA is ready, and CPUA then P The data necessary for ID calculation is transmitted to the CPUB, which then retrieves the data and performs PID calculation. Perform.

[0064] To make it easier to understand, in the technical proposal according to this embodiment, during the control process of a dual-processor device, When the control processor detects the occurrence of an arc, it sends a pre-turn-off output to the arithmetic processor. The shakehand signal is sent, and the processing unit outputs a pre-turn-off signal to the pre-shakehand. Based on this, the calculation of the received data is completed and the related calculation operations are stopped, and the control program After receiving a calculation stop notification sent by the processing unit, the cessator performs a turn-off operation. This is executed, and data transmission between the control processor and the arithmetic processor occurs through a shakehand. To ensure stability and consistency, when the control processor circuit is turned off, the other end of the arithmetic plane This avoids disruptive behavior of the entire circuit caused by the lossser still performing unnecessary calculations. Furthermore, when an arc occurs, it affects the data accuracy between the control processor and the arithmetic processor. Secure it as intended.

[0065] (Example 3) As shown in Figure 7, the embodiment of the present invention further provides a dual-processor device control method. The dual processor includes a control processor and an arithmetic processor, and the method includes an arithmetic processor This is achieved by a Rossessa and includes the following:

[0066] S31: The pre-turn-off output pre-shakehand sent by the control processor is received. I believe.

[0067] S32: After completing the calculations on the received data, the associated calculation operations are stopped.

[0068] S33: By sending a calculation stop notification to the control processor, the control processor stops the calculation. After receiving the stop notification, perform the turn-off operation.

[0069] To make it easier to understand, in the technical proposal according to this embodiment, during the control process of a dual-processor device, When the control processor detects the occurrence of an arc, it sends a pre-turn-off output to the arithmetic processor. The shakehand signal is sent, and the processing unit outputs a pre-turn-off signal to the pre-shakehand. Based on this, the calculation of the received data is completed and the related calculation operations are stopped, and the control program After receiving a calculation stop notification sent by the processing unit, the cessator performs a turn-off operation. This is executed, and data transmission between the control processor and the arithmetic processor occurs through a shakehand. To ensure stability and consistency, when the control processor circuit is turned off, the other end of the arithmetic plane This avoids disruptive behavior of the entire circuit caused by the lossser still performing unnecessary calculations. Furthermore, when an arc occurs, it affects the data accuracy between the control processor and the arithmetic processor. Secure it as intended.

[0070] (Example 4) As an improvement to Example 3, as shown in Figure 8, the embodiment of the present invention is a dual-processor machine The instrument control method is further provided, and the dual processor consists of a control processor and an arithmetic processor. The method includes the following, and is implemented by an arithmetic processor:

[0071] S41: The arithmetic processor receives the pre-turn-off output pre-transmission sent by the control processor. Receive a handshake.

[0072] S42: After completing the calculations on the received data, the processing unit performs the associated calculation operations. Stop production.

[0073] S43: The processing unit freezes the equipment operation data for the arc generation period.

[0074] S44: The arithmetic processor sends a notification to the control processor that the arithmetic has stopped, After receiving a notification that the calculation has stopped, the processor performs a turn-off operation.

[0075] S45: The processing unit enters sleep mode.

[0076] S46: The arithmetic processor is sent and restarted by the control processor. Received a call.

[0077] S47: The arithmetic processor uses the function of arithmetic recovery based on the restarted pre-shakehand. To complete an action.

[0078] S48: The arithmetic processor sends a recovery confirmation message to the control processor. The control processor recovers the acquisition of equipment operation data based on the recovery confirmation message.

[0079] S49: The arithmetic processor receives the device operation data transmitted by the control processor. ru.

[0080] To make it easier to understand, in the technical proposal according to this embodiment, during the control process of a dual-processor device, When the control processor detects the occurrence of an arc, it sends a pre-turn-off output to the arithmetic processor. The shakehand signal is sent, and the processing unit outputs a pre-turn-off signal to the pre-shakehand. Based on this, the calculation of the received data is completed and the related calculation operations are stopped, and the control program After receiving a calculation stop notification sent by the processing unit, the cessator performs a turn-off operation. This is executed, and data transmission between the control processor and the arithmetic processor occurs through a shakehand. To ensure stability and consistency, when the control processor circuit is turned off, the other end of the arithmetic plane This avoids disruptive behavior of the entire circuit caused by the lossser still performing unnecessary calculations. Furthermore, when an arc occurs, it affects the data accuracy between the control processor and the arithmetic processor. Secure it as intended.

[0081] (Example 5) As shown in Figure 9, an embodiment of the present invention is a control processor for a dual-processor device. Furthermore, the control processor for this dual-processor device provides arc generation. Upon detection, it sends a pre-turn-off output pre-shakehand to the processing unit. The arithmetic processor performs the relevant arithmetic operations based on the pre-turn-off output pre-shakehand. A pre-turn-off instruction module 51 for stopping, and transmitted by the arithmetic processor A pre-turn-off execution module 52 for receiving a calculation stop notification, and the calculation stop The notification is received after the arithmetic processor receives the pre-turn-off output pre-shakehand. The pre-turn-off execution module 52 is issued after the calculation of the data has been completed. It includes a turn-off module 53 for performing a turn-off operation.

[0082] In some selective embodiments, the control process is as shown by the dashed lines in the drawings. If the restart conditions are met, the system sends a restarted pre-shakehand to the arithmetic processor. By trusting, the computing processor restarts and prepares for calculation based on the pre-shakehand. A restart shakehand module 54 for recovery and a feed by the arithmetic processor After receiving the backed-up recovery confirmation message, the device operation data acquisition is restored, and the calculation process is performed. Recover the transmission of device operation data to the processor, and if the processing unit is not in sleep mode. , recovery to directly acquire device operation data and transmit device operation data to the processing processor Confirmation module 55, and recovery confirmation message indicates that the arithmetic processor has completed preparation for calculation. It further includes a recovery confirmation module 55, which is transmitted after the process has been completed.

[0083] In some selective embodiments, the control process is as shown by the dashed lines in the drawings. S is a first data freezing module 56 for freezing equipment operation data during the arc generation period. Then, after performing the turn-off operation, the control processor enters a sleep state. The sleep startup module 57 and the arithmetic processor are used to determine whether or not the arithmetic processor is in a sleep state. It further includes a sleep determination module 58.

[0084] Restart Shakehand Module 54 restarts pre-shakehand to the arithmetic processor. Sending a signal will cause the processing unit to be in sleep mode, which will trigger a restart shakehand. Module 54 sends a restarted pre-shakehand to the arithmetic processor. be.

[0085] In some selective embodiments, the restart condition is a turn-off time that is set to a preset time. This includes whether the length of the shutdown period is met and / or whether restart instruction information is received. .

[0086] To make it easier to understand, in the technical proposal according to this embodiment, during the control process of a dual-processor device, When the control processor detects the occurrence of an arc, it sends a pre-turn-off output to the arithmetic processor. The shakehand signal is sent, and the processing unit outputs a pre-turn-off signal to the pre-shakehand. Based on this, the calculation of the received data is completed and the related calculation operations are stopped, and the control program After receiving a calculation stop notification sent by the processing unit, the cessator performs a turn-off operation. This is executed, and data transmission between the control processor and the arithmetic processor occurs through a shakehand. To ensure stability and consistency, when the control processor circuit is turned off, the other end of the arithmetic plane This avoids disruptive behavior of the entire circuit caused by the lossser still performing unnecessary calculations. Furthermore, when an arc occurs, it affects the data accuracy between the control processor and the arithmetic processor. Secure it as intended.

[0087] (Example 6) As shown in Figure 10, an embodiment of the present invention provides a computing processor for a dual-processor device. To further enhance this dual-processor device, the computing processor for this device is a control processor. Pretender to receive pre-turn-off output pre-shakehand sent by the sender The ON-OFF instruction receiving module 61, after completing the calculation of the received data, performs the associated operations. A calculation stop control module 62 for stopping calculation operations and a notification to the control processor to stop calculation operations. By sending this message, the control processor will perform a turn-off operation after receiving a notification that it has stopped processing. It includes a calculation stop notification module 63 for that purpose.

[0088] In some selective embodiments, the calculation process is as shown by the dashed lines in the drawings. S is a second data freezing module 64 for freezing equipment operation data during the arc generation period. And a second sleep start module 65 for the arithmetic processor to enter a sleep state, and A share to receive the pre-shake hand sent and restarted by your processor. The shakehand receiving module 66 and the arithmetic recovery based on the restarted pre-shakehand The calculation recovery module 67 completes the preparation and sends a recovery confirmation message to the control processor. By sending a message, the control processor uses the recovery confirmation message to determine the device operation data. A recovery message sending module to recover acquisition and restore transmission of operational data to the device. R68 and, A device data receiving module for receiving device operation data transmitted by the control processor. It further includes 69.

[0089] To make it easier to understand, in the technical proposal according to this embodiment, during the control process of a dual-processor device, When the control processor detects the occurrence of an arc, it sends a pre-turn-off output to the arithmetic processor. The shakehand signal is sent, and the processing unit outputs a pre-turn-off signal to the pre-shakehand. Based on this, the calculation of the received data is completed and the related calculation operations are stopped, and the control program After receiving a calculation stop notification sent by the processing unit, the cessator performs a turn-off operation. This is executed, and data transmission between the control processor and the arithmetic processor occurs through a shakehand. To ensure stability and consistency, when the control processor circuit is turned off, the other end of the arithmetic plane This avoids disruptive behavior of the entire circuit caused by the lossser still performing unnecessary calculations. Furthermore, when an arc occurs, it affects the data accuracy between the control processor and the arithmetic processor. Secure it as intended.

[0090] (Example 7) As shown in Figure 11, the embodiment of the present invention further provides a dual-processor device, The dual-processor device is a control processor for the dual-processor device of the above embodiment 5. Includes a sasser and an arithmetic processor for the dual-processor device of the above embodiment 6.

[0091] To make it easier to understand, in the technical proposal according to this embodiment, during the control process of a dual-processor device, When the control processor detects the occurrence of an arc, it sends a pre-turn-off output to the arithmetic processor. The shakehand signal is sent, and the processing unit outputs a pre-turn-off signal to the pre-shakehand. Based on this, the calculation of the received data is completed and the related calculation operations are stopped, and the control program After receiving a calculation stop notification sent by the processing unit, the cessator performs a turn-off operation. This is executed, and data transmission between the control processor and the arithmetic processor occurs through a shakehand. To ensure stability and consistency, when the control processor circuit is turned off, the other end of the arithmetic plane This avoids disruptive behavior of the entire circuit caused by the lossser still performing unnecessary calculations. Furthermore, when an arc occurs, it affects the data accuracy between the control processor and the arithmetic processor. Secure it as intended.

[0092] (Example 8) As shown in Figure 12, a dual-processor device control method according to an embodiment disclosed in the present invention This is a flowchart of the law, and dual-processor devices consist of a control processor and an arithmetic processor. The method includes a shared memory, the shared memory is set with a turn-off instruction identifier, and the method is This is implemented by a control processor and includes the following:

[0093] S81: When arc generation is detected, the turn-off operation is performed.

[0094] S82: By setting the turn-off instruction identifier in the shared memory to the turn-off state The processing unit acquires first device operation data based on the state of the turn-off instruction identifier. By skipping this step, the first equipment operation data is acquired by the control processor during the arc generation period. This is the operation data of the equipment.

[0095] To make it easier to understand, the proposed technology in this embodiment uses a dual-processor-based PID control During the process, when the control processor detects the occurrence of an arc, it performs a turn-off operation, and the shared The turn-off instruction identifier in Mori is set to the turn-off state, and the arithmetic processor then... Based on the state of the off instruction identifier, the control processor acquires the following information during the arc generation period. The acquisition of device operation data is skipped, and one CPU writes to the shared memory. Even if area protection occurs, the other CPU can still read the shared data. By using this method, regardless of what tasks both CPUs are performing, data can be transferred from the high-speed memory unit. In the first hour, it is possible to acquire the changing data and operating status of the opponent's CPU, and control the program. To ensure the stability and consistency of data transmission between the separator and the processing processor, and the control processor When the circuit is turned off, the arithmetic processor on the other end still performs unnecessary calculations. This avoids disruptive operation of the entire circuit, and if an arc occurs, the control processor and Effectively ensures data accuracy between the processing unit and the data processor.

[0096] (Example 9) As an improvement to Example 8, as shown in Figure 13, another example according to the embodiments disclosed in the present invention This is a flowchart of the dual processor device control method, where the dual processor device is controlled It includes a processor, an arithmetic processor and shared memory, and the shared memory contains a turn-off indicator. A separate component is set, and the method is implemented by a control processor, and includes the following:

[0097] S91: The control processor acquires the operation data of the second device.

[0098] S92: The control processor transmits second device operation data to the arithmetic processor via shared memory. Send.

[0099] S93: When arc generation is detected, the control processor performs a turn-off operation.

[0100] S94: The control processor sets the turn-off instruction identifier in the shared memory to a turn-off state By setting it to this state, the arithmetic processor will determine the state of the turn-off instruction identifier. The acquisition of instrument operation data is skipped, and the first instrument operation data is arc processed by the control processor. This is equipment operation data acquired during the period in which the event occurred.

[0101] S95: The control processor freezes the equipment operation data for the arc generation period.

[0102] S96: The control processor enters sleep mode.

[0103] S97: If the restart conditions are met, the control processor will restart.

[0104] S98: The control processor sets the turn-off instruction identifier in the shared memory to a normal state. Determine and restore execution of S91.

[0105] In some selective embodiments, the control processor stores the second device operation data in a shared memory. By storing it in shared memory, the arithmetic processor can acquire second device operation data from shared memory. It is possible.

[0106] In some selective embodiments, the restart condition is a turn-off time that is set to a preset time. This includes whether the length of the shutdown period is met and / or whether restart instruction information is received. .

[0107] It should be explained that the embodiments described in this specific example are specific examples under the concept of the present invention. This is merely an illustrative description of the embodiments, and does not specify the execution order of the steps in each embodiment. The examples provided herein are not limited to those described herein, and in carrying out specific steps, those skilled in the art will actually The execution order of each step can be adjusted based on the situation, for example, S91 and S97 This means that there is no necessary cause-and-effect relationship or sequence of events, and the restart operation of S97 is related to the second device operation of S91. This may be written after obtaining the data.

[0108] To make it easier to understand, the proposed technology in this embodiment uses a dual-processor-based PID control During the process, when the control processor detects the occurrence of an arc, it performs a turn-off operation, and the shared The turn-off instruction identifier in Mori is set to the turn-off state, and the arithmetic processor then... Based on the state of the off instruction identifier, the control processor acquires the following information during the arc generation period. The acquisition of device operation data is skipped, and one CPU writes to the shared memory. Even if area protection occurs, the other CPU can still read the shared data. By using this method, regardless of what tasks both CPUs are performing, data can be transferred from the high-speed memory unit. In the first hour, it is possible to acquire the changing data and operating status of the opponent's CPU, and control the program. To ensure the stability and consistency of data transmission between the separator and the processing processor, and the control processor When the circuit is turned off, the arithmetic processor on the other end still performs unnecessary calculations. This avoids disruptive operation of the entire circuit, and if an arc occurs, the control processor and Effectively ensures data accuracy between the processing unit and the data processor.

[0109] (Example 10) As shown in Figure 14, the embodiment of the present invention further provides a dual-processor device control method. Furthermore, a dual-processor device includes a control processor, an arithmetic processor, and shared memory. A turn-off instruction identifier is set in the shared memory, and this method is implemented by the arithmetic processor. This includes the following:

[0110] S101: Retrieve the status of the turn-off instruction identifier in shared memory.

[0111] S102: If the turn-off indicator identifier is in the turn-off state, the turn-off indicator identifier Based on the state, the acquisition of the first device operation data is skipped, and the first device operation data is controlled This is equipment operation data acquired by the processor during the arc generation period.

[0112] To make it easier to understand, the proposed technology in this embodiment uses a dual-processor-based PID control During the process, when the control processor detects the occurrence of an arc, it performs a turn-off operation, and the shared The turn-off instruction identifier in Mori is set to the turn-off state, and the arithmetic processor then... Based on the state of the off instruction identifier, the control processor acquires the following information during the arc generation period. The acquisition of device operation data is skipped, and one CPU writes to the shared memory. Even if area protection occurs, the other CPU can still read the shared data. By using this method, regardless of what tasks both CPUs are performing, data can be transferred from the high-speed memory unit. In the first hour, data on the opponent's CPU changes or operating status can be obtained, and the control process To ensure the stability and consistency of data transmission between the sasser and the computing processor, and the control processor When the circuit is turned off, the arithmetic processor at the other end still performs unnecessary calculations. This avoids disruptive operation of the entire circuit, and if an arc occurs, the control processor and... Effectively ensures data accuracy between the computer and the processor.

[0113] (Example 11) As an improvement to Example 10, as shown in Figure 15, the embodiment of the present invention uses a dual processor. The system further provides a control method for the equipment, and the dual-processor equipment is a control processor arithmetic processor. The method includes a sasser and shared memory, the shared memory is set with a turn-off instruction identifier, and the method includes , implemented by a computing processor, and including the following:

[0114] S111: If the restart conditions are met, the arithmetic processor restarts and executes S42 again. To recover.

[0115] S112: The arithmetic processor obtains the state of the turn-off instruction identifier in the shared memory. do.

[0116] S113: If the turn-off instruction identifier is in a normal state, the arithmetic processor will share a memo. Obtain the operation data of the first device from R.

[0117] S114: The arithmetic processor performs control parameter calculations based on the operation data of the first device. cormorant.

[0118] S115: The arithmetic processor calculates and obtains from the control processor via shared memory. Send control parameters.

[0119] S116: If the turn-off instruction identifier is in the turn-off state, the arithmetic processor will Based on the state of the turn-off instruction identifier, the acquisition of the first device operation data is skipped, and the first device Operational data is equipment operation data acquired by the control processor during the arc generation period. .

[0120] S117: The processing unit freezes the equipment operation data for the arc generation period.

[0121] S118: If the turn-off instruction identifier is in the turn-off state, the arithmetic processor... Enters a leap state and waits for the restart condition to be triggered.

[0122] To make it easier to understand, the proposed technology in this embodiment uses a dual-processor-based PID control During the process, when the control processor detects the occurrence of an arc, it performs a turn-off operation, and the shared The turn-off instruction identifier in Mori is set to the turn-off state, and the arithmetic processor then... Based on the state of the off instruction identifier, the control processor acquires the following information during the arc generation period. The acquisition of device operation data is skipped, and one CPU writes to the shared memory. Even if area protection occurs, the other CPU can still read the shared data. By using this method, regardless of what tasks both CPUs are performing, data can be transferred from the high-speed memory unit. In the first hour, it is possible to acquire the changing data and operating status of the opponent's CPU, and control the program. To ensure the stability and consistency of data transmission between the separator and the processing processor, and the control processor When the circuit is turned off, the arithmetic processor on the other end still performs unnecessary calculations. This avoids disruptive operation of the entire circuit, and if an arc occurs, the control processor and Effectively ensures data accuracy between the processing unit and the data processor.

[0123] (Example 12) The embodiments of the present invention further provide a dual-processor device, the dual-processor device is It includes a control processor, an arithmetic processor and shared memory, and the shared memory contains turn-off indicators Once an identifier is set, the control processor detects the occurrence of an arc, as shown in Figure 16. , a turn-off instruction module 121 for performing a turn-off operation, By setting the turn-off instruction identifier in shared memory to the turn-off state, the arithmetic process The processor skips the acquisition of the first device operation data based on the state of the turn-off instruction identifier A turn-off state setting module 122 for doing so, where the first device operation data is device operation data acquired during the arc generation period by the control processor, includes the turn-off state setting module 122

[0124] In some optional embodiments, as shown by the dashed-line part in the drawings, the apparatus further includes an operation data acquisition module 123 for acquiring the second device operation data, sending the second device operation data to the arithmetic processor via the shared memory, resuming the acquisition, and by sending the second device operation data to the arithmetic processor via the shared memory, the arithmetic processor acquires the second device operation data from the shared memory based on the state of the turn-off instruction identifier an operation data transmission module 124 for doing so, a first data freezing module 125 for freezing the device operation data during the arc generation period, and a first sleep module 126 for entering the sleep state, a first restart module 127 for restarting when the restart condition is satisfied, a shared identifier setting module 128 for setting the turn-off instruction identifier in the shared memory to the normal state may further be included

[0125] In some optional embodiments, the restart condition includes whether the turn-off time meets the preset length of the turn-off time, and / or whether restart instruction information is received

[0126] As can be understood, in the technical solution according to this embodiment, the PID control based on the dual processor ​​​During the process, when the control processor detects arc generation, it executes a turn-off operation and sets the turn-off instruction identifier in the shared memory to the turn-off state. The arithmetic processor skips obtaining the device operation data acquired by the control processor during the arc generation period based on the state of the turn-off instruction identifier. By using a data sharing mode where, even if area protection occurs, the other CPU can still read the data written by one CPU, both CPUs can obtain the changing data and operating state of the other CPU from the high-speed storage unit at the first time, ensuring the stability and consistency of data transmission between the control processor and the arithmetic processor. When the control processor circuit is turned off, the arithmetic processor at the other end is prevented from performing unnecessary calculations that would cause chaotic operation of the entire circuit. When an arc occurs, the data accuracy between the control processor and the arithmetic processor is effectively ensured. In the shared memory, the turn-off instruction identifier is set to the turn-off state. The arithmetic processor skips obtaining the device operation data acquired by the control processor during the arc generation period based on the state of the turn-off instruction identifier. By using a data sharing mode where, even if area protection occurs, the other CPU can still read the data written by one CPU, both CPUs can obtain the changing data and operating state of the other CPU from the high-speed storage unit at the first time, ensuring the stability and consistency of data transmission between the control processor and the arithmetic processor. When the control processor circuit is turned off, the arithmetic processor at the other end is prevented from performing unnecessary calculations that would cause chaotic operation of the entire circuit. When an arc occurs, the data accuracy between the control processor and the arithmetic processor is effectively ensured. By using a data sharing mode where, even if area protection occurs, the other CPU can still read the data written by one CPU, both CPUs can perform any operation and obtain the changing data and operating state of the other CPU from the high-speed storage unit at the first time, ensuring the stability and consistency of data transmission between the control processor and the arithmetic processor. At the first time, the changing data and operating state of the other CPU can be obtained, ensuring the stability and consistency of data transmission between the control processor and the arithmetic processor. When the control processor circuit is turned off, the arithmetic processor at the other end is prevented from performing unnecessary calculations that would cause chaotic operation of the entire circuit. When an arc occurs, the data accuracy between the control processor and the arithmetic processor is effectively ensured. When the control processor circuit is turned off, the arithmetic processor at the other end is prevented from performing unnecessary calculations that would cause chaotic operation of the entire circuit. When an arc occurs, the data accuracy between the control processor and the arithmetic processor is effectively ensured. When an arc occurs, the chaotic operation of the entire circuit caused by the arithmetic processor at the other end performing unnecessary calculations is avoided, and the data accuracy between the control processor and the arithmetic processor is effectively ensured. When an arc occurs, the data accuracy between the control processor and the arithmetic processor is effectively ensured.

[0127] (Embodiment 13) An embodiment of the present invention further provides a dual-processor device, which includes a control processor, an arithmetic processor, and a shared memory. A turn-off instruction identifier is set in the shared memory. As shown in FIG. 17, the arithmetic processor includes a turn-off identifier acquisition module 131 for acquiring the state of the turn-off instruction identifier in the shared memory, and a turn-off data processing module 132 for skipping obtaining the first device operation data based on the state of the turn-off instruction identifier when the turn-off instruction identifier is in the turn-off state. The first device operation data is acquired by the control processor during the arc generation period. In the shared memory, a turn-off instruction identifier is set. As shown in FIG. 17, the arithmetic processor includes a turn-off identifier acquisition module 131 for acquiring the state of the turn-off instruction identifier in the shared memory, and a turn-off data processing module 132 for skipping obtaining the first device operation data based on the state of the turn-off instruction identifier when the turn-off instruction identifier is in the turn-off state. In the shared memory, the turn-off instruction identifier is set to the turn-off state. The arithmetic processor includes a turn-off identifier acquisition module 131 for acquiring the state of the turn-off instruction identifier in the shared memory, and a turn-off data processing module 132 for skipping obtaining the first device operation data based on the state of the turn-off instruction identifier when the turn-off instruction identifier is in the turn-off state. The first device operation data is acquired by the control processor during the arc generation period. When the turn-off instruction identifier is in the turn-off state, based on the state of the turn-off instruction identifier, the acquisition of the first device operation data is skipped. The first device operation data is acquired by the control processor during the arc generation period. ​​​​It includes a turn-off data processing module 132, which is the device operation data.

[0128] In some selective embodiments, as shown in the dashed lines in the drawings, the device is a tar If the OFF instruction identifier is in a normal state, the operation data of the first device is obtained from the shared memory. After a reboot, the operation to recover the acquisition of the state of the turn-off instruction identifier in shared memory. Data extraction module 133, Control parameter calculation module for calculating control parameters based on the operation data of the first device. Lure 134 and, To send the calculated control parameters to the control processor via shared memory. Control parameter transmission module 135, If the turn-off instruction identifier is in the turn-off state, the second step to enter sleep state is performed. Leap module 1313 and, If the restart conditions are met, the second restart module 137 for restarting is activated, A second data freezing module 138 for freezing equipment operation data during the arc generation period and It also includes.

[0129] To make it easier to understand, the proposed technology in this embodiment uses a dual-processor-based PID control During the process, when the control processor detects the occurrence of an arc, it performs a turn-off operation, and the shared The turn-off instruction identifier in Mori is set to the turn-off state, and the arithmetic processor then... Based on the state of the off instruction identifier, the control processor acquires the following information during the arc generation period. The acquisition of device operation data is skipped, and one CPU writes to the shared memory. Even if area protection occurs, the other CPU can still read the shared data. By using this method, regardless of what tasks both CPUs are performing, data can be transferred from the high-speed memory unit. At the first time, the changing data and operating state of the opponent's CPU can be obtained, and the control program Ensures the stability and consistency of data transmission between the sensor and the arithmetic processor, and when the control processor circuit is turned off, the arithmetic processor at the other end still executes unnecessary operations To avoid the chaotic operation of the entire circuit, and when an arc occurs, effectively ensure the data accuracy between the control processor and the arithmetic processor.

[0130] (Embodiment 14) As shown in FIG. 18, the embodiment of the present invention further provides a dual-processor device, which The dual-processor device includes a shared memory 141, a control processor 142 and an arithmetic processor 143 in the dual-processor device, and a turn-off indicator is set in the shared memory 141.

[0131] To facilitate the reader's understanding, hereinafter, the timing diagrams of FIGS. 19, 20, and 21 are combined to describe the dual-processor device in detail. CPUA is the control processor, CPUB is the arithmetic processor, RAM is the shared memory, FLAG is the turn-off indicator, and In the normal mode, the PID control of the dual-processor device includes the following process: CPUA has not detected an arc and does not change the operation FLAG of CPUA in the RAM. CPUA transmits the data required for PID calculation and writes it into the RAM. CPUB reads the operation FLAG of CPUA in the RAM and determines that it is ENABLE. CPUB reads the RAM, obtains the data and performs PID calculation. CPUB writes the circuit control parameters generated by the calculation into the RAM.​​​​ CPUA reads RAM to obtain parameters and controls circuit operation and power output. ru.

[0132] PID control of a dual-processor device in shared memory mode includes the following steps: At the first timing, CPUA detects arcs and disables the CPUA activation flag in RAM. Rewrite to E, CPUA performs the turn-off output. CPUB reads the activation flag of CPUA in RAM and disables it. I determined that there was, CPUB does not read RAM and does not perform PID calculations at the current timing.

[0133] Furthermore, data will be frozen, and CPUB or dual CPUs will enter a limited sleep mode. It is possible.

[0134] At the Nth timing, if N is an integer > 1, CPUA restarts the control circuit and outputs power. CPUA rewrites the CPUA operation FLAG in RAM, CPUA transmits the data necessary for PID calculation and writes it to RAM. CPUB reads the activation FLAG of CPUA in RAM and confirms that it is ENABLE. I decided that, CPUB reads RAM, retrieves data, and performs PID calculations. The CPUB writes the circuit control parameters generated by the calculations into RAM.

[0135] To make it easier to understand, the proposed technology in this embodiment uses a dual-processor-based PID control During the process, when the control processor detects the occurrence of an arc, it performs a turn-off operation, and the shared The turn-off instruction identifier in Mori is set to the turn-off state, and the arithmetic processor then... Based on the state of the off instruction identifier, the control processor acquires the following information during the arc generation period. The acquisition of device operation data is skipped, and one CPU writes to the shared memory. Even if area protection occurs, the other CPU can still read the shared data. By using this method, regardless of what tasks both CPUs are performing, data can be transferred from the high-speed memory unit. In the first hour, it is possible to acquire the changing data and operating status of the opponent's CPU, and control the program. To ensure the stability and consistency of data transmission between the separator and the processing processor, and the control processor When the circuit is turned off, the arithmetic processor on the other end still performs unnecessary calculations. This avoids disruptive operation of the entire circuit, and if an arc occurs, the control processor and Effectively ensures data accuracy between the processing unit and the data processor.

[0136] (Example 15) A schematic diagram of the dual-processor device according to the embodiments disclosed in this invention is shown in Figure 11. It is the same as, and the device is, When an arc is detected, a control processor 151 (not shown) executes a specified operation. The specified operation involves the acquisition of device operation data by the processor 152 (not shown) which performs the calculations. Operation 1 to stop the operation, and Operation 2 to send a turn-off operation instruction to the arithmetic processor 152. A control processor 151 (not shown) including at least one of the following, The control processor determines the operation policy based on the results generated by the specified operation. An arithmetic processor 152 that ensures 11 obtains accurate control parameters, The results of the specified operation are whether or not equipment operation data was acquired and the turn-off calculation signal. The operation policy includes whether or not to obtain the indication, Method 1 for interrupting the calculation operation of related control parameters, Stop sending the relevant control parameters, once the calculation is complete, to the control processor 151. It includes an arithmetic processor 152 that includes at least one of the methods 2.

[0137] To make it easier to understand, in the technical proposal according to this embodiment, during the control process of a dual-processor device, When the control processor detects an arc, the processor calculates the equipment operation data. It is possible to stop acquiring data and send a turn-off operation instruction to the arithmetic processor. Yes, it is possible. The processing unit will determine whether or not it has acquired the device operation data, or Based on whether or not a turn-off operation instruction has been received, the calculation operation of the relevant control parameters is interrupted. Whether to proceed or not, or to send the relevant control parameters, once the calculation is complete, to the control processor. By deciding whether or not to stop the process, the control processor obtains the precise control parameters. Ensure that the circuit is generated. When the control processor turns off the circuit, The data exchanged between dual processors can maintain good accuracy and PID can be updated in a timely manner. This avoids stopping the calculation and extending the turn-off occasion point, and also avoids data This reduces the need for discarding components, and when one end of the circuit is turned off, the other end continues to function. To avoid disruptive operation of the entire circuit and unless the calculation of the entire PID has not been started, The calculation may be interrupted, or the operation parameters for which the calculation has been completed may not be sent, the instruction, Applicable to handshake or data sharing, when turning off, the data is frozen and control is applied. To ensure the stability and consistency of data transmission between the processor and the control processor, When the sasser circuit is turned off, the arithmetic processor on the other end is still performing unnecessary calculations. This avoids disruptive operation of the entire circuit, and if an arc occurs, the control processor... This effectively ensures data accuracy between the system and the computing processor.

[0138] (Example 16) As an improvement to Example 15, the schematic diagram is the same as in Figure 18, and the implementation disclosed in the present invention Another dual-processor device, as an example, A control processor that detects the occurrence of an arc and executes a specified operation, wherein the specified operation is: Operation 1 stops the acquisition of device operation data by the processor performing the calculations, Includes at least one of the following: operation 2, which sends a turn-off operation instruction to the arithmetic processor. A control processor, The control processor determines the operation policy based on the results generated by the specified operation. 21 is an arithmetic processor that ensures that the specified control parameters are obtained. The results of this operation include whether or not equipment operation data was acquired and whether or not a turn-off calculation instruction was given. The operational policy includes whether or not a profit was made. Method 1 for interrupting the calculation operation of related control parameters, Stop sending the relevant control parameters, once the calculation is complete, to the control processor. Includes an arithmetic processor that includes at least one of Equation 2.

[0139] In some selective embodiments, the control processor is used by the processor to perform calculations on the device. The system stops acquiring operational data and simultaneously performs a turn-off operation.

[0140] One thing to explain is that the method by which the arithmetic control module acquires equipment operation data is control This may also involve the processor spontaneously transmitting device operation data to the arithmetic processor. The processing unit may also read device operation data from the control processor. In the embodiment of the invention, the control processor acquires device operation data from the processor on which calculations are performed. Stopping means the control processor spontaneously sends device operation data to the arithmetic processor. This can be understood as stopping the operation of the arithmetic processor, and the operation of the arithmetic processor's equipment This can be understood as voluntarily ceasing to read the generated data.

[0141] In some selective embodiments, the device is configured such that a turn-off instruction identifier is set in a shared memory In Mori, the state of the turn-off indicator identifier includes the turn-off state and the normal state, The control processor sends a turn-off operation instruction to the arithmetic processor. This performs a turn-off operation and sets the state of the turn-off instruction identifier to the turn-off state. A shared memory containing and retrieves the state of the turn-off instruction identifier from the shared memory, and turn off The system further includes an arithmetic processor that treats the "F" state as a turn-off operation instruction.

[0142] In some selective embodiments, the control processor receives the device movements from the processor being computed. The processing unit retrieves the data via shared memory and then retrieves the device operation data from the shared memory. The system retrieves data and sends control parameters to the control processor via shared memory.

[0143] In some selective embodiments, the control processor directs the arithmetic processor to turn off arithmetic instructions. Sending a message means The control processor sends a pre-turn-off output pre-shakehand to the arithmetic processor. That thing, The processing unit receives the pre-turn-off output pre-shakehand, and the pre-turn-off output Based on the power shake-hand, the associated arithmetic operations are stopped, and the calculations on the received data are performed. After completion, a notification to stop the calculation is sent to the control processor, After the control processor receives the calculation stop notification sent by the arithmetic processor, turn This involves performing the OFF operation.

[0144] In some selective embodiments, when the control processor detects arcing, it transmits When querying for control parameters that have not been sent, the system will respond if there are any control parameters that have not been sent. Stop sending the meter.

[0145] In some selective embodiments, the arithmetic processor is transmitted by the control processor. If instrument operation data has not been acquired, all current control parameter calculations will be stopped.

[0146] In some selective embodiments, the control parameter calculation is performed in the PID calculation stage and digital The process includes sequential analog conversion steps, and the processing processor determines the result of the specified operation. Determining the operating policy is the turn that the processing processor receives from the control processor. After obtaining an off-operation instruction, determine the current progress of the control parameter calculation, and related Equipment operation data has been acquired, and analog-to-digital conversion has started, but PID calculation has also started. If not done, PID calculation and subsequent digital-to-analog conversion will not be performed, and related equipment Instrument operation data was acquired and PID calculation was started, but then digital-to-analog calculation was started. If not, this includes completing the PID calculation.

[0147] In some selective embodiments, the arithmetic processor is transmitted by the control processor. If device operation data is not acquired, or if the processing unit acquires data from shared memory If the turn-off instruction identifier is in the turn-off state, the arithmetic processor will have a limited limit. Enters a loop state.

[0148] In some selective embodiments, the arithmetic processor pre-turn-off output pre-shake After stopping the associated calculation operations based on the state, the calculation processor enters a limited sleep state. Entering that state.

[0149] In some selective embodiments, the shared memory is a turn-off instruction. An identifier is set, and the state of the turn-off instruction identifier includes the turn-off state and the normal state. The control processor enters a limited sleep state after performing the turn-off operation. Your processor will restart if the restart conditions are met, and will turn off the shared memory. The indicator is set to the normal state, and the device operation data to be reacquired is sent via shared memory. Shared memory that recovers and sends to the processing processor, and turnover in shared memory The system further includes an arithmetic processor that recovers the state of the instruction identifier.

[0150] In some selective embodiments, the control processor performs a turn-off operation and then... It enters a certain sleep state. The control processor, if the restart conditions are met, will return the restarted preche to the arithmetic processor. A work hand is sent, and the recovery confirmation message is fed back by the processing processor. After receiving, the device operation data is recovered and calculated by the processor. The acquisition of data was recovered, and the arithmetic processor was sent and restarted by the control processor. Upon receiving a pre-shakehand, the system recovers operations based on the restarted pre-shakehand. Complete the operation and send a recovery confirmation message to the control processor.

[0151] In some selective embodiments, the arithmetic processor enters a limited sleep state before The acquired equipment operation data for the arc generation period is frozen, and the control processor has limitations. Before entering a leap state, the equipment operation data for the arc generation period is frozen.

[0152] To make it easier to understand, in the technical proposal according to this embodiment, during the control process of a dual-processor device, When the control processor detects an arc, the processor calculates the equipment operation data. It is possible to stop acquiring data and send a turn-off operation instruction to the arithmetic processor. The processing unit then determines, based on whether or not it has acquired the device operation data, or The calculation operation of the related control parameters is interrupted based on whether or not an off operation instruction has been received. Whether or not to do so, or to send the relevant control parameters for which calculations have been completed to the control processor. By deciding whether or not to stop, the control processor obtains the precise control parameters. This ensures that arc generation is ensured. When the control processor turns off the circuit, The data exchanged between the A-processors can maintain good accuracy and perform PID operations in a timely manner. Stop the calculation, avoid extending the turn-off occasion point, and discard the data. This reduces the situation where the circuit is discarded, and when one end of the circuit is turned off, the other end is still running. To avoid disruptive operation of the entire circuit and to avoid starting the calculation of the entire PID, The calculation may be interrupted, or the operation parameters that have been completed may not be sent, and the command, Applicable to wakehand or data sharing, when turned off, data is frozen and control is performed. To ensure the stability and consistency of data transmission between the separator and the processing processor, and the control processor When the circuit is turned off, the arithmetic processor on the other end still performs unnecessary calculations. This avoids disruptive operation of the entire circuit, and if an arc occurs, the control processor and Effectively ensures data accuracy between the processing unit and the data processor.

[0153] (Example 17) As shown in Figure 22, the embodiment of the present invention further provides a dual-processor device control method. Furthermore, this method is used in dual-processor devices, and the dual processors are control processors The method includes a processor and an arithmetic processor, and is used in a control processor, and includes the following: nothing.

[0154] S171: When arc generation is detected, the control processor executes the specified operation, and the specified operation This involves operation 1, which stops the acquisition of device operation data by the processing processor, and the calculation processor This includes at least one of the following operations: sending a turn-off operation instruction to the sasser.

[0155] S172: The arithmetic processor determines the operation policy based on the results produced by the specified operation. By making this determination, the control processor ensures that it obtains the correct control parameters, and the specified operation The results of this operation include whether or not equipment operation data was acquired and whether or not a turn-off calculation instruction was given. The operation policy, including whether or not a gain was made, is the one that interrupts the calculation operation of the relevant control parameters. Equation 1 and the transmission of the calculated and associated control parameters to the control processor are stopped. This includes at least one of the following methods:

[0156] In some selective embodiments, when the control processor detects arcing, it transmits When querying for control parameters that have not been sent, the system will respond if there are any control parameters that have not been sent. Stop sending meter data.

[0157] In some selective embodiments, the aforementioned specified operation is performed by the control processor on the process Simultaneously stop the acquisition of equipment operation data by the system and perform the turn-off operation. It also includes.

[0158] In some selective embodiments, the dual-processor device further includes shared memory. The shared memory is set with a turn-off instruction identifier, and the state of the turn-off instruction identifier is, This includes the off state and the normal state, and in the applicable embodiment, the control processor communicates to the arithmetic processor. Sending a turn-off operation instruction means the control processor will perform the turn-off operation and turn By setting the state of the off instruction identifier to the turn-off state, the arithmetic processor will turn off the shared memory The state of the turn-off instruction identifier is obtained, and the turn-off state is treated as a turn-off operation instruction. This includes doing so.

[0159] In some selective embodiments, the control processor uses shared memory to perform calculations. Sends device operation data to the system.

[0160] In some selective embodiments, the control processor directs the arithmetic processor to turn off arithmetic instructions. Sending an indication means the control processor sends a pre-turn-off output pre-shape to the arithmetic processor. After sending a hand and receiving the calculation stop notification sent by the arithmetic processor, turn The operation is performed, and the operation point is determined based on whether or not the processing unit has acquired device operation data. The task is to decide on the rarity.

[0161] In some selective embodiments, the control processor performs a turn-off operation and then... It enters a sleep state if certain conditions are met, and restarts when the restart conditions are met, and in shared memory The turn-off instruction identifier is set to the normal state, and the reacquired device operation data is shared. If the ability to send data to the processing processor via memory is restored, or if the restart conditions are met Then, it sends a restarted pre-shakehand to the arithmetic processor, and the arithmetic processor then... After receiving the feedback recovery confirmation message, the acquisition of device operation data is restored. This restores the acquisition of device operation data by the processing processor.

[0162] To make it easier to understand, in the technical proposal according to this embodiment, during the control process of a dual-processor device, When the control processor detects an arc, the processor calculates the equipment operation data. It is possible to stop acquiring data and send a turn-off operation instruction to the arithmetic processor. The processing unit then determines, based on whether or not it has acquired the device operation data, or The calculation operation of the related control parameters is interrupted based on whether or not an off operation instruction has been received. Whether or not to do so, or to send the relevant control parameters for which calculations have been completed to the control processor. By deciding whether or not to stop, the control processor obtains the precise control parameters. This ensures that arc generation is ensured. When the control processor turns off the circuit, The data exchanged between the A-processors can maintain good accuracy and perform PID operations in a timely manner. Stop the calculation, avoid extending the turn-off occasion point, and discard the data. This reduces the situation where the circuit is discarded, and when one end of the circuit is turned off, the other end is still running. To avoid disruptive operation of the entire circuit and to avoid starting the calculation of the entire PID, The calculation may be interrupted, or the operation parameters that have been completed may not be sent, and the command, Applicable to wakehand or data sharing, when turned off, data is frozen and control is performed. To ensure the stability and consistency of data transmission between the separator and the processing processor, and the control processor When the circuit is turned off, the arithmetic processor on the other end still performs unnecessary calculations. This avoids disruptive operation of the entire circuit, and if an arc occurs, the control processor and Effectively ensures data accuracy between the processing unit and the data processor.

[0163] (Example 18) As shown in Figure 23, the embodiment of the present invention further provides a dual-processor device control method. Furthermore, this method is used in dual-processor devices, and the dual processors are control processors The method includes a sasser and an arithmetic processor, and the method is used in the arithmetic processor and includes the following: .

[0164] S181: The arithmetic processor is responsible for the results that occur after the control processor has performed the specified operation. The specified operation is an operation that stops the acquisition of device operation data by the processor being calculated. At least one of the following: operation 1 and operation 2 which sends a turn-off operation instruction to the arithmetic processor The results generated by the specified operation include whether or not the equipment operation data was acquired and the This includes whether or not a turn-off operation instruction was obtained.

[0165] S182: The arithmetic processor determines the operation policy based on the results produced by the specified operation. By making this decision, the control processor ensures that it obtains the correct control parameters, and the operation point Rishi proposed a method 1 for interrupting the calculation operation of related control parameters, and a method for interrupting the calculation of related parameters once the calculation is complete. Method 2, which stops sending control parameters to the control processor, is less than Each includes one.

[0166] In some selective embodiments, the dual-processor device further includes shared memory. The shared memory is set with a turn-off instruction identifier, and the state of the turn-off instruction identifier is, Including the turn-off state and the normal state, in this embodiment the control processor performs the turn-off operation. After the operation, the state of the turn-off instruction identifier is set to the turn-off state, and the arithmetic processor, The state of the turn-off instruction identifier is retrieved from shared memory, and the turn-off state is used in the turn-off calculation. This will be considered an instruction.

[0167] In some selective embodiments, the arithmetic processor retrieves device operation data from shared memory. The data is retrieved and the control parameters are sent to the control processor via shared memory.

[0168] In some selective embodiments, the control processor outputs a pre-turnoff signal to the arithmetic processor. When a power pre-shakehand is sent, the arithmetic processor pre-turns off the output pre-shakehand. The hand is received, and the relevant arithmetic operations are performed based on the pre-turn-off output pre-shakehand. The process stops, and after completing the calculations on the received data, a notification of calculation stoppage is sent to the control processor. By trusting, the control processor receives the operation stop notification sent by the arithmetic processor. After that, perform the turn-off operation.

[0169] In some selective embodiments, the arithmetic processor controls the control processor's device operation data. If not acquired, all current control parameter calculations will be stopped.

[0170] In some selective embodiments, the control parameter calculation is performed in the PID calculation stage and digital The process includes sequential analog conversion steps, and the processing processor determines the result of the specified operation. Determining the operating policy is the turn that the processing processor receives from the control processor. After obtaining an off-operation instruction, determine the current progress of the control parameter calculation, and related Equipment operation data has been acquired, and analog-to-digital conversion has started, but PID calculation has also started. If not done, PID calculation and subsequent digital-to-analog conversion will not be performed, and related equipment Instrument operation data was acquired and PID calculation was started, but then digital-to-analog calculation was started. If not, this includes completing the PID calculation.

[0171] In some selective embodiments, the arithmetic processor controls the control processor's device operation data. If not acquired, or if the turn-off instruction identifier is acquired by the processing unit from shared memory, When the child is in a turned-off state, the processing unit enters a limited sleep state.

[0172] In some selective embodiments, the arithmetic processor pre-turn-off output pre-shake After stopping the associated calculation operations based on the state, the calculation processor enters a limited sleep state. Entering that state.

[0173] In some selective embodiments, the control processor provides a turn-off instruction in shared memory. The identifier is set to the normal state, and the device operation data to be reacquired is sent via shared memory. The system recovers the data and sends it to the computing processor, which then returns the data to the shared memory. The state of the off instruction identifier is recovered, or the arithmetic processor is controlled by the control processor. After receiving the sent and restarted pre-shake hands, restart the pre-shake Based on the hand, complete preparation for computation recovery and send a recovery confirmation message to the control processor. I believe.

[0174] In some selective embodiments, the arithmetic processor enters a limited sleep state before Then, the equipment operation data acquired during the arc generation period is frozen.

[0175] To make it easier to understand, in the technical proposal according to this embodiment, during the control process of a dual-processor device, When the control processor detects an arc, the processor calculates the equipment operation data. It is possible to stop acquiring data and send a turn-off operation instruction to the arithmetic processor. The processing unit then determines, based on whether or not it has acquired the device operation data, or The calculation operation of the related control parameters is interrupted based on whether or not an off operation instruction has been received. Whether or not to do so, or to send the relevant control parameters for which calculations have been completed to the control processor. By deciding whether or not to stop, the control processor obtains the precise control parameters. This ensures that arc generation is ensured. When the control processor turns off the circuit, The data exchanged between the A-processors can maintain good accuracy and perform PID operations in a timely manner. Stop the calculation, avoid extending the turn-off occasion point, and discard the data. This reduces the situation where the circuit is discarded, and when one end of the circuit is turned off, the other end is still running. To avoid disruptive operation of the entire circuit and to avoid starting the calculation of the entire PID, The calculation may be interrupted, or the operation parameters that have been completed may not be sent, and the command, Applicable to wakehand or data sharing, when turned off, data is frozen and control is performed. To ensure the stability and consistency of data transmission between the separator and the processing processor, and the control processor When the circuit is turned off, the arithmetic processor on the other end still performs unnecessary calculations. This avoids disruptive operation of the entire circuit, and if an arc occurs, the control processor and Effectively ensures data accuracy between the processing unit and the data processor.

[0176] (Example 19) To facilitate the reader's understanding, the following will use specific examples to illustrate the embodiments of the present invention. This document describes a dual processor device and its control method.

[0177] In this embodiment, CPUA is a control processor, and CPUB is an arithmetic processor. Each CPU operates independently, and each is connected to its own control circuit and PID processing unit. Each path is controlled. Instructions (COMMAND / ORDER) are exchanged between the dual CPUs. Shake hands, providing a flag, or sharing data The CPUB is made to perform a PID interrupt operation using an analog method. The entire PID calculation block is analog The three stages are the digital conversion stage, the PID calculation stage, and the digital-to-analog conversion stage, that is They can be divided into DC-PID-DAC.

[0178] The overall PID control flow is as follows:

[0179] At the first timing, CPUA transmits the data necessary for PID calculation to CPUB. CPUB acquires data and performs PID calculations. The CPUA detects the arc and sends a turn-off instruction or rewrite flag. CPUB acquires an instruction or flag and performs calculations at each stage depending on the current state of operation. Decide whether to interrupt, If it is between ADC and PID, the calculation after PID is stopped. If the PID period is before the DAC, the calculation is completed, but the calculation data is not output.

[0180] Or, When the CPUA decides to turn off, it will not transmit any data or information. At the time CPUB acquired the data, it had not yet acquired CPUA's data or information. Alternatively, if updated data or information is not retrieved from shared RAM, all PIDs will not be able to perform the necessary actions. Interrupt the calculation directly.

[0181] At the Nth timing, N is an integer > 1. CPUA restarts the control circuit and outputs power. CPUA transmits the data necessary for PID calculation to CPUB. CPUB acquires data and performs PID calculations.

[0182] Or, CPUA restarts the control circuit and outputs power. CPUA rewrites the CPUA operation FLAG in RAM, CPUA transmits the data necessary for PID calculation and writes it to RAM. CPUB reads the activation FLAG of CPUA in RAM and confirms that it is ENABLE. I decided that, CPUB reads RAM, retrieves data, and performs PID calculations. The CPUB writes the circuit control parameters generated by the calculations into RAM.

[0183] To make it easier to understand, in the technical proposal according to this embodiment, during the control process of a dual-processor device, When the control processor detects an arc, the processor calculates the equipment operation data. It is possible to stop acquiring data and send a turn-off operation instruction to the arithmetic processor. The processing unit then determines, based on whether or not it has acquired the device operation data, or The calculation operation of the related control parameters is interrupted based on whether or not an off operation instruction has been received. Whether or not to do so, or to send the relevant control parameters for which calculations have been completed to the control processor. By deciding whether or not to stop, the control processor obtains the precise control parameters. This ensures that arc generation is ensured. When the control processor turns off the circuit, The data exchanged between the A-processors can maintain good accuracy and perform PID operations in a timely manner. Stop the calculation, avoid extending the turn-off occasion point, and discard the data. This reduces the situation where the circuit is discarded, and when one end of the circuit is turned off, the other end is still running. To avoid disruptive operation of the entire circuit and to avoid starting the calculation of the entire PID, The calculation may be interrupted, or the operation parameters that have been completed may not be sent, and the command, Applicable to wakehand or data sharing, when turned off, data is frozen and control is performed. To ensure the stability and consistency of data transmission between the separator and the processing processor, and the control processor When the circuit is turned off, the arithmetic processor on the other end still performs unnecessary calculations. This avoids disruptive operation of the entire circuit, and if an arc occurs, the control processor and Effectively ensures data accuracy between the processing unit and the data processor.

[0184] (Example 20) Based on the same technical concept, the present embodiment further provides computer equipment, and this Computer equipment includes memory and a processor, and the memory contains computer programs. It is stored, and when the processor executes the computer program, any one of the above 1 The dual-processor device control method described in section [section number] is implemented.

[0185] Here, memory includes flash memory, hard disks, multimedia cards, and car drives. Type memory (e.g., SD or DX memory), magnetic memory, magnetic disks, optical disks The memory includes at least one type of readable storage medium, such as a q. In some embodiments, the memory is Internal storage unit of an OTT video traffic monitoring system, for example, hard drive It may also be a hard disk. In other embodiments, the memory may be a plug-in hard disk, smart Memory card (Smart Media Card, SMC), Secure Digital (S ecure Digital, SD card, flash memory card (Flash C External storage device for OTT video traffic monitoring systems such as ard) That's good too.

[0186] Furthermore, the memory is an internal storage unit of the OTT video traffic monitoring system. The memory may include external storage devices. Application software installed on the system, and OTT video service monitors In addition to storing various data such as the code of the taring program, it also stores the output data It can also be used to temporarily store the output data.

[0187] In some embodiments, the processor stores program code or processing information in memory. To execute data, for example, to run an OTT video traffic monitoring program. Central Processing Unit, Controller, It can be a microcontroller, microprocessor, or other data processing chip. Cut.

[0188] To make it easier to understand, the proposed technology in this embodiment uses a dual-processor-based PID control During the process, when the control processor detects the occurrence of an arc, it performs a turn-off operation, and the shared The turn-off instruction identifier in Mori is set to the turn-off state, and the arithmetic processor then... Based on the state of the off instruction identifier, the control processor acquires the following information during the arc generation period. The acquisition of device operation data is skipped, and one CPU writes to the shared memory. Even if area protection occurs, the other CPU can still read the shared data. By using this method, regardless of what tasks both CPUs are performing, data can be transferred from the high-speed memory unit. In the first hour, it is possible to acquire the changing data and operating status of the opponent's CPU, and control the program. To ensure the stability and consistency of data transmission between the separator and the processing processor, and the control processor When the circuit is turned off, the arithmetic processor on the other end still performs unnecessary calculations. This avoids disruptive operation of the entire circuit, and if an arc occurs, the control processor and Effectively ensures data accuracy between the processing unit and the data processor.

[0189] The embodiments disclosed in the present invention further provide a computer-readable storage medium, and the computer A computer program is stored in a data-readable storage medium, and the computer program When RAM is executed by the processor, the dual-processor device described in the above method embodiment The steps of the control method are executed. The storage medium is volatile or non-volatile computer-readable. It may be a storage medium. Dual processor device control according to the embodiments disclosed in the present invention The method of computer program products involves storing program code in a computer-readable format. The instructions included in the program code, which include a memory medium, are the dual described in the above embodiment of the method. It may be used to perform the steps of the processor device control method, specifically the above The method should be described in the examples provided; no further explanation is given here.

[0190] The embodiments disclosed in this invention further provide computer programs, and this computer When the data program is executed by the processor, one of the methods described in the above embodiment is implemented. The computer program product specifically refers to hardware, software, or related components. This is achieved by a combination of the following methods. In one selective embodiment, the computer The program product is specifically embodied as a computer storage medium, and in other selective embodiments... So, computer program products are specifically software products, for example, software. As a development kit (Software Development Kit, SDK), etc. It will be manifested.

[0191] To ensure understanding, the identical or similar parts in each of the above embodiments should refer to one another. This is possible, and details not described in detail in some embodiments are described in other embodiments. You may refer to the same or similar content.

[0192] In this description of the present invention, terms such as "First," "Second," etc., are used solely for explanatory purposes. This should not be understood as indicating or implying relative importance. In this context, unless otherwise specified, "plural" means at least two.

[0193] Any process or method described in a flowchart or otherwise in this specification A description is one of the executable instructions used to perform a specific logical function or step in a process. Or it may be understood as representing a module, segment, or part containing multiple codes. Often, the scope of preferred embodiments of the present invention includes other realizations, not necessarily in the order shown or discussed. This often involves performing functions basically simultaneously or in reverse order depending on the related functions. The embodiments of this invention should be understood by those skilled in the art in which the present invention relates.

[0194] It should be understood that each part of the present invention is hardware, software, firmware This may be achieved by A or a combination thereof. The program or method is software stored in memory and executed by an appropriate instruction execution system. This may be implemented by wearables or firmware. For example, it may be implemented in hardware. In this case, as in other embodiments, logic gates for realizing logical functions for data signals. Discrete logic circuits with circuits, application-specific integrated circuits with appropriate combinational logic gates. Circuits, programmable gate arrays (PGAs), field-programmable gate arrays This can be implemented using any or a combination of technologies known in this field, such as FPGAs. It is possible.

[0195] Those skilled in the art will be able to implement all or part of the steps included in the above embodiment. The program can instruct the related hardware to complete the process, and the program The program may be stored in a computer-readable storage medium and the program may be executed. Sometimes, it can be understood that the method may include one or a combination of the steps of the embodiment.

[0196] Furthermore, even if each functional unit in each embodiment of the present invention is integrated into a single processor, Often, each unit may exist physically on its own, or two or more units may be in a single module. It may be integrated into the module. The above integrated module is implemented in hardware form. The integrated module may be implemented in the form of a software function module. The file is implemented in the form of a software function module and sold or used as an independent product. If used, it may be stored on a computer-readable storage medium.

[0197] The above storage medium may be read-only memory, magnetic disk, optical disk, etc. stomach.

[0198] In this specification, the terms "one embodiment," "several embodiments," "examples," and "specific examples" are used. Descriptions that refer to terms such as "example" or "several examples" should refer to the relevant examples or embodiments. The specific features, structure, materials, or properties described are at least one embodiment or example of the present invention. This means that it is included in. In this specification, the schematic representation of the above terms does not necessarily mean the same This does not refer to the same embodiment or example. Furthermore, it does not refer to the specific features, structure, materials or characteristics described. The properties can be combined in an appropriate manner in any one or more embodiments or examples. Cut.

[0199] The embodiments of the present invention have been described above, but to ensure that this is understood, the above embodiments are illustrative examples. This invention is not limited to the present invention, and those skilled in the art can modify the above embodiments within the scope of the present invention. Further modifications, alterations, substitutions, and transformations can be performed.

Claims

1. A dual-processor device control method, The dual processor mentioned above includes a control processor and an arithmetic processor. The above method is implemented by the control processor, When arc generation is detected, the arithmetic processor outputs a pre-turn-off pre-shake-handle By sending a signal, the arithmetic processor performs the pre-turn-off output pre-shakehand The steps include stopping the associated arithmetic operations based on the above, Receiving a calculation stop notification transmitted by the aforementioned calculation processor, A stop notification is issued when the arithmetic processor receives the pre-turn-off output pre-shakehand. Then, there is the step that is performed after the calculation of the received data has been completed, A dual processor characterized by including the step of performing a turn-off operation. Equipment control method.

2. The aforementioned method, If the restart conditions are met, the restarted pre-shakehand is sent to the arithmetic processor. By doing so, the arithmetic processor performs based on the restarted pre-shakehand. Steps to restore financial reserves, After receiving the recovery confirmation message fed back by the aforementioned processing processor, To recover the acquisition of device operation data and transmit the device operation data to the processing processor. A step to recover, wherein the recovery confirmation message indicates that the arithmetic processor is performing calculations A request characterized by further including a step that is sent after the intention has been completed. A dual-processor device control method as described in Item 1.

3. Before sending the restarted pre-shakehand to the aforementioned processing unit, The process further includes determining whether the arithmetic processor is in a sleep state, Sending a restarted pre-shakehand to the aforementioned arithmetic processor means that the arithmetic processor If the processor is in sleep mode, the restarted preshake function is sent to the arithmetic processor. The dual-processor device according to claim 2, characterized in that it transmits a signal. Control method.

4. Before sending the restarted pre-shakehand to the aforementioned processing unit, If the aforementioned processing processor is not in sleep mode, the device operation data is directly acquired, The further step is to transmit the device operation data to the arithmetic processor. The dual-processor device control method according to claim 3.

5. The aforementioned restart conditions are: Whether the turn-off time meets the predetermined turn-off time length, The present invention, characterized in that it includes and / or whether or not to receive restart instruction information. A dual-processor device control method.

6. The system is characterized by further including a step of entering a sleep state after performing a turn-off operation. The dual-processor device control method according to claim 5.

7. Before entering sleep mode, The method further includes the step of freezing equipment operation data during the arc generation period. A dual-processor device control method according to claim 6, characterized by the above.

8. A control processor for a dual-processor device, When arc generation is detected, the processing unit outputs a pre-turn-off output pre-shakehand. By transmitting, the arithmetic processor based on the pre-turn-off output pre-shakehand A pre-turn-off instruction module for stopping related calculation operations, Pre-turn-off operation for receiving the calculation stop notification sent by the aforementioned processing processor A row module, wherein the calculation stop notification is when the calculation processor pre-turns off After receiving the output pre-shakehand, the output is sent after completing calculations on the received data. The pre-turn-off execution module and A turn-off module for performing a turn-off operation, characterized in that it includes A control processor for dual-processor devices.

9. A dual-processor device control method, The dual processor mentioned above includes a control processor and an arithmetic processor. The above method is implemented by a computing processor, The control processor receives the pre-turnoff output pre-shakehand transmitted by the control processor. The steps, The steps include: completing the calculations on the received data and then stopping the associated calculation operations; By sending a calculation stop notification to the control processor, the control processor stops the calculation The invention is characterized by including the step of performing a turn-off operation after receiving a stop notification. A dual-processor device control method.

10. The control processor receives the pre-shake hand that has been transmitted and restarted. Step and, Steps to complete preparation for recovery of operations based on the restarted pre-shakehand and, By sending a recovery confirmation message to the control processor, the control processor The steps include: recovering the acquisition of equipment operation data based on the recovery confirmation message, The steps include receiving the device operation data transmitted by the control processor, and The dual-processor device control method according to claim 9, characterized in that it includes the above.

11. After sending a notification to the control processor that the calculation has stopped, the method enters a sleep state. Dual processor device according to claim 9 or 10, further comprising the above Your method.

12. Before entering sleep mode, The aforementioned method, The method further includes the step of freezing equipment operation data during the arc generation period. The dual-processor device control method according to claim 11.

13. A computing processor for a dual-processor device, The control processor received a pre-turn-off output pre-shakehand. The pre-turn-off instruction receiving module, After completing calculations on the received data, the calculation stop function is used to stop the associated calculation operations. Control module and By sending a calculation stop notification to the control processor, the control processor stops the calculation A stop notification module for performing a turn-off operation after receiving a stop notification, A computing processor for a dual-processor device, characterized by including the following:

14. Dual-processor device, A control processor for a dual-processor device as described in claim 8 and as described in claim 13 A dual processor, characterized by including an arithmetic processor for a dual-processor device. Processor device.

15. A dual-processor device control method, The dual-processor device includes a control processor, an arithmetic processor, and shared memory. Furthermore, a turn-off instruction identifier is set in the shared memory. The above method is implemented by the control processor, Upon detecting the occurrence of an arc, the step of performing a turn-off operation, By setting the turn-off instruction identifier in the shared memory to the turn-off state The arithmetic processor generates first device operation data based on the state of the turn-off instruction identifier. A step of skipping the acquisition of the first device operation data, wherein the control processor This includes a step which is equipment operation data acquired during the arc generation period by the system, and A distinctive feature is the dual-processor device control method.

16. Before detecting the occurrence of an arc, The aforementioned method, Step 2: Acquire device operation data, The second device operation data is transmitted to the arithmetic processor via the shared memory. Dual processor device according to claim 15, further comprising a , Your method.

17. The second device operation data is transmitted to the arithmetic processor via the shared memory. The top is, In order for the arithmetic processor to acquire the second device operation data from the shared memory The method is characterized by including the step of storing the operation data of the second device in the shared memory. The dual-processor device control method according to claim 16.

18. After performing the turn-off operation, The method further includes a step of entering a sleep state, characterized in that 17 A dual-processor device control method described above.

19. The aforementioned method, If the restart conditions are met, the steps to restart are as follows: The steps include setting the turn-off instruction identifier in the shared memory to a normal state, The steps include: recovering the acquisition of the second device operation data, The operation data of the second device is transmitted to the arithmetic processor via the shared memory. By recovering the state of the turn-off instruction identifier, the arithmetic processor will recover the state of the turn-off instruction identifier. The further step includes obtaining the operation data of the second device from the shared memory. A dual-processor device control method as described in claim 18.

20. The aforementioned restart conditions are: Whether the turn-off time meets the predetermined turn-off time length, and / or, the feature of 19, which includes whether or not to receive restart instruction information. The dual-processor device control method described.

21. Before entering sleep mode, The method further includes the step of freezing equipment operation data during the arc generation period. A dual-processor device control method according to claim 20, characterized by the above.

22. Dual-processor device, The dual-processor device includes a control processor, an arithmetic processor, and shared memory. Furthermore, a turn-off instruction identifier is set in the shared memory. The control processor is When an arc is detected, the turn-off instruction module is activated to perform the turn-off operation. Ru and, Set the turn-off instruction identifier in the shared memory to the turn-off state. Then, the arithmetic processor calculates the first device operation date based on the state of the turn-off instruction identifier. A turn-off state setting module for skipping the acquisition of the first device The operation data is equipment operation data acquired by the control processor during the arc generation period. A dual-processor device characterized by including a turn-off state setting module. 。

23. A dual-processor device control method, The dual-processor device includes a control processor, an arithmetic processor, and shared memory. The shared memory is set with a turn-off instruction identifier. The above method is implemented by the arithmetic processor, The steps include: obtaining the state of the turn-off instruction identifier in the shared memory; If the turn-off instruction identifier is in the turn-off state, the turn-off instruction identifier This involves skipping the acquisition of first device operation data based on the state, and the first device The operation data is equipment operation data acquired by the control processor during the arc generation period. A dual-processor device control method characterized by including the step of

24. If the turn-off instruction identifier is in a normal state, the first device operation data is obtained from the shared memory. Steps to obtain data, A step of calculating control parameters based on the operation data of the first device, The calculated control parameters are transmitted to the control processor via the shared memory. The dual process according to claim 23 further includes the step of doing the following Control method for safety equipment.

25. If the turn-off instruction identifier is in the turn-off state, enter the sleep state. The dual processor device control method according to claim 24, further comprising:

26. Before obtaining the state of the turn-off instruction identifier in the shared memory, The aforementioned method, If the restart conditions are met, the process will further include a step to restart, The step of obtaining the state of the turn-off instruction identifier in the shared memory is shared This is a step to recover the state of the turn-off instruction identifier in memory. A dual-processor device control method as described in claim 24.

27. Before entering sleep mode, The method further includes the step of freezing equipment operation data during the arc generation period. A dual-processor device control method according to claim 25, characterized by the above.

28. Dual-processor device, It includes a control processor, an arithmetic processor and a shared memory, and the shared memory contains turn-on A directive identifier is set. The aforementioned processing processor is To obtain the state of the turn-off instruction identifier in the shared memory, turn-off A module for obtaining a f identifier, If the turn-off instruction identifier is in the turn-off state, then the turn-off instruction identifier Turn-off data processing to skip the acquisition of first device operation data based on the state. The module is configured such that the first device operation data is generated by the control processor. This includes a turn-off data processing module, which is equipment operation data acquired during the period, A dual-processor device characterized by [features].

29. Dual-processor device, Shared memory, control processor according to claim 22, and arithmetic processor according to claim 28 The system includes a setter, and the shared memory is characterized in that a turn-off instruction identifier is set in it. A dual-processor device.

30. A computer device comprising a processor, memory and bus, wherein the memory contains the The processor stores machine-readable instructions that it can execute, and the computer device executes them. When this happens, the processor and the memory communicate via the bus, and the machine-readable instruction is processed before When executed by the processor, claims 1-7, 9-12, 15-21, or 23-27 The dual processor device control method described in any one of the following items is performed. Computer equipment.

31. A computer-readable storage medium, wherein the computer-readable storage medium contains a computer A program is stored, and the computer program is executed by the processor. Then, the du A computer-readable storage medium characterized by executing an A-processor device control method.

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