Information processing device, quantum computer system, information processing method and program

Abstract

To improve the reliability of quantum operations performed by quantum computers. [Solution] The information processing device generates quantum circuit coupling information based on first physical circuit information, and generates a combinatorial optimization problem and constraints based on topology information, quantum circuit coupling information, and calibration data. Based on the optimal solution among one or more solutions of the combinatorial optimization problem that satisfies the constraints, the information processing device generates second physical circuit information representing a second physical quantum circuit obtained by updating the first physical quantum circuit.

Description

[Technical Field]

[0001] Embodiments of the present invention relate to an information processing apparatus, a quantum computer system, an information processing method, and a program. [Background technology]

[0002] A quantum computer is a next-generation computer that processes information using quantum bits (qubits). Conventional computers represent information using binary code, consisting of 0s and 1s. In contrast, quantum computers utilize the properties of quantum mechanics, such as "superposition," where a quantum bit can simultaneously exist in both 0 and 1 states, and "entanglement," where multiple quantum bits interact with each other. As a result, quantum computers can process complex problems that are difficult for conventional computers to solve at high speed.

[0003] A fault-tolerant quantum computer (FTQC) is a quantum computer that corrects errors that occur during quantum computation as it proceeds. Because qubits are extremely delicate, they are susceptible to external influences and prone to errors. FTQCs can achieve stable computation by correcting such errors in qubits.

[0004] However, FTQC has several challenges. First, FTQC requires a large number of qubits for error correction, resulting in a massive architecture. Second, the error correction process itself is complex, necessitating the development of efficient error correction algorithms.

[0005] In response to these challenges of FTQC, NISQ (Noisy Intermediate-Scale Quantum) devices have recently attracted attention. NISQ devices are medium-scale quantum computers with tens to hundreds of qubits, and while they do not perform complete error correction, they possess a certain level of computing power. NISQ devices have the potential to surpass conventional computers in certain fields such as quantum chemical calculations and optimization problems.

[0006] However, even NISQ devices are not immune to the effects of quantum noise, which leads to a decrease in computational accuracy and the collapse of quantum states. Therefore, NISQ devices must also reduce qubit noise to maximize their performance.

[0007] Device noise can be broadly categorized into two types: memory errors due to qubit decoherence and gate errors due to inaccuracies in gate operations. Memory errors due to qubit decoherence are more pronounced the longer the quantum program execution time. Gate errors due to inaccuracies in gate operations become more significant as the number of gates in the quantum program increases, particularly as the number of 2-qubit gates that operate pairs of qubits increases.

[0008] A quantum compiler is a process or program that converts a quantum program (or logic quantum circuit), which abstractly describes quantum operations, into physical circuit information representing the physical quantum circuit that will actually be executed by a quantum computer. The quantum compiler converts the quantum program into physical circuit information in a way that minimizes the impact of noise-induced errors while satisfying the inherent architectural constraints of the quantum computer, i.e., by using the fewest possible number of qubits, gates, and depth (critical path length). Generally, there is a trade-off relationship between the number of target qubits, gates, and depth used in quantum operations. Therefore, the quantum compiler must generate physical circuit information that represents a well-balanced and optimized physical quantum circuit while satisfying the architectural constraints of the quantum computer.

[0009] Qubit mapping is the process of mapping target qubits used in quantum operations, represented by quantum programs, to actual qubits in a way that satisfies the coupling constraints of a quantum computer, while also finding efficient mapping relationships. In many cases, qubit mapping is implemented as part of the quantum compiler's processing.

[0010] In the field of quantum computing, a parameter called fidelity is sometimes used. Fidelity represents the degree to which a gate operation performed on a qubit is executed as intended, i.e., the degree to which it matches the ideal behavior of the qubit. Fidelity is a value obtained by subtracting the error rate from 1. Generally, fidelity is expressed in the range of 0.0 to 1.0. Also, generally, fidelity does not reach the ideal behavior, i.e., it does not reach 1.0.

[0011] Fidelity varies from qubit to qubit and from gate to gate. Therefore, qubit mapping is thought to enable quantum computers to perform highly reliable quantum operations by associating target qubits represented by quantum programs with qubits of higher fidelity.

[0012] However, current quantum computers are heavily affected by gate errors caused by two-qubit gates. Quantum compilers often perform transformations to minimize the total number of gates or the number of gates on the critical path in order to reduce the impact of these gate errors. Therefore, it is difficult for quantum compilers to perform optimizations that take fidelity into account.

[0013] Even if a quantum program could be converted into a quantum circuit consisting of fewer 2-qubit gates and high-fidelity qubits, a quantum compiler must still perform qubit mapping to satisfy the coupling constraints of a quantum computer. For this reason, quantum compilers may insert many SWAP gates, which have the function of exchanging quantum states between two qubits, into the quantum circuit to satisfy the coupling constraints of a quantum computer. In such cases, even if the quantum compiler is able to generate a quantum physical circuit consisting of fewer 2-qubit gates and high-fidelity qubits in the initial stage, it may ultimately generate a physical quantum circuit with many 2-qubit gates or a physical quantum circuit with low-fidelity qubits associated with it during qubit mapping.

[0014] Furthermore, many current quantum computers rely on cloud access. When using a quantum computer that relies on cloud access, there is a waiting period, such as queuing time, before the physical quantum circuit generated by the user's computer is actually executed by the quantum computer. Fidelity changes depending on the noise level of the quantum computer, among other factors. In other words, fidelity changes over time. Therefore, even if a physical quantum circuit generated by a user is in an ideal state with high fidelity at the time of generation, it may deviate from the ideal state during execution. [Prior art documents] [Patent Documents]

[0015] [Patent Document 1] Japanese Patent Publication No. 2019-145010 [Patent Document 2] Japanese Patent Publication No. 2019-159566 [Patent Document 3] Japanese Patent Publication No. 2021-043667 [Patent Document 4] Japanese Patent Publication No. 2021-043589 [Non-patent literature]

[0016] [Non-Patent Document 1] Paul D. Nation and Matthew Treinish, “Suppressing Quantum Circuit Errors Due to System Variability”, PRX QUANTUM 4, 010327, (March, 2023) , DOI: 10.1103 / PRXQuantum.4.010327 [Non-Patent Document 2] Hayato Goto, Kosuke Tatsumura and Alexander R. Dixon, “Combinatorial optimization by simulating adiabatic bifurcations in nonlinear Hamiltonian systems,” Science Advances 5, eaav2372, 2019 [Non-Patent Document 3] Hayato Goto, Kotaro Endo, Masaru Suzuki, Yoshisato Sakai, Taro Kanao, Yohei Hamakawa, Ryo Hidaka, Masaya Yamasaki and Kosuke Tatsumura, “High-performance combinatorial optimization based on classical mechanics”, Science Advances 7, eabe7953, 2021. [Overview of the project] [Problems that the invention aims to solve]

[0017] The problem that this invention aims to solve is to improve the reliability of quantum operations performed by quantum computers. [Means for solving the problem]

[0018] The information processing apparatus according to the embodiment includes a processing unit. The processing unit generates quantum circuit coupling information representing the coupling relationship of a pair of target qubits that perform a two-qubit gate operation in two or more target qubits included in the first physical quantum circuit, based on first physical circuit information representing a first physical quantum circuit that causes a quantum computer including a plurality of qubits to perform quantum operations. The processing unit obtains calibration data for at least one qubit among the plurality of qubits and at least one pair of a plurality of pairs of qubits capable of performing a two-qubit gate operation in the plurality of qubits, including an error rate representing the degree to which an error occurs in the gate operation or a fidelity representing the degree to which the gate operation is executed as intended. Based on topology information representing the coupling relationship that enables the two-qubit gate operation in the plurality of qubits, the quantum circuit coupling information, and the calibration data, the processing unit generates a combinatorial optimization problem and constraints. The processing unit selects the optimal solution that satisfies the constraints from among the one or more solutions obtained by solving the combinatorial optimization problem. The processing unit generates second physical circuit information representing a second physical quantum circuit in which the correspondence between the plurality of qubits in the first physical quantum circuit and the two or more target qubits has been updated based on the optimal solution. [Brief explanation of the drawing]

[0019] [Figure 1] A diagram illustrating a model of the Ising problem. [Figure 2] A diagram showing the internal variables used by the simulated branching algorithm. [Figure 3] A flowchart illustrating the processing flow of a simulated branching machine. [Figure 4] A diagram showing the first example of a system configuration for solving combinatorial optimization problems. [Figure 5] A diagram showing the configuration of a problem-solving system equipped with a simulated branching machine. [Figure 6] A diagram showing the configuration of a quantum computer system according to the first embodiment. [Figure 7] A diagram illustrating the remapping process performed by a remapping device. [Figure 8] A diagram showing the functional configuration of the remapping device. [Figure 9] A diagram showing an example of a topology graph. [Figure 10] A diagram showing an example of a first physical quantum circuit. [Figure 11] Figure 10 shows an example of a quantum circuit graph based on the first physical quantum circuit. [Figure 12] A diagram representing node weights. [Figure 13] A diagram representing edge weights. [Figure 14] A diagram showing the error rate of a single-bit gate operation. [Figure 15] A diagram showing the error rate for 2-qubit gate operations. [Figure 16] A diagram showing the correspondence between quantum circuit graphs and topology graphs. [Figure 17] A diagram illustrating multiple decision variables. [Figure 18] A diagram showing the total cost function. [Figure 19] A flowchart illustrating the processing flow of a quantum computer system. [Figure 20] A diagram showing the configuration of a quantum computer system according to the second embodiment. [Figure 21] A diagram showing the configuration of a quantum computer system according to the third embodiment. [Figure 22] A diagram showing the configuration of a quantum computer system according to the fourth embodiment. [Figure 23] A diagram showing an example of a computer hardware configuration. [Modes for carrying out the invention]

[0020] In each embodiment described below, the quantum computer system 10 performs a remapping process that converts first physical circuit information, which represents a first physical quantum circuit generated by quantum compilation, into second physical circuit information, which represents a second physical quantum circuit that performs the same quantum operation using qubits with fewer errors, i.e., high fidelity. In the remapping process, the quantum computer system 10 generates a combinatorial optimization problem and has an optimization solver find the solution to the combinatorial optimization problem.

[0021] (Premise) First, we will explain the terminology and techniques related to combinatorial optimization problems, which are prerequisites for the remapping process.

[0022] A combinatorial optimization problem is a problem in which an objective function is defined with multiple decision variables representing the state of the system being optimized, and the goal is to find the combination of values ​​for these decision variables that minimizes or maximizes the defined objective function. The state of the system represented by the multiple decision variables is called a solution. In a combinatorial optimization problem, the number of possible solution states increases exponentially as the number of decision variables increases. This increase in the number of possible solution states is called a combinatorial explosion. Combinatorial optimization, which involves selecting the optimal solution from all candidate solutions, is known to be a computationally difficult problem. Performing large-scale combinatorial optimization in a short amount of time remains a challenging task.

[0023] An objective function is a function of order one or higher with respect to multiple decision variables, and it takes multiple decision variables as arguments. For example, an objective function can be expressed as a polynomial summing multiple terms. Each of the multiple terms is a function that multiplies one or more (but not exceeding a predetermined number) of the multiple decision variables by a coefficient. The coefficient in each of the multiple terms is a real number. In this case, each of the multiple terms that make up the objective function is expressed by multiplying one or more of the multiple decision variables by any one of the coefficients.

[0024] Each of the multiple decision variables is a discrete value. Furthermore, the discrete values ​​may represent 0 or 1, or they may represent Ising spins of -1 or +1. Also, some of the multiple decision variables included in the objective function may be discrete values, while others may be continuous values.

[0025] The set of all possible solutions for a system being optimized in combinatorially is called the solution space. In a problem of minimizing an objective function, the solution that minimizes the value of the objective function is called the exact solution, and a solution that brings the value of the objective function close to the minimum is called a good solution. Similarly, in a problem of maximizing an objective function, the solution that maximizes the value of the objective function is called the exact solution, and a solution that brings the value of the objective function close to the maximum is called a good solution.

[0026] An optimization solver is a device that, given a combinatorial optimization problem, seeks to solve it. An optimization solver may be implemented using a dedicated device or semiconductor circuit, or it may be implemented by a processor executing a program.

[0027] Furthermore, combinatorial optimization problems may include constraints. Constraints represent conditions that the solution must satisfy. Constraints are one or more constraint equations expressed using some of the decision variables included in the objective function. Constraint equations may be equalities or inequalities.

[0028] When a combinatorial optimization problem includes constraints, the objective function may also include a penalty function. For example, in a problem of minimizing the objective function, the penalty function is larger when the constraints are not met than when they are met. For instance, in a problem of minimizing the objective function, the penalty function is 0 when the constraints are met and greater than 0 when they are not. Conversely, in a problem of maximizing the objective function, the penalty function is smaller when the constraints are not met than when they are met. For example, in a problem of maximizing the objective function, the penalty function is 0 when the constraints are not met and greater than 0 when the constraints are met.

[0029] Even if an optimization solver cannot find a solution to a combinatorial optimization problem that includes constraints, it can find a solution that is identical or approximates the solution to the combinatorial optimization problem with constraints by solving a problem in which the objective function includes a penalty function.

[0030] An exact solution method is a method for solving a combinatorial optimization problem that finds an exact solution that gives the minimum or maximum value of the objective function, and it is guaranteed that the solution is an exact solution.

[0031] A heuristic solution is a method for solving combinatorial optimization problems that seeks either an exact solution that gives the minimum or maximum value of the objective function, or a good solution that gives a value close to the minimum or maximum value of the objective function. Heuristic solutions are also called heuristic solutions. Heuristic solutions do not guarantee the accuracy of the solution, that is, an indicator of how close the solution is to the minimum or maximum value of the objective function. Heuristic solutions can produce solutions with practically significant accuracy in a shorter time than exact solutions.

[0032] The computational complexity of solving a combinatorial optimization problem is the number of operations required to obtain the solution, such as the number of multiply-accumulate operations. The time required to solve a combinatorial optimization problem depends not only on the computational complexity but also on the configuration of the computer that performs the operations. For example, the solving time decreases as the degree of parallelism and operating frequency of the computer increase.

[0033] The QUBO (Quadratic Unconstrained Binary Optimization) problem is an unconstrained quadratic optimization problem where the decision variable is binary. In a QUBO problem, each of the multiple terms in the objective function can be expressed as a linear or quadratic expression of the decision variable.

[0034] The objective function of the QUBO problem is given by H in equation (1). total_QUBO It is represented by [this].

[0035]

Number

[0036] N is an integer greater than or equal to 2 and represents the number of decision variables. i and j represent any integers from 1 to N. b i is 0 or 1 and represents the i-th decision variable among the N decision variables. b j is 0 or 1 and represents the j-th decision variable among the N decision variables. Q ij represents the coefficient in the i-th row and j-th column of the N×N coefficient matrix (Q). Note that Q ij = Q ji is true. Q ii is the coefficient contained in the i-th row and i-th column of the coefficient matrix (Q), and is the coefficient multiplied by the linear term of the i-th decision variable. Q ii is called the bias coefficient.

[0037] Figure 1 is a diagram showing a model of the Ising problem. The Ising problem is a problem of searching for the ground state of the Ising model. The Ising problem is one of the QUBO problems. The decision variables of the Ising problem represent discrete variables of -1 or +1.

[0038] The objective function of the Ising problem is represented by H in Equation (2) total_Ising .

[0039]

Number

[0040] N is an integer greater than or equal to 2 and represents the number of decision variables. i and j represent any integers from 1 to N. s i is -1 or +1 and represents the i-th decision variable among the N decision variables. s j is -1 or +1 and represents the j-th decision variable among the N decision variables. J ij represents the coefficient in the i-th row and j-th column of the N×N coefficient matrix (J). Note that J ij = J ji is true. h ih is the coefficient multiplied by the linear term of the i-th decision variable. i This is called the bias coefficient.

[0041] The Ising problem corresponds to the problem of searching for the ground state of the Ising model, which is one of the magnetic material models in statistical mechanics. Therefore, s i This is sometimes called the spin variable. Also, N, which is the number of decision variables, is sometimes called the spin number. total_Ising This is sometimes called Ising energy. total_Ising N s that have the minimum value i The vector represented by this is sometimes called the ground state (ground spin configuration).

[0042] The objective functions of the QUBO problem and the Ising problem differ only in the value of the constant. Therefore, the QUBO problem and the Ising problem are identical as combinatorial optimization problems. In other words, the QUBO problem and the Ising problem can be converted to each other. For example, the Ising problem and the QUBO problem can be converted to each other by equations (3-1), (3-2), (3-3), and (3-4).

[0043]

number

[0044] The QUBO problem and the Ising problem are known to be NP-complete. That is, many NP-hard problems can be transformed into either a QUBO problem or an Ising problem in polynomial time. Therefore, many practical combinatorial optimization problems can be transformed into either a QUBO problem or an Ising problem.

[0045] An Ising machine is a device that solves the Ising problem. Many Ising machines solve the Ising problem using heuristic methods. Various Ising machines based on principles from fields such as electronics, optics, quantum mechanics, and statistical mechanics have been proposed. Many Ising machines can produce an exact solution or a good solution in a short amount of time.

[0046] Simulated bifurcation algorithms are algorithms for solving combinatorial optimization problems. Simulated bifurcation algorithms are heuristic solution algorithms.

[0047] Simulated bifurcation algorithms are shown, for example, in Non-Patent Documents 2-3 and Patent Documents 1-4. Because simulated bifurcation algorithms were discovered inspired by quantum mechanical optimization methods based on the quantum adiabatic theorem, they are also called quantum-inspired algorithms. Simulated bifurcation algorithms can solve combinatorial optimization problems where the objective function is a quadratic function of multiple decision variables. Simulated bifurcation algorithms can also solve combinatorial optimization problems where the objective function is a function of order cubic or higher, i.e., HUBO (Higher Order Binary Optimization) problems. For example, a simulated bifurcation algorithm for solving HUBO problems is shown in Patent Document 3. Furthermore, simulated bifurcation algorithms can also solve combinatorial optimization problems where some or all of the multiple decision variables include continuous variables. A simulated bifurcation algorithm for solving combinatorial optimization problems where some or all of the multiple decision variables include continuous variables is shown in Patent Document 4.

[0048] A simulated branching machine is a computing device that performs processing according to a simulated branching algorithm. A simulated branching machine that solves the QUBO problem or the Ising problem is an example of an Ising machine. In this embodiment, the simulated branching machine solves the Ising problem.

[0049] Figure 2 shows the internal variables used by the simulated branching algorithm.

[0050] The simulated branching algorithm has N decision variables (s1~s N When solving a combinatorial optimization problem in which the objective function is expressed using ), the internal variables are N position variables (x1~x N) and N momentum variables (y1~y N The simulated branching algorithm uses 2 × N internal variables.

[0051] N position variables (x i ) consists of N decision variables (s i ) corresponds one-to-one with the i-th position variable (x) among the N position variables. i ) is the i-th decision variable (s) among the N decision variables. i ) corresponds to N momentum variables (y i ) consists of N decision variables (s i It corresponds one-to-one with the i-th momentum variable (y) among the N momentum variables. i ) is the i-th decision variable (s) among the N decision variables. i ) corresponds to.

[0052] Figure 3 is a flowchart showing the processing flow of a simulated branching machine. The simulated branching machine executes processing according to the simulated branching algorithm in the flow shown in Figure 3.

[0053] First, in S11, the simulated branching machine obtains the Ising problem. Specifically, the simulated branching machine obtains J, which is a matrix containing N × N coefficients, and h, which contains N bias coefficients.

[0054] Next, in S12, the simulated branching machine has 2 × N internal variables, i.e., N position variables (x1~x N ) and N momentum variables (y1~y N Initialize the N position variables (x1~x N Initial values ​​of ) and N momentum variables (y1~y N The initial values ​​of both or either of the following can be obtained from an external source. In addition, the simulated branching machine has N position variables (x1~x N Initial values ​​of ) and N momentum variables (y1~y NThe initial value of ) may be generated by a random number generation circuit or set to a predetermined value. Note that since the simulated branching machine is a heuristic, even for the same problem, the N position variables (x1~x N Initial values ​​of ) and N momentum variables (y1~y N If at least one of the initial values ​​of ) is different, it may output different good solutions.

[0055] Next, the simulated branching machine repeats the process from S14 to S16 a predetermined number of times (loop processing between S13 and S17). The process from S14 to S16 involves N position variables (x1~x N A matrix operation that performs matrix multiplication of ) and a matrix containing coefficients in N rows × N columns, and N position variables (x1~x N ) and N momentum variables (y1~y N This is a time evolution process for evolving ) over time.

[0056] In S14, the simulated bifurcation machine has N momentum variables (y1~y N The simulated branching machine performs a y-update process that updates each of the i-th momentum variable (y) in the y-update process. i In the update process of ), N position variables (x1~x N ) and the i-th position variable (x) of the N×N matrix (J). i ) and other (N-1) position variables (x 1~i-1, x i+1~N N coefficients (J) representing the interaction between ) i,j ) and the i-th bias coefficient (h i ) and the i-th momentum variable (y i ) Update.

[0057] Next, in S15, the simulated branching machine has N position variables (x1~x N The simulated branch machine executes an x ​​update process that updates each of the i-th position variable (x) in the x update process. i In the update process of ), the i-th momentum variable (yi ) determines the i-th position variable (x i ) Update.

[0058] The simulated branching machine may execute the processes of S14 and S15 in a reversed order.

[0059] Next, in S16, the simulated branching machine has N position variables (x1~x N The simulated bifurcation machine performs wall processing on position variables whose absolute value exceeds 1. Furthermore, the simulated bifurcation machine also performs wall processing on momentum variables corresponding to position variables whose absolute value exceeds 1. For example, in wall processing, the simulated bifurcation machine changes the absolute value of position variables whose absolute value exceeds 1 to a value of 1 or less, while keeping the sign the same. Also, for example, in wall processing, the simulated bifurcation machine changes the value of momentum variables corresponding to position variables whose absolute value exceeds 1 to 0.

[0060] Simulated bifurcation algorithms have variations in the x-update, y-update, and wall-update operations. For example, variations of the simulated bifurcation algorithm include the adiabatic simulated bifurcation (aSB) algorithm, the ballistic simulated bifurcation (bSB) algorithm, and the discrete simulated bifurcation (dSB) algorithm.

[0061] When executing processing according to the adiabatic simulated branching algorithm, the simulated branching machine performs the operation shown in equation (4-1) in the y update process (S14) and the operation shown in equation (4-2) in the x update process (S15). Note that when executing processing according to the adiabatic simulated branching algorithm, the simulated branching machine does not perform the wall process (S15).

[0062]

number

[0063] When performing processing according to the ballistic simulated branching algorithm, the simulated branching machine performs the operation shown in equation (5-1) in the y update process (S14), the operation shown in equation (5-2) in the x update process (S15), and the operation shown in equation (5-3) in the wall processing (S16).

[0064]

number

[0065] When executing a process according to a discrete simulated branching algorithm, the simulated branching machine performs the operation shown in equation (6-1) in the y update process (S14), the operation shown in equation (6-2) in the x update process (S15), and the operation shown in equation (6-3) in the wall process (S16).

[0066]

number

[0067] Note that in equations (4-1), (4-2), (5-1), (5-2), (5-3), (6-1), (6-2), and (6-3), t k and t k+1 t represents time. k+1 is, t k This is the time obtained by adding a unit of time (Δt) to that value.

[0068] x i (t k ) is time (t k The i-th position variable (x) in ) i The value of x is shown. i (t k+1 ) is time (t k+1 The i-th position variable (x) in ) iIndicates the value of y i (t k ) represents the i-th momentum variable (y k ) at time (t i ) and indicates its value. y i (t k+1 ) represents the i-th momentum variable (y k+1 ) at time (t i ) and indicates its value.

[0069] K, a0, η, and c0 are predetermined constants. a(t k ) is a function that changes according to time. a(t k ) is, for example, a positive real number such that a(t1) = 0 and it increases as time increases, and becomes a0 at the end time (T) (a(T) = a0). Also, sgn(x i (t k )) is a function that outputs the sign of the i-th position variable (x k ) at time (t i ), and if x i (t<opposite000084>) is 0 or more, it is +1, and if x i (t k ) is less than 0, it is -1.

[0070] When the simulated branch machine executes the processes of S14 to S16 a predetermined number of times, that is, when the operation is executed until the time t reaches the end time T, it exits the loop process between S13 and S17 and advances the process to S18.

[0071] In S18, the simulated branch machine outputs N decision variables (s1 to s N ) based on the N position variables (x1 to x N ) at the end time, or the N decision variables (s1 to s N ) calculated based on the N position variables (x1 to x N ) at the end time. The simulated branch machine calculates the i-th decision variable (s i ) among the N decision variables (s1 to s i ) based on sgn(x

[0072] It should be noted that there seems to be an error in the original text where <opposite000084> is used. It should probably be k . This translation is based on the corrected understanding. When the simulated branching machine finishes processing S18, it terminates processing according to the simulated branching algorithm.

[0073] The number of iterations of the time evolution process (the loop between S13 and S17) is predetermined according to the application. The computational complexity required for one iteration of the time evolution process (one iteration from S14 to S16) does not vary. Therefore, the simulated branching machine can minimize the variation in solution time. Consequently, even when applied to real-time systems with time constraints that require processing to be completed by a predetermined time, the simulated branching machine can reliably output a solution within that time.

[0074] Furthermore, as shown in Patent Document 3, for example, a simulated branch machine can be configured using a dedicated parallel processing circuit that includes a large number of arithmetic units. This allows the simulated branch machine to extremely reduce the computation time for a single process in the time evolution process. Also, unlike software processing, a simulated branch machine implemented in a dedicated hardware circuit does not experience any interrupt processing, so the solution time is strictly fixed. For example, a simulated branch machine implemented in a dedicated hardware circuit can fix the time until a solution is obtained in units of clock cycles. Therefore, when a simulated branch machine implemented in a dedicated hardware circuit is applied to a real-time system, it can output a solution while more reliably adhering to time constraints.

[0075] Figure 4 shows a first example of the configuration of a problem-solving system 100 for solving combinatorial optimization problems. The problem-solving system 200 comprises a host device 210 and an optimization solver device 230.

[0076] The host device 210 receives a target optimization problem that minimizes the target objective function, and calculates the solution to the received target optimization problem using the optimization solver device 230. The host device 210 then outputs the calculated solution to the target optimization problem.

[0077] The host device 210 is a computer and includes a processor and accelerators other than the optimization solver device 230, an offloader, memory, storage, sensors, actuators, a communication interface, etc. The host device 210 performs processing other than that performed by the optimization solver device 230.

[0078] The optimization solver device 230 is an optimization solver that solves combinatorial optimization problems. For example, the optimization solver device 230 may be an Ising machine implemented in hardware. For example, the optimization solver device 230 may be implemented by an accelerator or offloader in the host device 210. Alternatively, the optimization solver device 230 may be implemented by a processor that constitutes the host device 210. For example, the host device 210 may function as the optimization solver device 230 itself by executing a program.

[0079] Furthermore, the optimization solver device 230 may be connected to the host device 210 via a network. For example, the host device 210 may be a client terminal device on the network, and the optimization solver device 230 may be implemented as a server or cloud on the network. Alternatively, the host device 210 and the optimization solver device 230 may be connected via a communication bus. For example, the host device 210 may be a computer, and the optimization solver device 230 may be implemented as an external device connected to the computer via a communication bus, or as a separate computer.

[0080] For example, the optimization solver device 230 may be a QUBO solver that solves a QUBO problem. In this case, the host device 210 generates coefficient information (matrix (Q)) that specifies the QUBO problem as coefficient information and outputs it to the optimization solver device 230. In this case, the optimization solver device 230 outputs the ground state information (b N ) representing the value of each of the N decision variables (b1 to b opt ) to the host device 210.

[0081] Also, the optimization solver device 230 may obtain coefficient information (matrix (Q)) that specifies the QUBO problem, reduce the QUBO problem to an Ising problem, and execute a solution process. Further, the optimization solver device 230 may be a HUBO solver that solves a HUBO problem, or may be a device capable of executing a solution process that minimizes an objective function including variables representing continuous values for some of the N decision variables. In this case, the host device 210 formulates an objective function in a form that can be solved by the optimization solver device 230 and outputs coefficient information representing a plurality of coefficients included in the formulated objective function to the optimization solver device 230.

[0082] FIG. 5 is a diagram showing the configuration of a solution system 20 including an optimization solver device 230 that is a simulated branching machine.

[0083] The optimization solver device 230 may be a simulated branching machine. In this case, the host device 210 gives information (matrix (J) and bias coefficient (h)) for specifying the Ising problem to the simulated branching machine. Further, the host device 210 may give the initial values of the N position variables (x1 to x N ) and the initial values of the N momentum variables (y1 to y N ) to the optimization solver device 230. Also, the host device 210 may give various constants and functions (for example, K, a0, c 0、 a(t) and Δt, etc.) used in the simulated branching algorithm to the optimization solver device 230. After the optimization process, the optimization solver device 230 outputs, as a solution, the N decision variables (s1 to s N) representing ground state information (s opt Instead of ), N position variables (x1~x N ) representing ground state information (x opt The following may be sent back to the host device 210. Alternatively, even if the optimization solver device 230 is a simulated branching machine, it may obtain coefficient information (matrix (Q)) that identifies the QUBO problem, reduce the QUBO problem to the Ising problem, and perform the solution process.

[0084] (First Embodiment) Next, the quantum computer system 10 according to the first embodiment will be described.

[0085] Figure 6 shows the configuration of the quantum computer system 10 according to the first embodiment. The quantum computer system 10 comprises a quantum computer 20 and an information processing device 30.

[0086] The quantum computer 20 includes a quantum processing unit 22 (QPU) and a management unit 24.

[0087] The quantum computing unit 22 includes multiple qubits. The quantum computing unit 22 is given physical circuit information representing a physical quantum circuit. The quantum computing unit 22 uses the multiple qubits to realize the physical quantum circuit represented by the given physical circuit information and performs quantum operations.

[0088] Each of the multiple qubits can perform single-bit gate operations of multiple operation types. Furthermore, among all possible combinations of pairs of qubits in the multiple qubits, some pairs of qubits can perform two-qubit gate operations. The quantum operation unit 22 executes gate operations on the qubits specified in the given quantum physical circuit in a specified order.

[0089] The quantum computing unit 22 then outputs the calculation result from the realized physical quantum circuit. In this embodiment, the quantum computing unit 22 acquires second physical circuit information from the information processing device 30 via the network, realizes the second physical quantum circuit represented by the acquired second physical circuit information, and performs quantum calculations.

[0090] The management unit 24 detects the error rate or fidelity when a single-bit gate operation of the corresponding operation type is performed on each of the multiple qubits included in the quantum operation unit 22, and for each of the multiple operation types of single-bit gate operations. The management unit 24 also detects the error rate or fidelity when a two-qubit gate operation of the corresponding operation type is performed on each of the multiple pairs of qubits capable of two-qubit gate operations, and for each of the one or more operation types of two-qubit gate operations.

[0091] Furthermore, the management unit 24 transmits calibration data, including the error rate or fidelity, to the information processing device 30 via the network for at least one of the multiple qubits and at least one of the multiple pairs of qubits capable of performing a two-qubit gate operation.

[0092] For example, the calibration data includes, for each of the multiple qubits and for each of the multiple operation types of a single-bit gate operation, the error rate or fidelity when a single-bit gate operation of the corresponding operation type is performed on the corresponding qubit. Alternatively, for example, the calibration data includes, for each of the multiple pairs of qubits capable of a two-qubit gate operation and for each of the one or more operation types of a two-qubit gate operation, the error rate or fidelity when a two-qubit gate operation of the corresponding operation type is performed on the corresponding pair.

[0093] In general, the quantum computer system 10 can only perform one type of two-qubit gate operation. Therefore, in this embodiment, the calibration data includes, for each of the multiple pairs of qubits capable of performing two-qubit gate operations, the error rate or fidelity when a specific one type of two-qubit gate operation is performed on the corresponding pair.

[0094] Furthermore, the error rate and fidelity change over time. Therefore, the calibration data changes over time. Accordingly, the management unit 24 detects the latest error rate or fidelity at regular intervals or for predetermined events, and transmits the calibration data, including the latest error rate or fidelity, to the information processing device 30. For example, the management unit 24 transmits the calibration data, including the latest error rate or fidelity, to the information processing device 30 in response to a request from the information processing device 30. Alternatively, the management unit 24 may broadcast the calibration data, including the latest error rate or fidelity, over the network at regular intervals or for predetermined events.

[0095] The information processing device 30 executes processing according to a program. The information processing device 30 is, for example, a computer and includes memory and a processor. The information processing device 30 may include one or more reconfigurable semiconductor devices such as FPGAs (Field-Programmable Gate Arrays). The information processing device 30 may also include accelerators, off-loaders, memory, storage, sensors, actuators, communication interfaces, etc. The processor may be implemented by one or more CPUs (Central Processing Units), microprocessors, GPUs (Graphics Processing Units), ASICs (Application Specific Integrated Circuits), or hardware electronic circuits including these circuits.

[0096] The information processing device 30 includes a quantum compilation device 32, a solver device 34, and a remapping device 40.

[0097] The quantum compilation device 32 acquires logic circuit information or a quantum program representing a logic quantum circuit. The quantum compilation device 32 further acquires topology information. The quantum compilation device 32 also acquires calibration data. Then, the quantum compilation device 32 performs quantum compilation and quantum dot mapping to convert the logic circuit information or quantum program into first physical circuit information representing a first physical quantum circuit based on the topology information and calibration data. The quantum compilation device 32 may perform quantum compilation and quantum dot mapping without using the calibration data.

[0098] Logic quantum circuits and quantum programs represent highly abstract quantum circuits that the quantum computer 20 cannot directly execute. For example, logic quantum circuits and quantum programs represent the execution sequence of single-bit gate operations performed on each of two or more virtual qubits, and multiple two-qubit gate operations performed on a pair of virtual qubits. Alternatively, logic quantum circuits and quantum programs may represent an execution sequence that includes gate operations performed on a pair of three or more virtual qubits.

[0099] The first physical quantum circuit is an example of a physical quantum circuit. A physical quantum circuit represents a quantum circuit that the quantum computer 20 can directly execute. More specifically, a physical quantum circuit represents the correspondence between multiple qubits contained in the quantum computer 20 and two or more target qubits, and the execution order of single-bit gate operations for each of the two or more target qubits and two-qubit gate operations for each pair of one or more target qubits from the two or more target qubits.

[0100] Note that each of two or more target qubits represents a bit that is the target of a single-bit gate operation in a physical quantum circuit. Each of one or more pairs of target qubits represents a pair of bits that are the target of a qubit gate operation in a physical quantum circuit.

[0101] A physical quantum circuit may be described based on, for example, the specifications of OpenQASM2 or OpenQASM3. Alternatively, a physical quantum circuit may be an object of type QuantumCircuit defined in Qiskit, one of the SDKs (Software Development Kits) for quantum computers, or it may be an object of a vendor-specific data type defined in another SDK for quantum computers.

[0102] Topology information represents multiple qubits contained in the quantum computer 20, and multiple pairs of qubits capable of performing 2-qubit gate operations on multiple qubits. The information processing device 30 may acquire topology information from the quantum computer 20 via a network, or it may acquire topology information about the quantum computer 20 from a server device or the like via a network. The information processing device 30 may also acquire topology information input by a user or the like.

[0103] The solver device 34 is an optimization solver that solves combinatorial optimization problems. In this embodiment, the solver device 34 solves the QUBO problem or the Ising problem using a heuristic solution algorithm. For example, the solver device 34 is a simulated branching machine.

[0104] The solver device 34 obtains the combinatorial optimization problem from the remapping device 40 and solves the obtained combinatorial optimization problem. Then, the solver device 34 provides the remapping device 40 with one or more solutions to the combinatorial optimization problem obtained by solving it.

[0105] For example, the solver device 34 may be implemented by hardware such as an FPGA. For example, the solver device 34 may be implemented by an accelerator or offloader in the information processing device 30. Alternatively, the solver device 34 may be implemented by a processor that constitutes the information processing device 30. For example, the information processing device 30 may function as the solver device 34 itself by executing a program.

[0106] Furthermore, the solver device 34 may be incorporated into the remapping device 40. For example, the solver device 34 may be realized by a processor constituting the remapping device 40 executing a program.

[0107] Furthermore, the solver device 34 may be implemented by a computer separate from the information processing device 30 and connected to the information processing device 30 via a network. For example, the information processing device 30 may be a client terminal device on the network, and the solver device 34 may be implemented as a server or cloud on the network. Alternatively, the information processing device 30 and the solver device 34 may be connected via a communication bus.

[0108] For example, if the solver device 34 is an Ising machine that solves the Ising problem, the information processing device 30 generates coefficient information (J, h) that identifies the Ising problem as coefficient information and provides it to the solver device 34. In this case, the solver device 34 also generates N decision variables (s1~s N Ground state information (s) representing each of the values ​​of ) opt Outputs ).

[0109] Furthermore, for example, if the solver device 34 is a QUBO solver that solves the QUBO problem, the information processing device 30 generates coefficient information (matrix (Q)) that identifies the QUBO problem as coefficient information and provides it to the solver device 34. In this case, the solver device 34 has N decision variables (b1~b N Ground state information (b) representing each of the values ​​of ) opt Outputs ).

[0110] Alternatively, the solver device 34 may acquire coefficient information (matrix (Q)) that identifies the QUBO problem, reduce the QUBO problem to the Ising problem, and perform a solution process. Furthermore, the solver device 34 may be a HUBO solver that solves the HUBO problem, or it may be a device capable of performing a solution process that minimizes an objective function in which some of the N decision variables include variables representing continuous values. In this case, the information processing device 30 formulates an objective function in a form solvable by the solver device 34 and provides the solver device 34 with coefficient information representing multiple coefficients included in the formulated objective function.

[0111] The remapping device 40 acquires first physical circuit information from the quantum compilation device 32. Furthermore, the remapping device 40 acquires topology information and calibration data. Then, the remapping device 40 performs a remapping process on the acquired first physical circuit information based on the topology information and calibration data, converting the first physical circuit information into second physical circuit information.

[0112] The remapping process generates a second physical quantum circuit by updating the correspondence between two or more target qubits for multiple qubits in the first physical quantum circuit, so as to minimize the composite error rate, which represents the degree to which errors occur when quantum operations are performed, or maximize the composite fidelity, which represents the degree to which operations are performed as intended when quantum operations are performed. Furthermore, the remapping process is performed under the constraint that the updated second physical quantum circuit performs the same quantum operation as the quantum operation represented by the first physical quantum circuit.

[0113] The second physical quantum circuit is an example of a physical quantum circuit. The second physical quantum circuit causes the quantum computer 20 to perform the same quantum operations as the first physical quantum circuit, but the correspondence between the multiple qubits contained in the quantum computer 20 and two or more target qubits differs from that of the first physical quantum circuit.

[0114] Furthermore, the remapping device 40 performs the remapping process using a combinatorial optimization problem incorporating constraints. In this embodiment, the combinatorial optimization problem used in the remapping process is a problem that minimizes the total cost function obtained by weighting the penalty function that is smallest when the constraints are satisfied and the cost function, or a problem that maximizes the total cost function obtained by weighting the penalty function that is largeest when the constraints are satisfied and the cost function.

[0115] The remapping device 40 then provides the second physical circuit information to the quantum computer 20, causing the quantum computer 20 to perform quantum operations according to the second physical quantum circuit.

[0116] The remapping device 40 may be implemented by the same computer that implements the quantum compilation device 32. Alternatively, the remapping device 40 may be implemented by a different computer from the one that implements the quantum compilation device 32 and connected to the quantum compilation device 32 via a network. For example, the quantum compilation device 32 and the remapping device 40 may be connected via a communication bus.

[0117] Figure 7 is a diagram illustrating the remapping process performed by the remapping device 40.

[0118] The quantum computer 20 that performs quantum operations has a predetermined device topology. Each of the multiple qubits contained in the quantum computer 20 is assigned a unique identification information, a qubit ID. For example, the correspondence represents the relationship between the target qubit ID that identifies each of two or more target qubits and the qubit ID.

[0119] The remapping process is a process that changes the correspondence without changing the content of the quantum operations performed by the quantum computer 20. In other words, the remapping process searches for a second physical quantum circuit that can perform the same quantum operations as the first physical quantum circuit by changing only the correspondence of the first physical quantum circuit within the constraints of the device topology, without decompiling the first physical quantum circuit or performing a re-compilation process based on the logic quantum circuit and logic program. Furthermore, by using calibration data, the remapping process searches for a second physical quantum circuit that reduces the errors caused by quantum operations, i.e., increases fidelity.

[0120] Figure 8 shows the functional configuration of the remapping device 40.

[0121] The remapping device 40 includes a topology graph generation unit 52, a quantum circuit graph generation unit 54, a calibration data acquisition unit 56, a problem generation unit 58, an optimization processing unit 60, a selection unit 62, an update unit 64, and an output unit 66.

[0122] The topology graph generation unit 52 acquires topology information. Based on the topology information, the topology graph generation unit 52 generates a topology graph. The topology graph graphically represents the coupling relationships that enable 2-qubit gate operations in multiple qubits contained in the quantum computer 20.

[0123] The quantum circuit graph generation unit 54 acquires first physical circuit information representing the first physical quantum circuit. Based on the acquired first physical circuit information, the quantum circuit graph generation unit 54 generates a quantum circuit graph. The quantum circuit graph is quantum circuit coupling information that represents the coupling relationship of pairs of target qubits that perform a 2-qubit gate operation in two or more target qubits included in the first physical quantum circuit, and the coupling relationship is represented as a graph.

[0124] The calibration data acquisition unit 56 acquires calibration data from the quantum computer 20. The calibration data changes over time. The calibration data acquisition unit 56 acquires the latest calibration data when generating second physical circuit information. For example, the calibration data acquisition unit 56 may acquire the latest calibration data at regular intervals or at predetermined events, or it may acquire the latest calibration data from the quantum computer 20 in response to acquiring first physical circuit information.

[0125] The problem generation unit 58 acquires a topology graph, a quantum circuit graph, and calibration data. Based on the topology graph, quantum circuit graph, and calibration data, the problem generation unit 58 generates constraints and a combinatorial optimization problem.

[0126] The combinatorial optimization problem is the problem of associating a quantum circuit graph with a subgraph of a topology graph. In addition, the combinatorial optimization problem is the problem of searching for a correspondence that minimizes the composite error rate, which represents the degree to which errors occur when quantum operations are performed on the part of the multiple qubits in the quantum computer 20 that corresponds to the subgraph, or maximizes the composite fidelity, which represents the degree to which operations are performed as intended when quantum operations are performed on the part of the subgraph that corresponds to the subgraph.

[0127] The constraint is that the quantum computer 20 is capable of executing the physical quantum circuit identified by the solution. In other words, the constraint is that the subgraphs of the topology graph are isomorphic to the quantum circuit graph.

[0128] The optimization processing unit 60 obtains the combinatorial optimization problem generated by the problem generation unit 58. The optimization processing unit 60 provides the combinatorial optimization problem to the solver device 34 and causes the solver device 34 to solve the combinatorial optimization problem.

[0129] The selection unit 62 obtains constraint conditions from the problem generation unit 58. Furthermore, the selection unit 62 obtains one or more solutions obtained by solving the combinatorial optimization problem from the solver device 34. From the obtained one or more solutions, the selection unit 62 selects the optimal solution that satisfies the constraint conditions. For example, the selection unit 62 selects one or more candidate solutions that satisfy the constraint conditions from the obtained one or more solutions. Furthermore, the selection unit 62 selects one or more of the candidate solutions as the optimal solution. In this case, the selection unit 62 selects as the candidate solution that minimizes the error that occurs when the quantum computer 20 executes the physical quantum circuit identified by the corresponding candidate solution, i.e., the candidate solution with the highest fidelity. Note that the selection unit 62 may select as the optimal solution a candidate solution that does not minimize the error or does not have the highest fidelity, as long as the constraint conditions are satisfied.

[0130] Furthermore, the selection unit 62 may output information indicating that it will not update if none of the acquired solutions satisfy the constraints. Also, the selection unit 62 may output information indicating that it will not update if the error that occurs when the quantum computer 20 executes the physical quantum circuit identified by the optimal solution is smaller than the error that occurs when the quantum computer 20 executes the original first physical quantum circuit. In other words, the selection unit 62 may output information indicating that it will not update if the physical quantum circuit identified by the optimal solution is less reliable than the first physical quantum circuit.

[0131] The update unit 64 obtains first physical circuit information representing the first physical quantum circuit and the optimal solution. Based on the optimal solution, the update unit 64 generates second physical circuit information representing the second physical quantum circuit, which is obtained by updating the correspondence between multiple qubits in the first physical quantum circuit and two or more target qubits. For example, the update unit 64 generates second physical circuit information representing the second physical quantum circuit by rewriting the qubits corresponding to each of the two or more target qubits in the correspondence represented by the first physical quantum circuit based on the optimal solution. If the selection unit 62 outputs information indicating that it will not update, the update unit 64 outputs the first physical circuit information as the second physical circuit information without updating it.

[0132] The output unit 66 acquires the second physical circuit information from the update unit 64. The output unit 66 provides the acquired second physical circuit information to the quantum computer 20 via the network, causing the quantum computer 20 to perform quantum operations according to the second physical circuit information.

[0133] Figure 9 shows an example of a topology graph.

[0134] The topology graph represents each of the multiple qubits contained in the quantum computer 20 as a node. Furthermore, the topology graph represents each of the multiple pairs of qubits capable of 2-qubit gate operations contained in the quantum computer 20 as an edge.

[0135] The nodes in the topology graph correspond one-to-one with the qubits in the quantum computer 20. For example, each node in the topology graph is assigned an index (v) that identifies the corresponding qubit among the qubits. The index (u,v) is represented, for example, by an integer greater than or equal to 0. For example, if the topology graph contains N2 nodes, each of the N2 nodes is assigned an integer index greater than or equal to 0 and (N2-1) that does not overlap with other nodes.

[0136] Figure 10 shows an example of a first physical quantum circuit.

[0137] The first physical quantum circuit represents the correspondence between each of two or more target qubits (e.g., L0, L1, L2, L3, L4) and any of the qubits (P26, P24, P23, P34, P25) contained in the quantum computer 20. In Figure 10, L0, L1, L2, L3, and L4 are identification information that identifies the target qubits. In Figure 10, P26, P24, P23, P34, and P25 are identification information that identifies the qubits contained in the quantum computer 20.

[0138] Furthermore, the first physical quantum circuit represents the execution order of single-bit gate operations on each of two or more target qubits (e.g., L0, L1, L2, L3, L4), and two-qubit gate operations on each pair of target qubits. Note that “x”, “sx”, “rz”, and “measure” in Figure 12 represent single-bit gate operations. “cx” in Figure 12 represents two-qubit gate operations.

[0139] Figure 11 shows an example of a quantum circuit graph based on the first physical quantum circuit shown in Figure 10.

[0140] A quantum circuit graph represents each of the two or more target qubits included in the first physical quantum circuit as a node. Furthermore, a quantum circuit graph represents each of the two or more pairs of target qubits performing a two-qubit gate operation as an edge.

[0141] Two or more nodes in a quantum circuit graph correspond one-to-one with two or more target qubits in the first physical quantum circuit. Each of the two or more nodes in the quantum circuit graph is assigned an index (i) that identifies the corresponding target qubit among the two or more target qubits in the first physical quantum circuit. The index (i) is represented, for example, by an integer of 0 or greater. For example, if the quantum circuit graph contains N1 nodes, each of the N1 nodes is assigned an integer index of 0 or greater and less than or equal to (N1-1) that does not overlap with other nodes.

[0142] Furthermore, each of the two or more nodes in the quantum circuit graph contains a node weight for each of the multiple operation types of single-bit gate operations. The node weight represents the number of times the corresponding single-bit gate operation of the corresponding operation type is performed on the corresponding target qubit in the first physical quantum circuit. For example, in the example in Figure 11, each of the two or more nodes contains the number of times the corresponding single-bit gate operation is performed on the target qubit as a node weight for each of “x”, “sx”, “rz”, and “measure”.

[0143] Furthermore, each of the two or more edges in the quantum circuit graph contains an edge weight. The edge weight represents the number of times a two-qubit gate operation is performed on the two corresponding target qubits.

[0144] In this embodiment, the quantum computer 20 performs only one type of two-qubit gate operation. However, if the quantum computer 20 is capable of performing multiple types of two-qubit gate operations, the edge weights represent the number of times the corresponding two-qubit gate operation is performed for each of the multiple operation types.

[0145] Figure 12 is a diagram representing the node weights.

[0146] In this embodiment, the node weights in the quantum circuit graph are identified by an index (i) that identifies the corresponding node and an index (g) that identifies the instruction type, as shown in Figure 12.

[0147] In this embodiment, the node weight is W i,g 1g It is expressed as W i,g 1g This represents the number of times a single-bit gate operation of the operation type identified by g among multiple operation types is performed on the target qubit corresponding to the node identified by i among the two or more target qubits included in the first physical quantum circuit.

[0148] Figure 13 is a diagram showing the edge weights.

[0149] In this embodiment, the edge weights in the quantum circuit graph are identified by an index (i) that identifies the first node of two nodes connected by a corresponding edge, and an index (j) that identifies a second node different from the first node of the two nodes, as shown in Figure 13.

[0150] In this embodiment, the edge weight is W i,j 2g It is expressed as W i,j 2g This represents the number of times a two-qubit gate operation is performed on a pair of target qubits: one corresponding to the node identified by i among two or more target qubits, and the other corresponding to the node identified by j among two or more target qubits.

[0151] Figure 14 shows the error rate of a single-bit gate operation included in the calibration data.

[0152] In this embodiment, the calibration data includes the error rate for each of the multiple qubits included in the quantum computer 20, and for each of the multiple operation types of single-bit gate operations, when a single-bit gate operation of the operation type corresponding to the corresponding qubit is performed. For example, as shown in Figure 14, the error rate of a single-bit gate operation is identified by an index (v) that identifies the corresponding qubit among the multiple qubits included in the quantum computer 20, and an index (g) that identifies the instruction type of the single-bit gate operation.

[0153] In this embodiment, the error rate of a single bit gate operation is e v,g 1g It is expressed as e v,g 1g This represents the error rate when a single-bit gate operation of the operation type identified by g (among several operation types) is performed on a qubit corresponding to a node identified by v (among several qubits in the topology graph) of the quantum computer 20. Note that the calibration data may include the fidelity of the single-bit gate operation instead of the error rate of the single-bit gate operation.

[0154] Figure 15 shows the error rate of 2-qubit gate operations included in the calibration data.

[0155] In this embodiment, the calibration data includes the error rate for each of the multiple pairs of qubits when a two-qubit gate operation is performed on the corresponding pair. Note that the calibration data does not need to include the error rate for the two-qubit gate operation for pairs of qubits that cannot be operated on. For example, the error rate for the two-qubit gate operation is identified by an index (u) that identifies the first qubit of the corresponding pair of qubits and an index (v) that identifies a second qubit that is different from the first qubit of the corresponding pair of qubits, as shown in Figure 15.

[0156] In this embodiment, the error rate of a 2-qubit gate operation is e u,v 2g It is expressed as e u,v 2g This represents the error rate when a two-qubit gate operation is performed on a pair of qubits in the quantum computer 20, specifically a qubit corresponding to a node identified by v in the topology graph and a qubit corresponding to a node identified by u in the topology graph. Note that the calibration data may include the fidelity of the two-qubit gate operation instead of the error rate of the two-qubit gate operation.

[0157] In this embodiment, the quantum computer 20 performs only one type of two-qubit gate operation. However, if the quantum computer 20 is capable of performing multiple types of two-qubit gate operations, the calibration data may include, for each of the multiple pairs of qubits and for each of the multiple types of two-qubit gate operations, the error rate or fidelity when performing the two-qubit gate operation of the operation type corresponding to the pair.

[0158] (Combinatorial optimization problem) Next, we will explain the constraints and combinatorial optimization problem generated by the problem generation unit 58.

[0159] The remapping process updates the correspondence between two or more target qubits and multiple qubits in the first physical quantum circuit so as to minimize the composite error rate, which represents the degree to which errors occur when quantum operations are performed, or maximize the composite fidelity, which represents the degree to which operations are performed as intended when quantum operations are performed. Furthermore, the remapping process is performed under the constraint that the updated second physical quantum circuit performs the same quantum operation as the quantum operation represented by the first physical quantum circuit.

[0160] The remapping device 40 according to this embodiment performs such remapping processing using a combinatorial optimization problem that incorporates constraints as penalties. The combinatorial optimization problem that incorporates constraints as penalties is a problem of minimizing a total cost function obtained by weighting and adding the penalty function that is smallest when the constraints are satisfied and the cost function, or a problem of maximizing a total cost function obtained by weighting and adding the penalty function that is largest when the constraints are satisfied and the cost function.

[0161] In the case of a problem to minimize the total cost function, the cost function represents the synthesis error rate when a physical quantum circuit represented by a quantum circuit graph is executed by the quantum computer 20. Alternatively, in the case of a problem to maximize the total cost function, the cost function represents the synthesis fidelity when a physical quantum circuit represented by a quantum circuit graph is executed by the quantum computer 20.

[0162] Figure 16 shows the correspondence between quantum circuit graphs and topology graphs.

[0163] In this embodiment, the quantum circuit graph used in the combinatorial optimization problem is represented as G1=(V1,E1).

[0164] V1 represents the set of two or more nodes in the quantum circuit graph. E1 represents the set of one or more edges in the quantum circuit graph. Each of the one or more edges may be directed or undirected. Also, |V1| represents the number of nodes in the quantum circuit graph. |E1| represents the number of edges in the quantum circuit graph.

[0165] In this embodiment, the topology graph used in the combinatorial optimization problem is represented as G2=(V2,E2).

[0166] V2 represents the set of nodes in the topology graph. E2 represents the set of one or more edges in the topology graph. Each of the one or more edges may be directed or undirected. Also, |V2| represents the number of nodes in the topology graph. |E2| represents the number of edges in the topology graph.

[0167] The relationship between such a quantum circuit graph and a topology graph is |V1|≦|V2| and |E1|≦|E2|.

[0168] The constraint is that the second physical quantum circuit performs the same quantum operation as the first physical quantum circuit. Therefore, the constraint is that the subgraph is isomorphic to the quantum circuit graph. More specifically, the constraint is that the node set of the quantum circuit graph is an injective map to the node set of the topology graph, and the quantum circuit graph is subgraph isomorphic to the topology graph. Such constraints are expressed by equation (7).

number

[0169] Figure 17 is a diagram illustrating the multiple decision variables included in a combinatorial optimization problem and its constraints.

[0170] In this embodiment, each of the multiple decision variables included in the combinatorial optimization problem is x i,v It is expressed as follows.

[0171] x i,v x is a binary decision variable that represents 1 if the node identified by i in the quantum circuit graph corresponds to the node identified by v in the topology graph, and 0 if it does not correspond. i,vThis value represents 1 if the target qubit corresponding to the node identified by i in the quantum circuit graph is associated with the qubit corresponding to the node identified by v in the topology graph, and 0 if it is not associated.

[0172] Furthermore, if we let N1 = |V1| be the number of nodes in the quantum circuit graph and N2 = |V2| be the number of nodes in the topology graph, then the number of decision variables in the combinatorial optimization problem will be (N1 × N2).

[0173] Figure 18 shows the total cost function.

[0174] In this embodiment, if the combinatorial optimization problem is a problem of minimizing the total cost function, the total cost function is given by H in equation (8). total It is represented by [this].

number

[0175] A, B, C, D, and E are predetermined real numbers greater than 0.

[0176] H A and H B This is the penalty function that is minimized when the set of nodes in the quantum circuit graph is an injective map to the set of nodes in the topology graph.

[0177] H C This is the penalty function that is minimized when the quantum circuit graph is a subgraph isomorphic with respect to the topology graph.

[0178] (DH D +EH E ) is the cost function. For more details, see H D This represents the average error rate of a single-bit gate operation when a physical quantum circuit, represented by a quantum circuit graph, is executed on the quantum computer 20. EThis represents the average error rate of a 2-qubit gate operation when a physical quantum circuit, represented by a quantum circuit graph, is executed on the quantum computer 20.

[0179] Furthermore, if the combinatorial optimization problem is one in which the goal is to maximize the total cost function, the total cost function is obtained by multiplying equation (8) by -1, that is, by reversing the sign of equation (8).

[0180] Such a total cost function (H total ) is (AH) if the constraints are met. A +BH B The total cost function (H) becomes 0. total The values ​​of A, B, C, D, and E allow for adjustment of the balance between the probability of obtaining a solution that satisfies the constraints and the probability of reducing the composite error rate, i.e., increasing the composite fidelity.

[0181] Next, H A ~H E Let me explain in more detail.

[0182] H A This is expressed by equation (9). Also, H B This is expressed by equation (10).

number

number

[0183] N1 is the number of nodes in the quantum circuit graph. N2 is the number of nodes in the topology graph.

[0184] i and i' are indices that identify nodes in the quantum circuit graph, and are integers greater than or equal to 0 and less than or equal to (N1-1). v is an index that identifies nodes in the topology graph, and is an integer greater than or equal to 0 and less than or equal to (N2-1).

[0185] xi,v is a decision variable that represents 1 when the node identified by i in the quantum circuit graph is associated with the node identified by v in the topology graph, and 0 when not associated. x i´,v is a decision variable that represents 1 when the node identified by i' in the quantum circuit graph is associated with the node identified by v in the topology graph, and 0 when not associated.

[0186] H C is represented by Equation (11).

Number

[0187] E1 is the set of edges in the quantum circuit graph. E2 is the set of edges in the topology graph.

[0188] j is an index that identifies a node in the quantum circuit graph and is an integer greater than or equal to 0 and less than or equal to (N1 - 1). u is an index that identifies a node in the topology graph and is an integer greater than or equal to 0 and less than or equal to (N2 - 1).

[0189] (i, j) is an edge that represents a pair of nodes identified by i and j in the quantum circuit graph. (u, v) is an edge that represents a pair of nodes identified by u and v in the topology graph.

[0190] x i,u is a decision variable that represents 1 when the node identified by i in the quantum circuit graph is associated with the node identified by u in the topology graph, and 0 when not associated. x j,v is a decision variable that represents 1 when the node identified by j in the quantum circuit graph is associated with the node identified by v in the topology graph, and 0 when not associated.

[0191] H D is represented by Equation (12). HE is represented by Equation (13).

Number

Number

[0192] ♯instrs represents the total number of executions of single-bit gate operations and two-qubit gate operations in the first physical quantum circuit. {instrs} represents a set of multiple operation types of single-bit gate operations. g represents an index that identifies the operation type of the single-bit gate operation.

[0193] W i,g 1g represents the number of executions of a single-bit gate operation of the operation type identified by g on the target qubit corresponding to the node identified by i in the quantum circuit graph.

[0194] e v,g 1g represents the error rate when a single-bit gate operation of the operation type identified by g is executed on the qubit corresponding to the node identified by v in the topology graph.

[0195] W i,j 2g represents the number of executions of a two-qubit gate operation for the pair of the target qubit corresponding to the node identified by i and the target qubit corresponding to the node identified by j in the quantum circuit graph.

[0196] e u,v 2g represents the error rate when a two-qubit gate operation is executed on the pair of the qubit corresponding to the node identified by u and the qubit corresponding to the node identified by v in the topology graph.

[0197] Equations (12) and (13) are derived from equation (14). Equation (14) represents the overall fidelity during quantum circuit execution in quantum computer 20.

number

[0198] Equation (14) differs for each execution of the gate operation in the first physical quantum circuit and is not a quadratic function of the decision variable. Therefore, equation (14) is not a QUBO equation, and a general QUBO solver cannot solve the problem of minimizing equation (14). Thus, the inventor derived equation (15) by taking the geometric mean and logarithm of equation (14). In this way, H in equation (12) D and H in equation (13) E This is an equation based on equation (15).

number

[0199] Also, H D This may also be expressed by formula (16). H E This can also be expressed by equation (17).

number

number

[0200] Equations (12) and (13) represent the error rate obtained by taking the logarithm of the geometric mean of the combined error rates, whereas equations (16) and (17) represent the error rate obtained by taking the arithmetic mean of the combined error rates.

[0201] Note that the calibration data may include fidelity rather than error rate. In this case, (1-e in equations (12) and (16) v,g 1g ) is replaced with the fidelity of a single-bit gate operation. Also, (1-e in equations (13) and (17) u,v2g ) is replaced with the fidelity of the two-qubit gate operation.

[0202] Also, when the quantum computer 20 can execute multiple types of two-qubit gate operations, the calibration data includes the error rate when performing a two-qubit gate operation for each of a plurality of pairs of two qubits and for each of a plurality of operation types of the two-qubit gate operation. In this case, the right sides of equations (13) and (16) become equations for cumulative summation for each operation type of the two-qubit gate operation.

[0203] Also, the total cost function described above is a QUBO formula. When the solver device 34 is an Ising machine, the problem generation unit 58 gives the solver device 34 an Ising problem obtained by converting the total cost function into an Ising model. Also, the problem generation unit 58 may directly generate an Ising model representing the total cost function.

[0204] FIG. 19 is a flowchart showing the processing flow of the quantum computer system 10. The quantum computer system 10 executes processing in the flow shown in FIG. 19.

[0205] First, in S101, the remapping device 40 generates a topology graph.

[0206] Subsequently, in S102, the quantum compilation device 32 generates first physical circuit information representing a first physical quantum circuit based on the logical circuit information representing the logical quantum circuit or the quantum program.

[0207] Subsequently, in S103, the remapping device 40 acquires the first physical circuit information generated by the quantum compilation device 32 and generates a quantum circuit graph based on the first physical circuit information.

[0208] Subsequently, in S104, the quantum computer 20 generates and outputs calibration data.

[0209] Next, in S105, the remapping device 40 generates constraints and combinatorial optimization problems based on the topology graph, quantum circuit graph, and calibration data.

[0210] Next, in S106, the remapping device 40 provides the generated combinatorial optimization problem to the solver device 34. In this case, the remapping device 40 may also provide the solver device 34 with the parameters for solving the combinatorial optimization problem.

[0211] Next, in S107, the solver device 34 solves the combinatorial optimization problem generated by the remapping device 40 and generates one or more solutions. The solver device 34 then provides the one or more solutions it has generated to the remapping device 40.

[0212] Next, in S108, the remapping device 40 analyzes whether each of the one or more solutions generated by the solver device 34 satisfies the constraint conditions.

[0213] Next, in S109, the remapping device 40 determines whether there is a solution that satisfies the constraints among the one or more solutions generated by the solver device 34. If there is a solution that satisfies the constraints among the one or more solutions (Yes in S109), the remapping device 40 proceeds to S110. If there is no solution that satisfies the constraints among the one or more solutions (No in S109), the remapping device 40 proceeds to S113.

[0214] In S110, the remapping device 40 selects the optimal solution for each of the one or more candidate solutions that satisfy the constraints among the one or more solutions generated by the solver device 34, which minimizes the error that occurs when the quantum computer 20 executes the physical quantum circuit identified by the corresponding candidate solution, i.e., maximizes fidelity. For example, the remapping device 40 evaluates the function value of the cost function for each of the one or more candidate solutions to select the optimal solution.

[0215] Next, in S111, the remapping device 40 determines whether the error that occurs when the quantum computer 20 executes the physical quantum circuit identified by the optimal solution is smaller than the error that occurs when the quantum computer 20 executes the original first physical quantum circuit. If the error that occurs when the quantum computer 20 executes the physical quantum circuit identified by the optimal solution is smaller than the error that occurs when the quantum computer 20 executes the original first physical quantum circuit (Yes in S111), the remapping device 40 proceeds to S112. If the error that occurs when the quantum computer 20 executes the physical quantum circuit identified by the optimal solution is not smaller than the error that occurs when the quantum computer 20 executes the original first physical quantum circuit (No in S111), the remapping device 40 proceeds to S113.

[0216] In S112, the remapping device 40 generates second physical circuit information representing the second physical quantum circuit, which has been updated based on the optimal solution, by updating the correspondence between multiple qubits in the first physical quantum circuit and two or more target qubits. After completing S112, the remapping device 40 proceeds to S114.

[0217] In S113, the remapping device 40 uses the first physical circuit information representing the first physical quantum circuit as the second physical circuit information without updating the correspondence of the first physical quantum circuit. After completing S113, the remapping device 40 proceeds to S114.

[0218] In S114, the remapping device 40 outputs second physical circuit information to the quantum computer 20.

[0219] Then, in S115, a quantum operation is performed according to the second physical circuit information generated by the remapping device 40, and the result of the quantum operation is output.

[0220] As described above, the remapping device 40 according to this embodiment generates second circuit information representing a second physical quantum circuit that can perform the same quantum operations as the first physical quantum circuit, by changing only the correspondence of the first physical quantum circuit within the constraints of the device topology, without decompiling the first physical quantum circuit or performing a re-compilation process based on the logic quantum circuit and logic program. As a result, the remapping device 40 can improve the reliability of quantum operations performed by the quantum computer 20 with simple processing. Furthermore, the remapping device 40 eliminates the need for the quantum compilation device 32 to generate first physical circuit information representing the optimal first physical quantum circuit, thereby reducing the processing load on the quantum compilation device 32.

[0221] (Second Embodiment) Next, a quantum computer system 10 according to the second embodiment will be described.

[0222] The quantum computer system 10 according to the second embodiment has substantially the same functions and configuration as the first embodiment. Therefore, a detailed description of the quantum computer system 10 according to the second embodiment will be omitted, except for the differences from the first embodiment. The same applies to the third embodiment and subsequent embodiments.

[0223] Figure 20 shows the configuration of the quantum computer system 10 according to the second embodiment. The quantum computer system 10 according to the second embodiment comprises a quantum computer 20, an information processing device 30, and a solver device 34.

[0224] The information processing device 30 according to the second embodiment includes a quantum compilation device 32. That is, the information processing device 30 according to the second embodiment does not include a solver device 34 and a remapping device 40, compared to the first embodiment. The information processing device 30 according to the second embodiment outputs the first physical circuit information generated by the quantum compilation device 32 to the quantum computer 20 via a network.

[0225] The quantum computer 20 according to the second embodiment includes a quantum computing unit 22, a management unit 24, and a remapping device 40.

[0226] The remapping device 40 according to the second embodiment acquires first physical circuit information from the information processing device 30 via a network. The remapping device 40 acquires calibration data, for example, immediately before the quantum computing unit 22 performs a quantum operation, and generates second physical circuit information based on the first physical circuit information. The remapping device 40 then provides the generated second physical circuit information to the quantum computing unit 22, causing the quantum computing unit 22 to perform a quantum operation according to the second physical circuit information.

[0227] The solver device 34 according to the second embodiment is connected to the remapping device 40 so that it can be accessed. For example, the solver device 34 may be incorporated into the quantum computer 20, or it may be implemented in a server device or the like that can be accessed via a network. Alternatively, the solver device 34 according to the second embodiment may be incorporated into the remapping device 40 within the quantum computer 20.

[0228] In the quantum computer 20, after the quantum compilation device 32 generates first physical circuit information representing the first physical quantum circuit, a long time may pass due to queue waiting, etc., before the quantum computer 20 actually executes the quantum operation. Even in such cases, the quantum computer system 10 according to the second embodiment can remap just before the quantum computer 20 executes the quantum operation, so it can generate second physical circuit information representing the second physical quantum circuit optimized according to the latest state of the quantum computer 20. As a result, the quantum computer system 10 according to the second embodiment can improve the reliability of the quantum operation performed by the quantum computer 20 according to the latest state.

[0229] (Third embodiment) Next, a quantum computer system 10 according to the third embodiment will be described.

[0230] Figure 21 shows the configuration of the quantum computer system 10 according to the third embodiment. The quantum computer system 10 according to the third embodiment comprises a quantum computer 20, a first information processing device 30-1, and a second information processing device 30-2.

[0231] The first information processing device 30-1 and the second information processing device 30-2 are computers similar to the information processing device 30 in the first embodiment, and are connected to each other via a network. Furthermore, the second information processing device 30-2 and the quantum computer 20 are connected via a network.

[0232] The first information processing device 30-1 includes a quantum compilation device 32. The quantum compilation device 32 generates first physical circuit information based on logic circuit information or a quantum program, and outputs the generated first physical circuit information to the second information processing device 30-2 via a network.

[0233] The second information processing device 30-2 includes a solver device 34 and a remapping device 40. The remapping device 40 acquires first physical circuit information from the first information processing device 30-1 via a network and generates second physical circuit information based on the acquired first physical circuit information. The remapping device 40 then provides the generated second physical circuit information to the quantum computer 20 and causes the quantum computer 20 to perform quantum operations according to the second physical quantum circuit.

[0234] According to the quantum computer system 10 of this third embodiment, a service can be provided to the user of the first information processing device 30-1 that converts first physical circuit information representing a first physical quantum circuit into second physical circuit information representing a second physical quantum circuit that improves the reliability of quantum operations performed by the quantum computer 20.

[0235] (Fourth embodiment) Next, a quantum computer system 10 according to the fourth embodiment will be described.

[0236] Figure 22 shows the configuration of the quantum computer system 10 according to the fourth embodiment. The quantum computer system 10 according to the fourth embodiment comprises a plurality of quantum computers 20 and an information processing device 30. For example, the quantum computer system 10 according to the fourth embodiment comprises quantum computers 20-1 to 20-A, where A is any integer greater than or equal to 2.

[0237] Each of the first to A-type quantum computers 20-1 to 20-A has the same configuration as the quantum computer 20 according to the first embodiment. That is, each of the first to A-type quantum computers 20-1 to 20-A is constructed with the same architecture and has the same topology information.

[0238] The information processing device 30 is connected to each of the multiple quantum computers 20 via a network. The information processing device 30 acquires calibration data separately from each of the multiple quantum computers 20. Although the multiple quantum computers 20 have the same architecture, their operating conditions differ. Therefore, each of the multiple quantum computers 20 outputs different calibration data.

[0239] The information processing device 30 further includes a selector 70.

[0240] When the remapping device 40 obtains first physical circuit information from the quantum compilation device 32, it generates second physical circuit information corresponding to each of the multiple quantum computers 20.

[0241] When the remapping device 40 generates second physical circuit information for the a-th quantum computer 20-a (where a is an integer between 1 and A), it utilizes calibration data obtained from the a-th quantum computer 20-a. This allows the remapping device 40 to generate second physical circuit information for each of the multiple quantum computers 20, representing a second physical quantum circuit that performs highly reliable quantum operations according to the state of the corresponding quantum computer 20. The remapping device 40 provides the selector 70 with multiple sets of second physical circuit information corresponding to the multiple quantum computers 20.

[0242] The selector 70 acquires second physical circuit information corresponding to each of the multiple quantum computers 20 from the remapping device 40. That is, the selector 70 acquires multiple second physical circuit information from the remapping device 40. The selector 70 selects one of the acquired second physical circuit information and provides the selected second physical circuit information to the quantum computer 20 corresponding to the selected second physical circuit information among the multiple quantum computers 20 via the network, causing it to perform quantum operations according to the second physical quantum circuit.

[0243] The selector 70 selects, for example, the second physical circuit information from among multiple second physical circuit information that, when executed on the corresponding quantum computer 20, results in the minimum error, i.e., the maximum fidelity. For example, the selector 70 calculates a function value by substituting the optimal solution selected when generating each of the multiple second physical circuit information into the cost function, and based on the calculated function value, selects the second physical circuit information that results in the minimum error, i.e., the maximum fidelity. Alternatively, the selector 70 may select one second physical circuit information from among multiple second physical circuit information based on other parameters. For example, the selector 70 may select the second physical circuit information corresponding to the quantum computer 20 that can output the calculation result at the earliest timing, or it may select the second physical circuit information corresponding to the quantum computer 20 that can perform quantum operations at the lowest cost.

[0244] According to the quantum computer system 10 of this fourth embodiment, the reliability of quantum operations can be improved by selecting the quantum computer 20 with the best conditions from among a plurality of quantum computers 20.

[0245] (Hardware configuration) Figure 23 shows an example of a computer hardware configuration. The remapping device 40 is implemented by a computer with a hardware configuration as shown in Figure 23. The remapping device 40 comprises a CPU (Central Processing Unit) 401, RAM (Random Access Memory) 402, ROM (Read Only Memory) 403, storage device 404, and communication interface device 405. These components are connected by a bus.

[0246] The CPU 401 is one or more processors that perform arithmetic and control processing according to a program. The CPU 401 uses a predetermined area of ​​the RAM 402 as a working area and performs various processes in cooperation with programs stored in the ROM 403 and storage device 404, etc.

[0247] RAM402 is a type of memory such as SDRAM (Synchronous Dynamic Random Access Memory). RAM402 functions as a workspace for CPU401. ROM403 is a memory that stores programs and various information in a non-rewritable format.

[0248] The storage device 404 is a device that writes and reads data to and from a storage medium made of semiconductors such as flash memory, or a storage medium that can record magnetically or optically. The storage device 404 writes and reads data to and from the storage medium in response to control from the CPU 401. The communication interface device 405 communicates with external devices via a network in response to control from the CPU 401.

[0249] The program executed on the computer causes the computer to function as a remapping device 40. This program is then loaded onto RAM 402 and executed by the CPU 401 (processor).

[0250] Furthermore, programs executed on a computer are provided as files in a format that can be installed on a computer or in an executable format, recorded on computer-readable recording media such as CD-ROMs, flexible disks, CD-Rs, and DVDs (Digital Versatile Disks).

[0251] Furthermore, this program may be configured to be stored on a computer connected to a network such as the Internet and provided by being downloaded via the network. Alternatively, this program may be configured to be provided or distributed via a network such as the Internet. Furthermore, the program executed by the remapping device 40 may be pre-installed in a ROM 403 or the like and provided in that configuration.

[0252] The program for causing the computer to function as a remapping device 40 includes a topology graph generation module, a quantum circuit graph generation module, a calibration data acquisition module, a problem generation module, an optimization processing module, a selection module, an update module, and an output module. When this program is executed by the CPU 401, each module is loaded into the RAM 402, causing the CPU 401 to function as a processing unit (hardware processor) including a topology graph generation unit 52, a quantum circuit graph generation unit 54, a calibration data acquisition unit 56, a problem generation unit 58, an optimization processing unit 60, a selection unit 62, an update unit 64, and an output unit 66. If the CPU 401 consists of multiple processors, these parts may be divided among the multiple processors. Note that some or all of these components may be configured by hardware.

[0253] Furthermore, the solver device 34 may also be implemented by a computer with a hardware configuration such as that shown in Figure 23.

[0254] Furthermore, the processing unit (hardware processor) of the remapping device 40 may be implemented by one or more reconfigurable semiconductor devices, such as an FPGA (Field-Programmable Gate Array). Alternatively, the processing unit of the remapping device 40 may be implemented by one or more CPUs, microprocessors, GPUs (Graphics Processing Units), ASICs (Application Specific Integrated Circuits), or electronic circuits including these circuits.

[0255] Furthermore, if the processing unit of the remapping device 40 is implemented by a reconfigurable semiconductor device such as an FPGA, the circuit information (configuration data) written to the reconfigurable semiconductor device in order to operate it as the processing unit of the remapping device 40 may be stored on a computer connected to a network such as the Internet and provided by being downloaded via the network. Alternatively, the circuit information (configuration data) written to the reconfigurable semiconductor device in order to operate it as the processing unit of the remapping device 40 may be recorded on a computer-readable recording medium and provided.

[0256] Furthermore, if the processing unit of the remapping device 40 is implemented by a semiconductor device such as an ASIC, the circuit information representing the configuration of the circuit described in a hardware description language used for the design and manufacture of the processing unit of the remapping device 40 may be stored on a computer connected to a network such as the Internet and provided by being downloaded via the network. Alternatively, the circuit information representing the configuration of the circuit described in a hardware description language used for the design and manufacture of the processing unit of the remapping device 40 may be recorded on a computer-readable recording medium and provided.

[0257] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents.

[0258] <Note> Furthermore, this technology can also be configured as follows.

[0259] [Note 1] Equipped with a processing unit, The aforementioned processing unit, Based on first physical circuit information representing a first physical quantum circuit that causes a quantum computer containing multiple qubits to perform quantum operations, quantum circuit coupling information is generated that represents the coupling relationship of a pair of target qubits that perform a two-qubit gate operation on two or more target qubits included in the first physical quantum circuit. Calibration data is obtained for at least one of the plurality of qubits and at least one pair of the plurality of pairs of qubits capable of performing a two-qubit gate operation in the plurality of qubits, including an error rate representing the degree to which errors occur in the gate operation or a fidelity representing the degree to which the gate operation is performed as intended. Based on topology information representing the coupling relationships that enable the two-qubit gate operation in the plurality of qubits, quantum circuit coupling information, and calibration data, a combinatorial optimization problem and constraints are generated. Select the optimal solution that satisfies the constraints from among the one or more solutions obtained by solving the aforementioned combinatorial optimization problem. Based on the aforementioned optimal solution, second physical circuit information is generated that represents a second physical quantum circuit in which the correspondence between the plurality of qubits in the first physical quantum circuit and the two or more target qubits has been updated. Information processing device.

[0260] [Note 2] The processing unit provides the second physical circuit information to the quantum computer and causes the quantum computer to perform the quantum operation according to the second physical quantum circuit. The information processing device described in Appendix 1.

[0261] [Note 3] The calibration data changes over time. When the processing unit generates the second physical circuit information, it acquires the latest calibration data. The information processing device described in Appendix 1 or 2.

[0262] [Note 4] The first physical quantum circuit represents the correspondence between the plurality of qubits included in the quantum computer and two or more target qubits, and the execution order of single-bit gate operations for each of the two or more target qubits and two-qubit gate operations for each pair of one or more target qubits from the two or more target qubits. An information processing device as described in any one of the appendices 1 to 3.

[0263] [Note 5] The calibration data includes, for each of the plurality of qubits and for each of the plurality of operation types of the single-bit gate operation, the error rate or fidelity when the single-bit gate operation of the operation type corresponding to the corresponding qubit is performed. The information processing device described in Appendix 4.

[0264] [Note 6] The calibration data includes, for each of the plurality of pairs of qubits and for each of the one or more operation types of the two-qubit gate operation, the error rate or fidelity when the two-qubit gate operation of the operation type corresponding to the pair is performed. The information processing device described in Appendix 5.

[0265] [Note 7] The aforementioned quantum circuit coupling information is represented as a quantum circuit graph, The aforementioned topology information is a topology graph represented by a graph, The aforementioned combinatorial optimization problem is a problem of associating the quantum circuit graph with a subgraph of the topology graph, and the problem is to search for a correspondence that minimizes the composite error rate, which represents the degree to which errors occur when the quantum operation is performed on the portion of the plurality of qubits included in the quantum computer that corresponds to the subgraph, or maximizes the composite fidelity, which represents the degree to which the operation is performed as intended when the quantum operation is performed on the portion that corresponds to the subgraph. The aforementioned constraint is the condition that the subgraph is isomorphic to the quantum circuit graph. The information processing device described in Appendix 5 or 6.

[0266] [Note 8] The aforementioned quantum circuit graph is, Each of the two or more target qubits included in the first physical quantum circuit is represented by a node, and each of the one or more pairs of target qubits that perform a two-qubit gate operation is represented by an edge, The weight for the node includes, for each of the plurality of operation types, the number of times the single-bit gate operation is performed on the corresponding target qubit by the first physical quantum circuit, The weight for the edge includes, for each of the plurality of operation types, the number of times the two-qubit gate operation is performed on the corresponding pair of target qubits by the first physical quantum circuit. The information processing device described in Appendix 7.

[0267] [Note 9] The topology graph represents each of the plurality of qubits included in the quantum computer as a node, and each of the plurality of pairs of qubits capable of performing 2-qubit gate operations included in the quantum computer as an edge. The information processing device described in Appendix 8.

[0268] [Note 10] The aforementioned combinatorial optimization problem is a problem of minimizing the total cost function obtained by weighting and adding the penalty function that is minimized when the constraints are satisfied and the cost function, or a problem of maximizing the total cost function obtained by weighting and adding the penalty function that is maximized when the constraints are satisfied and the cost function. The aforementioned constraints are that the node set of the quantum circuit graph is an injective mapping to the node set of the topology graph, and the quantum circuit graph is a subgraph isomorphic to the topology graph. In the case of a problem to minimize the total cost function, the cost function represents the synthesis error rate when the physical quantum circuit represented by the quantum circuit graph is executed by the quantum computer. In the case of a problem to maximize the total cost function, the cost function represents the composite fidelity when the physical quantum circuit represented by the quantum circuit graph is executed by the quantum computer. The information processing device described in Appendix 9.

[0269] [Note 11] The total cost function is given by H in equation (8). total It is represented by, A, B, C, D, and E are predetermined real numbers greater than 0. H A and H B This is the penalty function that is minimized when the node set of the quantum circuit graph is an injective mapping to the node set of the topology graph, H CThis is the penalty function that is minimized when the quantum circuit graph is a subgraph isomorphic to the topology graph, (DH D +EH E ) is the aforementioned cost function, H D This represents the average error rate of the single-bit gate operation when the physical quantum circuit represented by the quantum circuit graph is executed by the quantum computer. H E This represents the average error rate of the two-qubit gate operation when the physical quantum circuit represented by the quantum circuit graph is executed by the quantum computer. The information processing device described in Appendix 10.

[0270] [Note 12] H A This is expressed by equation (9), H B This is expressed by equation (10), N1 is the number of nodes in the quantum circuit graph, N2 is the number of nodes in the topology graph, i and i' are indices that identify the nodes of the quantum circuit graph, and are integers greater than or equal to 0 and less than or equal to (N1-1). v is an index that identifies a node in the topology graph, and is an integer greater than or equal to 0 and less than or equal to (N2-1). x i,v This is a decision variable that represents 1 if the node identified by i in the quantum circuit graph corresponds to the node identified by v in the topology graph, and 0 if it does not correspond to the node. x i´,v This is a decision variable that represents 1 if the node identified by i' in the quantum circuit graph corresponds to the node identified by v in the topology graph, and 0 if it does not correspond to that node. The information processing device described in Appendix 11.

[0271] [Note 13] H CThis is expressed by equation (11), E1 is the set of edges of the quantum circuit graph, E2 is the set of edges of the topology graph, j is an index that identifies a node in the quantum circuit graph, and is an integer between 0 and (N1-1), u is an index that identifies a node in the topology graph, and is an integer greater than or equal to 0 and less than or equal to (N2-1). (i,j) is an edge representing a pair of nodes in the quantum circuit graph, where i is identified by i and j is identified by j. (u,v) is an edge representing a pair of nodes in the topology graph identified by u and identified by v, x i,u This is a decision variable that represents 1 if the node identified by i in the quantum circuit graph corresponds to the node identified by u in the topology graph, and 0 if it does not correspond to that node. x j,v This is a decision variable that represents 1 if the node identified by j in the quantum circuit graph corresponds to the node identified by v in the topology graph, and 0 if it does not correspond. The information processing device described in Appendix 12.

[0272] [Note 14] H D This is expressed by equation (12), H E This is expressed by equation (13), #instrs represents the total number of executions of the single-bit gate operation and the two-qubit gate operation. {instrs} represents a set of multiple operation types for the single bit gate operation, g represents an index that identifies the type of operation for the single bit gate operation, W i,g 1gThis represents the number of times a single-bit gate operation of the operation type identified by g is performed on the target qubit corresponding to the node identified by i in the quantum circuit graph. e v,g 1g This represents the error rate when performing the single-bit gate operation of the operation type identified by g on the qubit corresponding to the node identified by v in the topology graph. W i,j 2g This represents the number of times the two-qubit gate operation is performed on the pair of target qubits corresponding to the node identified by i in the quantum circuit graph and the target qubits corresponding to the node identified by j. e u,v 2g This represents the error rate when the two-qubit gate operation is performed on a pair of qubits corresponding to the node identified by u in the topology graph and the qubit corresponding to the node identified by v. An information processing device as described in any one of the appendices 11 to 13.

[0273] [Note 15] H D This is expressed by equation (16), H E This is expressed by equation (17), #instrs represents the total number of executions of the single-bit gate operation and the two-qubit gate operation. {instrs} represents a set of multiple operation types for the single bit gate operation, g represents an index that identifies the type of operation for the single bit gate operation, W i,g 1g This represents the number of times a single-bit gate operation of the operation type identified by g is performed on the target qubit corresponding to the node identified by i in the quantum circuit graph. e v,g 1gThis represents the error rate when performing the single-bit gate operation of the operation type identified by g on the qubit corresponding to the node identified by v in the topology graph. W i,j 2g This represents the number of times the two-qubit gate operation is performed on the pair of target qubits corresponding to the node identified by i in the quantum circuit graph and the target qubits corresponding to the node identified by j. e u,v 2g This represents the error rate when the two-qubit gate operation is performed on a pair of qubits corresponding to the node identified by u in the topology graph and the qubit corresponding to the node identified by v. An information processing device as described in any one of the appendices 11 to 13.

[0274] [Note 16] The processing unit executes a solution-finding process to solve the combinatorial optimization problem and generates the one or more solutions. An information processing device as described in any one of the appendices 1 through 15.

[0275] [Note 17] The processing unit generates first physical circuit information representing the first physical quantum circuit based on logic circuit information representing a logic quantum circuit representing the quantum operation or a quantum program representing the quantum operation. An information processing device as described in any one of the appendices 1 through 16.

[0276] [Note 18] A quantum computer containing multiple qubits, A quantum compilation device that generates first physical circuit information representing a first physical quantum circuit that causes the quantum computer to perform quantum operations, Equipped with, The quantum computer comprises a processing unit and a quantum computing unit that performs the quantum operations. The aforementioned processing unit, The first physical circuit information is obtained from the quantum compilation device, Based on the first physical circuit information, quantum circuit coupling information is generated that represents the coupling relationship of a pair of target qubits that perform a two-qubit gate operation in two or more target qubits included in the first physical quantum circuit. Calibration data is obtained for at least one of the plurality of qubits and at least one pair of the plurality of pairs of qubits capable of performing a two-qubit gate operation in the plurality of qubits, including an error rate representing the degree to which errors occur in the gate operation or a fidelity representing the degree to which the gate operation is performed as intended. Based on topology information representing the coupling relationships that enable the two-qubit gate operation in the plurality of qubits, quantum circuit coupling information, and calibration data, a combinatorial optimization problem and constraints are generated. Select the optimal solution that satisfies the constraints from among the one or more solutions obtained by solving the aforementioned combinatorial optimization problem. Based on the aforementioned optimal solution, second physical circuit information is generated representing a second physical quantum circuit in which the correspondence between the plurality of qubits in the first physical quantum circuit and the two or more target qubits has been updated. The quantum computing unit performs quantum operations according to the second physical quantum circuit. Quantum computer system.

[0277] [Note 19] Multiple quantum computers, each with the same architecture containing multiple qubits, Information processing device and Equipped with, The information processing device acquires calibration data from each of the plurality of quantum computers, The calibration data includes an error rate representing the degree to which errors occur in gate operations, or a fidelity representing the degree to which gate operations are performed as intended, for at least one of the plurality of qubits and at least one pair of a plurality of pairs of qubits capable of performing a two-qubit gate operation in the plurality of qubits. For each of the aforementioned plurality of quantum computers, the information processing device is: Based on first physical circuit information representing a first physical quantum circuit that causes a quantum computer containing multiple qubits to perform quantum operations, quantum circuit coupling information is generated that represents the coupling relationship of a pair of target qubits that perform a two-qubit gate operation on two or more target qubits included in the first physical quantum circuit. The calibration data mentioned above is obtained, Based on topology information representing the coupling relationships that enable the two-qubit gate operation in the plurality of qubits, quantum circuit coupling information, and calibration data, a combinatorial optimization problem and constraints are generated. Select the optimal solution that satisfies the constraints from among the one or more solutions obtained by solving the aforementioned combinatorial optimization problem. Based on the aforementioned optimal solution, second physical circuit information is generated representing a second physical quantum circuit in which the correspondence between the plurality of qubits in the first physical quantum circuit and the two or more target qubits has been updated. The aforementioned information processing device is Select one of the second physical circuit information for each of the aforementioned plurality of quantum computers, The selected second physical circuit information is output to the quantum computer corresponding to the selected second physical circuit information, and quantum operations are performed. Quantum computer system.

[0278] [Note 20] Information processing equipment Based on first physical circuit information representing a first physical quantum circuit that causes a quantum computer containing multiple qubits to perform quantum operations, quantum circuit coupling information is generated that represents the coupling relationship of a pair of target qubits that perform a two-qubit gate operation on two or more target qubits included in the first physical quantum circuit. Calibration data is obtained for at least one of the plurality of qubits and at least one pair of the plurality of pairs of qubits capable of performing a two-qubit gate operation in the plurality of qubits, including an error rate representing the degree to which errors occur in the gate operation or a fidelity representing the degree to which the gate operation is performed as intended. Based on topology information representing the coupling relationships that enable the two-qubit gate operation in the plurality of qubits, quantum circuit coupling information, and calibration data, a combinatorial optimization problem and constraints are generated. Select the optimal solution that satisfies the constraints from among the one or more solutions obtained by solving the aforementioned combinatorial optimization problem. Based on the aforementioned optimal solution, second physical circuit information is generated that represents a second physical quantum circuit in which the correspondence between the plurality of qubits in the first physical quantum circuit and the two or more target qubits has been updated. Information processing methods.

[0279] [Note 21] Information processing equipment, Based on first physical circuit information representing a first physical quantum circuit that causes a quantum computer containing multiple qubits to perform quantum operations, quantum circuit coupling information is generated that represents the coupling relationship of a pair of target qubits that perform a two-qubit gate operation on two or more target qubits included in the first physical quantum circuit. Calibration data is obtained for at least one of the plurality of qubits and at least one pair of the plurality of pairs of qubits capable of performing a two-qubit gate operation in the plurality of qubits, including an error rate representing the degree to which errors occur in the gate operation or a fidelity representing the degree to which the gate operation is performed as intended. Based on topology information representing the coupling relationships that enable the two-qubit gate operation in the plurality of qubits, quantum circuit coupling information, and calibration data, a combinatorial optimization problem and constraints are generated. Select the optimal solution that satisfies the constraints from among the one or more solutions obtained by solving the aforementioned combinatorial optimization problem. Based on the aforementioned optimal solution, second physical circuit information is generated that represents a second physical quantum circuit in which the correspondence between the plurality of qubits in the first physical quantum circuit and the two or more target qubits has been updated. A program that makes it work in that way. [Explanation of symbols]

[0280] 10 Quantum Computer Systems 20 Quantum Computers 30 Information Processing Devices 32 Quantum Compilation Device 34 Solver device 40 Remapping device 52 Topology Graph Generation Unit 54 Quantum Circuit Graph Generation Unit 56 Calibration data acquisition unit 58 Problem generation part 60 Optimization Processing Unit 62 Selection Section 64 Update section Output section of 66 70 Selector

Claims

1. Equipped with a processing unit, The aforementioned processing unit, Based on first physical circuit information representing a first physical quantum circuit that causes a quantum computer containing multiple qubits to perform quantum operations, quantum circuit coupling information is generated that represents the coupling relationship of a pair of two target qubits that perform a two-qubit gate operation on two or more target qubits included in the first physical quantum circuit. Calibration data is obtained for at least one of the plurality of qubits and at least one pair of the plurality of pairs of qubits capable of performing a two-qubit gate operation in the plurality of qubits, including an error rate representing the degree to which errors occur in the gate operation or a fidelity representing the degree to which the gate operation is performed as intended. Based on topology information representing the coupling relationships that enable the two-qubit gate operation in the plurality of qubits, quantum circuit coupling information, and calibration data, a combinatorial optimization problem and constraints are generated. Select the optimal solution that satisfies the constraints from among the one or more solutions obtained by solving the aforementioned combinatorial optimization problem. Based on the aforementioned optimal solution, second physical circuit information is generated that represents a second physical quantum circuit in which the correspondence between the plurality of qubits in the first physical quantum circuit and the two or more target qubits has been updated. Information processing device.

2. The processing unit provides the second physical circuit information to the quantum computer and causes the quantum computer to perform the quantum operation according to the second physical quantum circuit. The information processing apparatus according to claim 1.

3. The calibration data changes over time. When the processing unit generates the second physical circuit information, it acquires the latest calibration data. The information processing apparatus according to claim 1.

4. The first physical quantum circuit represents the correspondence between the plurality of qubits included in the quantum computer and two or more target qubits, and the execution order of single-bit gate operations for each of the two or more target qubits and two-qubit gate operations for each pair of one or more target qubits from the two or more target qubits. The information processing apparatus according to claim 1.

5. The calibration data includes, for each of the plurality of qubits and for each of the plurality of operation types of the single-bit gate operation, the error rate or fidelity when the single-bit gate operation of the operation type corresponding to the corresponding qubit is performed. The information processing apparatus according to claim 4.

6. The calibration data includes, for each of the plurality of pairs of qubits and for each of the one or more operation types of the two-qubit gate operation, the error rate or fidelity when the two-qubit gate operation of the operation type corresponding to the pair is performed. The information processing apparatus according to claim 5.

7. The aforementioned quantum circuit coupling information is represented as a quantum circuit graph, The aforementioned topology information is a topology graph represented by a graph, The aforementioned combinatorial optimization problem is a problem of associating the quantum circuit graph with a subgraph of the topology graph, and the problem is to search for a correspondence that minimizes the composite error rate, which represents the degree to which errors occur when the quantum operation is performed on the portion of the plurality of qubits included in the quantum computer that corresponds to the subgraph, or maximizes the composite fidelity, which represents the degree to which the operation is performed as intended when the quantum operation is performed on the portion that corresponds to the subgraph. The aforementioned constraint is the condition that the subgraph is isomorphic to the quantum circuit graph. The information processing apparatus according to claim 5.

8. The aforementioned quantum circuit graph is, Each of the two or more target qubits included in the first physical quantum circuit is represented by a node, and each of the one or more pairs of target qubits that perform a two-qubit gate operation is represented by an edge, The weight for the node includes, for each of the plurality of operation types, the number of times the single-bit gate operation is performed on the corresponding target qubit by the first physical quantum circuit, The weight for the edge includes, for each of the plurality of operation types, the number of times the two-qubit gate operation is performed on the corresponding pair of target qubits by the first physical quantum circuit. The information processing apparatus according to claim 7.

9. The topology graph represents each of the plurality of qubits included in the quantum computer as a node, and each of the plurality of pairs of qubits capable of performing two-qubit gate operations included in the quantum computer as an edge. The information processing apparatus according to claim 8.

10. The aforementioned combinatorial optimization problem is a problem of minimizing the total cost function obtained by weighting and adding the penalty function that is minimized when the constraints are satisfied and the cost function, or a problem of maximizing the total cost function obtained by weighting and adding the penalty function that is maximized when the constraints are satisfied and the cost function. The aforementioned constraints are that the node set of the quantum circuit graph is an injective mapping to the node set of the topology graph, and the quantum circuit graph is a subgraph isomorphic to the topology graph. In the case of a problem to minimize the total cost function, the cost function represents the synthesis error rate when the physical quantum circuit represented by the quantum circuit graph is executed by the quantum computer. In the case of a problem to maximize the total cost function, the cost function represents the composite fidelity when the physical quantum circuit represented by the quantum circuit graph is executed by the quantum computer. The information processing apparatus according to claim 9.

11. The total cost function is given by H in equation (1). ｔｏｔａｌ It is represented by, [Math 1] A, B, C, D, and E are predetermined real numbers greater than 0. H Ａ and H Ｂ This is the penalty function that is minimized when the node set of the quantum circuit graph is an injective map to the node set of the topology graph, H Ｃ This is the penalty function that is minimized when the quantum circuit graph is a subgraph isomorphic to the topology graph, (DH Ｄ +EH Ｅ ) is the aforementioned cost function, H Ｄ This represents the average error rate of the single-bit gate operation when the physical quantum circuit represented by the quantum circuit graph is executed by the quantum computer. H Ｅ This represents the average error rate of the two-qubit gate operation when the physical quantum circuit represented by the quantum circuit graph is executed by the quantum computer. The information processing apparatus according to claim 10.

12. H Ａ is represented by formula (2), H Ｂ This is expressed by equation (3), [Math 2] [Math 3] N １ This is the number of nodes in the quantum circuit graph, N ２ This is the number of nodes in the topology graph, i and i' are indices that identify the nodes of the quantum circuit graph, and are greater than or equal to (N). １ -1) An integer less than or equal to the following: v is an index that identifies a node in the topology graph, and is greater than or equal to (N). ２ -1) An integer less than or equal to the following: x ｉ，ｖ This is a decision variable that represents 1 if the node identified by i in the quantum circuit graph corresponds to the node identified by v in the topology graph, and 0 if it does not correspond to the node. x ｉ´，ｖ This is a decision variable that represents 1 if the node identified by i' in the quantum circuit graph corresponds to the node identified by v in the topology graph, and 0 if it does not correspond. The information processing apparatus according to claim 11.

13. H Ｃ This is expressed by equation (4), [Math 4] E １ This is the set of edges of the quantum circuit graph, E ２ This is the set of edges of the topology graph, j is an index that identifies a node in the quantum circuit graph, and is greater than or equal to (N). １ -1) An integer less than or equal to the following: u is an index that identifies a node in the topology graph, and is greater than or equal to (N). ２ -1) An integer less than or equal to the following: (i, j) is an edge representing a pair of nodes in the quantum circuit graph, where i is identified by i and j is identified by j. (u, v) is an edge representing a pair of nodes in the topology graph identified by u and identified by v, x ｉ，ｕ This is a decision variable that represents 1 if the node identified by i in the quantum circuit graph corresponds to the node identified by u in the topology graph, and 0 if it does not correspond to that node. x ｊ，ｖ This is a decision variable that represents 1 if the node identified by j in the quantum circuit graph corresponds to the node identified by v in the topology graph, and 0 if they do not correspond. The information processing apparatus according to claim 12.

14. H Ｄ This is expressed by equation (5), H Ｅ This is expressed by equation (6), [Math 5] [Math 6] #instruments represents the total number of executions of the single-bit gate operation and the two-qubit gate operation. {instruments} represents a set of multiple operation types for the single bit gate operation, g represents an index that identifies the type of operation for the single bit gate operation, W ｉ，ｇ １ｇ This represents the number of times a single-bit gate operation of the operation type identified by g is performed on the target qubit corresponding to the node identified by i in the quantum circuit graph. e ｖ，ｇ １ｇ This represents the error rate when performing the single-bit gate operation of the operation type identified by g on the qubit corresponding to the node identified by v in the topology graph. W ｉ，ｊ ２ｇ This represents the number of times the two-qubit gate operation is performed on the pair of target qubits corresponding to the node identified by i in the quantum circuit graph and target qubits corresponding to the node identified by j. e ｕ，ｖ ２ｇ This represents the error rate when the two-qubit gate operation is performed on a pair of qubits corresponding to the node identified by u in the topology graph and the qubit corresponding to the node identified by v. The information processing apparatus according to claim 11.

15. H Ｄ This is expressed by equation (7), H Ｅ This is expressed by equation (8), [Number 7] [Number 8] #instruments represents the total number of executions of the single-bit gate operation and the two-qubit gate operation. {instruments} represents a set of multiple operation types for the single bit gate operation, g represents an index that identifies the type of operation for the single bit gate operation, W ｉ，ｇ １ｇ This represents the number of times a single-bit gate operation of the operation type identified by g is performed on the target qubit corresponding to the node identified by i in the quantum circuit graph. e ｖ，ｇ １ｇ This represents the error rate when performing the single-bit gate operation of the operation type identified by g on the qubit corresponding to the node identified by v in the topology graph. W ｉ，ｊ ２ｇ This represents the number of times the two-qubit gate operation is performed on the pair of target qubits corresponding to the node identified by i in the quantum circuit graph and target qubits corresponding to the node identified by j. e ｕ，ｖ ２ｇ This represents the error rate when the two-qubit gate operation is performed on a pair of qubits corresponding to the node identified by u in the topology graph and the qubit corresponding to the node identified by v. The information processing apparatus according to claim 11.

16. The processing unit executes a solution-finding process to solve the combinatorial optimization problem and generates one or more solutions. The information processing apparatus according to claim 1.

17. The processing unit generates first physical circuit information representing the first physical quantum circuit based on logic circuit information representing a logic quantum circuit representing the quantum operation or a quantum program representing the quantum operation. The information processing apparatus according to claim 1.

18. A quantum computer containing multiple qubits, A quantum compilation device that generates first physical circuit information representing a first physical quantum circuit that causes the quantum computer to perform quantum operations, Equipped with, The quantum computer comprises a processing unit and a quantum computing unit that performs the quantum operations. The aforementioned processing unit, The first physical circuit information is obtained from the quantum compilation device, Based on the first physical circuit information, quantum circuit coupling information is generated that represents the coupling relationship of a pair of target qubits that perform a two-qubit gate operation in two or more target qubits included in the first physical quantum circuit. Calibration data is obtained for at least one of the plurality of qubits and at least one pair of the plurality of pairs of qubits capable of performing a two-qubit gate operation in the plurality of qubits, including an error rate representing the degree to which errors occur in the gate operation or a fidelity representing the degree to which the gate operation is performed as intended. Based on topology information representing the coupling relationships that enable the two-qubit gate operation in the plurality of qubits, quantum circuit coupling information, and calibration data, a combinatorial optimization problem and constraints are generated. Select the optimal solution that satisfies the constraints from among the one or more solutions obtained by solving the aforementioned combinatorial optimization problem. Based on the aforementioned optimal solution, second physical circuit information is generated representing a second physical quantum circuit in which the correspondence between the plurality of qubits in the first physical quantum circuit and the two or more target qubits has been updated. The quantum computing unit performs quantum operations according to the second physical quantum circuit. Quantum computer system.

19. Multiple quantum computers, each with the same architecture containing multiple qubits, Information processing device and Equipped with, The information processing device acquires calibration data from each of the plurality of quantum computers, The calibration data includes an error rate representing the degree to which errors occur in gate operations, or a fidelity representing the degree to which gate operations are performed as intended, for at least one of the plurality of qubits and at least one of the plurality of pairs of qubits capable of performing two-qubit gate operations in the plurality of qubits. For each of the aforementioned quantum computers, the information processing device is: Based on first physical circuit information representing a first physical quantum circuit that causes a quantum computer containing multiple qubits to perform quantum operations, quantum circuit coupling information is generated that represents the coupling relationship of a pair of two target qubits that perform a two-qubit gate operation on two or more target qubits included in the first physical quantum circuit. The calibration data is obtained, Based on topology information representing the coupling relationships that enable the two-qubit gate operation in the plurality of qubits, quantum circuit coupling information, and calibration data, a combinatorial optimization problem and constraints are generated. Select the optimal solution that satisfies the constraints from among the one or more solutions obtained by solving the aforementioned combinatorial optimization problem. Based on the aforementioned optimal solution, second physical circuit information is generated representing a second physical quantum circuit in which the correspondence between the plurality of qubits in the first physical quantum circuit and the two or more target qubits has been updated. The aforementioned information processing device is Select one of the second physical circuit information for each of the aforementioned plurality of quantum computers, The selected second physical circuit information is output to the quantum computer corresponding to the selected second physical circuit information, and quantum computation is performed. Quantum computer system.

20. Information processing equipment Based on first physical circuit information representing a first physical quantum circuit that causes a quantum computer containing multiple qubits to perform quantum operations, quantum circuit coupling information is generated that represents the coupling relationship of a pair of two target qubits that perform a two-qubit gate operation on two or more target qubits included in the first physical quantum circuit. Calibration data is obtained for at least one of the plurality of qubits and at least one pair of the plurality of pairs of qubits capable of performing a two-qubit gate operation in the plurality of qubits, including an error rate representing the degree to which errors occur in the gate operation or a fidelity representing the degree to which the gate operation is performed as intended. Based on topology information representing the coupling relationships that enable the two-qubit gate operation in the plurality of qubits, quantum circuit coupling information, and calibration data, a combinatorial optimization problem and constraints are generated. Select the optimal solution that satisfies the constraints from among the one or more solutions obtained by solving the aforementioned combinatorial optimization problem. Based on the aforementioned optimal solution, second physical circuit information is generated that represents a second physical quantum circuit in which the correspondence between the plurality of qubits in the first physical quantum circuit and the two or more target qubits has been updated. Information processing methods.

21. Information processing equipment, Based on first physical circuit information representing a first physical quantum circuit that causes a quantum computer containing multiple qubits to perform quantum operations, quantum circuit coupling information is generated that represents the coupling relationship of a pair of two target qubits that perform a two-qubit gate operation on two or more target qubits included in the first physical quantum circuit. Calibration data is obtained for at least one of the plurality of qubits and at least one pair of the plurality of pairs of qubits capable of performing a two-qubit gate operation in the plurality of qubits, including an error rate representing the degree to which errors occur in the gate operation or a fidelity representing the degree to which the gate operation is performed as intended. Based on topology information representing the coupling relationships that enable the two-qubit gate operation in the plurality of qubits, quantum circuit coupling information, and calibration data, a combinatorial optimization problem and constraints are generated. Select the optimal solution that satisfies the constraints from among the one or more solutions obtained by solving the aforementioned combinatorial optimization problem. Based on the aforementioned optimal solution, second physical circuit information is generated that represents a second physical quantum circuit in which the correspondence between the plurality of qubits in the first physical quantum circuit and the two or more target qubits has been updated. A program that makes it work in that way.

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