Memory systems and memory controllers

Abstract

This provides a memory system that can appropriately control the writing method. [Solution] According to the embodiment, the memory system includes a non-volatile memory and a memory controller that controls the non-volatile memory. The memory controller is configured to have two methods for writing data to the non-volatile memory: a first writing method that writes 1 bit of data to each memory cell, and a second writing method that writes N bits of data to each memory cell. When the capacity of the write data is less than or equal to a threshold related to the execution of garbage collection processing, the write data is written to the non-volatile memory using the first writing method. When the capacity of the write data exceeds the threshold, at least (amount exceeding the threshold) + ((amount exceeding the threshold) / (N-1)) of the write data is written to the non-volatile memory using the second writing method, and the remaining write data is written to the non-volatile memory using the first writing method.

Description

Technical Field

[0001] Embodiments of the present invention relate to a memory system and a memory controller.

Background Art

[0002] In recent years, memory systems equipped with flash memory have become widespread. Currently, memory systems support, for example, the write method of SLC (Single Level Cell) in addition to the write method of TLC (Triple Level Cell) in TLC products. Also, in QLC (Quad Level Cell) products, the write method of SLC is supported in addition to the write method of QLC.

[0003] Compared with TLC writing and QLC writing, SLC writing has high sequential write performance. Therefore, among TLC products and QLC products, there are also those equipped with a function such as WB (Write Booster) to utilize the high sequential write performance of SLC writing as needed.

[0004] However, there are concerns about SLC writing regarding the deterioration of WAF (Write Amplification Factor) and the performance degradation due to GC (Garbage Collection) caused by the tightness of the physical capacity of the flash memory.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

[0006] One embodiment of the present invention provides a memory system and a memory controller capable of appropriately controlling the writing method. [Means for solving the problem]

[0007] According to one embodiment, the memory system comprises a non-volatile memory and a memory controller. The non-volatile memory has multiple blocks, each containing multiple memory cells. The memory controller is connectable to a host and controls the non-volatile memory. The memory controller supports two methods for writing data to non-volatile memory: a first writing method that writes 1 bit of data to each memory cell, and a second writing method that writes N bits (where N is a natural number greater than or equal to 2) of data to each memory cell. When the controller receives a write command from the host that should apply the first writing method, it determines whether the amount of data to be written exceeds a threshold obtained by subtracting a predetermined value indicating the remaining capacity of non-volatile memory at which garbage collection processing to increase the remaining capacity of non-volatile memory occurs, from the remaining capacity of non-volatile memory. If the amount of data to be written is less than or equal to the threshold, the data is written to the non-volatile memory using the first writing method. If the amount of data to be written exceeds the threshold, at least (amount exceeding the threshold) + ((amount exceeding the threshold) / (N-1)) of data is written to the non-volatile memory using the second writing method, and the remaining data is written to the non-volatile memory using the first writing method. [Brief explanation of the drawing]

[0008] [Figure 1] A diagram showing an example configuration of the memory system of the first embodiment. [Figure 2] This figure shows an example of a comparison of write times between SLC writing (with garbage collection) and MLC writing (without garbage collection). [Figure 3] A flowchart showing the data writing process flow of the memory system in the first embodiment. [Figure 4] A diagram showing an example configuration of the memory system of the second embodiment. [Figure 5] A flowchart showing the data writing process flow of the memory system in the second embodiment. [Figure 6] A diagram showing an example configuration of the memory system according to the third embodiment. [Figure 7] This figure shows an example of a writing method to flash memory determined by a first flag (fWriteBoosterEn flag) and a second flag (fWriteBoosterMLC flag) in the memory system of the third embodiment. [Figure 8] A flowchart showing the data writing process flow of the memory system in the third embodiment. [Figure 9] A diagram showing an example configuration of the memory system according to the fourth embodiment. [Figure 10] A diagram showing an example of a table for selecting the writing method of the memory system in the fourth embodiment. [Figure 11] This diagram shows the transfer performance of each device for each gear (HS-GEAR) as defined by the UFS (Universal Flash Storage) 4.0 standard. [Figure 12] A diagram showing the maximum light performance for each gear. [Figure 13] A diagram showing the light performance of each gear in each writing method. [Figure 14] A flowchart showing the data writing process flow of the memory system in the fourth embodiment. [Figure 15] A flowchart showing a modified example of the data writing process of the memory system according to the fourth embodiment. [Figure 16] A flowchart showing the data writing process flow of the memory system according to the fifth embodiment. [Modes for carrying out the invention]

[0009] The embodiments will be described below with reference to the drawings.

[0010] (First Embodiment) First, the first embodiment will be described.

[0011] FIG. 1 is a diagram showing a configuration example of a memory system 1 according to the first embodiment. FIG. 1 shows a memory system 1 connected to a host 2 and constituting an information processing system together with the host 2. The host 2 is an information processing device such as a personal computer or a server.

[0012] The memory system 1 includes a controller (memory controller) 10 and a flash memory 20.

[0013] The controller 10 is a device that controls the flash memory 20. Specifically, the controller 10 controls the data writing process to the flash memory 20 or the data reading process from the flash memory 20 in response to a command from the host 2. The controller 10 may spontaneously control the data writing process to the flash memory 20 or the data reading process from the flash memory 20 regardless of a command from the host 2 for the management of the flash memory 20. The controller 10 is realized as a SoC (System on a Chip) or the like.

[0014] The flash memory 20 is a non-volatile storage medium having a characteristic that data cannot be overwritten to an area where data has already been written. Therefore, the update of the data stored in the flash memory 20 is performed by invalidating the old data and writing the new data to another area. The area where the invalidated data is stored becomes reusable by performing an erase process. The flash memory 20 has a plurality of blocks each including a plurality of memory cells. The erase process is executed in block units. A block in which the erase process has been performed and the entire area is in a state where data can be written is called a free block or the like. Note that the data writing to the flash memory 20 is executed in page units, each of which is included in a predetermined number in each block.

[0015] The flash memory 20 is divided into a system data storage area 21 and a user data storage area 22 under the control of the controller 10. The user data storage area 22 is provided to the host 2. The system data storage area 21 stores data used by the controller 10 for controlling the entire memory system 1.

[0016] The controller 10 includes a host interface unit (host I / F unit) 11, a memory interface unit (memory I / F unit) 12, a read / write processing unit (RW processing unit) 13, a memory area management unit 14, and a GC processing unit 15. Here, we show an example in which the host I / F unit 11 and the memory I / F unit 12 of the controller 10 are implemented by hardware such as electrical circuits, and the RW processing unit 13, the memory area management unit 14, and the GC processing unit 15 are implemented by a CPU (Central Processing Unit) 100 built into the controller 10 executing a program called firmware or the like. The RW processing unit 13, the memory area management unit 14, and the GC processing unit 15 may also be implemented by hardware such as electrical circuits, similar to the host I / F unit 11 and the memory I / F unit 12.

[0017] The host I / F unit 11 is, for example, PCIe TM Connects to host 2 via a standard-compliant interface, NVMe TM This controls communication with host 2 using a protocol compliant with the standard.

[0018] The memory interface unit 12 controls the writing of data to the flash memory 20 and the reading of data from the flash memory 20.

[0019] When a read command is received by the host interface unit 11, the RW processing unit 13 reads the data to be read (read data) from the flash memory 20 via the memory interface unit 12. The RW processing unit 13 then transmits the read data read from the flash memory 20 by the memory interface unit 12 to the host 2 via the host interface unit 11.

[0020] Furthermore, when the RW processing unit 13 receives a write command from the host I / F unit 11, it writes the data to be written (write data) to the flash memory 20 via the memory I / F unit 12. When the RW processing unit 13 successfully writes the write data to the flash memory 20, it notifies the host 2 of the completion of the write via the host I / F unit 11.

[0021] The RW processing unit 13 has a WB unit 131. The WB unit 131 is a module provided to realize the functions of WB and manages a first flag (fWriteBoosterEn flag) that indicates the writing method to be applied by the RW processing unit 13. The first flag is a flag that conforms to the current WB specifications.

[0022] The flash memory 20 has multiple blocks, each containing multiple memory cells. The RW processing unit 13, in cooperation with the memory I / F unit 12, can perform SLC writing, which writes 1 bit of data to each memory cell of the flash memory 20, or MLC (Multi-Level Cell) writing, which writes 2 bits of data to each memory cell of the flash memory 20. The RW processing unit 13 writes the write data to the flash memory 20 using SLC writing while the first flag is on. When the first flag is off, the RW processing unit 13 writes the write data to the flash memory 20 using MLC writing. The following describes an example in which the memory system 1 of the embodiment supports both SLC writing and MLC writing, but it is not limited to this. For example, it may support SLC writing and TLC writing, which writes 3 bits of data to each memory cell. Alternatively, it may support all three: SLC writing, MLC writing, and TLC writing. Hereinafter, SLC writing due to the first flag being on may be referred to as writing by WB, etc.

[0023] Furthermore, from here on, the write performance of each writing method will be assumed to be 3800 MiBps for SLC writing, 2500 MiBps for MLC writing, 835 MiBps for TLC writing, and 69 MiBps for QLC writing. The write performance of a writing method indicates the writing capability per unit of time.

[0024] The first flag managed by the WB unit 131 can be switched on or off by a command called QUERY REQUEST. In other words, host 2 can specify whether to write the write data to the flash memory 20 using SLC writing or MLC writing. Specifically, host 2 can select SLC writing by switching the first flag on as needed.

[0025] SLC writing offers higher sequential write performance compared to MLC writing. However, SLC writing consumes twice the memory space of MLC writing, which can lead to performance degradation due to garbage collection (GC). Therefore, in the memory system 1 of the first embodiment, when SLC writing is specified during the period when the first flag is ON, if writing the entire data using SLC would potentially lead to performance degradation, the system voluntarily changes part or all of the data to be written using MLC writing to suppress performance degradation. This point will be discussed later.

[0026] The memory area management unit 14 manages the state of the flash memory 20. As information indicating the state of the flash memory 20, the memory area management unit 14 manages, for example, the remaining capacity of the flash memory 20.

[0027] The GC processing unit 15 executes GC processing to generate free blocks when the remaining capacity of the flash memory 20, which is managed by the memory area management unit 14, falls below a predetermined value. The GC processing generates (number of source blocks)-1 free blocks by, for example, moving valid data from two or more blocks where invalid data occupies a large proportion of the area into one block. Information regarding the proportion of the area where invalid data is stored in each block is managed by the memory area management unit 14.

[0028] As mentioned above, the memory area management unit 14 manages the remaining capacity of the flash memory 20. Therefore, it can calculate how much more memory area needs to be consumed before the remaining capacity of the flash memory 20 falls below a predetermined value. When the RW processing unit 13 writes data to the flash memory 20 using SLC during the period when the first flag is on, it first subtracts a predetermined value from the remaining capacity of the flash memory 20 to calculate a threshold that indicates the amount of data that can be written using SLC without generating garbage collection (GC). Next, the RW processing unit 13 determines whether the amount of data to be written exceeds the calculated threshold. If the amount of data to be written exceeds the threshold, the RW processing unit 13 decides to combine SLC writing and MLC writing to perform the maximum amount of SLC writing within the range that does not generate GC.

[0029] Specifically, the RW processing unit 13 writes twice the amount exceeding the threshold to MLC and the remainder to SLC. The order of MLC writing and SLC writing does not matter. By changing a portion to MLC writing to avoid garbage collection, the memory system 1 of the first embodiment can suppress performance degradation compared to when the entire write data is written to SLC as specified.

[0030] Through the above control, if GC can be executed and completed after writing the write data to the flash memory 20 without generating garbage collection (GC), and before the next write command is received from host 2, then GC will not occur during the writing of the next data, and performance degradation can be suppressed. Even if the next write command is received from host 2 in the middle of GC, the impact of GC can be mitigated.

[0031] Figure 2 shows an example of a comparison of write times between SLC writing (with garbage collection) and MLC writing (without garbage collection).

[0032] Here, we consider a case where, during a 5 GiB write operation using WB, the GC threshold is exceeded when 4 GiB has been written using SLC. In this case, in the memory system 1 of the first embodiment, for example, 3 GiB is written using SLC and the remaining 2 GiB is written using MLC (Figure 2: symbol a1). If the entire 5 GiB is written using SLC as shown by symbol a2, it will trigger GC and actually lead to a decrease in performance.

[0033] Furthermore, if the memory system 1 of the first embodiment supports both SLC writing and TLC writing, the RW processing unit 13 should write (amount exceeding the threshold) + ((amount exceeding the threshold) / 2) in the write data using TLC. In other words, if the memory system 1 of the first embodiment supports both SLC writing and a writing method in which N bits of data are written to each memory cell of the flash memory 20, the RW processing unit 13 should write (amount exceeding the threshold) + ((amount exceeding the threshold) / N-1) in the write data using the latter writing method.

[0034] Figure 3 is a flowchart showing the data writing process of the memory system 1 in the first embodiment.

[0035] The RW processing unit 13 determines whether the first flag (fWriteBoosterEn flag) is on or off (S101). If the first flag is off (S101: NO), the RW processing unit 13 writes the entire write data to the flash memory 20 using MLC (S102). Note that even if the first flag is off, SLC writing may still occur if other conditions for SLC writing are met, but here we will focus only on WB.

[0036] If the first flag is on (S101:YES), the RW processing unit 13 determines whether the amount of write data exceeds a threshold (S103). The threshold is the amount of data that can be written by SLC without generating garbage collection. If the amount of write data does not exceed the threshold (S103:NO), the RW processing unit 13 writes the entire write data to the flash memory 20 by SLC (S104).

[0037] If the amount of write data exceeds the threshold (S103: YES), the RW processing unit 13 writes twice the excess amount of write data to the flash memory 20 using MLC (S105) and writes the remaining write data to the flash memory 20 using SLC (S106). The order of the MLC write in S105 and the SLC write in S106 may be reversed.

[0038] As described above, in the memory system 1 of the first embodiment, when SLC writing is specified during the period when the first flag is ON, if writing the entire write data using SLC may actually lead to a performance degradation, the system suppresses the performance degradation by changing part or all of the write data to MLC writing.

[0039] In other words, the memory system 1 of the first embodiment can appropriately control the writing method.

[0040] (Second Embodiment) Next, a second embodiment will be described.

[0041] Figure 4 shows an example configuration of the memory system 1-2 of the second embodiment. The same reference numerals are used for the same components as in the memory system 1 of the first embodiment, and their descriptions are omitted.

[0042] The controller 10-2 of the second embodiment has a command analysis unit 16 in addition to the configuration of the controller 10 of the first embodiment. Here, an example is shown in which the command analysis unit 16 is implemented by the CPU 100 executing a program such as firmware, but the command analysis unit 16 may also be implemented by hardware such as an electrical circuit.

[0043] When a write command is received from the host 2, the command analysis unit 16 analyzes the write command or any functions associated with it to determine whether or not SLC writing should be applied. In the memory system 1 of the first embodiment, the decision of whether or not SLC writing should be applied to a write command from the host 2 is based on whether or not the first flag (fWriteBoosterEn flag) is on. In contrast, in the memory system 1-2 of the second embodiment, if the first flag is off, the command analysis unit 16 further determines whether or not SLC writing should be applied to a write command from the host 2.

[0044] For example, FUA (Force Unit Access) is a parameter that can instruct the system to quickly devolve the write data instead of storing it in the cache. Specifically, by setting FUA to "1" and associating it with a write command, the system can instruct the system to quickly devolve the write data. The command analysis unit 16 determines that SLC writing should be applied to write commands that are associated with FUA set to "1". In addition to FUA, the command analysis unit 16 can maintain various other determination conditions.

[0045] If the command analysis unit 16 determines that SLC writing should be applied, the RW processing unit 13-2, similar to the memory system 1 of the first embodiment, determines whether the amount of write data for that write command exceeds a threshold. If the amount of write data does not exceed the threshold, the RW processing unit 13 decides to write the entire write data using SLC. On the other hand, if the amount of write data exceeds the threshold, the RW processing unit 13 decides to combine SLC writing and MLC writing to perform the maximum amount of SLC writing within the range that does not cause garbage collection. The respective write amounts for SLC and MLC are calculated in the same way as in the memory system 1 of the first embodiment.

[0046] Figure 5 is a flowchart showing the data writing process flow of the memory system 1-2 of the second embodiment. Here, we take the case where the memory system 1-2 of the second embodiment supports both SLC writing and MLC writing as an example.

[0047] The command analysis unit 16 analyzes the write command from the host 2 (S201). If the command analysis unit 16 does not determine that SLC writing should be applied (S202: NO), the RW processing unit 13 writes the entire write data to the flash memory 20 using MLC (S203).

[0048] If the analysis determines that SLC writing should be applied (S202:YES), the RW processing unit 13 determines whether the amount of data to be written exceeds a threshold (S204). The threshold is the amount of data that can be written using SLC without generating garbage collection. If the amount of data to be written does not exceed the threshold (S204:NO), the RW processing unit 13 writes the entire amount of data to the flash memory 20 using SLC (S205).

[0049] If the amount of write data exceeds the threshold (S204: YES), the RW processing unit 13 writes twice the excess amount of write data to the flash memory 20 using MLC (S206) and writes the remaining write data to the flash memory 20 using SLC (S207). The order of the TLC write in S206 and the SLC write in S207 may be reversed.

[0050] As described above, in the memory system 1-2 of the second embodiment, when a write command that should be written using SLC is received, if writing the entire write data using SLC may actually lead to a performance degradation, the system suppresses the performance degradation by changing part or all of the write data to be written using MLC, similar to the memory system 1 of the first embodiment.

[0051] In other words, the memory system 1-2 of the second embodiment can also appropriately control the writing method.

[0052] (Third embodiment) Next, a third embodiment will be described.

[0053] Figure 6 shows an example configuration of the memory system 1-3 of the third embodiment. The same reference numerals are used for the same components as in the memory system 1 of the first embodiment, and their descriptions are omitted.

[0054] In the third embodiment, the controller 10-3 has an extended WB unit 132 in the RW processing unit 13-3. The extended WB unit 132 is a module provided to extend the WB functionality realized by the WB unit 131, and manages a second flag (fWriteBoosterMLC flag). The second flag is a flag that is not present in the current WB specification and has been uniquely added in the memory system 1-3 of the third embodiment.

[0055] The second flag is a flag that functions when the first flag (fWriteBoosterEn flag) is on. When the first flag is off, the second flag is also off. Like the first flag, the second flag can also be switched on / off by a command from host 2.

[0056] If the first flag is on and the second flag is off, the RW processing unit 13-3 writes the write data requested by the write command to the flash memory 20 by SLC writing, in accordance with the current WB specifications.

[0057] On the other hand, if both the first flag and the second flag are on, the RW processing unit 13-3 writes the write data requested by the write command to the flash memory 20 by MLC writing. In other words, the memory system 1-3 of the third embodiment enables the host 2 to instruct not only SLC writing but also MLC writing.

[0058] If the first flag is off, the RW processing unit 13-3 basically writes the write data requested by the write command to the flash memory 20 using MLC writing. However, there are no specification constraints, and the RW processing unit 13-2 can also perform SLC writing, and if TLC writing is supported, it can also perform TLC writing.

[0059] Note that the memory area management unit 14 and the GC processing unit 15 are omitted in Figure 6. This does not mean that the controller 10-3 of the third embodiment does not have a memory area management unit 14 and a GC processing unit 15.

[0060] Figure 7 shows an example of a writing method to the flash memory 20 determined by the first flag (fWriteBoosterEn flag) and the second flag (fWriteBoosterMLC flag).

[0061] If the first flag is ON (FLG_ON) and the second flag is OFF (FLG_OFF), the RW processing unit 13-2 writes the write data requested by the write command to the flash memory 20 using SLC (SLC fixed).

[0062] Furthermore, if both the first and second flags are on, the RW processing unit 13-2 performs MLC writing (MLC fixed).

[0063] If the first flag is off, the RW processing unit 13-2 writes the write data to the flash memory 20 using any writing method (any writing method).

[0064] Figure 8 is a flowchart showing the data writing process flow of the memory system 1-3 in the third embodiment.

[0065] The RW processing unit 13 determines whether the first flag (fWriteBoosterEn flag) is on or off (S301). If the first flag is on (S301: YES), the RW processing unit 13 then determines whether the second flag (fWriteBoosterMLC flag) is on or off (S302).

[0066] If the second flag is on (S301: YES), the RW processing unit 13 writes the write data to the flash memory 20 using MLC (S303). On the other hand, if the second flag is off (S301: NO), the RW processing unit 13 writes the write data to the flash memory 20 using SLC (S303).

[0067] Furthermore, if the first flag is off (S301: NO), the RW processing unit 13 writes the write data to the flash memory 20 using an arbitrary writing method (S305).

[0068] As described above, the memory system 1-3 of the third embodiment enables the host 2 to instruct not only SLC writing but also MLC writing.

[0069] In other words, the memory systems 1-3 of the third embodiment can also appropriately control the writing method.

[0070] (Fourth Embodiment) Next, a fourth embodiment will be described.

[0071] Figure 9 shows an example configuration of the memory system 1-4 of the fourth embodiment. The same reference numerals are used for the same components as in the memory system 1-2 of the second embodiment, and their descriptions are omitted.

[0072] The data transfer speed between host 2 and memory systems 1-4 depends on the transfer rate set between host 2 and memory systems 1-4. For example, even if you perform SLC writing to achieve the high performance of SLC, depending on the transfer rate, it may only achieve performance equivalent to or lower than that of MLC.

[0073] Therefore, the controller 10-4 of the fourth embodiment has a write performance determination unit 17. Based on the transfer rate, the write performance determination unit 17 determines whether the writing method specified by the host 2 can achieve the maximum write performance that the writing method can achieve. The write performance determination unit 17 also determines the writing method that can achieve the maximum write performance at that transfer rate and has the best WAF among the writing methods that can achieve the maximum write performance. In other words, the write performance determination unit 17 determines the writing method with the best write capability per unit of time. If there is no difference in the write capability per unit of time for each writing method due to the transfer rate limitation, the write performance determination unit 17 determines the writing method with the lowest WAF. The RW processing unit 13 in the memory system 1-4 of the fourth embodiment changes the writing method as necessary based on the determination result of the write performance determination unit 17.

[0074] For example, MIPI TM In the Mobile Industry Processor Interface (UFS) standard, transfer rates are referred to as "gears," and the UFS (Universal Flash Storage) 4.0 standard defines five transfer rates: HS-GEAR1 to HS-GEAR5. HS-GEAR1 is the slowest transfer rate, and HS-GEAR5 is the fastest.

[0075] Furthermore, the controller 10-4 of the fourth embodiment has a writing method selection table 31. Figure 10 shows an example of the writing method selection table 31.

[0076] The write method selection table 31 is provided, for example, in the SRAM (Static RAM [Random Access Memory]) built into the controller 10-4. The write method selection table 31 is a table that the write performance determination unit 17 refers to in order to determine the write method that can achieve the maximum write performance based on the transfer rate.

[0077] As shown in Figure 10, the writing method selection table 31 holds data in which numbers from 1 to 4 are arranged in a matrix, for example, with the vertical axis representing the gear and the horizontal axis representing the writing method specified by the host 2. The numbers from 1 to 4 represent, for example, SLC writing for 1, MLC writing for 2, TLC writing for 3, and QLC writing for 4.

[0078] For example, if the gear is HS-GEAR1 and the programming method specified by host 2 is SLC or MLC, the programming method will not achieve maximum write performance with SLC or MLC programming, and only TLC programming will achieve maximum write performance. Therefore, the programming performance determination unit 17 will refer to the programming method selection table 31 and decide to change the programming method from SLC or MLC to TLC. In the case of TLC or QLC, maximum write performance can be achieved, so the programming performance determination unit 17 will refer to the programming method selection table 31 and decide not to change the programming method.

[0079] In other words, the writing method selection table 31 holds information (1 to 4) indicating the writing method that should actually be applied for each combination of the gear and the writing method specified by the host 2.

[0080] Even when the gear is HS-GEAR2, just like with HS-GEAR1, SLC and MLC do not allow for the maximum light performance achievable with those programming methods. The programming methods that can achieve the maximum light performance are TLC and QLC. Therefore, if the specified programming method is SLC or MLC, it will be changed to TLC; if it is TLC or QLC, it will not be changed.

[0081] For HS-GEAR3 and HS-GEAR4, MLC is the programming method that provides the best lighting performance. Therefore, it will only be changed to TLC if the specified programming method is SLC; there is no need to change it if it is MLC, TLC, or QLC.

[0082] If the gear is HS-GEAR5, SLC will be the programming method that delivers the maximum writing performance, and no change will occur regardless of which programming method is specified.

[0083] Figure 11 shows the transfer performance of each device for each gear (HS-GEAR) as defined in the UFS4.0 standard. Here, an example of a Rate B-series device with a REF_CLK frequency value of 38.4MHz and 2 lanes is shown.

[0084] Due to system updates and header overhead, the SLC's write performance is 3800 MiBps. Assuming these overheads are 0.1467 s, the maximum write performance for each gear is as shown in Figure 12. Figure 12 shows the maximum write performance for each gear.

[0085] Figure 13 shows the light performance of each gear in each writing method.

[0086] For example, focusing on the HS-GEAR4, we see that the write performance is the same for both SLC and MLC, indicating that the gear is the limiting factor in write performance. In this case, writing with SLC will only yield the same performance as with MLC, and the WAF will also be worse compared to MLC, so MLC writing is chosen.

[0087] Specifically, if the gear is HS-GEAR4 and the writing method specified by the host 2 is SLC, the write performance determination unit 17 selects MLC as the writing method based on the writing method selection table 31.

[0088] Figure 14 is a flowchart showing the data writing process flow of the memory system in the fourth embodiment.

[0089] The write performance determination unit 17 determines, based on the write method selection table 31, whether the write method specified by the host 2 can achieve the maximum write performance possible with the current gear (S401). If the maximum write performance can be achieved (S401: YES), the RW processing unit 13 writes the write data to the flash memory 20 using the specified write method (S402).

[0090] If the maximum write performance cannot be achieved (S401: NO), the write performance determination unit 17 determines, based on the write method selection table 31, the best write method for the WAF among those that can achieve the maximum write performance with the current gear (S403). The RW processing unit 13 writes the write data to the flash memory 20 using the determined write method (S404).

[0091] By the way, the above example describes how, regardless of the writing method specified by Host 2, if the maximum write performance of the writing method specified by the gear cannot be achieved, the system will switch to the writing method with the best WAF that can achieve the maximum write performance with the same gear. As a variation, for example, if a writing method is specified by Host 2, that method will be followed, and if no writing method is specified, the system will select the writing method with the best WAF that can achieve the maximum write performance.

[0092] Figure 15 is a flowchart showing a modified example of the data writing process of the memory system of the fourth embodiment.

[0093] The RW processing unit 13 determines whether or not the host 2 has specified a writing method (S501). If a method has been specified (S501: YES), the RW processing unit 13 writes the write data to the flash memory 20 using the specified writing method (S502).

[0094] If no writing method is specified from host 2 (S501: NO), the write performance determination unit 17 determines the writing method that can achieve the maximum write performance based on the writing method selection table 31 (S503). The RW processing unit 13 writes the write data to the flash memory 20 using the determined writing method (S504).

[0095] As described above, the memory system 1-4 of the fourth embodiment focuses on the fact that the write performance is limited by the gear, and if the writing method specified by the host 2 cannot achieve the maximum write performance that can be achieved with that writing method, it changes to the writing method that can achieve the maximum write performance with that gear and is the best among the writing methods that can achieve the maximum write performance, with the WAF being the best.

[0096] In other words, the memory system 1-4 of the fourth embodiment can also appropriately control the writing method.

[0097] (Fifth embodiment) Next, a fifth embodiment will be described.

[0098] The fifth embodiment is an application example of the memory system 1-2 of the second embodiment. In the second embodiment, an example was shown in which the write data was completely written to the flash memory 20 without generating garbage collection by changing part of the write data writing from SLC to MLC.

[0099] In contrast, in the fifth embodiment, if garbage collection (GC) occurs even after changing from SLC to MLC, the occurrence of GC is further delayed by using TLC writing.

[0100] The purpose of controlling this writing method is to prevent a decrease in write performance due to garbage collection (GC), so in some situations, the entire write data may be changed to MLC. If GC still occurs even after changing the entire write data to MLC, the occurrence of GC can be delayed by changing the entire write data to TLC.

[0101] Figure 16 is a flowchart showing the data writing process flow of the memory system in the fifth embodiment.

[0102] The RW processing unit 13 determines whether the amount of write data exceeds a threshold (S601). If the amount of write data does not exceed the threshold (S601: NO), the RW processing unit 13 writes the entire write data to the flash memory 20 using SLC (S602).

[0103] If the amount of write data exceeds the threshold (S601: YES), the RW processing unit 13 then determines whether half of the write data exceeds the threshold (S603). If half of the write data does not exceed the threshold (S603: NO), the RW processing unit 13 writes twice the excess amount of write data that exceeds the threshold to the flash memory 20 using MLC (S604), and writes the remaining write data to the flash memory 20 using SLC (S605). The order of the MLC write in S604 and the SLC write in S605 may be reversed.

[0104] If half of the write data exceeds the threshold (S603: YES), the RW processing unit 13 writes the entire write data to the flash memory 20 using TLC (S606).

[0105] As described above, the memory system 1-2 of the fifth embodiment further delays the occurrence of garbage collection by utilizing TLC writing.

[0106] In other words, the memory system 1-2 of the fifth embodiment can also appropriately control the writing method.

[0107] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0108] 1...Memory system, 2...Host, 10...Controller, 11...Host I / F section, 12...Memory I / F section, 13...RW processing section, 14...Memory area management section, 15...GC processing section, 16...Command analysis section, 17...Write performance determination section, 20...Flash memory, 21...System data storage area, 22...User data storage area, 31...Write method selection table, 100...CPU, 131...WB section, 132...Extended WB section.

Claims

1. A non-volatile memory having multiple blocks, each containing multiple memory cells, A memory controller that can connect to a host and controls the non-volatile memory, It is equipped with, The aforementioned memory controller The methods for writing data to the aforementioned non-volatile memory include a first writing method in which 1 bit of data is written to each memory cell, and a second writing method in which N bits (where N is a natural number greater than or equal to 2) of data are written to each memory cell. When a write command to which the first writing method should be applied is received from the host, It is determined whether the amount of data to be written exceeds a threshold obtained by subtracting a predetermined value indicating the remaining capacity of the non-volatile memory at which garbage collection processing to increase the remaining capacity of the non-volatile memory occurs, from the remaining capacity of the non-volatile memory. If the capacity of the write data is less than or equal to the threshold, the write data is written to the non-volatile memory using the first writing method. If the capacity of the write data exceeds the threshold, At least (the amount exceeding the threshold) + ((the amount exceeding the threshold) / (the amount N-1)) of the write data is written to the non-volatile memory using the second writing method, and the remaining write data is written to the non-volatile memory using the first writing method. It is structured in such a way. Memory system.

2. The aforementioned memory controller A first flag that can be switched on or off by a command from the host is managed, During the period when the first flag is on, it is determined that the first writing method should be applied to the write command received from the host. It is structured in such a way. The memory system according to claim 1.

3. The aforementioned memory controller Further managing a second flag that can be switched on / off by a command from the aforementioned host, During the period when the first flag is ON, if the second flag is OFF, it is determined that the first write method should be applied to the write command received from the host; and if the second flag is ON, it is determined that the second write method should be applied to the write command received from the host. It is structured in such a way. The memory system according to claim 2.

4. The aforementioned memory controller When the write command received from the host is a write command to which the first write method should be applied, and it is estimated that the write performance to the non-volatile memory using the first write method is equal to or less than the write performance to the non-volatile memory using the second write method, based on the transfer rate applied in the communication with the host, the system is configured to determine that the second write method should be applied to the write command received from the host. The memory system according to claim 2.

5. The aforementioned memory controller As a method for writing data to the aforementioned non-volatile memory, a third writing method is further supported, in which K bits (where K is a natural number greater than N) of data are written to each memory cell. If the capacity of the write data exceeds the threshold, and if the remaining capacity of the non-volatile memory falls below the predetermined value even after writing all of the write data to the non-volatile memory using the second writing method, then write all of the write data to the non-volatile memory using the third writing method. It is structured in such a way. The memory system according to claim 1.

6. A memory controller that is connectable to a host and controls a non-volatile memory having multiple blocks, each containing multiple memory cells, The methods for writing data to the aforementioned non-volatile memory include a first writing method in which 1 bit of data is written to each memory cell, and a second writing method in which N bits (where N is a natural number greater than or equal to 2) of data are written to each memory cell. When a write command to which the first writing method should be applied is received from the host, It is determined whether the amount of data to be written exceeds a threshold obtained by subtracting a predetermined value indicating the remaining capacity of the non-volatile memory at which garbage collection processing to increase the remaining capacity of the non-volatile memory occurs, from the remaining capacity of the non-volatile memory. If the capacity of the write data is less than or equal to the threshold, the write data is written to the non-volatile memory using the first writing method. If the capacity of the write data exceeds the threshold, At least (the amount exceeding the threshold) + ((the amount exceeding the threshold) / (the amount N-1)) of the write data is written to the non-volatile memory using the second writing method, and the remaining write data is written to the non-volatile memory using the first writing method. It is structured in such a way. Memory controller.

7. A first flag that can be switched on or off by a command from the host is managed, During the period when the first flag is on, it is determined that the first writing method should be applied to the write command received from the host. It is structured in such a way. The memory controller according to claim 6.

8. Further managing a second flag that can be switched on / off by a command from the aforementioned host, During the period when the first flag is ON, if the second flag is OFF, it is determined that the first write method should be applied to the write command received from the host; and if the second flag is ON, it is determined that the second write method should be applied to the write command received from the host. It is structured in such a way. The memory controller according to claim 7.

9. When the write command received from the host is a write command to which the first write method should be applied, and it is estimated that the write performance to the non-volatile memory using the first write method is equal to or less than the write performance to the non-volatile memory using the second write method, based on the transfer rate applied in the communication with the host, the system is configured to determine that the second write method should be applied to the write command received from the host. The memory controller according to claim 7.

10. As a method for writing data to the aforementioned non-volatile memory, a third writing method is further supported, in which K bits (where K is a natural number greater than N) of data are written to each memory cell. If the capacity of the write data exceeds the threshold, and if the remaining capacity of the non-volatile memory falls below the predetermined value even after writing all of the write data to the non-volatile memory using the second writing method, then write all of the write data to the non-volatile memory using the third writing method. It is structured in such a way. The memory controller according to claim 6.

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