Semiconductor memory

Abstract

Provides memory that can be refreshed during read or write operations. [Solution] The memory comprises a plurality of first data lines and a plurality of first control lines for writing, and a plurality of second data lines and a plurality of second control lines for reading. The memory cell includes a first transistor whose gate is connected to a first control line and one end is connected to a first data line, a second transistor whose gate is connected to a second control line and one end is connected to a second data line, and a third transistor whose gate is connected to the other end of the first transistor and one end is connected to the other end of the second transistor. The third data lines correspond to a plurality of first data lines, and the fourth data lines correspond to a plurality of second data lines. The input of the detection circuit is connected to the fourth data line. The holding circuit is provided between the output of the detection circuit and the third data line. The fourth transistor is provided in parallel with the holding circuit between the output of the detection circuit and the third data line.

Description

Technical Field

[0001] This embodiment relates to a semiconductor memory device.

Background Art

[0002] As an alternative to the memory cells of DRAM (Dynamic Random Access Memory), gain cell memory has been developed. In DRAM, during a read operation or a write operation, a refresh operation for writing back the stored data to the same memory cell could not be performed.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Non-Patent Documents

[0004]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] To provide a semiconductor memory device capable of performing a refresh operation during a read operation or a write operation.

Means for Solving the Problems

[0006] The semiconductor memory device according to this embodiment comprises a plurality of first data lines and a plurality of first control lines used for writing data, and a plurality of second data lines and a plurality of second control lines used for reading data. Each plurality of memory cells includes a first transistor whose gate is connected to one of the plurality of first control lines and one end is connected to one of the plurality of first data lines, a second transistor whose gate is connected to one of the plurality of second control lines and one end is connected to one of the plurality of second data lines, and a third transistor whose gate is connected to the other end of the first transistor and holds data from the first data lines, and whose one end is connected to the other end of the second transistor and conducts according to the data. The third data lines are provided corresponding to the plurality of first data lines. The fourth data lines are provided corresponding to the plurality of second data lines. A detection circuit is provided corresponding to the third or fourth data line, with its input connected to the fourth data line, and detects data. A holding circuit is provided corresponding to the third or fourth data line, between the output of the detection circuit and the third data line, and holds the data detected by the detection circuit. The fourth transistor is provided corresponding to the third or fourth data line and is located in parallel with the holding circuit between the output of the detection circuit and the third data line. [Brief explanation of the drawing]

[0007] [Figure 1] This is a circuit diagram showing an example of a single memory cell configuration according to the first embodiment. [Figure 2A] This is a perspective view showing an example of the configuration of a gain cell memory according to the first embodiment. [Figure 2B] This is a perspective view showing an example of the configuration of a gain cell memory according to the first embodiment. [Figure 3] This figure shows an example configuration of a gain cell memory according to the first embodiment. [Figure 4] This is a circuit diagram showing an example of the internal configuration of a latch circuit. [Figure 5] This is a timing diagram showing an example of the operation of a gain cell memory according to the first embodiment. [Figure 6] This is a timing diagram showing an example of the operation of a gain cell memory according to the second embodiment. [Figure 7] This figure shows an example configuration of a gain cell memory according to the third embodiment. [Figure 8] This is a circuit diagram showing an example of a sense amplifier configuration. [Modes for carrying out the invention]

[0008] Embodiments of the present invention will be described below with reference to the drawings. These embodiments are not limiting to the present invention. The drawings are schematic or conceptual. The same elements are denoted by the same reference numerals in the specification and the drawings.

[0009] (First Embodiment) Figure 1 is a circuit diagram showing an example of a single memory cell configuration according to the first embodiment. The memory cell MC of the gain cell memory is composed of three transistors MW1, MR1, and MR2. Transistors MW1, MR1, and MR2 are composed of, for example, n-type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors).

[0010] The gate of transistor MW1, which acts as the first transistor, is connected to the write word line WWL, which acts as the first control line. One electrode of transistor MW1 is connected to the write bit line WBL, which acts as the first data line. The other electrode of transistor MW1 is connected to the gate of transistor MR1. The one and the other electrode of transistor MW1 function as source electrodes or drain electrodes depending on the voltage supplied to transistor MW1. Under the control of the write word line WWL, transistor MW1 connects the write bit line WBL to the gate of transistor MR1, which acts as a sense node SN (hereinafter also referred to as sense node SN). When transistor MW1 is conducting (on), it transmits the voltage of the write bit line WBL to sense node SN. When transistor MW1 is not conducting (off), it holds the voltage of sense node SN. In this way, transistor MW1 can write the voltage (data) from the write bit line WBL to sense node SN, or hold the written voltage (data) in sense node SN.

[0011] The gate of transistor MR1, acting as a third transistor, is connected to the other electrode of transistor MW1 and functions as a sense node SN. One electrode of transistor MR1 (e.g., source) is connected to a low voltage source VSS. The other electrode of transistor MR1 (e.g., drain) is connected to one electrode of transistor MR2. Transistor MR1 conducts depending on the voltage (i.e., data) of the sense node SN. For example, when the sense node SN is held at a high level voltage (e.g., data "1"), transistor MR1 is ON. When the sense node SN is held at a low level voltage (e.g., data "0"), transistor MR1 is OFF.

[0012] The gate of transistor MR2, acting as the second transistor, is connected to the read word line RWL, acting as the second control line. One electrode of transistor MR2 is connected to the drain of transistor MR1. The other electrode of transistor MR2 is connected to the read bit line RBL, acting as the second data line. Both electrodes of transistor MR2 can function as source or drain electrodes depending on the voltage supplied to transistor MR2. Under the control of the read word line RWL, transistor MR2 connects the read bit line RBL to the drain of transistor MR1. Transistor MR1 is in a state (on or off) depending on the voltage (data) held at the sense node SN. When transistor MR2 is in the ON state, connecting the read bit line RBL to transistor MR1 causes charge from the read bit line RBL to flow to the low voltage source VSS depending on the state of transistor MR1. When transistor MR1 is in the ON state, charge from the read bit line RBL flows to the low voltage source VSS, and the voltage of the read bit line RBL becomes low. When transistor MR1 is off, very little charge flows from the read bit line RBL to the low-voltage source VSS, and the voltage across the read bit line RBL remains high. This allows the voltage based on the data held in sense node SN to be transmitted to the read bit line RBL.

[0013] The sense amplifier SA, acting as a detection circuit, is connected to the read bit line RBL. The sense amplifier SA is not directly connected to the write bit line WBL. The sense amplifier SA detects read data based on the voltage of the read bit line RBL. The read data latched by the sense amplifier SA is transmitted externally via the latch circuit LAT. The sense amplifier SA also precharges the read bit line RBL. In refresh operation, the sense amplifier SA writes the read data back directly to the write bit line WBL without going through the latch circuit LAT.

[0014] The latch circuit LAT is connected to the write bit line WBL and the sense amplifier SA. The latch circuit LAT latches the externally written data and applies a voltage corresponding to the written data to the write bit line WBL. Further, the latch circuit LAT temporarily latches the read data from the sense amplifier SA. The read data latched by the latch circuit LAT is transmitted to the outside at a predetermined timing.

[0015] The controller CTL is connected to the write word line WWL and the read word line RWL, and controls the voltages of the write word line WWL and the read word line RWL.

[0016] The write word line WWL and the write bit line WBL are wirings used for writing data. The read word line RWL and the read bit line RBL are wirings used for reading data. Thus, the gain cell memory uses different word lines and bit lines for writing and reading data. Thereby, the gain cell memory can read data while maintaining the data of the sense node SN (non-destructive readout). Also, one memory cell MC is composed of three transistors MW1, MR, and MR2 and does not have a capacitor that is difficult to miniaturize as in DRAM. Therefore, the gain cell memory is excellent in miniaturization.

[0017] FIGS. 2A and 2B are perspective views showing a configuration example of a gain cell memory according to the first embodiment. The gain cell memory according to the present embodiment includes a three-dimensional memory cell array in which a plurality of memory cells MC are three-dimensionally arranged. The plurality of memory cells MC are arranged in a matrix consisting of a plurality of rows and a plurality of columns. A row is an array of the memory cells MC in the X direction. A column is an array of the memory cells MC in the Z direction. Further, the memory cells MC are arranged in the Y direction with respect to the matrix of the memory cells MC. Thereby, the memory cell array MCA is a three-dimensional array in which a plurality of memory cells MC are three-dimensionally arranged. Note that the number of rows, columns, and matrices of the memory cells MC is not particularly limited. Hereinafter, the memory cell array MCA will be described with reference to FIG. 2A.

[0018] Multiple write word lines (WWL) are provided, corresponding to each of the multiple rows of the memory cell MC. Multiple read word lines (RWL), acting as multiple second control lines, are also provided, corresponding to each of the multiple rows of the memory cell MC. The write word lines (WWL) are used for writing data and extend in the X direction. The read word lines (RWL) are used for reading data and extend in the X direction.

[0019] A drive line WDRV is provided in common for multiple write word lines WWL and multiple read word lines RWL, which are arranged in the Y direction. The drive line WDRV transmits the selection voltage for writing data. Each of the multiple drive lines WDRV extends in the Y direction and is arranged in the Z direction.

[0020] Multiple transistors WT1 are each connected between multiple write word lines WWL and drive line WDRV. One electrode of each of the multiple transistors WT1 is connected to multiple write word lines WWL. The other electrodes of the multiple transistors WT1 arranged in the Y direction are commonly connected to a single drive line WDRV. Furthermore, one and the other electrodes of each of the transistors WT1, RT1, WT2, WTbl, and RTbl can function as source electrodes or drain electrodes depending on the voltage supplied to the transistors WT1, RT1, WT2, WTbl, and RTbl.

[0021] Multiple transistors RT1 are each connected between multiple read word lines RWL and drive lines WDRV. One electrode of each of the multiple transistors RT1 is connected to multiple read word lines RWL. The other electrodes of multiple transistors RT1 arranged in the Y direction are commonly connected to one drive line WDRV. Multiple transistors WT1 and RT1 arranged in the Y direction are commonly connected to one drive line WDRV.

[0022] The main write word line WMWL is commonly connected to the gates of multiple transistors WT1 arranged in the Z direction. That is, the main write word line WMWL is commonly provided to multiple write word lines WWL arranged in the Z direction. Each of the multiple write main word lines WMWL extends in the Z direction and is arranged in the Y direction. The main write word line WMWL selectively turns on the multiple transistors WT1 connected to it, connecting the drive line WDRV to the corresponding write word line WWL. Each of the multiple write main word lines WMWL arranged in the Y direction is driven independently. Therefore, the transistors WT1 shown in Figure 2A are individually controlled to be on or off for each of the multiple rows arranged in the Z direction.

[0023] The read main word line RMWL is commonly connected to the gates of multiple transistors RT1 arranged in the Z direction. That is, the read main word line RMWL is commonly provided to multiple read word lines RWL arranged in the Z direction. Each of the multiple read main word lines RMWL extends in the Z direction and is arranged in the Y direction. The read main word line RMWL turns on the multiple transistors RT1 connected to it and connects the drive line WDRV to the corresponding multiple read word lines RWL. Each of the multiple read main word lines RMWL arranged in the Y direction is driven independently. Therefore, the transistors RT1 shown in Figure 2A are individually controlled to be on or off for each of the multiple rows arranged in the Z direction.

[0024] Non-write voltage lines VUW are provided in common to multiple write word lines WWL arranged in the Y direction. Non-write voltage lines VUW transmit a non-selective voltage that does not write data. Each of the multiple non-write voltage lines VUW extends in the Y direction and is arranged in the Z direction.

[0025] Multiple transistors WT2 are connected between multiple write word lines WWL and multiple non-write voltage lines VUW. One electrode of each of the multiple transistors WT2 is connected to multiple write word lines WWL. The other electrodes of multiple transistors WT2 arranged in the Y direction are commonly connected to one non-write voltage line VUW. On the other hand, multiple read word lines RWL are electrically isolated from multiple non-write voltage lines VUW. Note that if the non-selective voltage is constant, the multiple non-write voltage lines VUW may be short-circuited to each other as a single drive line.

[0026] The unselected main word line bWMWL is commonly connected to the gates of multiple transistors WT2 arranged in the Z direction. Each of the multiple unselected main word lines bWMWL extends in the Z direction and is arranged in the Y direction. The unselected main word line bWMWL turns on multiple transistors WT2 that are connected to the write word line WWL corresponding to memory cells MC that do not write data, and connects the unwrite voltage line VUW to the corresponding write word line WWL.

[0027] Multiple write bit lines (WBLs) are provided corresponding to each of the multiple rows of the memory cell (MC). Multiple read bit lines (RBLs) as second data lines are also provided corresponding to each of the multiple rows of the memory cell (MC). Note that in Figure 2A, only one row each of the write bit lines (WBLs) and read bit lines (RBLs) arranged in the Y direction is shown. The write bit lines (WBLs) are used for writing data and extend in the Z direction. The read bit lines (RBLs) are used for reading data and extend in the Z direction. The read bit lines (RBLs), write bit lines (WBLs), write main word line (WMWL), read main word line (RMWL), and unselected main word line (bWMWL) all extend in the Z direction.

[0028] The write global bit line WGBL is provided in common to multiple write bit lines WBL arranged in the Y direction. Each of the multiple write global bit lines WGBL extends in the Y direction and is arranged in the X direction. Note that in Figure 2A, only one write global bit line WGBL is shown. The write global bit line WGBL is connected to a write bit line WBL selected from the multiple corresponding write bit lines WBL, and transmits data from the latch circuit LAT or sense amplifier SA to this selected write bit line WBL.

[0029] The read global bit line RGBL is provided in common to multiple read bit lines RBL arranged in the Y direction. Each of the multiple read global bit lines RGBL extends in the Y direction and is arranged in the X direction. Note that in Figure 2A, only one read global bit line RGBL is shown. The read global bit line RGBL is connected to a read bit line RBL selected from the multiple read bit lines RBL that correspond to it, and transmits the data from the selected read bit line RBL to the sense amplifier SA.

[0030] The same number of bits as the number of pairs of write global bit lines WGBL and read global bit lines RGBL can be written to or read simultaneously. This simultaneously writable or readable data is called a "page".

[0031] Furthermore, by layering the bit line structure with global bit lines WGBL and RGBL, and bit lines WBL and RBL, the capacity of bit lines WBL and RBL can be reduced.

[0032] Multiple transistors WTbl are connected between multiple write bit lines WBL and one write global bit line WGBL. One electrode of each of the multiple transistors WTbl is connected to multiple write bit lines WBL. The other electrodes of multiple transistors WTbl arranged in the Y direction are commonly connected to one write global bit line WGBL. The gates of multiple transistors WTbl arranged in the X direction are commonly connected to a write selection line WSEL. Multiple write selection lines WSEL each extend in the X direction and are arranged in the Y direction. A transistor WTbl connects one of the multiple write bit lines WBL to one write global bit line WGBL.

[0033] During a write operation, one of several write selection lines WSEL is selectively driven. Multiple transistors WTbl connected to the selected write selection line WSEL are turned on, electrically connecting the corresponding write bit line WBL and the write global bit line WGBL. As a result, the multiple transistors WTbl connected to the selected write selection line WSEL transmit data from the latch circuit LAT or sense amplifier SA from the corresponding write global bit line WGBL to the write bit line WBL.

[0034] To reduce the capacitance of the write bit line WBL and enable high-speed operation of the write bit line WBL, it is preferable to provide the transistor WTbl. However, if operating speed is not a consideration, the transistor WTbl may be omitted.

[0035] Multiple transistors RTbl are connected between multiple read bit lines RBL and read global bit lines RGBL. One electrode of each of the multiple transistors RTbl is connected to multiple read bit lines RBL. The other electrode of multiple transistors RTbl arranged in the Y direction is commonly connected to one read global bit line RGBL. The gates of multiple transistors RTbl arranged in the X direction are commonly connected to a read selection line RSEL. Multiple read selection lines RSEL each extend in the X direction and are arranged in the Y direction. A transistor RTbl connects one of the multiple read bit lines RBL to one read global bit line RGBL.

[0036] During a read operation, one of several read selection lines RSEL is selectively driven. Multiple transistors RTbl connected to the selected read selection line RSEL are turned on, electrically connecting the corresponding read bit line RBL and the read global bit line RGBL. As a result, the multiple transistors RTbl connected to the selected read selection line RSEL transmit data from the memory cell MC from the corresponding read bit line RBL to the read global bit line RGBL.

[0037] Multiple memory cells (MCs) are provided corresponding to the intersections of pairs of write word lines (WWL) and read word lines (RWL) adjacent to each other in the Y direction, and pairs of write bit lines (WBL) and read bit lines (RBL) adjacent to each other in the X direction. Therefore, in this embodiment, data can be written to one memory cell (MC) by selecting one write word line (WWL) and one write bit line (WBL) during writing. Similarly, during reading, data can be read from one memory cell (MC) by selecting one read word line (RWL) and one read bit line (RBL).

[0038] A layer containing multiple write word lines WWL, multiple read word lines RWL, and multiple memory cells MC, each corresponding to a single drive line WDRV, constitutes one set. In this case, one write main word line WMWL is commonly connected to the gates of multiple transistors WT1 corresponding to multiple sets. Similarly, one read main word line RMWL is commonly connected to the gates of multiple transistors RT1 corresponding to multiple sets. Furthermore, one unselected main word line bWMWL is commonly connected to the gates of multiple transistors WT2 corresponding to multiple sets. One write main word line WMWL is commonly provided across multiple write word lines WWL corresponding to multiple sets. One read main word line RMWL is commonly provided across multiple read word lines RWL corresponding to multiple sets.

[0039] One end of the write word line WWL is connected to the drive line WDRV via transistor WT1, and the other end is connected to the non-write voltage line VUW via transistor WT2. On the other hand, one end of the read word line RWL is connected to the drive line WDRV via transistor RT1, but the other end is not connected to a transistor or drive line.

[0040] Figure 3 shows an example configuration of a gain cell memory according to the first embodiment. In Figure 3, the arrangement of memory cells MC and global bit lines RGBL and WGBL is reversed in the Z direction compared to the arrangement shown in Figure 2A. However, the configuration in Figure 3 can be the same as the configuration in Figure 2A.

[0041] Memory cells MCa(m) are provided corresponding to the intersections of the read word line RWLa and the read bit line RBL(m), and the intersections of the write word line WWLa and the write bit line WBL(m). Memory cells MCa(n) are provided corresponding to the intersections of the read word line RWLa and the read bit line RBL(n), and the intersections of the write word line WWLa and the write bit line WBL(n). Memory cells MCa(m) and MCa(n) are shown in Figure 3 by dashed frames surrounding the "black circles".

[0042] Memory cells MCb(m) are provided corresponding to the intersections of the read word line RWLb and the read bit line RBL(m), and the intersections of the write word line WWLb and the write bit line WBL(m). Memory cells MCb(n) are provided corresponding to the intersections of the read word line RWLb and the read bit line RBL(n), and the intersections of the write word line WWLb and the write bit line WBL(n). Memory cells MCb(m) and MCb(n) are shown in Figure 3 by dashed lines surrounding the “black triangles”. m and n can be any integers. Figure 3 shows a configuration corresponding to two columns, m and n, but a configuration corresponding to three or more columns may be provided.

[0043] A column is a unit configuration that can be selected by the column selection signal CSL during read and write operations. Each column can read or write 1 bit of data at a time. Data from multiple columns that can be read or written simultaneously constitutes a "page".

[0044] Multiple read bit lines RBL(m) are each connected to a sense amplifier SA(m) via multiple transistors RTbl(m).

[0045] Multiple read bit lines RBL(n) are each connected to a sense amplifier SA(n) via multiple transistors RTbl(n).

[0046] The detection unit SAC includes multiple sense amplifiers SA(m) and SA(n). The number of sense amplifiers included in the detection unit SAC is not limited. In the following description, configurations with (m) appended to the reference numeral will be described, and the description of configurations with (n) appended may be omitted. Also, if columns m and n are not distinguished, the notations (m) and (n) may be omitted.

[0047] Furthermore, m represents the column number of multiple memory cell groups that share the global bit lines WGBL(m) and RGBL(m). n represents the column number of multiple memory cell groups that share the global bit lines WGBL(n) and RGBL(n).

[0048] A sense amplifier SA is provided for each read global bit line RGBL. That is, a sense amplifier SA is provided for each column. For example, each sense amplifier SA(m) is connected to its corresponding read global bit line RGBL(m), but not to the write global bit line WGBL(m). The input of the sense amplifier SA(m) is connected to the corresponding read global bit line RGBL(m). The output of the sense amplifier SA(m) is connected to the latch circuit LAT(m) and the transistor Tref(m).

[0049] The refresh section REFC includes multiple transistors Tref(m) and Tref(n), and multiple inverters INref(m) and INref(n).

[0050] Both the transistor Tref and the inverter INref are provided in correspondence with the write global bit line WGBL or the sense amplifier SA. That is, pairs of transistor Tref and inverter INref are also provided corresponding to each column. For example, the transistor Tref(m) and inverter INref(m) are connected in series between the output of the corresponding sense amplifier SA(m) and the write global bit line WGBL(m). The transistor Tref(m) is provided in parallel with the latch circuit LAT(m) between the output of the corresponding sense amplifier SA(m) and the write global bit line WGBL(m). The inverter INref(m) is connected between the corresponding transistor Tref(m) and the write global bit line WGBL(m). The transistor Tref(m) may be composed of, for example, an n-type MOSFET. The inverter INref(m) may be composed of, for example, a CMOS (Complementary MOS).

[0051] One end (e.g., the drain) of transistor Tref(m) is connected to the output of sense amplifier SA(m). In this embodiment, one end of transistor Tref(m) is connected to the non-inverting signal output of sense amplifier SA(m). The other end (e.g., the source) of transistor Tref(m) is connected to the input of inverter INref(m). The gate of transistor Tref(m) is connected to a signal line that transmits the refresh signal REF. The refresh signal REF is a signal that is activated during the refresh operation period.

[0052] The input of inverter INref(m) is connected to the other end of transistor Tref(m). The output of inverter INref(m) is connected to the write global bit line WGBL(m).

[0053] As a result, the transistor Tref(m) and inverter INref(m) can directly write back the read data detected by the sense amplifier SA(m) to the write global bit line WGBL(m) without going through the latch circuit LAT(m) and the sense amplifier SA(m). In other words, during the refresh operation, the transistor Tref(m) and inverter INref(m) function as a bypass path.

[0054] In this embodiment, transistor Tref(m) receives a non-inverted signal of the read data from sense amplifier SA(m). Inverter INref(m) outputs an inverted signal of this read data. As a result, the inverted signal of the read data is transmitted to the write global bit line WGBL(m), and the inverse logic data is transmitted to the sense node SN of the memory cell MC in Figure 1. The memory cell MC in Figure 1 outputs data of the voltage level of the sense node SN and the voltage level of the inverse logic. Therefore, the write-back of the read data is successfully completed by writing the inverse logic data of the read data back to the sense node SN.

[0055] The transistor Tref(n) and inverter INref(n) have a similar configuration to the sense amplifier SA(n) and the write global bit line WGBL(n), and similarly function as bypass paths.

[0056] The latch section LATC includes multiple latch circuits LAT(m) and LAT(n). Each latch circuit LAT is provided in correspondence with the write global bit line WGBL or the sense amplifier SA. That is, each latch circuit LAT is also provided in correspondence with each column. For example, latch circuit LAT(m) is connected between the output of the corresponding sense amplifier SA(m) and the write global bit line WGBL(m). In this embodiment, latch circuit LAT(m) is connected to the output of the non-inverting signal of the sense amplifier SA(m) and receives the non-inverting signal of the read data.

[0057] The latch circuit LAT(m) operates according to the control signals LTI and LTO and the column selection signal CSL(m). The control signal LTI is a signal that inputs the read data from the sense amplifier SA(m) to the latch circuit LAT(m). The control signal LTO is a signal that causes the latch circuit LAT(m) to output the write data acquired from an external source to the write global bit line WGBL(m). The column selection signal CSL(m) is a signal that outputs the latched read data to the input / output signal line LIO, or a signal that inputs the write data to the latch circuit LAT(m). The refresh signal REF signal line, the control signals LTI and LTO signal lines, and the input / output signal line LIO are provided in common for each column in the detection unit SAC, the refresh unit REFC, and the latch unit LATC.

[0058] Figure 4 is a circuit diagram showing an example of the internal configuration of a latch circuit. Note that the internal configuration of latch circuit LAT(n) is the same as that of latch circuit LAT(m), so its explanation is omitted.

[0059] The latch circuit LAT(m) includes transistors Tlti, Tlto, Tlio and inverters INlat1, INlat2.

[0060] One end of transistor Tlti (e.g., the drain) is connected to the output of sense amplifier SA(m). The other end of transistor Tlti (e.g., the source) is connected to the input (node ​​Nsa) of inverter INlat1 and the output of inverter INlat2. The gate of transistor Tlti is connected to the signal line of control signal LTI.

[0061] One end of transistor Tlto (e.g., the drain) is connected to the output (node ​​bNsa) of inverter INlat1 and the input of inverter INlat2. The other end of transistor Tlto (e.g., the source) is connected to the write global bit line WGBL(m). The gate of transistor Tlto is connected to the signal line of the control signal LTO.

[0062] One end of transistor Tlio (e.g., the drain) is connected to the input (node ​​Nsa) of inverter INlat1 and the output of inverter INlat2. The other end of transistor Tlio (e.g., the source) is connected to the input / output signal line LIO. The gate of transistor Tlio is connected to the signal line of column selection signal CSL(m), which selectively connects one of several latch circuits LAT to the input / output signal line LIO.

[0063] The transistors Tlti, Tlto, and Tlio can be composed of, for example, n-type MOSFETs.

[0064] Inverters INlat1 and INlat2 form a latch circuit by connecting the input of one to the output of the other. For example, the input of inverter INlat1 and the output of inverter INlat2 are connected by node Nsa. The output of inverter INlat1 and the input of inverter INlat2 are connected by node bNsa. Inverters INlat1 and INlat2 may be constructed using CMOS.

[0065] Node Nsa holds the non-inverted signal of the data from sense amplifier SA(m). Node bNsa holds the inverse logic of the data from node Nsa (the inverted signal of the data from sense amplifier SA(m)).

[0066] During the read operation, when the control signal LTI is activated to a high voltage level, the transistor Tlti becomes conductive (on), and the read data from the sense amplifier SA(m) is held in inverters INlat1 and INlat2.

[0067] When the column selection signal CSL(m) is activated to a high voltage level, transistor Tlio turns on, and the read data held by the cross-coupled inverters INlat1 and INlat2 is transmitted to the input / output signal line LIO. This allows the read data to be output externally.

[0068] Furthermore, when the control signal LTO is activated to a high voltage level, transistor Tlto turns on, and the read data held by inverters INlat1 and INlat2 is transmitted to the write global bit line WGBL(m). This allows the read data to be written back to memory cell MCa(m) or MCb(m).

[0069] The control signal LTI is activated to a high voltage level, and the data read from the sense amplifier SA is held by inverters INlat1 and INlat2. In the write operation, the column selection signal CSL(m) is then activated to a high voltage level, and the write data from the input / output signal line LIO is transmitted to inverters INlat1 and INlat2, and the data held by inverters INlat1 and INlat2 is updated with the write data.

[0070] Subsequently, the control signal LTO is activated to a high-level voltage, and the write data held by inverters INlat1 and INlat2 is transmitted to the write global bit line WGBL(m). This allows the write data to be written to memory cell MCa(m) or MCb(m).

[0071] Furthermore, the data transmitted from the latch circuit LAT(m) to the write global bit line WGBL(m) is inverted data with the opposite logic to the data read from the sense amplifier SA(m) or the data written from the input / output signal line LIO. This is because the data read from the memory cell MCa(m) or MCb(m) in Figure 1 to the read bit line RBL(m) is inverse logic to the data stored in the sense node SN(m).

[0072] During a refresh operation, when the refresh signal REF is activated to a high voltage level, the transistor Tref(m) turns on. This causes the data read from the sense amplifier SA(m) to be inverted via the inverter INref(m) and transmitted to the write global bit line WGBL(m). At this time, the refresh unit REFC transmits (bypasses) the read data to the write global bit line WGBL(m) without going through the latch circuit LAT(m) and the sense amplifier SA(m). This allows the memory cell MCa(m) or MCb(m) to be refreshed. The refresh operation is an operation in which data stored in the memory cell MCa(m) or MCb(m) is read out and then written back to the same memory cell.

[0073] As mentioned above, the read data transmitted from the memory cell MC to the read bit line RBL has the inverse logic of the data stored in the sense node SN. Therefore, the read data is transmitted to the write global bit line WGBL after its logic is inverted by the inverter INref. This allows the refresh operation to be completed successfully.

[0074] The operation of the sense amplifier SA(n), transistor Tref(n), latch circuit LAT(n), etc., may be the same as that of the sense amplifier SA(m), transistor Tref(m), latch circuit LAT(m), etc.

[0075] The array chip containing memory cells MCa(m), MCa(n), MCb(m), and MCb(n) may be configured as a separate semiconductor chip from the peripheral circuit chip containing the detection unit SAC, refresh unit REFC, and latch unit LATC, and may be stacked with the peripheral circuit chip. This allows for a reduction in chip area.

[0076] Next, the operation of the gain cell memory according to this embodiment will be described in more detail.

[0077] Figure 5 is a timing diagram showing an example of the operation of a gain cell memory according to the first embodiment. In this example, data is read from memory cells MCa(m) and MCa(n) in Figure 3, and data is written to memory cell MCa(m). Simultaneously, a refresh operation is performed on memory cells MCb(m) and MCb(n).

[0078] First, at t0, the active command ACTa is issued, followed by the refresh command REF at t1. The active command ACTa is a command to access memory cells MCa(m) and MCa(n) with subscripts such as "a". The refresh command REF is a command to perform a refresh operation. For convenience, here we will perform a refresh operation on memory cells MCb(m) and MCb(n) with subscripts such as "b". The address b to be refreshed is determined by an internal memory counter.

[0079] Upon issuance of the active command ACTa, the read word line RWLa is activated to a high voltage level at t2. As a result, at t3, the data Am from memory cell MCa(m) is transmitted to the read bit line RBL(m). The data An from memory cell MCa(n) is transmitted to the read bit line RBL(n). At this time, the read transistors RTbl(m) and RTbl(n) corresponding to memory cells MCa(m) and MCa(n) in Figure 3 are in the ON state.

[0080] Next, at t4, sense amplifier SA(m) detects and amplifies the data Am. Sense amplifier SA(n) detects and amplifies the data An.

[0081] Next, at t5, when the control signal LTI is activated to a high voltage level, the transistors Tlti (see Figure 4) of the latch circuits LAT(m) and LAT(n) are turned on. As a result, at t6, the latch circuits LAT(m) and LAT(n) acquire and latch the data Am and An, respectively. At t7, when the control signal LTI is deactivated to a low voltage level, the transistors Tlti of the latch circuits LAT(m) and LAT(n) are turned off. As a result, the latch circuits LAT(m) and LAT(n) are electrically isolated from the sense amplifiers SA(m) and SA(n). At this time, the transistors Tlio and Tlto also remain off. As a result, the latch circuits LAT(m) and LAT(n) hold the data Am and An at node Nsa, respectively. The latch circuits LAT(m) and LAT(n) hold the inverted signals of the data Am and An at node bNsa.

[0082] At t8, when the read word line RWLa is deactivated to a low voltage level, the memory cells MCa(m) and MCa(n) are electrically isolated from the read bit lines RBL(m) and RBL(n). At this time, the latch circuits LAT(m) and LAT(n) are electrically isolated from the sense amplifiers SA(m) and SA(n) while holding the data Am and An. Therefore, the sense amplifiers SA(m) and SA(n) can operate independently of the latch circuits LAT(m) and LAT(n). As a result, the read operation of the latches LAT(m) and LAT(n) and the refresh operation of the sense amplifiers SA(m) and SA(n) can be executed simultaneously thereafter.

[0083] (Read operation of data Am and An from latches LAT(m) and LAT(n)) At t9, the read command RED(m) is issued. As a result, at t11, the column selection signal CSL(m) is activated to a high voltage level, and the transistor Tlio of the latch circuit LAT(m) in Figure 4 is turned on. When transistor Tlio is turned on, the data Am latched in the latch circuit LAT(m) is output to the input / output signal line LIO. Thus, at t11~t15, the data Am is transmitted to the input / output signal line LIO, and at t18~t19, it is read out externally as data Qm.

[0084] At t13, the read command RED(n) is issued. As a result, at t14, the column selection signal CSL(m) is deactivated to a low voltage level, and the column selection signal CSL(n) is activated to a high voltage level. Therefore, the transistor Tlio of the latch circuit LAT(m) in Figure 4 is turned off, and the transistor Tlio of the latch circuit LAT(n) is turned on. When transistor Tlio is turned on, the data An latched in the latch circuit LAT(n) is output to the input / output signal line LIO. As a result, at t15~t16, the data An is transmitted to the input / output signal line LIO. At t16, when the column selection signal CSL(n) is deactivated to a low voltage level, the output of data An from the latch circuit LAT(n) to the input / output signal line LIO ends. At t19~t21, the data An is read out externally as data Qn.

[0085] (Refresh operation of memory cells MCb(m) and MCb(n)) On the other hand, upon issuance of the refresh command REF, after the read word line RWLa is deactivated at t8, the read word line RWLb is activated to a high voltage level at t10. As a result, at t11, the data Bm of memory cell MCb(m) is transmitted to the read bit line RBL(m). The data Bn of memory cell MCb(n) is transmitted to the read bit line RBL(n). Note that the read transistors RTbl(m) and RTbl(n) corresponding to memory cells MCb(m) and MCb(n) in Figure 3 are in the ON state. At this time, since the read word line RWLa has already been deactivated, memory cells MCa(m) and MCa(n) are electrically isolated from the read global bit lines RGBL(m) and RGBL(n). Therefore, there is no problem even if the data Bm and Bn of memory cells MCb(m) and MCb(n) are transmitted to the read global bit lines RGBL(m) and RGBL(n).

[0086] Next, at t12, sense amplifier SA(m) detects and amplifies data Bm. Sense amplifier SA(n) detects and amplifies data Bn.

[0087] Next, at t14, when the refresh signal REF is activated to a high voltage level, transistors Tref(m) and Tref(n) (see Figure 4) are turned on. As a result, the data Bm detected by sense amplifier SA(m) is transmitted to the write bit line WBL(m) via transistor Tref(m) and inverter INref(m). That is, the data Bm detected by sense amplifier SA(m) is transmitted from sense amplifier SA(m) to the write bit line WBL(m) bypassing the latch circuit LAT(m). The data Bn detected by sense amplifier SA(n) is transmitted to the write bit line WBL(n) via transistor Tref(n) and inverter INref(n). That is, the data Bn detected by sense amplifier SA(n) is transmitted from sense amplifier SA(n) to the write bit line WBL(n) bypassing the latch circuit LAT(n). At this time, the writing transistors WTbl(m) and WTbl(n), corresponding to the memory cells MCb(m) and MCb(n) in Figure 3, are in the ON state.

[0088] At t20, when the write word line WWLb is activated to a high voltage level, the transistor MW1 (see Figure 1) of memory cells MCb(m) and MCb(n) (see Figure 3) is turned on. As a result, data Bm is written back to the sense node SN of memory cell MCb(m). Data Bn is written back to the sense node SN of memory cell MCb(n). The write-back (refresh operation) of memory cells MCb(m) and MCb(n) is performed until at t25, when the refresh signal REF and the write word line WWLb are deactivated to a low voltage level (just before precharging begins).

[0089] A refresh operation for memory cells MCb(m) and MCb(n) can be performed after the data Am and An of the memory cells MCa(m) and MCa(n) to be read are latched by the latch circuits LAT(m) and LAT(n), and the control signal LTI and the read word line RWLa are deactivated. Even while the latch circuits LAT(m) and LAT(n) are outputting the data Am and An to the outside (for example, t11 to t21), a refresh operation (for example, t14 to t25) can be performed on memory cells MCb(m) and MCb(n). In other words, this embodiment allows the read operation and the refresh operation to be performed in overlapping order.

[0090] (Writing operation to memory cell MCa(m)) In this embodiment, at t17, a write command WRT(m) is issued to the memory cell MCa(m). Following the issuance of the write command, data Dm is acquired at t22-t23.

[0091] Between t23 and t24, the data Dm is transmitted to the input / output signal line LIO as data Awm. When the column selection signal CSL(m) is activated to a high voltage level, the data Awm is latched into the latch circuit LAT(m). As a result, at t23, the read data Am held in the latch circuit LAT(m) is updated with the written data Awm.

[0092] At t24, when the column selection signal CSL(m) is deactivated by a low voltage level, the latch circuit LAT(m) holds the write data Awm.

[0093] At t25, the refresh operation is completed. Next, when a precharge command PRE is issued to write back to the sense nodes SN of memory cells MCa(m) and MCa(n) and precharge the write bit lines WBL(m) and WBL(n), at t26 the control signal LTO and the write word line WWLa are activated to a high voltage level. As a result, the transistors Tlto (see Figure 4) of the latch circuits LAT(m) and LAT(n) are turned on.

[0094] At t26, the latch circuit LAT(m) transmits the inverted signal of the write data Awm to the write bit line WBL(m). As a result, the inverted signal of the write data Awm is held in the sense node SN of the memory cell MCa(m). At this time, the write transistor WTbl(m) corresponding to the memory cell MCa(m) in Figure 3 is in the ON state. In this case, the data read from the memory cell MCa(m) is the non-inverted signal of the data Awm.

[0095] At t26, the latch circuit LAT(n) holds the read data An as is, and transmits the inverted signal of data An to the write bit line WBL(n). As a result, the inverted signal of data An is written back to the sense node SN of memory cell MCa(n). At this time, the write transistor WTbl(n) corresponding to memory cell MCa(n) in Figure 3 is in the ON state. In this case, the data read from memory cell MCa(n) is the non-inverted signal of data An.

[0096] The refresh operation can be performed during the write operation, overlapping with the period from when the write data Awm is latched to the latch circuit LAT(m) until the control signal LTO is activated (for example, t23~t26). However, the refresh operation must be completed during the precharge operation when the control signal LTO is activated (t26).

[0097] As described above, in the gain cell memory according to this embodiment, the sense amplifier SA is connected to the read global bit line RGBL, but is not directly connected to the write global bit line WGBL. Therefore, the sense amplifier SA detects data in the memory cell MC, but is not used for writing or writing back data.

[0098] On the other hand, the transistor Tref of the refresh section REFC is located between the output of the sense amplifier SA and the write global bit line WGBL. This allows the data detected by the sense amplifier SA during the refresh operation to be bypassed to the write global bit line WGBL via transistor Tref and written back to the original memory cell MC. In other words, transistor Tref can function as a bypass path during the refresh operation.

[0099] The latch circuit LAT is connected in parallel to the transistor Tref between the output of the sense amplifier SA and the write global bit line WGBL. The latch circuit LAT can temporarily hold the data detected by the sense amplifier SA. The data held in the latch circuit LAT can be output externally via the input / output signal line LIO, and write data can be acquired externally via the input / output signal line LIO. The write data acquired by the latch circuit LAT can be written to the memory cell MC via the write global bit line WGBL. This enables read and write operations.

[0100] With this configuration, the gain cell memory allows the sense amplifier SA and transistor Tref to perform detection and refresh operations during the retention period when the latch circuit LAT holds data. During the retention period, the sense amplifier SA and transistor Tref are electrically isolated from the latch circuit LAT, and can therefore operate independently of the latch circuit LAT without affecting the data held by the latch circuit LAT. At this time, the latch circuit LAT may read data to the outside in accordance with a read command, or it may update the retained data by receiving written data from the outside in accordance with a write command, without being affected by the refresh operation.

[0101] In this way, in parallel with the operation of the latch circuit LAT, the sense amplifier SA can detect data in the memory cell MC, and the transistor Tref can write this detected data back to the same memory cell MC. In other words, the sense amplifier SA and transistor Tref can perform a refresh operation in parallel with the operation of the latch circuit LAT.

[0102] For example, in Figure 5, during the retention period from after the latch circuit LAT holds the read data (t7) until before the data held by the latch circuit LAT (read data or write data) is written back to or written to the memory cell MC (t26), the sense amplifier SA and transistor Tref can perform refresh operations (t14~t25). That is, during the retention period, the sense amplifier SA can detect the data of the memory cell MC that is the target of the refresh operation. Also, during the retention period, transistor Tref is turned on by the activation of the refresh signal REF, and the data detected by the sense amplifier SA can be written back from the sense amplifier SA to the memory cell MC that is the target of the refresh operation without going through the latch circuit LA. During the retention period, the latch circuit LAT is electrically isolated from the read global bit line RGBL and the write global bit line WGBL, so there is no problem even if the sense amplifier SA and transistor Tref perform refresh operations independently.

[0103] Conversely, transistor Tref is in the off state during the period when the latch circuit LAT is connected to the read global bit line RGBL (the period t5~t7 when the control signal LTI is activated), and during the period when the latch circuit LAT is connected to the write global bit line WGBL (the period t26~ when the control signal LTO is activated). In other words, transistor Tref is in the off state when either transistor Tlti or Tlto of the latch circuit LAT is on. This prevents the data Bm and Bn from being generated by the refresh operation from colliding with other read data Am and An or write data Awm on the read global bit line RGBL and the write global bit line WGBL.

[0104] Furthermore, the refresh operation may be performed on the memory cell MC that is being read from or written to. In this case, after the refresh operation, the data held in the latch circuit LAT will be written back to or written to the refreshed memory cell MC, but no problems will occur.

[0105] In this embodiment, the gain cell memory allows the detection unit SAC and the refresh unit REFC to perform refresh operations concurrently during the read or write operation of the latch circuit LAT. Therefore, the execution period for read and write operations is less limited by the refresh operation, thereby improving the execution bandwidth.

[0106] (Second Embodiment) Figure 6 is a timing diagram showing an example of the operation of a gain cell memory according to the second embodiment. Note that the configuration of the second embodiment may be the same as that of the first embodiment. In the second embodiment, while the sense amplifier SA is detecting data in the memory cell MCa, the latch circuit LAT writes back or writes data to the memory cell MCc.

[0107] In the first embodiment, when the sense amplifier SA detects data during a read operation, the read global bit line RGBL is used, but the write global bit line WGBL is not used.

[0108] Therefore, in the second embodiment, when the sense amplifier SA detects data in memory cell MCa during a read operation, the latch circuit LAT writes the data to memory cell MCc via the write global bit line WGBL. Although not shown in the diagram, memory cell MCc corresponds to the same global bit lines RGBL and WGBL as memory cell MCa and belongs to the same column, but it is a different memory cell. Like memory cells MCa and MCb, memory cell MCc is provided for each pair of global bit lines RGBL and WGBL (i.e., for each column m and n). Memory cell MCc(m) belongs to column m, and memory cell MCc(n) belongs to column n.

[0109] For example, first, at t0, the active command ACTa and the precharge command PREc are issued. At t1, the refresh command REF is issued. The operation of the gain cell memory by the active command ACTa and the refresh command REF is the same as the operation in the first embodiment.

[0110] At time t0, it is assumed that the latch circuits LAT(m) and LAT(n) already hold data that will be written back to or written to the memory cell MCc, due to operations prior to t0. For convenience, the precharge command PREc is a command that performs a write operation on the memory cell MCc and precharges the write bit lines WBL(m) and WBL(n), and is issued to address c stored in memory.

[0111] When the precharge command PREc is issued, at t2, the control signal LTO and the write word line WWLc are activated to a high voltage level. As a result, the latch circuits LAT(m) and LAT(n) are connected to the write global bit lines WGBL(m) and WGBL(n), respectively, and the retained data Cm and Cn are transmitted. As a result, the data Cm from the latch circuit LAT(m) is written to the memory cell MCc(m). The data Cn from the latch circuit LAT(n) is written to the memory cell MCc(n). At this time, the write transistor WTbl(m) corresponding to the memory cell MCc(m) is ON, and the write transistor WTbl(n) corresponding to MCc(n) is ON.

[0112] In t4_1, when the write word line WWLc is deactivated to a low voltage level, the memory cells MCc(m) and MCc(n), with the data Cm and Cn stored in them respectively, are electrically isolated from the write global bit lines WGBL(m) and WGBL(n).

[0113] Furthermore, at t8, when the control signal LTO is deactivated to a low voltage level, the latch circuits LAT(m) and LAT(n) are electrically isolated from the write global bit lines WGBL(m) and WGBL(n). Therefore, the latch circuits LAT(m) and LAT(n) can hold data from another memory cell MCa or MCb in the same column, or hold data written from an external source.

[0114] On the other hand, upon issuance of the active command ACTa, in t2~t8, the data Am and An from memory cells MCa(m) and MCa(n) are read out and detected by sense amplifiers SA(m) and SA(n) via global bit lines RGBL(m) and RGBL(n).

[0115] At t9, when the control signal LTI is activated, the latch circuits LAT(m) and LAT(n) are connected to the read global bit lines RGBL(m) and RGBL(n), and the data Am and An are acquired.

[0116] The read, write, and refresh operations from t9 onward may be the same as those from t9 onward in the first embodiment. Therefore, the second embodiment can obtain the same effects as the first embodiment.

[0117] In the second embodiment, the sense amplifier SA detects the data Am and An of the memory cells MCa(m) and MCa(n), and during the detection period (t0 to t9) before the latch circuits LAT(m) and LAT(n) hold the data Cm and Cn of the memory cells MCc(m) and MCc(n), the latch circuits LAT(m) and LAT(n) hold the data Cm and Cn. During this detection period, the latch circuits LAT(m) and LAT(n) write the data Cm and Cn back to the memory cells MCc(m) and MCc(n).

[0118] Alternatively, during the detection period described above, the latch circuits LAT(m) and LAT(n) hold the data that they intend to write to the memory cells MCc(m) and MCc(n). During this detection period, the latch circuits LAT(m) and LAT(n) write this data to the memory cells MCc(m) and MCc(n).

[0119] Thus, in the second embodiment, the data detection period (t0~t9) from memory cells MCa(m) and MCa(n) and the data write-back period (or write period) (t2~t8) to other memory cells MCc(m) and MCc(n) in the same column as memory cells MCa(m) and MCa(n) can be overlapped. As a result, the read and write operations can be made even faster in the second embodiment.

[0120] (Third embodiment) Figure 7 shows an example configuration of a gain cell memory according to the third embodiment. In the third embodiment, transistor Tref is connected between the output section SABO of the inverted signal of sense amplifier SA and the write global bit line WGBL. Transistor Tref is directly connected to the write global bit line WGBL. Accordingly, the inverter INref in Figure 3 is omitted. The other configurations of the third embodiment may be the same as those of the first embodiment.

[0121] The transistor Tref is connected to the output section SABO of the inverted signal of the sense amplifier SA. Therefore, the inverted signal of the read data is transmitted to the write global bit line WGBL. Thus, the third embodiment does not require the inverter INref, but the same effect as the first embodiment can be obtained. The third embodiment may be combined with the second embodiment.

[0122] Figure 8 is a circuit diagram showing an example configuration of a sense amplifier. An operational amplifier circuit AMP is provided between the output section SAO of the non-inverting signal and the output section SABO of the inverting signal. The operational amplifier circuit AMP compares the reference voltage Vref with the read data from the read global bit line RGBL, amplifies the difference between them, and outputs it from the output sections SAO and SABO.

[0123] For example, if the voltage of the read data is higher than the reference voltage Vref, the output unit SAO outputs a high-level voltage as a non-inverting signal, and the output unit SABO outputs a low-level voltage as an inverting signal. If the voltage of the read data is lower than the reference voltage Vref, the output unit SAO outputs a low-level voltage as a non-inverting signal, and the output unit SABO outputs a high-level voltage as an inverting signal.

[0124] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0125] MC memory cell MW1, MR1, MR2, Tlti, Tlto, Tlio transistors WWL writing word line WBL write bit line RWL Read Word Line RBL Read Bit Line WGBL Write Global Bit Line RGBL Read Global Bit Line SAC detection unit SA SenseAmp REFC Refresh Department Tref Transistor INref, INlat1, INlat2 inverters LATC latch LAT latch circuit

Claims

1. Multiple first data lines and multiple first control lines used for writing data, Multiple second data lines and multiple second control lines used for reading data, A plurality of memory cells, each including a first transistor whose gate is connected to one of the plurality of first control lines and one end of which is connected to one of the plurality of first data lines, a second transistor whose gate is connected to one of the plurality of second control lines and one end of which is connected to one of the plurality of second data lines, and a third transistor whose gate is connected to the other end of the first transistor and holds data from the first data lines, and one end of which is connected to the other end of the second transistor and enters a conductive state according to the data, A third data line provided corresponding to the plurality of first data lines, A fourth data line provided corresponding to the plurality of second data lines, A detection circuit is provided corresponding to the third or fourth data line, with its input connected to the fourth data line, and which detects the data. A holding circuit is provided between the output section of the detection circuit and the third data line, corresponding to the third or fourth data line, and which holds the data detected by the detection circuit. A semiconductor memory device comprising a fourth transistor provided in parallel with the holding circuit, corresponding to the third or fourth data line, and located between the output section of the detection circuit and the third data line.

2. The inverter circuit is further provided between the fourth transistor and the third data line, The detection circuit includes a first output unit that outputs data from the fourth data line in a non-inverted state, and a second output unit that outputs data from the fourth data line in an inverted state. The semiconductor memory device according to claim 1, wherein the fourth transistor is connected to the first output section of the detection circuit.

3. The detection circuit includes a first output unit that outputs data from the fourth data line in a non-inverted state, and a second output unit that outputs data from the fourth data line in an inverted state. The semiconductor memory device according to claim 1, wherein the fourth transistor is connected between the second output section and the third data line of the detection circuit.

4. The semiconductor memory device according to claim 3, wherein the fourth transistor is directly connected to the third data line.

5. The semiconductor memory device according to any one of claims 2 to 4, wherein the holding circuit is connected between the first output section of the detection circuit and the third data line.

6. The semiconductor memory device according to claim 1, wherein the fourth transistor becomes conductive during a refresh operation in which data from the memory cell is read and the data is written back to the same memory cell.

7. The semiconductor memory device according to claim 1, wherein the fourth transistor is in a non-conductive state during the period when the holding circuit is electrically connected to the detection circuit or the third data line.

8. The holding circuit is Between the first node and the second node, there are two inverters, one of which has an input connected to the other's output, A fifth transistor is provided between the first node and the detection circuit, A sixth transistor is provided between the input / output signal line (LIO) that inputs and outputs the aforementioned data to and from the outside and the first node, The semiconductor memory device according to claim 1, further comprising a seventh transistor provided between the second node and the third data line.

9. The holding circuit is The fifth transistor becomes conductive when it acquires data from the detection circuit. The sixth transistor becomes conductive when it transmits the held data to the input / output signal line, or when it receives data from the input / output signal line. The semiconductor memory device according to claim 8, wherein the seventh transistor becomes conductive when the held data is transmitted to the third data line.

10. The semiconductor memory device according to claim 8 or 9, wherein the fourth transistor is in a non-conductive state when the fifth or seventh transistor is in a conductive state.

11. The semiconductor memory device according to claim 8 or 9, wherein the gate of the sixth transistor is connected to a selection signal line that selectively connects one of the plurality of holding circuits to the input / output signal line.

12. The semiconductor memory device according to claim 1, wherein, during the period from when the holding circuit holds the data of the first memory cell to be read from among the plurality of memory cells, until the data held by the holding circuit is written back to the first memory cell, the detection circuit detects the data of the second memory cell to be refreshed from among the plurality of memory cells, and the fourth transistor becomes conductive and transmits the data detected by the detection circuit to the third data line and writes it back to the second memory cell.

13. The semiconductor memory device according to claim 12, wherein the fourth transistor transmits the data detected by the detection circuit to the third data line without going through the holding circuit.

14. The semiconductor memory device according to claim 1, wherein, after the holding circuit has held the data of the first memory cell to be written to among the plurality of memory cells, and before the holding circuit writes the updated data to the first memory cell, the detection circuit detects the data of the second memory cell to be refreshed among the plurality of memory cells, and the fourth transistor becomes conductive and transmits the data detected by the detection circuit to the third data line and writes it back to the second memory cell.

15. The semiconductor memory device according to claim 14, wherein the fourth transistor transmits the data detected by the detection circuit to the third data line without going through the holding circuit.

16. The semiconductor memory device according to claim 1, wherein, after the detection circuit detects the data of the first memory cell to be read from among the plurality of memory cells, and before the retention circuit holds the data of a second memory cell different from the first memory cell among the plurality of memory cells, the retention circuit holds the data of a second memory cell different from the first memory cell among the plurality of memory cells, and writes the data back to the second memory cell.

17. The semiconductor memory device according to claim 1, wherein, after the detection circuit detects the data of the first memory cell to be read from among the plurality of memory cells, and before the holding circuit holds it, the holding circuit holds write data to a second memory cell different from the first memory cell among the plurality of memory cells, and writes the write data to the second memory cell.

18. A plurality of eighth transistors are provided between the plurality of first data lines and the third data line, The system further comprises a plurality of ninth transistors provided between the plurality of second data lines and the fourth data line, Each of the plurality of eighth transistors connects one of the plurality of first data lines to the third data line. The semiconductor memory device according to claim 1, wherein the plurality of ninth transistors connect any one of the plurality of second data lines to the fourth data line.

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