Signal processing device, signal processing method, and program

Abstract

This makes it possible to suppress or reduce the increase in the overall circuit size and power consumption of the circuit. [Solution] A signal processing device that performs an inverse fast Fourier transform on N input data (where N is a positive integer greater than or equal to 3 and not a power of 2), comprising: a butterfly arithmetic processing means that performs a butterfly arithmetic operation on the input data; a transform twist arithmetic processing means that performs a twist arithmetic operation using a transform twist arithmetic coefficient obtained by multiplying the twist arithmetic coefficient for realizing the inverse fast Fourier transform by M / N; and a 1 / M arithmetic processing means that performs a 1 / M arithmetic operation (where M is a positive integer greater than or equal to 2 and not a power of 2) on the output data and outputs the operation result.

Description

[Technical Field]

[0001] This disclosure relates to a signal processing device, a signal processing method, and a program. [Background technology]

[0002] One of the important processes in digital signal processing is the Fast Fourier Transform (FFT). Another known technique is Frequency Domain Equalization (FDE), used to compensate for waveform distortion during signal transmission in wireless and wired communications. In frequency domain equalization, first, the FFT transforms the time-domain signal data into frequency-domain data. Next, a filter is applied for equalization. Finally, the filtered data is transformed back into time-domain signal data using the Inverse Fast Fourier Transform (IFFT). This process compensates for the waveform distortion of the original time-domain signal. Hereafter, when FFT and IFFT are not distinguished, they will be referred to as "FFT / IFFT".

[0003] Generally, the "butterfly operation" is used in FFT / IFFT processing. For example, Patent Document 1 describes an FFT device that uses the butterfly operation. Patent Document 1 also describes the "twiddle operation," which will be described later, that is, multiplication using a twiddle coefficient (twiddle factor: rotor). Furthermore, for example, Non-Patent Document 1 describes the Cooley-Tukey butterfly operation as an efficient FFT / IFFT processing method. Furthermore, for example, Reference Document 1 discloses the Prime Factor method as an efficient FFT / IFFT processing method.

[0004] Figure 12 shows the data flow 500 of a 64-point FFT process, which is decomposed into two stages of radix-8 butterfly operations using the Cooley-Tukey method. The data flow 500 consists of a total of 16 radix-8 butterfly operations, comprising the first stage of eight radix-8 butterfly operations 502-1 to 508 and the second stage of eight radix-8 butterfly operations 503-1 to 503-8, as well as the twist coefficient W(k)(W(k)=exp(-2πjk / N(=64), j×j=-1, k=0,.., N-1, W N k It includes a twist operation 504 that multiplies by (sometimes written as ). In Figure 12, the twist operation coefficients are (W(0), W(0),...,W(0)), (W(0), W(1), W(2),...,W(7)), (W(0), W(2), W(4),...,W(14)),..., (W(0), W(7),W(14),...,W(49)). In the data flow 500 shown in Figure 12, the input time-domain data x(n) (n=0,1,...,63) is subjected to a Fast Fourier Transform (FFT) to obtain a frequency-domain signal X(k) (k=0,1,...,63). Note that some data flow diagrams are omitted in Figure 12.

[0005] The data flow 500 shown in Figure 12 has the same basic configuration and butterfly arithmetic processing even when performing IFFT processing, but the direction of the twist operation is different. Furthermore, when the number of points in the IFFT processing is N (where N is a positive integer), an additional process is added to calculate 1 / N on the data value.

[0006] Figure 13 shows the data flow 510 of a 64-point IFFT process, which is broken down into two stages of radix-8 butterfly operations using the Cooley-Tukey method. The data flow 510 consists of a total of 16 radix-8 butterfly operations, comprising eight radix-8 butterfly operations in the first stage 512-1 to 512-8 and eight radix-8 butterfly operations in the second stage 513-1 to 513-8, as well as a twist operation 514 that multiplies by a twist coefficient W(k) (W(k)=exp(2πjk / N), j×j=-1) (in Figure 13, the twist coefficients are (W(0), W(0),…,W(0)), (W(0), W(1),…,W(7)),…,(W(0), W(7),…,W(49)), and a 1 / N operation 515 that calculates 1 / 64.

[0007] The twist coefficient W(k) in the IFFT process has the opposite sign to the twist coefficient in the FFT process, and therefore the twist direction is reversed. In the data flow 510 shown in Figure 13, the input frequency data X(k) (k=0,1,···,63) is inversely fast-fourier transformed into a time-domain signal x(n) (n=0,1,···,63) by the IFFT process. Note that some data flow diagrams are omitted in Figure 13.

[0008] The number of points N=64 in the FFT process shown in Figure 12 and the IFFT process shown in Figure 13 is a power of 2. However, FFT and IFFT processes where the number of points N is not a power of 2 can also be implemented using the same basic configuration.

[0009] FIG. 14 shows a data flow 520 of a 72-point IFFT process that is decomposed into two stages of a radix-8 butterfly process and a radix-9 butterfly process using the Cooley-Tukey method. The data flow 520 includes a butterfly operation process consisting of nine radix-8 butterfly operations 522-1 to 9 in the first stage, eight radix-9 butterfly operations 523-1 to 8 in the second stage, and a rotation operation 524 that multiplies a rotation operation coefficient W(k) (W(k) = exp(2πjk / N), j×j = -1). In FIG. 14, the rotation operation coefficients are (W(0), W(0),..., W(0)), (W(0), W(1),..., W(8)),..., (W(0), W(7),..., W(56)), and an operation 525 of 1 / N that calculates 1 / 72.

[0010] In the data flow 520 shown in FIG. 14, the input frequency data X(k) (k = 0, 1, ···, 71) is inverse fast Fourier transformed into a time-domain signal x(n) (n = 0, 1, ···, 71) by the IFFT process. Note that in FIG. 14, the illustration of some data flows is omitted.

Prior Art Documents

Non-Patent Documents

[0011]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0012] When the number of points of the IFFT process, N (N is a positive integer), is a power of 2, the process of calculating 1 / N can be realized not by division by N or multiplication by 1 / N, but by shift processing or the like. Specifically, when the number of points N of the IFFT process is 2 to the power of n (n is a positive integer) and the signal data is in fixed-point format, it can be realized by a right shift process of n bits for the signal data. Alternatively, when the signal data is in floating-point format, it can be realized by a subtraction process of n for the exponent part of the signal data.

[0013] For example, in the 64-point IFFT process shown in FIG. 13, the calculation process of 1 / 64 can be realized by a right shift process of 6 bits for the signal data or a subtraction process of subtracting 6 from the exponent part of the signal data. Therefore, in an IFFT circuit that realizes an IFFT process where the number of points N is a power of 2, the 1 / N calculation unit can be realized by a shift circuit or a subtraction circuit with a smaller circuit scale and power consumption than a division circuit or a multiplication circuit.

[0014] On the other hand, when the number of points N (N is a positive integer) of the IFFT process is not a power of 2, the process of calculating 1 / N cannot be realized by shift processing or the like. Therefore, it is necessary to be realized by division by N or multiplication by 1 / N.

[0015] For example, in the 72-point IFFT processing shown in Figure 14, the 1 / 72 calculation must be performed by division by 72 or multiplication by 1 / 72. Therefore, the 1 / N calculation unit in an IFFT circuit that implements IFFT processing where the number of points N is not a power of 2 will have a larger circuit size and higher power consumption compared to the 1 / N calculation unit in an IFFT circuit that implements IFFT processing where the number of points N is a power of 2. As a result, an IFFT circuit that implements IFFT processing where the number of points N is not a power of 2 will have a larger circuit size and higher power consumption compared to an IFFT circuit that implements IFFT processing where the number of points N is a power of 2. A signal processing device equipped with a digital filter circuit that implements frequency domain equalization processing using IFFT processing where the number of points N is not a power of 2 will have a larger circuit size and higher power consumption compared to a signal processing device equipped with a digital filter circuit that implements frequency domain equalization processing using IFFT processing where the number of points N is a power of 2.

[0016] Therefore, this disclosure was conceived in view of the above-mentioned problems, and aims to provide a signal processing device, a signal processing method, and a program that can suppress or reduce the increase in the overall circuit size and power consumption of the circuit. [Means for solving the problem]

[0017] One embodiment of the signal processing device of the present disclosure is an inverse fast Fourier transform device that performs an inverse fast Fourier transform on input frequency domain input data for each of N consecutive input data (where N is a positive integer greater than or equal to 3 and not a power of 2), and includes a butterfly arithmetic processing means for performing butterfly arithmetic processing, a conversion twist arithmetic processing means for performing conversion twist arithmetic processing, and a 1 / M arithmetic processing means for performing 1 / M arithmetic processing (where M is a positive integer greater than or equal to 2 and not a power of 2), wherein the conversion twist arithmetic processing means multiplies the twist coefficients that realize the inverse fast Fourier transform by a conversion twist coefficient obtained by multiplying it by M / N.

[0018] One embodiment of the signal processing device of the present disclosure includes: a Fast Fourier Transform (FFT) device that performs a Fast Fourier Transform on time-domain input data for each of N consecutive input data (where N is a positive integer that is not a power of 2); a Conversion Filter Calculator that performs a Conversion Filter Calculator on N first frequency-domain data generated by the Fast Fourier Transform device; and an Inverse Fast Fourier Transform (FFT) device that receives N second frequency-domain data filtered by the Filter Calculator and performs an Inverse Fast Fourier Transform on the input data. The Inverse Fast Fourier Transform (FFT) device includes: a butterfly calculation means that performs a butterfly calculation on the input data; a twist calculation means that performs a twist calculation to realize the Inverse Fast Fourier Transform; and a 1 / M calculation means that performs a 1 / M calculation (where M is a positive integer that is a power of 2) on the output data and outputs the calculation result. The aforementioned conversion filter calculation device multiplies the filter coefficients that achieve frequency domain equalization by a conversion filter coefficient obtained by multiplying the M / N ratio.

[0019] One embodiment of the present disclosure involves a process of performing a discrete or fast Fourier transform on N data points (where N is a positive integer greater than or equal to 3 and not a power of 2), and an inverse discrete or inverse fast Fourier transform on the N data points. In the Fourier transform process where the output data is multiplied by (1 / N) before output, the twist coefficient, which is complex multiplied on the data in response to one or more stages of butterfly operations, is multiplied by (M / N) (where M is 2 to the power of n and n is a predetermined integer) to obtain a transform twist coefficient, and instead of performing (1 / N) on the output data, the result of performing (1 / M) on the output data is output.

[0020] One form of the method described herein is a Fast Fourier Transform process that transforms N data points in the time domain (where N is a positive integer greater than or equal to 3 and not a power of 2) into the frequency domain. The process involves multiplying the converted data in the frequency domain by the filter coefficients, and An inverse fast Fourier transform process that converts N data points in the frequency domain back into N data points in the time domain and outputs the result. Execute, In the multiplication process of the filter coefficients, the data is multiplied by a transformed filter coefficient obtained by multiplying the filter coefficient by (M / N) (where M is 2 to the power of n and n is a predetermined integer). In the inverse fast Fourier transform process, instead of calculating (1 / N) on the output data, the result of calculating (1 / M) on the output data is output.

[0021] One form of the program described herein is a process of performing discrete or fast Fourier transform on N data points (where N is a positive integer greater than or equal to 3 and not a power of 2), and among the inverse discrete or inverse fast Fourier transform processes on the N data points, the Fourier transform process is one in which the output data is multiplied by (1 / N) before outputting, The twist coefficient, which is complex multiplied on the data in response to one operation of one or more stages of butterfly operations, is multiplied by (M / N) (where M is 2 to the power of n and n is a predetermined integer) to obtain a transformed twist coefficient, which is then complex multiplied on the data. Instead of calculating (1 / N) on the output data, the result of calculating (1 / M) on the output data is output. It consists of a program that causes a processor to execute a process.

[0022] One form of the program described herein is a Fast Fourier Transform (FCR) process that transforms N data points in the time domain (where N is a positive integer greater than or equal to 3 and not a power of 2) into the frequency domain. The process involves multiplying the converted data in the frequency domain by the filter coefficients, and An inverse fast Fourier transform process that converts N data points in the frequency domain back into N data points in the time domain and outputs the result. A program that includes, In the multiplication process of the filter coefficients, the data is multiplied by a transformed filter coefficient obtained by multiplying the filter coefficient by (M / N) (where M is 2 to the power of n and n is a predetermined integer). In the inverse fast Fourier transform process, instead of calculating (1 / N) on the output data, the result of calculating (1 / M) on the output data is output. This may also be a program that causes a processor to perform processing. According to one embodiment of this disclosure, this also includes a computer-readable non-temporary medium storing the program. [Effects of the Invention]

[0023] According to this disclosure, it is possible to suppress or reduce the increase in circuit size and power consumption of the signal processing device. [Brief explanation of the drawing]

[0024] [Figure 1] This diagram illustrates the data flow of an IFFT process according to one example of several embodiments of the present disclosure. [Figure 2] This figure schematically illustrates an example of the configuration of an IFFT circuit according to one of several embodiments of the present disclosure. [Figure 3] This figure schematically illustrates an example of the configuration of a conversion twist calculation processing unit according to one of several embodiments of the present disclosure. [Figure 4] This figure schematically illustrates an example of the configuration of a complex multiplication circuit according to one of several embodiments of the present disclosure. [Figure 5] This figure schematically illustrates an example of the configuration of a digital filter circuit according to one of several embodiments of the present disclosure. [Figure 6] This figure schematically illustrates an example of the configuration of an FFT circuit according to one of several embodiments of the present disclosure. [Figure 7] This figure schematically illustrates an example of the configuration of an IFFT circuit according to one of several embodiments of the present disclosure. [Figure 8] This figure schematically illustrates an example of the configuration of a conversion filter processing circuit according to one of several embodiments of the present disclosure. [Figure 9] This figure schematically illustrates an example of the configuration of a complex multiplication circuit according to one of several embodiments of the present disclosure. [Figure 10]This figure schematically illustrates an example of the configuration of a digital filter circuit according to one of several embodiments of the present disclosure. [Figure 11] This figure schematically illustrates an example of the configuration of an IFFT circuit according to one of several embodiments of the present disclosure. [Figure 12] This diagram illustrates an example of the data flow for a 64-point FFT processing technique related to this technology. [Figure 13] This diagram illustrates an example of the data flow for a 64-point IFFT processing technique related to this technology. [Figure 14] This diagram illustrates an example of the data flow for a 72-point IFFT processing technique related to this technology. [Figure 15] This figure illustrates a signal flow graph of a DFT with N=9. [Figure 16] Figure 15 illustrates an alternative signal flow graph (cardin 3). [Figure 17] This figure illustrates an IDFT signal flow graph for N=9. [Figure 18] This diagram schematically illustrates an example of implementation in a signal processing processor. [Modes for carrying out the invention]

[0025] Embodiments of the present invention will be described with reference to the drawings. Figure 1 is a diagram showing the data flow of an IFFT process according to an embodiment of the present disclosure. Figure 1 shows the data flow 100 of a 72-point IFFT process, which is decomposed into two stages: a radix 8 butterfly process and a radix 9 butterfly process, using the Cooley-Tukey method. The data flow 100 includes a butterfly operation process consisting of nine radix 8 butterfly operations 102-1 to 9 in the first stage and eight radix 9 butterfly operations 103-1 to 8 in the second stage, as well as a transform twist operation 104 that multiplies by a transform twist operation coefficient W'(k)(W'(k)=W(k)×M / N, W(k)=exp(2πj*k / N), j×j=-1), and a 1 / M operation 105 that calculates 1 / M. Here, N is the number of IFFT points and M is a power of 2. In Figure 1, W'(0), W'(0), ..., W'(0)), (W'(0), W'(1), ..., W'(8)), ..., (W'(0), W'(8), ..., W'(56) are the transformation torsion coefficients. The transformation torsion calculation coefficient W'(k) is the coefficient obtained by multiplying the original torsion calculation coefficient W(k) (W(k) = exp(2πjk / N), j × j = -1) in the IFFT process by M / N. In this embodiment, N = 72, M = 64, and M / N = 64 / 72.

[0026] In the data flow 100 shown in Figure 1, 72 input frequency domain signal data X(k) (k=0,1,···,71) are inversely fast Fourier transformed into 72 time domain signal data x(n) (n=0,1,···,71) by IFFT processing. Note that some data flow diagrams are omitted in Figure 1.

[0027] Figure 2 is a diagram showing an example configuration of an IFFT circuit 200 according to an exemplary first embodiment of the present disclosure. Figure 2 shows an example configuration of an IFFT circuit that realizes the data flow 100 of the IFFT processing according to the first embodiment of the present disclosure shown in Figure 1, and shows a 72-point IFFT circuit 200 that is decomposed into two stages, a radix 8 butterfly processing and a radix 9 butterfly processing, using the Cooley-Tukey method.

[0028] The IFFT circuit 200 consists of a butterfly arithmetic processing unit 202 with base 8 and a butterfly arithmetic processing unit 203 with base 9, and a conversion twist arithmetic processing unit 204 that multiplies by a conversion twist arithmetic coefficient W'(k) (W'(k)=W(k)×M / N, W(k)=exp(2πjk / N), j×j=-1) (In Figure 1, the twist arithmetic coefficients are (W'(0),W'(0),…,W'(0)), (W'(0), W'(1),…,W'(8)),…,(W'(0), It includes a 1 / M calculation unit 205 that calculates W'(8), ..., W'(56)) and 1 / M. These are units (circuits) that perform the butterfly calculation 102, butterfly calculation 103, transform twist calculation 104, and 1 / M calculation 105, respectively, in the data flow 100 of Figure 1. Here, N is the number of IFFT points and M is a power of 2. The transform twist calculation coefficient W'(k) is the coefficient obtained by multiplying the original twist calculation coefficient W(k) (W(k)=exp(2πjk / N), j×j=-1) in the IFFT process by M / N.

[0029] In this embodiment, N=72, M=64, and M / N=64 / 72. Since M is a power of 2, the 1 / M calculation unit 205 can be implemented with a circuit that has a small circuit size and low power consumption, such as a right shift circuit.

[0030] In the IFFT circuit 200 shown in Figure 2, 72 input frequency domain signal data X(k) (k=0,1,···,71) are inversely fast Fourier transformed into 72 time domain signal data x(n) (n=0,1,···,71) by IFFT processing. Note that some data flow diagrams are omitted in Figure 2.

[0031] Figure 3 shows an example of the configuration of the transformation twist calculation processing unit 204 in Figure 2. The transformation twist calculation processing unit 204 consists of N=72 complex multiplication circuits 214-1 to 214-72, which is the number of IFFT points. The complex multiplication circuits 214-1 to 214-72 multiply each of the signal data y(k) (k=0, 1, …71), which is the result of the radix 8 butterfly calculation processing output by the butterfly calculation processing unit 202, by the transformation twist calculation coefficient W'(k) (W'(k)=W(k)×M / N, W(k)=exp(2πjk / N), j×j=-1), and output the result as signal data y'(k) (k=0, 1, …71) to the radix 9 butterfly calculation processing unit 203.

[0032] Figure 4 is a schematic diagram illustrating the details of the configuration of the complex multiplication circuit 214 shown in Figure 3. The complex multiplication circuit 214 multiplies the input signal data y(k) by the transformation twist coefficient W'(k) and outputs the multiplication result to the signal data y'(k). Here, y(k), y'(k), and W'(k) are all complex numbers and are therefore given by the following equations. y(k) = yi(k) + jyq(k) …(1) W'(k) = W'i(k) + jW'q(k) …(2) y'(k) = y'i(k) + jy'q(k) …(3) So, y'i(k) = yi(k)×W'i(k) - yq(k)×W'q(k) …(4) y'q(k) = yi(k)×W'q(k) + yq(k)×W'i(k) …(5)

[0033] As explained above, in this embodiment, in IFFT processing where the number of points N is not a power of 2 (in this embodiment, N=72), the calculation of 1 / N required for IFFT processing is performed in both the conversion twist calculation processing unit 204 and the 1 / M calculation unit 205 (in this embodiment, M=64). Specifically, in the conversion twist calculation processing unit 204, the signal data is multiplied by M / N in addition to the original twist calculation coefficient W(k) (W(k)=exp(2πjk / N), j×j=-1) in IFFT processing. Next, in the 1 / M calculation unit 205, the signal data is multiplied by 1 / M. As a result, the signal data is multiplied by M / N × 1 / M = 1 / N, and the 1 / N multiplication required for IFFT processing is realized.

[0034] Here, since M is a power of 2, the 1 / M multiplication in the 1 / M calculation unit 205 can be achieved by shift processing, etc. Specifically, M=64 is 2 to the power of n (M=2 n (where n is a positive integer) and (M=2 6 If the signal data is in fixed-point format, this can be achieved by a 6-bit right shift operation on the signal data. Alternatively, if the signal data is in floating-point format, this can be achieved by subtracting 6 from the exponent of the signal data. Furthermore, in the conversion twist calculation processing unit 204, the conversion twist calculation coefficient W'(k) (W'(k)=W(k)×M / N, W(k)=exp(2πjk / N), j×j=-1) is a constant value that does not depend on the signal data value, and can therefore be calculated in advance during circuit design. Consequently, a new multiplication circuit is not required to calculate the conversion twist calculation coefficient W'(k) itself, and the multiplication circuit that realizes the twist calculation processing inherent in the IFFT circuit can be used to perform the multiplication processing between the signal data y(k) and the conversion twist calculation coefficient W'(k). As a result, compared to conventional IFFT circuits that require a division circuit by M or a multiplication circuit of 1 / M to achieve 1 / M multiplication, this embodiment allows the IFFT circuit to be realized with a smaller circuit size and lower power consumption. In this embodiment, the cases of N=72 and M=64 have been described above. However, this embodiment is not limited to these values, and can be applied to any positive integer N that is not a power of 2, and any positive integer M that is a power of 2.

[0035] Another embodiment of the present disclosure (a second embodiment) will be described. Figure 5 shows an example of the configuration of a digital filter circuit 300 according to this embodiment. The digital filter circuit 300 includes an FFT circuit 301, a conversion filter processing circuit 320, and an IFFT circuit 310, and performs digital filter processing using frequency domain equalization technology. In this embodiment, the number of points N=72 for the FFT circuit 301 and the IFFT circuit 310.

[0036] The FFT circuit 301 converts 72 signal data x(n) (n=0, 1, …, 71) in the time domain into 72 signal data X(k) (k=0, 1, …, 71) in the frequency domain. Next, the conversion filter processing circuit 320 multiplies the 72 signal data X(k) (k=0, 1, …, 71) output by the FFT circuit 301 by 72 conversion filter coefficients C'(k) (C'(k)=C(k)×M / N), and outputs the 72 signal data X'(k) =X(k)×C'(k) (k=0, 1, …, 71). Here, N is the number of FFT / IFFT points, and M is a power of 2. Therefore, the conversion filter coefficient C'(k) is a coefficient obtained by multiplying the filter coefficient C(k) that achieves frequency domain equalization by M / N, and in this embodiment, N=72, M=64, and M / N=64 / 72.

[0037] Figure 6 shows an example of the configuration of the FFT circuit 301 according to this embodiment. Figure 6 shows a 72-point FFT circuit 301 that is decomposed into two stages, a radix 8 butterfly process and a radix 9 butterfly process, using the Cooley-Tukey method. The FFT circuit 301 includes a butterfly arithmetic processing unit consisting of a radix 8 butterfly arithmetic processing unit 302 and a radix 9 butterfly arithmetic processing unit 303, and a twist arithmetic processing unit 304 that multiplies by a twist arithmetic coefficient W(k) (W(k)=exp(-2πjk / N), j×j=-1) (in Figure 6, the twist arithmetic coefficients are (W(0),W(0),…,W(0)), (W(0),W(1),…,W(8)),…,(W(0), W(8),…,W(56)). In the FFT circuit 301 shown in Figure 6, the input time-domain signal data x(n) (n=0,1,···,71) is subjected to a Fast Fourier Transform to frequency-domain signal data X(k) (k=0,1,···,71) by FFT processing. Note that some data flow diagrams are omitted in Figure 6.

[0038] Figure 7 shows an example of the configuration of the IFFT circuit 310 according to this embodiment. Figure 7 shows a 72-point IFFT circuit 310 that is decomposed into two stages, a radix 8 butterfly processing and a radix 9 butterfly processing, using the Cooley-Tukey method. The IFFT circuit 310 consists of a butterfly processing unit 312 for radix 8 and a butterfly processing unit 313 for radix 9, and a twist processing unit 314 that multiplies by a twist calculation coefficient W(k) (W(k)=exp(2πjk / N), j×j=-1) (in Figure 7, the twist calculation coefficients are (W(0),W(0),…,W(0)), (W(0), W(1),…,W(8)),…,(W(0), The circuit includes a 1 / M calculation unit 315 that calculates W(8), ..., W(56)) and 1 / M. Here, M is a power of 2, and in this embodiment, M = 64. Since M is a power of 2, the 1 / M calculation unit 315 can be implemented with a circuit that is small in size and power consumption, such as a right shift circuit. In the IFFT circuit 310 shown in Figure 7, the input frequency domain signal data X'(k) (k=0,1,···,71) is inversely fast Fourier transformed into time domain signal data x'(n) (n=0,1,···,71) by IFFT processing. Note that some data flow diagrams are omitted in Figure 7.

[0039] Figure 8 shows an example of the configuration of the conversion filter processing circuit 320 according to this embodiment. The conversion filter processing circuit 320 is composed of N=72 complex multiplication circuits 324-1 to 72, which is the number of FFT / IFFT points. For each of the 72 frequency domain signal data X(k) (k=0,1,...,71) output by the FFT circuit 301, 72 conversion filter coefficients C'(k) (C'(k)=C(k)×M / N) are multiplied, and the result is output to the IFFT circuit 310 as 72 signal data X'(k)=X(k)×C'(k) (k=0, 1, ...71).

[0040] Figure 9 schematically illustrates the details of the configuration of the complex multiplier circuit 324. The complex multiplier circuit 324 multiplies the input signal data X(k) by the transformation filter coefficient C'(k) and outputs the result to the signal data X'(k). Here, X(k), X'(k), and C'(k) are all complex numbers and are therefore given by the following equation.

[0041] X(k) = Xi(k) + jXq(k) …(6) C'(k) = C'i(k) + jC'q(k) …(7) X'(k) = X'i(k) + jX'q(k) …(8) So, X'i(k) = Xi(k)×C'i(k) - Xq(k)×C'q(k) …(9) X'q(k) = Xi(k)×C'q(k) + Xq(k)×C'i(k) …(10)

[0042] As explained above, in this embodiment, in an IFFT circuit where the number of points N in the digital filter circuit 300 is not a power of 2 (in this embodiment, N=72), the process of calculating 1 / N required for IFFT processing is performed in both the conversion filter processing circuit 320 and the 1 / M calculation unit 315 of the IFFT circuit 310 (in this embodiment, M=64). Specifically, in the conversion filter processing circuit 320, the signal data is multiplied by M / N in addition to the filter coefficient C(k) that realizes frequency domain equalization. Next, in the 1 / M calculation unit 315 of the IFFT circuit 310, the signal data is multiplied by 1 / M. As a result, the signal data is multiplied by M / N × 1 / M = 1 / N, and the 1 / N multiplication process required for IFFT processing is realized. Here, since M is a power of 2, the 1 / M multiplication process in the 1 / M calculation unit 315 can be realized by shift processing, etc. Specifically, M=64 is 2 to the power of n (M=2 n (where n is a positive integer) and (M=2 6If the signal data is in fixed-point format, this can be achieved by a 6-bit right shift operation on the signal data. Alternatively, if the signal data is in floating-point format, this can be achieved by subtracting 6 from the exponent of the signal data.

[0043] Furthermore, in the conversion filter processing circuit 320, the conversion filter C'(k) (C'(k) = C(k) × M / N) is a constant value that does not change while the filtering process is being performed, regardless of the signal data value, etc., and can therefore be calculated in advance during circuit design or before the filtering process is executed. Consequently, a new multiplication circuit is not required to calculate the conversion filter coefficient C'(k) itself, and the multiplication process between the signal data X(k) and the conversion filter coefficient C'(k) can be achieved using the multiplication circuit necessary to achieve frequency domain equalization. As a result, compared to conventional IFFT circuits that require a division circuit by M or a multiplication circuit of 1 / M to achieve 1 / M multiplication, this embodiment has the effect of realizing an IFFT circuit with a smaller circuit size and lower power consumption. Moreover, the circuit size and power consumption of the digital filter circuit that realizes frequency domain equalization, including the IFFT circuit, can be reduced.

[0044] In this embodiment, the cases of N=72 and M=64 have been described above. However, this embodiment is not limited to these values, and can be applied to any positive integer N that is not a power of 2, and any positive integer M that is a power of 2.

[0045] Further embodiments of the present disclosure (a third embodiment) will be described. Figure 10 shows an example of the configuration of a digital filter circuit 330 according to this embodiment. The digital filter circuit 330 comprises an FFT circuit 301, a conversion filter processing circuit 320, an IFFT circuit 331, an M selection circuit 332, and a coefficient table circuit 333, and performs digital filter processing by frequency domain equalization technique. In this embodiment, the FFT circuit 301 and the conversion filter processing circuit 320 have the same configuration as in the second embodiment described above, and the number of points N=72 for the FFT circuit 301 and the IFFT circuit 331.

[0046] The M selection circuit 332 is a circuit that selects a value of M, which is a power of 2, by referring to the value of the filter coefficient C(k) that achieves frequency domain equalization. Specifically, the conversion filter coefficient C'(k) = C(k) × M / N …(11) We calculate the value and select a power of 2, M, such that the calculated value C'(k) is the largest value within the range of possible values ​​for C'(k).

[0047] Therefore, when the value of C(k) is small, the value of M becomes large, and as a result, the value of C'(k) becomes large. On the other hand, when the value of C(k) is large, the value of M becomes small, and as a result, the value of C'(k) becomes small.

[0048] In other words, the M selection circuit 332 is a circuit that appropriately selects M by referring to the value of the filter coefficient C(k), and regardless of the value of C(k), realizes the function of keeping the value of the conversion filter coefficient C'(k) within a predetermined range.

[0049] The M selection circuit 332 outputs the selected power of two, M, to the IFFT circuit 331. Based on the selected power of two, M, it also outputs M / N (in this embodiment, N=72, M=128, M / N=128 / 72) to the coefficient table circuit 333.

[0050] The coefficient table circuit 333 is a circuit that stores 72 conversion filter coefficients C'(k) = C(k) × M / N (k=0,1,…,71) calculated from the input C(k) and the M / N output by the M selection circuit 332.

[0051] In this embodiment, the 72 filter coefficients C(k) are input one by one, and the converted filter coefficient C'(k) is calculated one by one and stored in the coefficient table circuit 333. The coefficient table circuit 333 simultaneously outputs the 72 stored converted filter coefficients C'(k) (k=0,1,...,61) to the converted filter processing circuit 320.

[0052] Similar to the second embodiment, in this embodiment as well, the conversion filter processing circuit 320 multiplies each of the frequency domain signal data X(k) (k=0,1,···,71) output by the FFT circuit 301 by the conversion filter coefficient C'(k) (C'(k)=C(k)×M / N).

[0053] Furthermore, the conversion filter processing circuit 320 outputs the result of multiplying the signal data X(k) by the conversion filter coefficient C'(k) as signal data X'(k) (k=0, 1, …71) to the IFFT circuit 331.

[0054] Figure 11 shows an example configuration of the IFFT circuit 331 of the digital filter circuit 330 in Figure 10. Figure 11 shows a 72-point IFFT circuit 410 that is decomposed into two stages, a radix 8 butterfly process and a radix 9 butterfly process, using the Cooley-Tukey method. The IFFT circuit 410 includes a butterfly arithmetic processing unit consisting of nine base-8 butterfly arithmetic processing units 412-1 to 412-9 and eight base-9 butterfly arithmetic processing units 413-1 to 413-8, a twist arithmetic processing unit 414 that multiplies by a twist arithmetic coefficient W(k) (W(k)=exp(2πjk / N), j×j=-1) (in Figure 11, the twist arithmetic coefficients are (W(0),W(0),…,W(0)), (W(0), W(1),…,W(8)),…,(W(0), W(8),…,W(56)), and a 1 / M arithmetic unit 415 that calculates 1 / M.

[0055] In this embodiment, the butterfly arithmetic processing units 412, 413 and the twist arithmetic processing unit 414 have the same configuration as the circuits that constitute the IFFT circuit 310 in the second embodiment. The 1 / M calculation unit 415 calculates 1 / M on the signal data output by the butterfly arithmetic processing units 413-1 to 418 based on the M output by the M selection circuit 332 (Figure 10). Here, M is a power of 2, and in this embodiment, M = 128. Since M is a power of 2, the 1 / M calculation unit 415 can be implemented with a circuit that has a small circuit size and low power consumption, such as a right shift circuit. In the IFFT circuit 410 shown in Figure 11, the input frequency domain signal data X'(k) (k=0,1,···,71) is inversely fast Fourier transformed into time domain signal data x'(n) (n=0,1,···,71) by IFFT processing. Note that some data flow diagrams are omitted in Figure 11.

[0056] As explained above, in this embodiment, in an IFFT circuit where the number of points N in the digital filter circuit 330 is not a power of 2 (in this embodiment, N=72), the process of calculating 1 / N required for IFFT processing is performed in both the conversion filter processing circuit 320 and the 1 / M calculation unit 415 in the IFFT circuit 331 (in this embodiment, M=128).

[0057] Specifically, in the conversion filter processing circuit 320, the signal data is multiplied by M / N in addition to the filter coefficient C(k) that realizes frequency domain equalization. Next, in the 1 / M calculation unit 315 of the IFFT circuit 310, the signal data is multiplied by 1 / M. As a result, the signal data is multiplied by M / N × 1 / M = 1 / N, and the 1 / N multiplication required for IFFT processing is realized. Here, since M is a power of 2, the 1 / M multiplication in the 1 / M calculation unit 415 can be realized by shift processing, etc. Specifically, M=128 is 2 to the power of n (M=2 n (where n is a positive integer) and (M=2 7) When the signal data is in fixed-point format, it can be realized by a 7-bit right shift operation on the signal data. Alternatively, when the signal data is in floating-point format, it can be realized by subtracting 7 from the exponent part of the signal data.

[0058] Also, in the conversion filter processing circuit 320, since the conversion filter C'(k) (C'(k) = C(k) × M / N) is a constant value that does not change while the filter processing is being executed regardless of the signal data value or the like, it can be calculated one by one in advance before the execution of the filter processing and stored in the coefficient table circuit 333. Therefore, only one multiplication circuit is newly required for calculating the conversion filter coefficient C'(k) itself, and the multiplication process of the signal data X(k) and the conversion filter coefficient C'(k) can be realized by the multiplication circuit that is originally provided to realize frequency domain equalization. As a result, compared with the conventional IFFT circuit that requires a division circuit by M or a multiplication circuit of 1 / M to realize the 1 / M multiplication process, according to this embodiment, there is an effect that the IFFT circuit can be realized with a small circuit scale and low power consumption. Furthermore, the circuit scale and power consumption of the digital filter circuit that realizes frequency domain equalization including the IFFT circuit can be reduced.

[0059] Also, the M selection circuit 332 has a function of appropriately selecting M by referring to the value of the filter coefficient C(k) and keeping the value of the conversion filter coefficient C'(k) within a certain range. As a result, the signal amplitude of the signal data X'(k) = X(k) × C'(k), which is the input of the IFFT circuit 331, is adjusted to an appropriate range, and even when the value of the filter coefficient C(k) is small, the calculation error in the IFFT circuit 331 can be reduced. Therefore, since it is not necessary to increase the calculation accuracy of the IFFT circuit 331 in preparation for the case where the value of C(k) is small, the circuit scale and power consumption of the IFFT circuit 331 can be reduced.

[0060] As described above, in this embodiment, N = 72, and M = 128 (= 2 7Although the case described above is limited to these values, this embodiment can be applied to any positive integer N that is not a power of 2, and any positive integer M that is a power of 2.

[0061] In the Discrete Fourier Transform (DFT), the number of complex multiplications is given as the square of the number of points N, whereas in the Fast Fourier Transform (FFT), when the number of points N is a power of 2, the number of complex multiplications is (N / 2)log2(N) and the number of complex additions is Nlog2(N). However, this disclosure is also applicable to the DFT. An N-point DFT can be expressed as follows.

[0062] TIFF2026136788000002.tif19153 …(12) TIFF2026136788000003.tif15153 …(13) W N This is the twiddle factor, which corresponds to the twist calculation coefficient mentioned above.

[0063] The inverse discrete Fourier transform (IDFT) can be expressed as follows: TIFF2026136788000004.tif19153 …(14)

[0064] Here, as the simplest example where N is not a power of 2, we will explain the 3-point DFT for the case N=3. The result of performing a 3-point DFT on (x(0),x(1),x(2)) (X(0),X(1),X(2)) can be expressed by equation (15) from equation (12).

[0065] TIFF2026136788000005.tif16150…(15)

[0066] The result of performing a 3-point IDFT operation on (X(0),X(1),X(2)) (x(0),X(1),X(2)) can be expressed by equation (16) from equation (14).

[0067] TIFF2026136788000006.tif16150…(16)

[0068] Substituting equation (15) into (X(0),X(1),X(2)) in equation (16), we obtain equation (17) below.

[0069] TIFF2026136788000007.tif16150 TIFF2026136788000008.tif16150…(17)

[0070] Here, TIFF2026136788000009.tif6150 Therefore, equation (17) is given by:

[0071] TIFF2026136788000010.tif16150…(18)

[0072] From equation (18), by the (1 / N) operation in the IDFT of equation (14), (x(1), x(2), …,x(N))=IDFT(DFT[(x(1), x(2), …,x(N))]) …(19) It is confirmed that this holds true.

[0073] N=2 n In that case, 1 / N is 2 (-n) Therefore, each coefficient in the binary representation can be arithmetic shifted by n bits. When N=3, according to this disclosure, for example, if M is 2 to the power of n (n: integer), then 1 / N = (1 / M) × (M / N), and as shown in equation (20), the rotor W N k Multiply (k=0,2,2) by (M / 3) and then multiply by (1 / M) (Note that in equation (20), M=2 n For example, n=0, or rotor WN k (If there are no issues with the multiplication precision, etc., n can include negative integers.)

[0074] TIFF2026136788000011.tif31150…(20)

[0075] Figure 15 illustrates the signal flow 600 of a DFT with N=9 as a simple example where the number of points N is not a power of 2. In Figure 15, as a simple example of a mixed-cardinal DFT, we outline the DFT of equation (21) with the number of points N=p1×q1=3×3 (p1=3, q1=3).

[0076] TIFF2026136788000012.tif14150…(21) TIFF2026136788000013.tif6150…(22)

[0077] The inner loop of equation (21) can be expressed as a q1-point DFT, as shown in equation (23). TIFF2026136788000014.tif14150…(23)

[0078] The inner loop of equation (21) consists of radix 3 butterfly operations (arithmetic processing units) 601-1 to 60-3 (previous butterfly operations) in Figure 15. More specifically, The radix 3 butterfly operation 601-1 in Figure 15 takes (x(0), x(3), x(6)) as input and outputs (G0(0), G0(1), G0(2)), which corresponds to l=0 and k=0, 1, 2 in equation (23). The radix 3 butterfly operation 601-2 in Figure 15 takes (x(1), x(4), x(7)) as input and outputs (G1(0), G1(1), G1(2)), which corresponds to l=1 and k=0, 1, 2 in equation (23). The radix 3 butterfly operation 601-3 in Figure 15 takes (x(2), x(5), x(8)) as input and outputs (G2(0), G2(1), G2(2)), which corresponds to l=2 and k=0, 1, 2 in equation (23).

[0079] The butterfly operation (processing unit) 602 of the outer loop in equation (21) can be expressed as a DFT at p1 points. TIFF2026136788000015.tif14150…(24)

[0080] In Figure 15, the rotor (torsion coefficient) in the butterfly operation 602 is given by W in equation (24). N lk This corresponds to the above, but due to the limitations of the drawing, only a portion is shown, and instead, it is written within each equation of X(k)(k=0,..,N-1).

[0081] The butterfly operation (processing unit) 602 in Figure 15 may be configured to improve efficiency as a radix 3 butterfly operation, for example, as shown in Figure 16.

[0082] X(k) = G0(k) + W N k G1(k)+W N 2k G2(k) …(25) X(k+q1)=G0(k)+W N k W N q1 G1(k)+W N 2k W N 2q1 G2(k) …(26) X(k+2q1)=G0(k)+W N k W N 2q1 G1(k)+W N 2k W N 4q1 G2(k) …(27) (k=0,1,2, q1=3, N=9)

[0083] however, TIFF2026136788000016.tif9150…(28)

[0084] In Figure 15, TIFF2026136788000017.tif9150…(29) As a result, the signal flow of the IDFT with N=9 points in this disclosure is as shown in Figure 17.

[0085] In Figure 17, the butterfly operation (processing unit) 702, which is the second stage of the three sets of base 3 butterfly operations, performs the same butterfly operation as the butterfly operation 602 in Figure 15. Note that, for the sake of drawing convenience, the formula for the butterfly operation result (twist operation processing result), (g(0), g(1), g(2), ..., g(8)), is omitted.

[0086] The conversion torsion calculation (processing unit) 704 calculates each rotor W in equation (24). N lk (l=0,…,p1-1,k=0,1,2,) with (M / N)=(2 n Multiply by (M / N)(=2) in Figure 17. Therefore, (g(0), g(1), g(2), ..., g(8)) in Figure 17 is the result of the butterfly operation in Figure 15, (X(0), X(1), X(2), ..., X(8)) multiplied by (M / N)(=2). n This is the value obtained by multiplying by ( / 9).

[0087] The 1 / M calculation (processing unit) 705 calculates (1 / M) (=2) for (g(0), g(1), g(2), ..., g(8)). -n Multiply by ) and output (x(0), x(1), x(2), ..., x(8)).

[0088] Of course, the butterfly operation 702 in Figure 17 may also be configured as shown in Figure 16.

[0089] The above-described embodiment can also accommodate the following variations of DFT (FFT). For example, it can be applied to configurations where the calculation result is multiplied by (1 / N) on the DFT (FFT) side and the (1 / N) calculation is not performed in IDFT (IFFT) (see equations (30) and (31) below), or configurations where the calculation result is multiplied by (1 / √N) in DFT (FFT) and output, and the calculation result is multiplied by (1 / √N) in IDFT (IFFT) and output (see equations (31) and (32) below).

[0090] TIFF2026136788000018.tif13150…(30)

[0091] TIFF2026136788000019.tif19153 …(31)

[0092] TIFF2026136788000020.tif19153 …(32)

[0093] TIFF2026136788000021.tif19153 …(33)

[0094] In the above-described embodiment, as shown in Figure 18, the processor 801 may be implemented as a signal processing processor 800 such as a DSP (Digital Signal Processor) whose performance is variable by a program stored in memory 802. In Figure 8, the I / O device 803 connected to the processor 801 by bus 804 is used for data input and output of calculation result data. The memory 802 may be configured to include any of the following: DRAM (Dynamic RAM (Random Access Memory)), ROM (Read-Only Memory), EEPROM (Electrically Erasable Programmable Read-Only Memory), SSD (Solid State Drive), HDD (Hard Disk Drive), etc.

[0095] Note that a butterfly operation with base 8 may also be a butterfly operation with base 4 × base 2, and a butterfly operation with base 9 may also be a butterfly operation with base 3 × base 3.

[0096] [Reference 1] Japanese Patent Publication No. Hei 8-137832 (pp. 3-5, Figure 25) [Reference 2] DPKolba, "A Prime Factor FFT Algorithm Using High-Speed ​​Convolution," IEEE Trans. on Acoustics, US, IEEE Signal Processing Society, Aug. 1977, Vol.29, No.4, pp. 281-294

[0097] Furthermore, the disclosures in the above-mentioned non-patent literature and references are incorporated into this book by reference. Within the framework of the entire disclosure in this book (including the claims), further modifications and adjustments to the embodiments or examples are possible based on the fundamental technical concept. Also, within the framework of the claims, various combinations or selections of various disclosed elements (including each element of each claim, each element of each embodiment, each element of each drawing, etc.) are possible. That is, of course, this includes various modifications and alterations that a person skilled in the art could make in accordance with the entire disclosure and the technical concept. [Explanation of Symbols]

[0098] 100 Data Flow (Signal Flow) 10²⁻¹~9, 10³⁻¹~8 butterfly operation 104 Transformation Twist Operation 105 1 / M operation 200 IFFT circuit 202-1~9, 203-1~8 Butterfly arithmetic processing unit 204 Conversion Twist Calculation Processing Unit 205 1 / M calculation section 214 Complex Multiplication Circuit 300 Digital Filter Circuits 301 FFT circuit 302-1~9, 303-1~8 Butterfly arithmetic processing unit 304 Twist calculation processing unit 310 IFFT circuit 312-1~9, 313-1~8 Butterfly arithmetic processing unit 314 Twist calculation processing unit 315 1 / M operation section 320 Conversion Filter Processing Circuit 324 Complex Multiplication Circuit 330 Digital Filter Circuit 331 IFFT circuit 332 M Selector Circuit 333 Coefficient Table Circuit 400, 410 IFFT circuit 412-1~9, 413-1~8 Butterfly arithmetic processing unit 414 Twist calculation processing unit 415 1 / M operation section 500 data flows 501 Data Sorting Processing Unit 502-1~8, 503-1~8 Butterfly arithmetic processing unit 504 Twist calculation processing unit 510 Dataflow 512-1~8, 513-1~8 Butterfly arithmetic processing unit 514 Twist calculation processing unit 515 1 / N calculation section 520 Dataflows 522-1~8, 523-1~8 Butterfly arithmetic processing unit 523 Butterfly arithmetic processing unit 524 Twist calculation processing unit 525 1 / N calculation section 600 data flows (signal flows of 9-point DFT) 601-1 to 601-3: Butterfly arithmetic in base 3 602 Butterfly operation 700 Dataflow (Signal flow of 9-point IDFT) 701-1~701-3 Base 3 butterfly arithmetic (processing unit) 702 Butterfly arithmetic (processing unit) 704 Conversion Twist Calculation (Processing Unit) 705 1 / M calculation (processing unit) 800 signal processing processors 801 Processor 802 memory 803 IO device 804 Bus (Common Bus)

Claims

1. A signal processing device that performs an inverse fast Fourier transform on N input data (where N is a positive integer greater than or equal to 3 and not a power of 2), A butterfly arithmetic processing means performs butterfly arithmetic processing on the aforementioned input data, A transformation torsion calculation processing means performs a torsion calculation using a transformation torsion calculation coefficient obtained by multiplying the torsion calculation coefficient for realizing the inverse fast Fourier transform by M / N, A 1 / M calculation processing means performs a 1 / M calculation on the output data (where M is a positive integer that is a power of 2 greater than or equal to 2) and outputs the calculation result. A signal processing device, including a signal processing device.

2. A Fast Fourier Transform (FFT) device that performs a Fast Fourier Transform on time-domain input data for every N consecutive input data points (where N is a positive integer, not a power of 2), A transformation filter calculation device performs transformation filter calculation processing on N first frequency domain data generated by the fast Fourier transform device, An inverse fast Fourier transform device that receives N data points in a second frequency domain that have been filtered by the aforementioned conversion filter device and performs an inverse fast Fourier transform on the input data, Equipped with, The inverse fast Fourier transform device is, A butterfly arithmetic processing means performs butterfly arithmetic processing on the aforementioned input data, A torsion calculation processing means that performs the torsion calculation processing to realize the inverse fast Fourier transform, A 1 / M calculation processing means performs a 1 / M calculation (where M is a positive integer that is a power of 2) on the output data and outputs the calculation result. Includes, The aforementioned conversion filter calculation device is a signal processing device that multiplies the filter coefficients that achieve frequency domain equalization by a conversion filter coefficient obtained by multiplying the M / N ratio.

3. M selection means for selecting M by referring to the filter coefficients that achieve the frequency domain equalization, A coefficient table means for holding the conversion filter coefficients, Equipped with, The M selection means selects M according to the range of values ​​that can be set for the conversion filter coefficient, The signal processing apparatus according to claim 2, wherein the 1 / M calculation processing means performs a 1 / M calculation based on the M selected by the M selection means.

4. In the process of performing a discrete or fast Fourier transform on N data points (where N is a positive integer greater than or equal to 3 and not a power of 2), and in the process of performing an inverse discrete or inverse fast Fourier transform on the said N data points, in the Fourier transform process where the output data is multiplied by (1 / N), The twist coefficient, which is complex multiplied on the data in response to one operation of one or more stages of butterfly operations, is multiplied by (M / N) (where M is 2 to the power of n and n is a predetermined integer) to obtain a transformed twist coefficient, which is then complex multiplied on the data. A signal processing device that outputs the result of calculating (1 / M) on the output data, instead of calculating (1 / N) on the output data.

5. In the process of performing a discrete or fast Fourier transform on N data points (where N is a positive integer greater than or equal to 3 and not a power of 2), and in the process of performing an inverse discrete or inverse fast Fourier transform on the said N data points, in the Fourier transform process where the output data is multiplied by (1 / N), The twist coefficient, which is complex multiplied on the data in response to one operation of one or more stages of butterfly operations, is multiplied by (M / N) (where M is 2 to the power of n and n is a predetermined integer) to obtain a transformed twist coefficient, which is then complex multiplied on the data. A signal processing method that outputs the result of calculating (1 / M) on the output data, instead of calculating (1 / N) on the output data.

6. Fast Fourier Transform (FFT) is a process that transforms N data points in the time domain (where N is a positive integer greater than or equal to 3, and not a power of 2) into the frequency domain. The process involves multiplying the converted data in the frequency domain by the filter coefficients, and An inverse fast Fourier transform process is performed to convert N data points in the frequency domain back into N data points in the time domain and output the result. In the multiplication process of the filter coefficients, the data is multiplied by a transformed filter coefficient obtained by multiplying the filter coefficient by (M / N) (where M is 2 to the power of n and n is a predetermined integer). In the inverse fast Fourier transform process, instead of calculating (1 / N) on the output data, the signal processing method outputs the result of calculating (1 / M) on the output data.

7. The signal processing method according to claim 6, wherein M is selected according to the possible values ​​of the filter coefficient.

8. The process of performing a discrete or fast Fourier transform on N data points (where N is a positive integer greater than or equal to 3 and not a power of 2), and the process of performing an inverse discrete or inverse fast Fourier transform on the said N data points, is defined as a Fourier transform process in which the output data is multiplied by (1 / N) before outputting, The twist coefficient, which is complex multiplied on the data in response to one operation of one or more stages of butterfly operations, is multiplied by (M / N) (where M is 2 to the power of n and n is a predetermined integer) to obtain a transformed twist coefficient, which is then complex multiplied on the data. Instead of calculating (1 / N) on the output data, the result of calculating (1 / M) on the output data is output. A program that causes a processor to execute a process.

9. Fast Fourier Transform (FFT) is a process that transforms N data points in the time domain (where N is a positive integer greater than or equal to 3, and not a power of 2) into the frequency domain. The process involves multiplying the converted data in the frequency domain by the filter coefficients, and A program that includes an inverse fast Fourier transform process that inversely transforms N data in the frequency domain into N data in the time domain and outputs the result, In the multiplication process of the filter coefficients, the data is multiplied by a transformed filter coefficient obtained by multiplying the filter coefficient by (M / N) (where M is 2 to the power of n and n is a predetermined integer). In the inverse fast Fourier transform process, instead of calculating (1 / N) on the output data, the result of calculating (1 / M) on the output data is output. A program that causes a processor to execute a process.

10. The program according to claim 9, which causes the processor to perform a process of selecting the M according to the possible values ​​of the filter coefficient.

Images