Semiconductor device and method for manufacturing a semiconductor device

Abstract

To provide a semiconductor device and a method for manufacturing a semiconductor device that can improve yield. [Solution] Insulating layers 12 and 13 are provided on the front surface of the semiconductor substrate 11 in the edge termination region 2. Insulating layer 12 is provided inside the scribe region 3 remaining on the outer circumference of the semiconductor substrate 11 and covers the withstand voltage structure 30 and the channel stopper region 33. Insulating layer 13 is provided in the scribe region 3. The thickness t2 of insulating layer 13 is thinner than the thickness t1 of insulating layer 12. The scribe region 3 is the remainder of the scribe line of the semiconductor wafer. Because the insulating layers 12 and 13 reduce the stress on the front surface side of the semiconductor wafer, the magnitude of the stress imbalance between the front and back surfaces of the semiconductor wafer after the formation of the surface electrode 54 can be reduced compared to the case where an insulating layer of a constant thickness is provided on the front surface of the semiconductor substrate 11 in the edge termination region 2, and the amount of warping of the semiconductor wafer is reduced.

Description

[Technical Field]

[0001] This disclosure relates to semiconductor devices and methods for manufacturing semiconductor devices. [Background technology]

[0002] During the manufacturing process of semiconductor devices, warping can occur in semiconductor wafers. If the warping becomes too large, problems such as the inability to transport the semiconductor wafer can occur. Patent Document 1 below describes a technique for suppressing warping by forming an oxide film with a thicker thickness on the C side than on the Si side of a silicon carbide semiconductor wafer. On the other hand, Patent Document 2 below describes a technique for selectively removing the oxide film formed by thermal oxidation during gate insulating film formation in the dicing region of a semiconductor wafer using a semiconductor material with a wider band gap than silicon (Si), thereby exposing the front surface of the semiconductor wafer. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2024-148882 [Patent Document 2] Japanese Patent Publication No. 2021-68741 [Overview of the project] [Problems that the invention aims to solve]

[0004] While the above-mentioned Patent Document 2 may potentially suppress warping of semiconductor wafers, the front surface of the semiconductor wafer is exposed during the manufacturing process of the semiconductor device. This may lead to a decrease in yield due to dust adhering to the exposed front surface of the semiconductor wafer or the formation of a plating film.

[0005] This disclosure aims to provide a semiconductor device and a method for manufacturing a semiconductor device that can improve yield while suppressing warping of semiconductor wafers. [Means for solving the problem]

[0006] A semiconductor device according to one aspect of this disclosure is as follows: A semiconductor substrate comprises an active region through which a main current flows and a termination region surrounding the active region. The termination region includes a scribe line remaining on the outer periphery of the semiconductor substrate, a channel stopper region provided on the first main surface side of the semiconductor substrate inside the scribe line, a first insulating layer provided on the first main surface of the semiconductor substrate inside the scribe line and covering the channel stopper region, and a second insulating layer provided on the first main surface of the semiconductor substrate at the scribe line. The thickness of the second insulating layer is thinner than the thickness of the first insulating layer.

[0007] Furthermore, a method for manufacturing a semiconductor device according to one aspect of this disclosure is a method for manufacturing a semiconductor device comprising a semiconductor substrate having an active region through which a main current flows and a termination region surrounding the active region, and is as follows: A first step is performed to form a channel stopper region on the first main surface side of the semiconductor wafer in a region corresponding to the termination region of the chip region of the semiconductor wafer. A second step is performed to form an insulating layer on the first main surface of the semiconductor wafer. A third step is performed to cut the semiconductor wafer along a scribe line surrounding the chip region and separate the chip region from the semiconductor wafer into individual pieces on the semiconductor substrate. In the second step, an insulating layer is formed having a first insulating layer covering the channel stopper region and a second insulating layer covering the scribe line, and the thickness of the second insulating layer is made thinner than the thickness of the first insulating layer. [Effects of the Invention]

[0008] The semiconductor device and method for manufacturing the semiconductor device described herein have the effect of improving yield. [Brief explanation of the drawing]

[0009] [Figure 1] This is a plan view showing the layout of the semiconductor device according to the embodiment, as seen from the front side of the semiconductor substrate. [Figure 2] This is a cross-sectional view showing the cross-sectional structure along the cutting lines A1-A2-A3 in Figure 1. [Figure 3] This is a cross-sectional view showing another example of the cross-sectional structure along the cutting line A2-A3 in Figure 1. [Figure 4] This is a flowchart illustrating the outline of the method for manufacturing a semiconductor device according to the embodiment. [Figure 5] This is a cross-sectional view showing the layout of a semiconductor device during the manufacturing process according to an embodiment, as seen from the front side of the semiconductor wafer. [Figure 6] This is a cross-sectional view (part 1) showing the semiconductor device according to the embodiment in the process of being manufactured. [Figure 7] This is a cross-sectional view (part 2) showing the semiconductor device according to the embodiment in the process of being manufactured. [Figure 8] This is a cross-sectional view showing the structure of the edge termination region of a reference semiconductor device. [Modes for carrying out the invention]

[0010] <Summary of the embodiments of this disclosure> (1) A semiconductor device according to one aspect of this disclosure is as follows: A semiconductor substrate comprises an active region through which a main current flows and a termination region surrounding the active region. The termination region comprises a scribe line remaining on the outer circumference of the semiconductor substrate, a channel stopper region provided on the first main surface side of the semiconductor substrate inside the scribe line, a first insulating layer provided on the first main surface of the semiconductor substrate inside the scribe line and covering the channel stopper region, and a second insulating layer provided on the first main surface of the semiconductor substrate at the scribe line. The thickness of the second insulating layer is thinner than the thickness of the first insulating layer.

[0011] According to the above disclosure, the stress applied to the first main surface side of the semiconductor wafer is reduced by the first and second insulating layers during the fabrication (manufacturing) of the semiconductor device, thereby reducing or mitigating the warping of the semiconductor wafer in subsequent manufacturing processes. This suppresses the occurrence of problems caused by the warping of the semiconductor wafer in subsequent manufacturing processes (e.g., reduced alignment accuracy and increased variation in the thickness of the deposited film). Since variations in electrical characteristics between multiple semiconductor chips (semiconductor devices) of the same structure in the same lot can be suppressed, the yield of semiconductor devices can be improved.

[0012] (2) In addition, in the semiconductor device relating to this disclosure, the thickness of the second insulating layer may be 1 / 2 or less of the thickness of the first insulating layer as described in (1) above.

[0013] According to the disclosure described above, the thinner the second insulating layer, the more the warping of the semiconductor wafer can be reduced or mitigated during the fabrication of the semiconductor device.

[0014] (3) In addition, in the semiconductor device relating to this disclosure, the thickness of the second insulating layer may be 8000 Å or less, as described in (1) or (2) above.

[0015] According to the disclosure described above, the thinner the second insulating layer, the more the warping of the semiconductor wafer can be reduced or mitigated during the fabrication of the semiconductor device.

[0016] (4) In addition, in any one of (1) to (3) above, the outer peripheral end of the channel stopper region may be located at the inner peripheral end of the scribe line.

[0017] According to the disclosure described above, it is possible to suppress the increase in the inactive region outside the channel stopper region, which does not function as a semiconductor device.

[0018] (5) The semiconductor device according to this disclosure also includes, in any one of (1) to (4) described above, a breakdown voltage structure provided in the terminal region on the first main surface side of the semiconductor substrate, away from the channel stopper region and inside the channel stopper region, and the first insulating layer may cover the breakdown voltage structure and the channel stopper region.

[0019] According to the disclosure described above, the breakdown voltage inside the semiconductor substrate can be secured by the breakdown voltage structure and the channel stopper region, and the breakdown voltage on the upper surface (front surface of the semiconductor substrate) of the breakdown voltage structure and the channel stopper region can be secured by the first insulating layer.

[0020] (6) A method for manufacturing a semiconductor device according to one aspect of this disclosure is a method for manufacturing a semiconductor device comprising a semiconductor substrate having an active region through which a main current flows and a termination region surrounding the active region, and is as follows: A first step is performed to form a channel stopper region on the first main surface side of the semiconductor wafer in a region corresponding to the termination region of the chip region of the semiconductor wafer. A second step is performed to form an insulating layer on the first main surface of the semiconductor wafer. A third step is performed to cut the semiconductor wafer along a scribe line surrounding the chip region and separate the chip region from the semiconductor wafer into individual pieces on the semiconductor substrate. In the second step, an insulating layer is formed having a first insulating layer covering the channel stopper region and a second insulating layer covering the scribe line, and the thickness of the second insulating layer is made thinner than the thickness of the first insulating layer.

[0021] According to the disclosure described above, the first and second insulating layers reduce the stress on the first main surface side of the semiconductor wafer, thereby reducing or mitigating warping of the semiconductor wafer in the subsequent manufacturing process. As a result, even if warping occurs in the semiconductor wafer, the manufacturing process can be continued without discarding the semiconductor wafer, thereby improving the yield of semiconductor devices.

[0022] (7) Furthermore, in the method for manufacturing a semiconductor device according to the disclosure, in the second step described in (6) above, a plurality of insulating films may be laminated on the first main surface of the semiconductor wafer, forming a first insulating layer formed by laminating all of the insulating films and a second insulating layer formed by laminating some of the insulating films among the plurality of insulating films.

[0023] According to the disclosure described above, the thickness of the first and second insulating layers can be easily set.

[0024] <Knowledge forming the basis of this disclosure> First, the structure of the reference example semiconductor device will be described. Figure 8 is a cross-sectional view showing the structure of the edge termination region of the reference example semiconductor device. The reference example semiconductor device 110 shown in Figure 8 includes a semiconductor substrate (semiconductor chip) 111, an edge termination region 102, a scribe region 103 on the outer periphery of the semiconductor substrate 111, and an insulating layer 112 covering the entire front surface of the semiconductor substrate 111. The semiconductor substrate 111 has an active region 101 through which the main current (drift current) of the semiconductor device 110 flows, and an edge termination region 102 between the active region 101 and the edge (chip edge) of the semiconductor substrate 111. The edge termination region 102 surrounds the active region 101.

[0025] The scribe region 103 is the remaining portion of the cutting allowance (scribe line of the semiconductor wafer) when cutting individual semiconductor chips (semiconductor substrate 111) from a semiconductor wafer. The scribe region 103 is provided around the entire outer circumference of the semiconductor substrate 111. The insulating layer 112 is formed by stacking a field oxide film 121, a gate insulating film 122, and an interlayer insulating film 123 in that order, and covers the withstand voltage structure (not shown) and channel stopper region (not shown) of the edge termination region 102. The thickness t101 of the insulating layer 112 is relatively thick, for example, about 15000 Å, and is substantially constant throughout the entire edge termination region 102 up to the chip edge.

[0026] When forming a plating film on the surface electrode 131 on the front surface of a semiconductor substrate 111, the insulating layer 112 is also formed on the scribe lines of the semiconductor wafer (not shown) to prevent the surface of the semiconductor wafer from being exposed during the plating process on the surface electrode 131 (the metal layer that fills the contact holes 112a of the insulating layer 112), thereby preventing the plating film from adhering to the front surface of the semiconductor wafer. However, experiments conducted by the inventors have confirmed that the relatively thick thickness t101 of the insulating layer 112 formed extending to the scribe lines of the semiconductor wafer causes significant warping of the semiconductor wafer.

[0027] When a semiconductor wafer is warped, it means that, for example, the entire semiconductor wafer has a roughly arc-shaped cross-section, with one point (a predetermined point or area) on the main surface (front and back) of the wafer acting as its apex, and the curved portion protruding convexly towards the front or back side in a direction approximately perpendicular to the main surface. Another type of warping in a semiconductor wafer is saddle warping (wave-shaped). The amount of warping in a semiconductor wafer is the distance between the apex of the main surface of the warped and curved semiconductor wafer in a direction perpendicular to the main surface of the wafer before warping occurs, and the point on the main surface of the semiconductor wafer furthest from that apex (specifically, the edge of the semiconductor wafer). In other words, the amount of warping in a semiconductor wafer is the height of the arc (arc height) of a semiconductor wafer with a roughly arc-shaped cross-section.

[0028] For example, on a semiconductor wafer, multiple chip regions that will become semiconductor chips (semiconductor substrates 111) are arranged in a matrix, and scribe lines are formed in a grid pattern surrounding each chip region. When manufacturing a semiconductor device 110 using a semiconductor wafer made of silicon carbide (SiC), which is expected to be the next-generation semiconductor material to replace silicon (Si), an insulating layer 112 with a thickness t101 of about 15,000 Å is formed on the entire surface of the front of the semiconductor wafer so as to cover the entire area of ​​the scribe lines. After that, the metal layer formed on the entire surface of the front of the semiconductor wafer is patterned and etched to leave the portion that will become the surface electrode 131, and the amount of warpage of the semiconductor wafer becomes about 150 μm or more.

[0029] Furthermore, warping of the semiconductor wafer can also occur due to the adverse effects of heat associated with ion implantation. Warping of the semiconductor wafer can also occur when insulating layers 112, polysilicon (poly-Si) layers such as wiring layers, and metal layers such as surface electrodes 131 and 132 are formed on the surface of the semiconductor wafer, due to the difference in thermal expansion coefficients between these layers and the semiconductor wafer, which creates a stress difference between the front and back sides of the semiconductor wafer. Warping of the semiconductor wafer can also occur when the semiconductor wafer is thinned to a predetermined thickness by grinding from the back side, as the stress balance between the front and back sides of the semiconductor wafer is disrupted. The warping that occurs in the semiconductor wafer in this way accumulates and increases as the manufacturing process of the semiconductor device 110 progresses.

[0030] When the amount of warping of a semiconductor wafer increases, it may become impossible to place the semiconductor wafer on the stage of the semiconductor manufacturing equipment, or cracks may occur in the semiconductor wafer, making it difficult to feed the semiconductor wafer into subsequent manufacturing processes and thus reducing the product yield. Yield is the ratio of the number of actual products (semiconductor devices that satisfy predetermined design conditions) to the calculated number of semiconductor devices (semiconductor chips separated from the semiconductor wafer) obtained from the semiconductor wafer fed into the manufacturing process. As a result of diligent research, the inventors have found that the amount of warping of a semiconductor wafer changes depending on the thickness of the insulating layer 112 on the scribe line of the semiconductor wafer. This disclosure is based on experimental findings and theoretical considerations.

[0031] One of the problems to be solved in this embodiment is to improve yield by reducing the warping of semiconductor wafers.

[0032] Preferred embodiments of the semiconductor device and method for manufacturing the semiconductor device according to this disclosure will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers or regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. Furthermore, the + and - signs attached to n and p indicate higher and lower impurity concentrations, respectively, compared to layers or regions without these signs. In the following description of embodiments and in the accompanying drawings, similar components are denoted by the same reference numerals, and redundant explanations are omitted.

[0033] (Details of the embodiment) A semiconductor device according to an embodiment that solves the above-mentioned problems will be described below. Figure 1 is a plan view showing the layout of the semiconductor device according to the embodiment as seen from the front side of the semiconductor substrate. Figure 2 is a cross-sectional view showing the cross-sectional structure along the cutting lines A1-A2-A3 in Figure 1. Figure 3 is a cross-sectional view showing another example of the cross-sectional structure along the cutting lines A2-A3 in Figure 2. The configuration of the edge termination region 2 shown in Figure 3 is the same as in Figure 2, except for the insulating layers 12 and 13. The semiconductor device 10 according to the embodiment shown in Figures 1 and 2 comprises, in the edge termination region 2 of the semiconductor substrate (semiconductor chip) 11, a scribe region 3 on the outer periphery of the semiconductor substrate 11, and insulating layers (first and second insulating layers) 12 and 13 that cover the front surface of the semiconductor substrate 11 with different thicknesses t1 and t2.

[0034] The semiconductor substrate 11 can be made of compound semiconductors such as silicon carbide (SiC) or gallium nitride (GaN). For example, semiconductor devices using SiC as the semiconductor material have various advantages compared to semiconductor devices using silicon (Si), such as being able to reduce the thickness of the semiconductor substrate 11 while maintaining the breakdown voltage, thereby reducing the on-resistance to about a few hundredths of the original, and being usable in high-temperature environments (e.g., around 200°C or higher). This is due to the inherent characteristics of SiC, which has a bandgap about three times larger than Si and a dielectric breakdown field strength nearly an order of magnitude greater than Si. Breakdown voltage is the upper limit voltage at which a semiconductor device will not malfunction or break down at its operating voltage.

[0035] As shown in Figure 1, the semiconductor substrate 11 has an active region 1 and an edge termination region 2. The active region 1 has a roughly rectangular planar shape and is located approximately in the center of the semiconductor substrate 11 (the center of the chip). Multiple cells (functional units of elements) of the same structure are arranged in parallel in the central part 1a of the active region 1. The central part 1a of the active region 1 has, for example, a roughly rectangular planar shape and is the region through which the main current (drift current) flows when the semiconductor device 10 is turned on. The outer periphery 1b of the active region 1 surrounds the central part 1a of the active region 1 in a roughly rectangular shape. A p-type outer periphery region 55 (see Figure 2), which will be described later, is provided in the outer periphery region 1b of the active region 1. The active region 1 is the part from the outer edge of the p-type outer periphery region 55 inward (towards the center of the chip).

[0036] Examples of semiconductor devices 10 using SiC as a semiconductor material include Schottky barrier diodes (SBDs), and vertical MOSFETs (Metal Oxide Semiconductor Field Effect Transistors: MOS-type field-effect transistors with an insulated gate consisting of a three-layer structure of metal-oxide-semiconductor) with planar gate or trench gate structures. The semiconductor device 10 may also be an IGBT (Insulated Gate Bipolar Transistor). Here, we will explain using the case where the semiconductor device 10 is a vertical MOSFET with a trench gate structure as an example.

[0037] The edge termination region 2 is the region between the active region 1 and the chip edge, and surrounds the active region 1 in a roughly rectangular shape. A predetermined withstand voltage structure 30 (see Figure 2), such as a field limiting ring (FLR), a junction termination extension (JTE) structure, or a guard ring, is placed in the edge termination region. The withstand voltage structure 30 has the function of mitigating the electric field applied to the inside of the semiconductor substrate 11 (the surface region on the front side) and maintaining the withstand voltage. The edge termination region 2 has a scribe region 3 around the entire outer circumference of the semiconductor substrate 11. The scribe region 3 is the remaining portion of the cutting allowance (scribe line 62: see Figure 5, described later) when cutting the semiconductor chip (semiconductor substrate 11) from the semiconductor wafer 60 with a dicing blade or the like.

[0038] As shown in Figure 2, the semiconductor substrate 11 is, for example, n + On the front surface of the mold starting substrate (bulk substrate) 21, n + The semiconductor substrate 11 is formed by epitaxially growing an epitaxial layer 22 made of the same material as the starting substrate 21. The semiconductor substrate 11 has the first main surface on the epitaxial layer 22 side as the front surface, n + The second main surface on the mold starting substrate 21 side is considered the back surface. Here, we will explain using the case where the semiconductor substrate 11 is made of SiC as an example. SiC has an extremely small impurity diffusion coefficient compared to Si, and with ion implantation at normal acceleration energies (for example, around 900 KeV or less), impurities do not easily penetrate deep into the SiC from the ion implantation surface. For this reason, by performing ion implantation in each epitaxial layer as the epitaxial layers are stacked in multiple stages, a diffusion region of a predetermined conductive impurity that has been ion-implanted deep from the front surface of the semiconductor substrate 11 is formed.

[0039] Also, when the material of the semiconductor substrate 11 is SiC, a diffusion region of a predetermined conductivity type impurity may be formed in the SiC by combining ion implantation at normal acceleration energy and ion implantation at a high acceleration energy (for example, about 1 MeV or more) capable of implanting impurities to a deep position from the ion implantation surface. In this case or when the material of the semiconductor substrate 11 is Si, the semiconductor substrate 11 may be composed of only a bulk substrate. When the semiconductor substrate 11 is composed of only a bulk substrate, by not performing epitaxial growth, process control of an epitaxial growth apparatus is not required, and crystal defects due to epitaxial growth are not formed in the semiconductor substrate 11, so that characteristic variations of the semiconductor device 10 can be suppressed. Also, maintenance costs of the epitaxial growth apparatus can be reduced.

[0040] n + -type starting substrate 21 is an n + -type drain region 41. The epitaxial layer 22 becomes an n - -type drift region 42. At the front surface side of the semiconductor substrate 11 in the central portion 1a of the active region 1, a trench gate structure including a p-type base region 45, an n + -type source region 46, base contact regions 47, 48, a trench 49, a gate insulating film 50, and a gate electrode 51 is provided. The n - -type drift region 42 is a portion of the n - -type epitaxial layer 22 excluding the trench gate structure, an n-type current diffusion region 43, a p + -type region 44, a p-type outer peripheral region 55, a p + -type outer peripheral contact region 56, a breakdown voltage structure 30 (p-type region 31, p + -type region 32), and a channel stopper region 33, and reaches the chip end portion provided between these regions and the n + -type starting substrate 21 from the active region 1 to the edge termination region 2.

[0041] The p-type base region 45, n + -type source region 46, base contact regions 47, 48, n-type current diffusion region 43, p + [[ID=3^2]]-type region 44, p-type outer peripheral region 55, p +Type outer peripheral contact area 56, p-type area 31, p + The p-type region 32 and the channel stopper region 33 are diffusion regions of a predetermined conductive type impurity selectively formed inside the epitaxial layer 22 by ion implantation. The p-type base region 45 and the p-type base contact region 47 are located in the central part 1a of the active region 1, between the front surface of the semiconductor substrate 11 and n - They are selectively provided between the type drift region 42 and the other region. + The p-type source region 46 is provided in contact with the p-type base region 45, covering the entire area between the front surface of the semiconductor substrate 11 and the p-type base region 45. + The p-type base contact region 48 is provided in contact with the p-type base contact region 47, covering the entire area between the front surface of the semiconductor substrate 11 and the p-type base contact region 47.

[0042] p-type base region 45 and n + The p-type source region 46 faces the gate electrode 51 via the gate insulating film 50 at the side wall of the trench 49. The p-type base contact region 47 and p + The type base contact region 48 is provided away from the trench 49, and the p-type base region 45 and n-type base region are respectively located away from the trench 49. + It faces the side wall of the trench 49 via the type source region 46. + Type source region 46 is p + n is greater than the base contact area 48 of the type. + The p-type drain region 41 may be terminated at a deeper position. The p-type base contact region 47 is n-type. + The drain region 41 may be terminated at a deeper position. + Type source region 46 and p + The base contact region 48 is in contact with the barrier metal 53 on the front surface of the semiconductor substrate 11. + The p-type base contact region 47 may be in contact with the barrier metal 53 on the front surface of the semiconductor substrate 11 without providing the p-type base contact region 48.

[0043] The n-type current diffusion region 43 is n -Between the p-type drift region 42 and the p-type base region 45 and the p-type base contact region 47, n is greater than the bottom surface of the trench 49. + It is selectively provided at a deep position on the drain region 41 side. The n-type current spreading region 43 is a so-called current spreading layer that reduces the carrier spreading resistance. The n-type current spreading region 43 is n - Type drift region 42, p + The n-type current diffusion region 43 is in contact with the type region 44, the p-type base region 45, and the p-type base contact region 47, and faces the gate electrode 51 via the gate insulating film 50 at the side wall of the trench 49. The n-type current diffusion region 43 may extend to the outer periphery 1b or edge termination region 2 of the active region 1, or it may reach the tip edge. If the n-type current diffusion region 43 is not provided, - The type drift region 42 may be in contact with the p-type base region 45 and the p-type base contact region 47.

[0044] p + Type region 44 is n - Between the p-type drift region 42 and the p-type base region 45, n is greater than the bottom surface of the trench 49. + It is selectively provided at a deep position on the drain region 41 side. + The mold region 44 is provided separately from the p-type base region 45 and the p-type base contact region 47, and faces the bottom surface of the trench 49 in the depth direction. + The mold region 44 has the function of mitigating the electric field applied to the gate insulating film 50 at the bottom surface of the trench 49. + The p-type region 44 is partially connected to, for example, the p-type base contact region 47 or the p-type outer peripheral region 55, and is fixed to the potential of the source electrode. + The mold region 44 may be in contact with the gate insulating film 50 at the bottom of the trench 49, and may also be along the side wall of the trench 49. + It may extend toward the type source area 46. + The type region 44 may be separate from the trench 49. + Type region 44 and n - An n-type current diffusion region 43 may be interposed between the n-type drift region 42 and the n-type current diffusion region 43.

[0045] The trench 49 extends in the depth direction from the front surface of the semiconductor substrate 11 to n + The n-type current diffusion region 43 penetrates the p-type source region 46 and the p-type base region 45 (if the n-type current diffusion region 43 is not provided, then n - Either terminates within the n-type drift region 42) or passes through the n-type current diffusion region 43 to p + It terminates inside the type region 44. The trench 49 is n greater than the p-type base contact region 47. + The trench may be terminated at a deeper position on the drain region 41 side. Inside the trench 49, a gate insulating film 50 is provided along the inner walls (side walls and bottom surface) of the trench 49. The gate insulating film 50 extends from the side walls of the trench 49 onto the front surface of the semiconductor substrate 11 to the chip edge, covering the entire front surface of the semiconductor substrate 11. Inside the trench 49, a gate electrode 51 is provided on the gate insulating film 50 so as to embed the trench 49.

[0046] In the outer peripheral portion 1b of the active region 1, the front surface of the semiconductor substrate 11 and n - A p-type outer peripheral region 55 is provided throughout the entire area between the type drift region 42 and the trench 49. The p-type outer peripheral region 55 is n + It terminates at a shallow position on the source region 46 side. The outer region 55 of the p type is n + The p-type drain region 41 may be terminated at a deeper position. The p-type outer peripheral region 55 surrounds the central part 1a of the active region 1 in a roughly rectangular shape. The entire area between the front surface of the semiconductor substrate 11 and the p-type outer peripheral region 55 is in contact with the p-type outer peripheral region 55. + A mold outer peripheral contact area 56 is provided. + The outer peripheral contact region 56 of the mold contacts the barrier metal 53 on the front surface of the semiconductor substrate 11. + The p-type outer peripheral region 55 may contact the barrier metal 53 on the front surface of the semiconductor substrate 11 without providing the type outer peripheral contact region 56.

[0047] The interlayer insulating film 52 is provided over the entire surface of the front surface of the semiconductor substrate 11 via the gate insulating film 50 so as to cover the gate electrode 51. The interlayer insulating film 52 is a single layer of silicon oxide (SiO2) film such as BPSG (Boron Phospho Silicate Glass), PSG (Phospho Silicate Glass), BSG (Boron Silicate Glass), or NSG (Non-doped Silicate Glass), or a silicon nitride (SixNy, where x and y are positive numbers) film, or a laminate of two or more of these. An SiO2 film such as a high-temperature oxide (HTO) film may be provided over the entire area between the gate insulating film 50 and the interlayer insulating film 52. Contact holes 52a and 52b are provided that penetrate the interlayer insulating film 52 and the gate insulating film 50 in the depth direction.

[0048] The barrier metal 53 makes ohmic contact with the front surface of the semiconductor substrate 11 at the contact holes 52a and 52b. The barrier metal 53 is, for example, a titanium nitride (TiN) film or a titanium (Ti) film, or a multilayer film thereof. The surface electrode 54 on the front surface of the semiconductor substrate 11 is provided on the interlayer insulating film 52 in the active region 1 so as to fill the contact holes 52a and 52b. The surface electrode 54 is in contact with the p-type base region 45, n-type base region 45 via the barrier metal 53 at the contact hole 52a. + The p-type source region 46 and base contact regions 47, 48 are electrically connected. The surface electrode 54 is connected to the p-type outer peripheral region 55 and p through the barrier metal 53 in the contact hole 52b. + It is electrically connected to the outer peripheral contact region 56 of the mold. A barrier metal 53 may be interposed between the surface electrode 54 and the interlayer insulating film 52.

[0049] The surface electrode 54 is made of, for example, aluminum (Al), aluminum-silicon (Al-Si), aluminum-copper (Al-Cu), or copper (Cu). The surface electrode 54 and barrier metal 53 function as source electrodes. The front surface of the semiconductor substrate 11 is protected by an uppermost surface protective film (not shown) made of polyimide. The portion of the surface electrode 54 exposed to the opening of the surface protective film (passivation film) functions as a source pad (electrode pad). A plating film (not shown) may be formed on the surface of the source pad. This plating film provides solder wettability to the surface of the source pad. The plating film on the surface of the source pad has the function of improving the adhesion between the source pad and metal wiring, such as bonding wires, when soldering metal wiring to the surface of the source pad.

[0050] In the edge termination region 2, the front surface of the semiconductor substrate 11 and n - Between the p-type drift region 42 and the pressure-resistant structure 30, multiple (three in Figure 2) p-type regions 31 are selectively provided. The multiple p-type regions 31 are the p-type outer peripheral region 55 and p + It is located away from the outer peripheral contact region 56 and further out (towards the tip end) than these regions, concentrically surrounding the active region 1. The entire area between the front surface of the semiconductor substrate 11 and the p-type region 31 is in contact with the p-type region 31. + A type region 32 is provided. + The p-type region 32 is exposed on the front surface of the semiconductor substrate 11. + The type region 32 is, for example, the p-type outer region 55 and p + It is formed simultaneously with the outer peripheral contact region 56 of the mold. + The p-type region 31 may reach the front surface of the semiconductor substrate 11 without providing the type region 32.

[0051] Figure 2 illustrates a pressure-resistant structure 30 in which multiple p-type regions 31 (FLRs) with the same impurity concentration and floating potential are arranged concentrically around the active region 1, separated from each other, forming an FLR structure (guard ring structure). -Between the p-type drift region 42 and the p-type outer peripheral region 55 and the p-type region 31, an n-type current diffusion region 43 may extend from the central part 1a of the active region 1, adjacent to these regions. - The p-type drift region 42) extends between the outer p-type region 55 and the innermost p-type region 31, and between adjacent p-type regions 31, + The outer peripheral contact area 56 and the innermost p + Between type region 32 and adjacent p + It passes between the mold regions 32 and reaches the front surface of the semiconductor substrate 11.

[0052] The pressure-resistant structure 30 may be a JTE structure (for example, a multi-zone JTE structure or a spatially modulated JTE structure). The multi-zone JTE structure is a structure in which three or more p-type regions fixed to the potential of the source electrode are arranged concentrically adjacent to the active region 1 such that the p-type regions with lower impurity concentrations are located further away from the active region 1. The spatially modulated JTE structure is an improved JTE structure in which a p-type spatially modulated region is placed between two adjacent p-type regions, adjacent to these two p-type regions, and has an impurity concentration distribution spatially equivalent to the intermediate impurity concentration of the two p-type regions, thereby gradually decreasing the impurity concentration distribution of the entire JTE structure outward. The spatially modulated region is formed by repeatedly arranging two small p-type regions, each with approximately the same impurity concentration as the p-type regions adjacent to it on both sides, in a predetermined pattern concentrically adjacent to the active region 1.

[0053] Furthermore, in the edge termination region 2, the front surface of the semiconductor substrate 11 and n - Between the drift region 42 and the floating potential n + type or p +A channel stopper region 33 of a certain type is selectively provided. The channel stopper region 33 is provided outside the withstand voltage structure 30, at a distance from the withstand voltage structure 30, and surrounds the withstand voltage structure 30. The channel stopper region 33 is provided inside the scribe region 3 and does not reach the tip edge. The channel stopper region 33 is exposed on the front surface of the semiconductor substrate 11. The outer edge of the channel stopper region 33 is preferably located at the inner edge of the scribe region 3. The portion of the semiconductor substrate 11 outside the channel stopper region 33 is an inactive region that does not function as a semiconductor device 10. By having the outer edge of the channel stopper region 33 located at the inner edge of the scribe region 3, it is possible to suppress an increase in the surface area of ​​the inactive region of the semiconductor substrate 11.

[0054] n - The n-type current diffusion region 43 of the central part 1a of the active region 1 may extend to the tip edge, adjacent to the n-type drift region 42 and the channel stopper region 33. The channel stopper region 33 is an n-type current diffusion region 43 (if an n-type current diffusion region 43 is not provided, then n - It is surrounded by the n-type drift region 42). The n-type current diffusion region 43 consists of the channel stopper region 33 and the outermost p-type region 31 and p + The space between the type region 32 and the channel stopper region 33 and the chip edge extends to the front surface of the semiconductor substrate 11. The channel stopper region 33 has the function of suppressing the depletion layer extending from the pn junction by the p-type region 31 of the breakdown structure 30 to reach the chip edge when the semiconductor device 10 is turned off. The channel stopper region 33 is, for example, n + It is formed simultaneously with the mold source region 46. A field plate and channel stopper electrodes are not provided.

[0055] In the edge end region 2, the entire front surface of the semiconductor substrate 11 inside the scribe region 3 is covered by the insulating layer 12, and the entire front surface of the semiconductor substrate 11 in the scribe region 3 is covered by the insulating layer 13. The insulating layer 12 covers the entire upper surface (front surface of the semiconductor substrate 11) of the pressure-resistant structure 30 and the channel stopper region 33, and has a function of ensuring a predetermined withstand voltage on the upper surfaces of the pressure-resistant structure 30 and the channel stopper region 33. The insulating layer 12 extends to the outer peripheral portion 1b of the active region 1 and is p + -type outer peripheral contact region 56 (p + -type outer peripheral contact region 56 may cover the outer peripheral portion of the p-type outer peripheral region 55 when not provided). When the insulating layer 12 has a laminated structure formed by a plurality of insulating films (for example, a field oxide film 34, a gate insulating film 50, and an interlayer insulating film 52), only some insulating films (for example, the gate insulating film 50 and the interlayer insulating film 52) constituting the insulating layer 12 may extend to the outer peripheral portion 1b of the active region 1.

[0056] The insulating layer 13 is the remainder of the insulating layer (for example, the gate insulating film 50 and the interlayer insulating film 52: refer to FIG. 7 described later) formed on the front surface of the semiconductor wafer 60 in the scribe line 62 of the semiconductor wafer 60 during the fabrication (manufacture) of the semiconductor device 10. The thickness t2 of the insulating layer 13 is thinner than the thickness t1 of the insulating layer 12, and is appropriately set so that the magnitude of the stress imbalance between the front surface side and the back surface side of the semiconductor wafer 60 after the process of step S11 (refer to FIG. 4) described later during the fabrication of the semiconductor device 10 becomes small. Specifically, the thickness t2 of the insulating layer 13 is preferably, for example, about 1 / 2 or less of the thickness t1 of the insulating layer 12. More specifically, the thickness t2 of the insulating layer 13 is preferably, for example, about 8000 Å or less. Also, the thickness t2 of the insulating layer 13 is as thin as possible within a range where the front surface of the semiconductor substrate 11 is not exposed (that is, 0 Å < t2), and is preferably, for example, about 50 Å or more.

[0057] The difference in thickness between the insulating layer 12 and the insulating layer 13 should be as large as possible without degrading, for example, the coverage of the etching mask used when patterning the surface electrode 54 or the coverage of the surface protective film which is the uppermost layer on the front surface of the semiconductor substrate 11. The insulating layer 12 may be a laminated structure composed of all the insulating films laminated on the front surface of the semiconductor substrate 11 in the edge termination region 2, and the insulating layer 13 may be a laminated structure (see Figure 2) or a single-layer structure composed of some of the insulating films laminated on the front surface of the semiconductor substrate 11 in the edge termination region 2. In this case, the thicknesses t1 and t2 of the insulating layers 12 and 13 can be easily set by the number of insulating films laminated. Specifically, for example, the insulating layer 12 may be a laminated structure in which the field oxide film 34, gate insulating film 50, and interlayer insulating film 52 are laminated in this order (Figure 2). The field oxide film 34 is provided in the entire area between the front surface of the semiconductor substrate 11 and the gate insulating film 50, inside the scribe region 3 in the edge termination region 2, but not in the scribe region 3.

[0058] The gate insulating film 50 and the interlayer insulating film 52 are stacked in this order on the field oxide film 34. The gate insulating film 50 and the interlayer insulating film 52 extend outward along the surface of the field oxide film 34 to the chip edge, covering the entire surface of the front of the semiconductor substrate 11 in the scribe region 3. The gate insulating film 50 and the interlayer insulating film 52 covering the front of the semiconductor substrate 11 in the scribe region 3 constitute the insulating layer 13. The thickness t1 of the insulating layer 12 is, for example, about 15,000 Å. The thickness of the field oxide film 34 is thicker than the thickness of the gate insulating film 50 and the interlayer insulating film 52, and since the insulating layer 13 does not include the field oxide film 34, the thickness t2 of the insulating layer 13 is, for example, about 8,000 Å or less. In this way, by removing the portion of one of the insulating films (in this case, the field oxide film 34) on the scribe region 3 of the multiple insulating films stacked on the front of the semiconductor substrate 11 in the edge termination region 2, the thickness t2 of the insulating layer 13 can be made thinner than the thickness t1 of the insulating layer 12.

[0059] The thickness t2 of the insulating layer 13 may be partially thicker due to, for example, a step between the upper surface of the field oxide film 34 and the front surface of the semiconductor substrate 11 (see Figure 2), but it is preferable that it be approximately constant throughout the entire scribe region 3 (see Figure 3). By making the thickness t2 of the insulating layer 13 approximately constant, the stress applied to the front surface side of the semiconductor wafer 60 by the insulating layer 13 can be reduced compared to the case where the thickness t2 of the insulating layer 13 is partially thickened. The insulating layers 12 and 13 may also be a single-layer structure of one insulating film with a relatively thinner thickness t2 in the scribe region 3 (see Figure 3). For example, the thickness t2 of the insulating layer 13 may be adjusted by adding a process to etch only the insulating layer 13, making the thickness t2 of the insulating layer 13 approximately constant or further thinning the thickness t2 of the insulating layer 13. + The front electrode 57, which is provided on the entire surface of the back surface of the mold starting substrate 21, is a drain electrode, and n + Type drain region 41(n + It is electrically connected to the starting substrate 21).

[0060] A method for manufacturing a semiconductor device 10 according to an embodiment will be described. Figure 4 is a flowchart showing an overview of the method for manufacturing a semiconductor device according to an embodiment. Figure 5 is a cross-sectional view showing the layout of the semiconductor device during manufacturing, as seen from the front side of the semiconductor wafer. Figures 6 and 7 are cross-sectional views showing the cross-sectional structure along the cutting line B1-B2 in Figure 5. Figures 6 and 7 illustrate a chip region 61 and a scribe line 62 adjacent to the chip region 61, using the cross-sectional structure of the edge termination region 2 in Figure 2 as an example. The chip region 61 is a region that is cut from the semiconductor wafer 60 along the scribe line 62 by a dicing blade or the like to become a semiconductor chip (semiconductor substrate 11). The width w1 of the scribe line 62 on the semiconductor wafer 60 is, for example, about 200 μm.

[0061] First, as shown in Figures 5 and 6, n + n becomes the type drain region 41 + On the front surface of the mold starting wafer 63, n - n is in the drift region 42.- A semiconductor wafer 60 is fabricated by epitaxially growing an epitaxial layer 22 of a certain type. Next, by photolithography and ion implantation, diffusion regions of impurities of a predetermined conductivity type with the same structure are selectively formed on the front surface (the surface on the epitaxial layer 22 side) of the semiconductor wafer 60 in each chip region 61 (Step S1: First step). In the process of Step S1, for example, a p-type base region 45, an n + -type source region 46, base contact regions 47, 48, an n-type current diffusion region 43, a p + -type region 44, a p-type outer peripheral region 55, a p + -type outer peripheral contact region 56, a breakdown voltage structure 30 (a p-type region 31, a p + -type region 32) and a channel stopper region 33 are formed.

[0062] Next, the impurities ion-implanted into the semiconductor wafer 60 are electrically activated by heat treatment (activation annealing) (Step S2). Here, a case where activation annealing is performed once collectively after all the ion implantation processes is described as an example, but activation annealing may be performed individually each time an ion implantation process is performed. Also, the formation order of the plurality of diffusion regions formed in the process of Step S1 can be set as appropriate. Next, a trench (gate trench) 49 is formed by photolithography and etching (Step S3). Next, for example, by chemical vapor deposition (CVD: Chemical Vapor Deposition) method under normal pressure or reduced pressure, a field oxide film 34 is deposited (formed) on the entire front surface of the semiconductor wafer 60 (Step S4: Second step).

[0063] Next, an etching mask 71 is formed on the field oxide film 34. The etching mask 71 has an opening 71a that exposes the portion of each chip region 61 corresponding to the active region 1, and an opening 71b that exposes the portion corresponding to the scribe line 62. Next, the field oxide film 34 is selectively removed by etching using the etching mask 71 as a mask, leaving the field oxide film 34 only on the outer periphery of each chip region 61 excluding the active region 1 (Step S5: Second step). The field oxide film 34 may extend towards the center of each chip region 61 so as to cover the outer periphery 1b of the active region 1 in each chip region 61. In this case, the front surface of the semiconductor wafer 60 is exposed at the central portion 1a of the active region 1 in each chip region 61 and at the scribe line 62. Then, the etching mask 71 is removed.

[0064] Next, as shown in Figure 7, a gate insulating film 50 is formed along the inner wall of the trench 49 by, for example, CVD under normal pressure or reduced pressure, high-temperature oxidation (HTO), or thermal oxidation (Step S6: Second step). At this time, the gate insulating film 50 is also formed on the exposed surface of the front surface of the semiconductor wafer 60 and on the surface of the field oxide film 34. Next, a polysilicon layer (doped polysilicon layer) with impurities such as phosphorus (P) and boron (B) is deposited (formed) on the gate insulating film 50 so as to be embedded inside the trench 49, for example by CVD. Then, the polysilicon layer is partially removed by photolithography and etching, leaving only the portion that will become the gate electrode 51 inside the trench 49, thereby forming the gate electrode 51 on the gate insulating film 50 inside the trench 49 (Step S7).

[0065] Next, an interlayer insulating film 52 is deposited (formed) over the entire surface of the front surface of the semiconductor wafer 60 so as to cover the gate electrode 51, for example, by a CVD method under normal pressure or reduced pressure (Step S8: Second step). Next, contact holes 52a and 52b that penetrate the interlayer insulating film 52 and the gate insulating film 50 in the depth direction are formed by photolithography and etching (Step S9). Next, the interlayer insulating film 52 is planarized by heat treatment (reflow) (Step S10). The insulating layer 12 is formed by the field oxide film 34, gate insulating film 50 and interlayer insulating film 52 formed in the parts of each chip region 61 of the semiconductor wafer 60 excluding the active region 1. The gate insulating film 50 and interlayer insulating film 52 formed on the scribe lines 62 of the semiconductor wafer 60 form an insulating layer 13 that is thinner than the insulating layer 12 in thickness t1, with a thickness t2.

[0066] The thicknesses t1 and t2 of the insulating layers 12 and 13 are determined in advance, for example, by experimentation or simulation, so as to minimize the stress imbalance between the front and back sides of the semiconductor wafer 60 after the processing in step S11 described later. The thicknesses of the interlayer insulating film 52 and the field oxide film 34 may be set according to the thicknesses t1 and t2 of the insulating layers 12 and 13. The thickness t2 of the insulating layer 13 may be adjusted by adding a step to etch only the insulating layer 13 at any timing between the processing in step S6 and the processing in step S11, thereby making the thickness t2 of the insulating layer 13 approximately constant or further thinning it. The etching of the field oxide film 34, gate insulating film 50 and interlayer insulating film 52 (processing in steps S5 and S9, or additional steps to adjust the thickness t1 of the insulating layer 13) may be dry etching or wet etching.

[0067] Next, a barrier metal 53 and a surface electrode 54, which will serve as the source electrode, are deposited (formed) in this order on the front surface of the semiconductor wafer 60 by sputtering or vapor deposition, and the source electrode is patterned by photolithography and etching and left in the active region 1 of each chip region 61. The back surface (n+ A surface electrode 57, which will serve as a drain electrode, is formed on the entire surface of the back surface of the mold starting wafer 63 (step S11). For example, n + n + Using the mold starting wafer 63, after the processing in step S10 and before the processing in step S11, the semiconductor wafer 60 is ground from the back side (backside grinding), n + The mold starting wafer 63 may be thinned to a predetermined thickness, thereby reducing the semiconductor wafer 60 to the product thickness required for use as a semiconductor device 10.

[0068] During the process in step S11, the thickness t2 of the insulating layer 13 on the front surface of the semiconductor wafer 60 is thinner than the thickness t1 of the insulating layer 12 in at least a portion of the insulating layer 13, thereby reducing the stress on the front side of the semiconductor wafer 60 due to the insulating layers 12 and 13. This reduces the magnitude of the stress imbalance between the front and back sides of the semiconductor wafer 60 after the process in step S11 (i.e., deposition of surface electrodes 54 and 57, and patterning of surface electrode 54). Therefore, even if the semiconductor wafer 60 warps with a convex protrusion in either the front or back direction after the process in step S11, the amount of warping of the semiconductor wafer 60 can be reduced compared to when manufacturing the semiconductor device 110 of the reference example (see Figure 8).

[0069] Specifically, as described above, in the fabrication of the semiconductor device 110 of the reference example, the amount of warpage of the semiconductor wafer after the formation of surface electrodes (deposition of surface electrodes on both main surfaces of the semiconductor wafer and patterning of the surface electrodes 131) was approximately 150 μm. In contrast, experiments by the inventors have confirmed that by applying the manufacturing method of the semiconductor device 10 according to this embodiment, the amount of warpage of the semiconductor wafer 60 after processing in step S11 becomes 100 μm or less (for example, approximately 60 μm). Furthermore, experiments by the inventors have confirmed that by applying the manufacturing method of the semiconductor device 10 according to this embodiment, the range in which the amount of warpage is maximum within the surface of the semiconductor wafer 60 after processing in step S11 can be reduced compared to the case in which the semiconductor device 110 of the reference example (see Figure 8) is fabricated.

[0070] Next, a surface protective film (passivation film: not shown) made of an organic insulator such as polyimide is formed as the uppermost layer on the front surface of the semiconductor wafer 60. The surface protective film is formed over the entire front surface of the semiconductor wafer 60, covering the surface electrodes 54, gate pads, and interlayer insulating films 52 (insulating layers 12, 13). Next, by photolithography and etching, openings are formed in the surface protective film that expose each electrode pad (the source pad portion of the surface electrode 54, the gate pad, etc., not shown), and openings that expose the scribe lines 62. The surface protective film and its openings may be formed at any time between the formation of the surface electrodes 54 and the processing in step S12, which will be described later. As a result, the uppermost layer on the front surface of the semiconductor wafer 60 in the scribe lines 62 becomes the insulating layer 13.

[0071] Next, protective tape is applied to the back surface (the surface of the surface electrode 57) and the outer periphery of the semiconductor wafer 60, respectively, to cover the entire back surface and edges of the semiconductor wafer 60 with protective tape. Next, a plating film (not shown) is formed on the surface of the surface electrode 54 by, for example, electrolytic plating or electroless plating (step S12). As a result of the process in step S12, a plating film is formed on the metal (electrode pad) surface exposed at the opening of the surface protective film. The plating film is made by stacking, for example, a nickel (Ni) plating film and a gold (Au) plating film in that order. After that, the semiconductor wafer 60 is diced along the scribe line 62 using a dicing blade or the like, to separate each chip region 61 of the semiconductor wafer 60 into individual semiconductor chips (semiconductor substrate 11) (step S13: third step).

[0072] For example, on a semiconductor wafer 60, multiple chip regions 61 are arranged in a matrix, and scribe lines 62 are formed in a grid pattern surrounding all of the chip regions 61 (see Figure 5). As a result, the remaining portion of the scribe lines 62 of the semiconductor wafer 60 remains as a scribe region 3 around the entire circumference of the semiconductor substrate 11, which is formed by separating each chip region 61 of the semiconductor wafer 60. In the scribe region 3, an insulating layer 13 remains on the front surface of the semiconductor substrate 11 with a thickness t2 that is thinner than the thickness t1 of the insulating layer 12. Because the front surface (semiconductor surface) of the semiconductor wafer 60 in the scribe lines 62 is covered by the insulating layer 13, contamination of the front surface of the semiconductor substrate 11 in the scribe region 3 by processing debris or plating film adhesion does not occur. This completes the semiconductor device 10 shown in Figures 1-3.

[0073] As described above, according to the embodiment, the thickness of the insulating layer covering the front surface of the semiconductor wafer in the scribe line is made thinner than the thickness of the insulating layer covering the front surface of the semiconductor wafer at the outer periphery of each chip region of the semiconductor wafer. Because the insulating layer on the front surface of the semiconductor wafer reduces the stress on the front side of the semiconductor wafer, the magnitude of the stress imbalance between the front and back sides of the semiconductor wafer after the formation of the surface electrodes can be reduced. As a result, even if warping occurs in the semiconductor wafer after the formation of the surface electrodes, causing it to curve and protrude in either the front or back direction, the amount of warping is small, and the warping of the semiconductor wafer is reduced, bringing it closer to a substantially flat state, or the warping of the semiconductor wafer is mitigated, allowing the semiconductor wafer to be in a substantially flat state.

[0074] By reducing or mitigating the warping of semiconductor wafers, problems caused by the warping of semiconductor wafers in subsequent manufacturing processes (such as poor transport of semiconductor wafers, poor chucking (adsorption) of semiconductor wafers to the stage of semiconductor manufacturing equipment, reduced alignment accuracy, and increased variation in the thickness of deposited films) can be suppressed. As a result, even if a semiconductor wafer warps, the manufacturing process can be continued without discarding the wafer, thereby improving the yield of the product (semiconductor device). Furthermore, according to this embodiment, since it is only necessary to appropriately set the thickness of the insulating layer on the top surface of the semiconductor wafer in the scribe line, the warping of the semiconductor wafer can be reduced or mitigated while maintaining the chip area (surface area of ​​the chip region). In addition, by maintaining the chip area, the number of semiconductor chips per semiconductor wafer is maintained.

[0075] Furthermore, for example, if an existing semiconductor device (e.g., the semiconductor device in the reference example: see Figure 8) has an insulating layer formed by stacking multiple insulating films on the front surface of a semiconductor substrate in the edge termination region, when selectively etching one of the insulating films (e.g., a field oxide film) constituting the insulating layer in the manufacturing method of the existing semiconductor device to remove the portion corresponding to the active region of the chip region of the semiconductor wafer, the portion on the scribe line of the insulating film can also be removed at the same time, thereby making the scribe region of the existing semiconductor device the same structure as the scribe region of the semiconductor device according to the embodiment. Therefore, according to the embodiment, the semiconductor device according to the embodiment can be manufactured by applying the existing manufacturing method of the semiconductor device and without increasing the number of steps, simply by changing the pattern of the etching mask for the insulating film.

[0076] In the foregoing, this disclosure is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit of this disclosure. For example, in the embodiments described above, a semiconductor device having surface electrodes on both main surfaces of a semiconductor substrate is described as an example, but this disclosure may also be applied to a semiconductor device having surface electrodes only on the front surface of the semiconductor substrate. Also, in the embodiments described above, a structure in which three insulating films (field oxide film, gate insulating film, and interlayer insulating film) are stacked on the front surface of the semiconductor substrate in the edge termination region is used, but the number of stacked insulating films can be set as appropriate and may be increased or decreased. The material of the semiconductor substrate may also be Si. [Industrial applicability]

[0077] As described above, the semiconductor device and method for manufacturing a semiconductor device according to this disclosure are useful for semiconductor devices fabricated (manufactured) on thin semiconductor substrates (semiconductor chips) that are prone to warping due to stress from deposited films (electrode layers and insulating layers) on the main surface of the semiconductor substrate, and are particularly suitable for semiconductor devices using SiC as the semiconductor material. [Explanation of Symbols]

[0078] 1,101 active area 1a Central part of the active region 1b Outer peripheral part of the active region 2,102 Edge termination region 3,103 Scribe region 10,110 Semiconductor device 11,111 Semiconductor substrate 12,13,112 Insulating layer 21 n + -type starting substrate 22 Epitaxial layer 30 Breakdown voltage structure 31 p-type region 32,44 p + -type region 33 Channel stopper region 34,121 Field oxide film 41 n + -type drain region 42 n - -type drift region 43 n-type current diffusion region 45 p-type base region 46 n + -type source region 47,48 Base contact region 49 Trench 50,122 Gate insulating film 51 Gate electrode 52,123 Interlayer insulating film 52a,52b,112a Contact hole<00​​​​​​​​​​​​​​​​​​​​​​​​​​

Claims

1. Semiconductor substrate, The active region through which the main current flows, The active region comprises a terminal region surrounding the active region, In the aforementioned terminal region, The scribe lines remaining on the outer circumference of the semiconductor substrate, A channel stopper region is provided on the first main surface side of the semiconductor substrate, inside the scribe line, A first insulating layer is provided on the first main surface of the semiconductor substrate inside the scribe line and covering the channel stopper region, The scribe line comprises a second insulating layer provided on the first main surface of the semiconductor substrate, A semiconductor device characterized in that the thickness of the second insulating layer is thinner than the thickness of the first insulating layer.

2. The semiconductor device according to claim 1, characterized in that the thickness of the second insulating layer is 1 / 2 or less of the thickness of the first insulating layer.

3. The semiconductor device according to claim 1, characterized in that the thickness of the second insulating layer is 8000 Å or less.

4. The semiconductor device according to claim 1, characterized in that the outer peripheral end of the channel stopper region is located at the inner peripheral end of the scribe line.

5. In the terminal region, the semiconductor substrate is provided with a pressure-resistant structure located on the first main surface side, separated from the channel stopper region and located inward from the channel stopper region. The semiconductor device according to claim 1, characterized in that the first insulating layer covers the withstand voltage structure and the channel stopper region.

6. A method for manufacturing a semiconductor device comprising a semiconductor substrate, an active region through which a main current flows, and a termination region surrounding the active region, A first step is to form a channel stopper region on the first main surface side of the semiconductor wafer in a region corresponding to the terminal region of the chip region of the semiconductor wafer, A second step of forming an insulating layer on the first main surface of the semiconductor wafer, A third step involves cutting the semiconductor wafer along the scribe line surrounding the chip region, thereby separating the chip region from the semiconductor wafer into individual pieces on the semiconductor substrate. Includes, In the second step described above, The insulating layer is formed having a first insulating layer covering the channel stopper region and a second insulating layer covering the scribe line. A method for manufacturing a semiconductor device, characterized in that the thickness of the second insulating layer is thinner than the thickness of the first insulating layer.

7. The method for manufacturing a semiconductor device according to claim 6, characterized in that, in the second step, a plurality of insulating films are laminated on the first main surface of the semiconductor wafer, and a first insulating layer formed by laminating all of the insulating films and a second insulating layer formed by laminating some of the plurality of insulating films are formed.

Images