Manufacturing technology for split-cell 3D-NAND memory devices

Abstract

This provides an exemplary method for manufacturing 3D-NAND memory devices. [Solution] Techniques for manufacturing memory devices such as 3D-NAND memory devices may include dividing a gate plane (e.g., a plane containing word lines) into strips, thereby dividing memory cells and increasing the density of memory cells in each memory device. The techniques described herein are applicable to various types of 3D-NAND or other memory devices.

Description

Technical Field

[0001] This application claims the priority of U.S. Patent Application No. 17 / 362,557, filed on June 29, 2021, which is a non-provisional application of U.S. Provisional Patent Application No. 63 / 048,342, filed on July 6, 2020, and claims its priority based on 35 USC§119(e), which is hereby incorporated by reference in its entirety as if fully set forth herein.

Background Art

[0002] NAND flash memory is a type of non-volatile storage technology. NAND flash memory provides a large storage capacity with fast access time and low power consumption in a rugged package, and is common in many modern electronic devices such as semiconductor hard drives, smartphones, flash drives, memory cards, and computers. Conventional NAND flash has a planar memory cell structure and is sometimes called planar NAND. 3D (three-dimensional) NAND flash memory uses a charge trapping or floating gate flash architecture and includes memory cells stacked vertically, and is sometimes also called vertical NAND flash (VNAND). The vertical layers enable a higher area density without requiring a larger footprint.

[0003] Generally, the density of memory cells is limited by the number of layers in the stack of a 3D-NAND memory device and the area of the layers in the stack. Therefore, increasing the density of memory cells per layer can increase the number of memory cells per 3D-NAND memory device. In addition, the density can be increased by storing multiple bits of data in each cell by changing the amount of charge stored in each cell.

Summary of the Invention

[0004] The following is a detailed explanation with reference to the attached drawings. In the drawings, the leftmost digit(s) of the reference number identifies the drawing in which the reference number first appears. The use of the same reference number in different drawings indicates similar or identical elements. The systems shown in the attached drawings are not to scale, and components within the drawings may not be depicted to scale relative to each other. [Brief explanation of the drawing]

[0005] [Figure 1] This is a perspective view of an example of a 3D-NAND memory device. [Figure 2A] Figure 1 schematically shows an example of a manufacturing method for 3D-NAND memory devices, such as the 3D-NAND memory device shown. [Figure 2B] Figure 1 schematically shows an example of a manufacturing method for 3D-NAND memory devices, such as the 3D-NAND memory device shown. [Figure 2C] Figure 1 schematically shows an example of a manufacturing method for 3D-NAND memory devices, such as the 3D-NAND memory device shown. [Figure 2D] Figure 1 schematically shows an example of a manufacturing method for 3D-NAND memory devices, such as the 3D-NAND memory device shown. [Figure 2E] Figure 1 schematically shows an example of a manufacturing method for 3D-NAND memory devices, such as the 3D-NAND memory device shown. [Figure 2F] Figure 1 schematically shows an example of a manufacturing method for 3D-NAND memory devices, such as the 3D-NAND memory device shown. [Figure 2G] Figure 1 schematically shows an example of a manufacturing method for 3D-NAND memory devices, such as the 3D-NAND memory device shown. [Figure 2H] Figure 1 schematically shows an example of a manufacturing method for 3D-NAND memory devices, such as the 3D-NAND memory device shown. [Figure 2I] Figure 1 schematically shows an example of a manufacturing method for 3D-NAND memory devices, such as the 3D-NAND memory device shown. [Figure 2J]Figure 1 schematically shows an example of a manufacturing method for 3D-NAND memory devices, such as the 3D-NAND memory device shown. [Figure 2K] Figure 1 schematically shows an example of a manufacturing method for 3D-NAND memory devices, such as the 3D-NAND memory device shown. [Figure 2L] Figure 1 schematically shows an example of a manufacturing method for 3D-NAND memory devices, such as the 3D-NAND memory device shown. [Figure 2M] Figure 1 schematically shows an example of a manufacturing method for 3D-NAND memory devices, such as the 3D-NAND memory device shown. [Figure 2N] Figure 1 schematically shows an example of a manufacturing method for 3D-NAND memory devices, such as the 3D-NAND memory device shown. [Figure 2O] Figure 1 schematically shows an example of a manufacturing method for 3D-NAND memory devices, such as the 3D-NAND memory device shown. [Figure 2P] Figure 1 schematically shows an example of a manufacturing method for 3D-NAND memory devices, such as the 3D-NAND memory device shown. [Figure 2Q] Figure 1 schematically shows an example of a manufacturing method for 3D-NAND memory devices, such as the 3D-NAND memory device shown. [Figure 3A] Figure 1 schematically illustrates another example of a manufacturing method for 3D-NAND memory devices, such as the 3D-NAND memory device shown. [Figure 3B] Figure 1 schematically illustrates another example of a manufacturing method for 3D-NAND memory devices, such as the 3D-NAND memory device shown. [Figure 3C] Figure 1 schematically illustrates another example of a manufacturing method for 3D-NAND memory devices, such as the 3D-NAND memory device shown. [Figure 3D] Figure 1 schematically illustrates another example of a manufacturing method for 3D-NAND memory devices, such as the 3D-NAND memory device shown. [Figure 3E] Figure 1 schematically illustrates another example of a manufacturing method for 3D-NAND memory devices, such as the 3D-NAND memory device shown. [Figure 3F]Another example of a method for manufacturing a 3D-NAND memory device, such as the 3D-NAND memory device of FIG. 1, is schematically shown. [Figure 3G] Another example of a method for manufacturing a 3D-NAND memory device, such as the 3D-NAND memory device of FIG. 1, is schematically shown. [Figure 3H] Another example of a method for manufacturing a 3D-NAND memory device, such as the 3D-NAND memory device of FIG. 1, is schematically shown. [Figure 3I] Another example of a method for manufacturing a 3D-NAND memory device, such as the 3D-NAND memory device of FIG. 1, is schematically shown. [Figure 3J] Another example of a method for manufacturing a 3D-NAND memory device, such as the 3D-NAND memory device of FIG. 1, is schematically shown. [Figure 4A] A further example of a method for manufacturing a 3D-NAND memory device, such as the 3D-NAND memory device of FIG. 1, is schematically shown. [Figure 4B] A further example of a method for manufacturing a 3D-NAND memory device, such as the 3D-NAND memory device of FIG. 1, is schematically shown. [Figure 4C] A further example of a method for manufacturing a 3D-NAND memory device, such as the 3D-NAND memory device of FIG. 1, is schematically shown. [Figure 4D] A further example of a method for manufacturing a 3D-NAND memory device, such as the 3D-NAND memory device of FIG. 1, is schematically shown. [Figure 4E] A further example of a method for manufacturing a 3D-NAND memory device, such as the 3D-NAND memory device of FIG. 1, is schematically shown. [Figure 4F] A further example of a method for manufacturing a 3D-NAND memory device, such as the 3D-NAND memory device of FIG. 1, is schematically shown. [Figure 4G] A further example of a method for manufacturing a 3D-NAND memory device, such as the 3D-NAND memory device of FIG. 1, is schematically shown. [Figure 4H] A further example of a method for manufacturing a 3D-NAND memory device, such as the 3D-NAND memory device of FIG. 1, is schematically shown. [Figure 4I] A further example of a method for manufacturing a 3D-NAND memory device, such as the 3D-NAND memory device of FIG. 1, is schematically shown. [Figure 4J] A further example of a method for manufacturing a 3D-NAND memory device, such as the 3D-NAND memory device of FIG. 1, is schematically shown. [Figure 4K] A further example of a method for manufacturing a 3D-NAND memory device, such as the 3D-NAND memory device of FIG. 1, is schematically shown. [Figure 4L] A further example of a method for manufacturing a 3D-NAND memory device, such as the 3D-NAND memory device of FIG. 1, is schematically shown. [Figure 4M] A further example of a method for manufacturing a 3D-NAND memory device, such as the 3D-NAND memory device of FIG. 1, is schematically shown. [Figure 4N] A further example of a method for manufacturing a 3D-NAND memory device, such as the 3D-NAND memory device of FIG. 1, is schematically shown. [Figure 4O] A further example of a method for manufacturing a 3D-NAND memory device, such as the 3D-NAND memory device of FIG. 1, is schematically shown. [Figure 4P] A further example of a method for manufacturing a 3D-NAND memory device, such as the 3D-NAND memory device of FIG. 1, is schematically shown. [Figure 4Q] A further example of a method for manufacturing a 3D-NAND memory device, such as the 3D-NAND memory device of FIG. 1, is schematically shown. [Figure 4R] A further example of a method for manufacturing a 3D-NAND memory device, such as the 3D-NAND memory device of FIG. 1, is schematically shown. [Figure 4S] A further example of a method for manufacturing a 3D-NAND memory device, such as the 3D-NAND memory device of FIG. 1, is schematically shown. [Figure 4T] A further example of a method for manufacturing a 3D-NAND memory device, such as the 3D-NAND memory device of FIG. 1, is schematically shown. [Figure 4U]Further examples of manufacturing methods for 3D-NAND memory devices, such as the 3D-NAND memory device shown in Figure 1, are schematically illustrated. [Figure 4V] Further examples of manufacturing methods for 3D-NAND memory devices, such as the 3D-NAND memory device shown in Figure 1, are schematically illustrated. [Figure 4W] Further examples of manufacturing methods for 3D-NAND memory devices, such as the 3D-NAND memory device shown in Figure 1, are schematically illustrated. [Figure 5] A schematic diagram of the vertical channel of a 3D-NAND memory device, which has multiple memory cells in holes of the vertical channel along the gate plane, is shown. [Figure 6] Figure 1 is a flowchart illustrating an example of a manufacturing method for 3D-NAND memory devices, such as the 3D-NAND memory device shown. [Modes for carrying out the invention]

[0006] Overview This disclosure describes exemplary methods for manufacturing 3D-NAND memory devices. These methods enable increasing the memory cell density within a 3D-NAND memory device (e.g., doubling it). In some examples, the increase in memory cell density is achieved at least partially by dividing the word plane (e.g., the plane containing the word lines) into long strips. The various methods described herein are applicable to various types of 3D-NAND memory devices.

[0007] In some examples, a method for manufacturing a 3D-NAND memory device may include forming pipe connections within a substrate, where conductive materials such as polysilicon can be used. Layers can be deposited on the substrate. A layer may comprise a first layer comprising alternating first insulating materials such as silicon oxide, oxynitride, or carbonitride, and a second layer comprising a second material such as polysilicon or a metal such as tungsten. In this example, the first layer functions as an insulating layer. In this example, the second layer functions as the word plane of the 3D-NAND memory device. Depending on the configuration, as further described herein, the second layer may initially include nitrides that are eventually replaced by metals. Alternating layers generally provide a stack. Depending on the configuration, the stack may contain 24 to 256 or more layers to form memory cells therein, but depending on the configuration, it may contain more or fewer layers. The stack may have a surrounding staircase region for electrically contacting word lines and select signal lines.

[0008] Once the stack is formed, multiple grooves can be etched within the stack. In some embodiments, the grooves can be etched through all the layers in the stack and extend completely through the step region. However, in other embodiments, some grooves can be etched through most of the layers, leaving some layers at the bottom of the stack unetched, and some grooves can extend partially through the step region. The grooves can be filled with a first material, such as an oxide. In other embodiments, the grooves can be filled with some other suitable dielectric material.

[0009] Once the grooves are filled with the first material, multiple vertical channel holes can be etched into the stack. In some examples, the memory layer and channel layer are deposited on the walls of the vertical holes, and then the first material, for example, an oxide, can be deposited to partially or completely fill the vertical channel holes and form a vertical NAND string of a 3D-NAND memory device.

[0010] In other embodiments, after the channel holes are filled, a second material, such as a nitride, can be removed from the stack. For example, the nitride can be etched from the stack.

[0011] Once the nitride is removed from the stack, a third material, such as a metal like tungsten, can be deposited in the space reserved by the nitride. The third material typically functions as the transistor gate, word line, and select signal line of a 3D-NAND memory device. This technique of removing the silicon nitride layer and replacing it with a conductive material (e.g., tungsten) is commonly known as the replacement gate technique. Prior to the tungsten replacement, one or more layers of other materials, such as aluminum oxide or titanium nitride, can be deposited for performance and process advantages. The third material, along with the memory layer and channel layer formed in the channel holes, forms a stack or string of memory cells in the 3D-NAND memory device. In embodiments, one or more cells or layers at the top and bottom of the 3D memory device can perform different functions from other cells or layers of the 3D memory device (i.e., intermediate cells or layers). For example, some cells or layers can be configured to function as string selectors, source selectors, or dummy cells. Dielectric-filled grooves divide the third material around the channel holes into separate strips. Therefore, the memory cell can be effectively partitioned so that one side of the channel engages with one strip of the third material and the other side of the channel engages with another strip of the third material in the word plane, thereby increasing the density of the memory stack (by a factor of 2 in this example).

[0012] In another embodiment, a vertical NAND string may have one vertical hole (circular, elongated, or other regular or irregular shape), and multiple memory cells may be formed for each hole in the same word plane. This can be done by creating physical separation between one or more of the memory layers and channel layers deposited within the hole.

[0013] After forming a vertical NAND string, contacts can be formed on the vertical NAND string, and bit wires, for example, containing copper wires, can be formed on the NAND string and electrically coupled to the NAND string via the contacts.

[0014] In some embodiments, the method further includes forming separation trenches in the stack. The separation trenches may extend parallel to the grooves. The separation trenches may be used to remove a second material, such as nitride, and backfill the stack with a third material, such as tungsten. In some embodiments, the separation trenches are wider than the grooves.

[0015] In some embodiments, the substrate comprises silicon or polysilicon, and diffusion within the substrate can function as a common source for vertical NAND strings. In other embodiments, a pipe connection can be formed within the substrate to electrically couple the lower ends of two adjacent vertical NAND strings.

[0016] In some embodiments, the grooves can be formed in a discontinuous manner with gaps between the groove segments in the longitudinal direction. In such embodiments, after the grooves are filled with a dielectric, for example, a first material, the isolation trenches can be etched into the stack. During the substitution metal gate process, the gaps provide a path for removing a second material, for example, a nitride, and depositing a third material.

[0017] Examples of methods for depositing a third material onto a stack include, for example, atomic layer deposition, chemical vapor deposition, physical vapor deposition, plasma-assisted atomic layer deposition, and / or plasma-enhanced chemical vapor deposition. Once the third material is deposited onto the stack, any material remaining in the separation trench can be removed, the separation trench can be etched through the stack at the location of the gap, and the trench can then be filled with the first material, such as an oxide.

[0018] In some embodiments, instead of forming isolation trenches in the stack, the second material can be removed from the stack through a plurality of holes etched through the stack, at least one of which is etched through each of the seamlessly connected dielectric packing grooves. Once the second material is removed, the third material can be deposited in the stack through holes that may be smaller or larger in diameter compared to channel holes.

[0019] Exemplary Embodiments The memory cells of a NAND flash memory device are arranged in a matrix of NAND strings. Each NAND string may include a source selection transistor connected to a source line (SL), a string selection transistor connected to a bit line (BL), and a plurality of memory cell transistors connected in series and electrically connected between the string selection transistor and the source selection transistor. A 3D-NAND flash memory device comprises vertically stacked memory cells arranged in vertical NAND strings.

[0020] Figure 1 is a perspective view of an exemplary 3D-NAND memory device 100. The 3D-NAND memory device 100 includes a substrate 102. The substrate may include, for example, an insulating material such as silicon oxide or silicon nitride, and / or a semiconductor material such as silicon or polysilicon. Alternating insulating layers 104, for example silicon oxide, and conductive material layers 106, as further described herein, such as polysilicon, doped polysilicon, silicon, or a metal such as tungsten, are deposited on the substrate 102 to form a stack 108. The conductive material layers 106 provide the memory transistor gate, selection transistor gate, word line, and selection signal line of the 3D-NAND memory device 100, and can therefore be referred to herein as gate planes. Isolation or isolation trenches 112 may be provided between the stacks 108. The space between two adjacent isolation trenches 112, as further described herein, can vary in different NAND string architectures.

[0021] As can be seen in Figure 1, individual memory cells 114 are stacked vertically within a vertical NAND string 116. Each individual memory cell 114 comprises a vertical channel and a gate material in a gate plane 106 that corresponds to the vertical channel in a gate-all-around architecture, or in a split-cell architecture as further described herein. Each memory cell 114 comprises a memory layer (not shown) which includes a charge storage layer, a blocking dielectric that isolates the charge storage layer from the gate region, and a tunnel dielectric that isolates the charge storage layer from the channel region. In one embodiment, the memory layer comprises a charge trapping layer (e.g., silicon nitride). In another embodiment, the memory layer comprises a floating gate.

[0022] A bit line 118, which may include a conductive material such as copper, is located at the top of the vertical NAND string 116 and is coupled to the NAND string through a bit line contact (not shown) which may include a conductive material such as copper or tungsten. In one embodiment (described with respect to Figures 2A-2Q), the NAND string 116 is U-shaped, with the lower ends of two adjacent vertical strings 116 electrically coupled via a pipe connector (not shown in the figure), the upper end of one vertical string 116 coupled to the bit line 118 via a bit line contact, and the upper end of the other vertical string 116 coupled to a source line via a source line contact, and the top transistors or groups of transistors of the two vertical strings 116 are used as string and source selection transistors, respectively. In other embodiments (described with reference to Figures 3A-3J), the NAND strings 116 have a linear shape, and the upper end of each vertical string 116 is coupled to the bit line 118 via a bit line contact comprising the most significant transistor or group of transistors used as a string selection transistor, and the lower end of each vertical string 116 is coupled to the source line via a source line contact comprising the least significant transistor or group of transistors used as a source selection transistor.

[0023] As can be seen in Figure 1, the stack 108 is formed with a stepped shape 124 for making electrical contact with the gate plane 106. Arrow 122 indicates the longitudinal direction of the dielectric packing grooves (not shown in Figure 1) and isolation trenches 112 in the 3D-NAND memory device 100, as will be further described herein. The dielectric packing isolation trenches 112 and dielectric packing grooves may extend along the length L of the 3D-NAND memory device 100.

[0024] Figures 2A-2Q schematically illustrate an example of a method for manufacturing one type of 3D-NAND memory device, for example, the 3D-NAND memory device 100 in Figure 1. Figure 2A is a cross-sectional view of a portion 200 of the 3D-NAND memory device viewed along line 2A-2A in Figure 2B. Figure 2B is a plan view of a portion 200 of the 3D-NAND memory device viewed along line 2B-2B in Figure 2A. Figures 2C, 2E, 2G, 2I, 2K, 2M, and 2P are plan views of a portion 200 of the 3D-NAND memory device viewed along line 2B-2B in Figure 2A at various stages of the manufacturing process. Figures 2D, 2F, 2H, 2J, 2L, 2N, 2O, and 2Q are cross-sectional views of a portion 200 of the 3D-NAND memory device viewed along line 2A-2A in Figure 2B at various stages of the manufacturing process. The portion 200 can represent at least a part of the stack 108 of the 3D-NAND memory device 100 in Figure 1.

[0025] As can be seen from Figure 2A, portion 200 includes a substrate 202, for example, substrate 102, which includes a pipe connection portion 204. In embodiments, the substrate 202 may include one or more layers of conductive and / or nonconductive layers of varying thicknesses. In embodiments, the substrate 202 may include an active layer comprising NMOS and PMOS transistors.

[0026] As illustrated with respect to Figure 1, portion 200 includes alternating layers 104 of insulating material, such as oxide, and layers 106 of conductive material, such as metal, such as tungsten. Other metals or conductive materials may be used as needed. Portion 200 also includes vertical strings 116a, 116b located above the pipe connection portion 204. The vertical strings 116a, 116b comprise vertically stacked transistors in which a portion of the conductive material layer 106 is used as the transistor gate, and as described above, the conductive material layer 106 may also be called the gate plane. The gate plane 106 is located around a channel hole 214 formed through the alternating stack 108 of layers 104, 106. A channel layer 218 is formed on the sidewall of the channel hole 214. A memory layer 216 is formed between the gate plane 106 and the channel layer 218. The memory layer 216 may comprise a charge storage layer separated from the gate plane by a blocking dielectric and separated from the channel layer by a tunnel dielectric (not shown). A portion of the gate plane 106 and corresponding portions of the memory layer and channel layer form memory cell transistors (for example, memory cell 114 in Figure 1 and 230a and 230b in Figure 2B). A portion of the gate plane 106 and corresponding portions of the channel layer, with or without a memory layer, form selection transistors. Vertically stacked memory cell transistors and selection transistors form vertical strings 116a and 116b.

[0027] The pipe connection section 204 electrically connects the lower ends of the vertical strings 116a and 116b, forming a U-shaped NAND string. In one embodiment, the pipe connection section 204 is an inversion region controlled by a gate plane 106 or a group of gate planes 106 around the lower ends of the vertical strings 116a and 116b. In another embodiment, the pipe connection section 204 is a conductive material such as doped polysilicon or metal, electrically insulated from the substrate 202. Contacts 120 are provided at the upper ends of the vertical strings 116a and 116b, connecting the upper ends of 116a and 116b to the bit line 118 and source line 234, respectively. A conductive material 240 embedded in channel holes 214 at the upper ends of the vertical strings 116a and 116b and electrically connected to the channel layer 218 provides landing pads for the contacts 120 of the bit line and source line. The top transistors or groups of transistors in vertical strings 116a and 116b are used as string and source selection transistors, respectively.

[0028] As shown in Figures 2A and 2B, dielectric-filled isolation trenches 226 and grooves 212 isolate the gate plane 106 into strips (e.g., 228, 228a, 228b) that provide not only transistor gates but also word lines and string / source selection signal lines. Channel holes 214 are formed through the dielectric-filled grooves 212. Channel layers 218 formed on the sidewalls of channel holes 214 have two portions controlled by separate gates in each layer of the gate plane 106. Thus, the circular memory cell 114 of the 3D-NAND memory device 100 in Figure 1 is divided into two separate memory cells having a substantially semicircular or curved shape. For example, as shown in Figure 2B, the memory cells on the left and right sides of line 232 are effectively separated, with one side 230a of the channel layer of channel hole 214a engaging with the gate material of one strip 228a to form a first memory cell, and the other side 230b of the channel layer of channel hole 214a engaging with another strip 228b to form a second memory cell.

[0029] Referring to Figures 2C and 2D, in the exemplary method shown in Figures 2A-2Q, alternating layers of insulating material, such as silicon oxide layer 206 (corresponding to layer 104) and sacrificial material layer 208 are deposited on the substrate 202. In embodiments, the sacrificial material may include silicon nitride, silicon oxynitride, silicon carbide, amorphous silicon, or polycrystalline silicon, which can be selectively removed in a later process to provide space for forming a metal layer corresponding to the gate plane 106 that forms the word line and selection signal line in portion 200. Layers 206 and 208 may be of the same thickness, or, in embodiments, of different thicknesses.

[0030] Referring to Figures 2E and 2F, when the stack of layers 206 and 208 is formed, multiple grooves 210 can be formed within the portion 200. In the example of Figures 2A-2Q, two grooves 210a and 210b are shown, but generally more grooves 210 are included. As can be seen from Figure 2F, in some embodiments, grooves 210a and 210b are etched through all of layers 206 and 208, partially exposing the pipe connection portion 204. In other embodiments, some grooves 210 are etched through all of layers 206 and 208, and other grooves 210 are etched through most of layers 206 and 208, leaving some layers 206 and 208 unetched at the bottom of the stack, so that after the sacrificial layers 208 are replaced by gate planes, e.g., gate plane 106, in a later process, some gate planes at the bottom of the stack can be used as control gates.

[0031] In an embodiment, the groove 210 extends in the same longitudinal direction as the dielectric packing isolation trench 226, as indicated by arrow 122 in Figure 1. In an embodiment, the groove 210 may also extend partially or entirely through the stepped region 124 in Figure 1 in the longitudinal direction. In one embodiment, the groove 210 may extend longitudinally through the entire stepped region 124 to separate the word lines and selection signal lines on both sides of the groove 210. In another embodiment, the groove 210 may extend longitudinally through the stepped region 124 in a partial manner, where the word lines on both sides of the groove 210 are separated by the groove 210, while the selection signal lines on both sides of the groove 210 remain coupled.

[0032] Referring to Figures 2G and 2H, grooves 210a and 210b can be filled with insulating dielectric material to form dielectric filling grooves 212. The insulating dielectric material can be the same material as layer 206.

[0033] Once grooves 210a and 210b are filled with insulating material to form the dielectric packing groove 212, the channel hole 214 can be etched through the lamination of layers 206 and 208 and the dielectric packing groove 212, as shown in Figures 2I and 2J, to partially expose the pipe connection portion 204. In the embodiment, the channel hole 214 can be wider than the width of the dielectric packing groove 212 in a direction perpendicular to the longitudinal direction, as illustrated in Figure 1, and the channel hole has substantially semicircular or curved portions on both sides of the dielectric packing groove 212.

[0034] Referring to Figures 2K and 2L, a memory layer 216 comprising one or more material layers can be deposited on the wall of a channel hole 214. In an embodiment, the memory layer 216 comprises a charge storage layer, a first dielectric between the channel hole sidewall and the charge storage layer, and a second dielectric on the charge storage layer. The first dielectric may include silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, and combinations thereof, and can be used as a blocking oxide or as part of a blocking oxide in a flash memory cell transistor. The second dielectric can be used as a tunnel dielectric in a flash memory cell transistor. In one embodiment, the charge storage layer comprises a charge trapping layer (e.g., silicon nitride). In another embodiment, the charge storage layer comprises a floating gate. The floating gate can be formed by first selectively recessing a sacrificial layer 208 into the channel hole 214, and then forming the floating gate in the recess, separated from layers 206 and 208 by the first dielectric or a portion of the first dielectric.

[0035] Once the memory layer 216 is deposited within the channel hole 214, the channel material 218 can be formed on top of the memory layer 216 within the channel hole 214. In embodiments, the channel material 218 can be a conformal layer, include amorphous, single-crystal, or polycrystalline semiconductor materials, and can be formed using a CVD process, an ALD process, an epitaxial growth process, or a combination thereof. In embodiments, heat treatment can be performed to convert amorphous semiconductor materials to polycrystalline or single-crystal materials, to convert polycrystalline semiconductor materials to single-crystal materials, or to change the grain size of polycrystalline semiconductor materials. In one embodiment, heat treatment can be performed using a metal-induced crystallization process to convert polycrystalline semiconductor materials to single-crystal materials. In one embodiment, the channel material 218 may include amorphous, single-crystal, or polycrystalline silicon or silicon-germanium materials. In embodiments, the channel material 218 can be a conformal layer having a thickness that partially fills the channel hole 214. An insulating material 220, such as silicon oxide, can fill the channel hole 214. In one embodiment, the insulating material 220 can be a conformal layer on the channel material 218 having a thickness that partially fills the channel hole 214, leaving a void in the center of the channel hole 214. Once the material layer 216, the channel material 218, and the insulating material 220 are formed in the channel hole 214, a recess can be formed at the upper end of the channel hole 214, and a conductive material landing pad 240, which serves as a bit wire and source wire contact landing pad, can be formed in the recess. The conductive material of the landing pad 240 may include doped polysilicon or metal.

[0036] In the embodiment, the channel material 218 and the landing pad 240 can be made of different materials. For example, in the embodiment, the channel material may include polysilicon, and the landing pad 240 may include polysilicon, a similar material, or a different material.

[0037] Referring to Figures 2M and 2N, trenches 222 are formed in a portion of 200, for example, by etching. In the exemplary method shown in Figures 2A-2Q, trenches 222 are formed on both sides of the dielectric packing groove 212. In some embodiments, as can be seen from Figure 2N, the trenches 222 are etched through all of layers 206, 208, partially exposing the substrate 202. In other embodiments, some trenches 222 are etched through all of layers 206, 208, while other trenches 222 are etched through most of layers 206, 208, leaving some unetched layers 206, 208 at the bottom of the stack, which can then be used as control gates after the sacrificial layers 208 are replaced by gate planes in a later process.

[0038] In some embodiments, the trench 222 extends longitudinally, as indicated by arrow 122 in Figure 1. In some embodiments, similar to the dielectric packing groove 212, the trench 222 may also extend longitudinally partially or entirely through the stepped region 124 in Figure 1. In one embodiment, the trench 222 may extend longitudinally through the entire stepped region 124 to separate the word lines and selection signal lines on both sides of the trench 222. In another embodiment, the trench 222 may extend longitudinally through the stepped region 124 in some cases, where the word lines on both sides of the separation trench 222 are separated by the trench 222, while the selection signal lines on both sides of the separation trench 222 remain coupled.

[0039] Referring to Figure 2O, the trench 222 exposes a sacrificial layer 208 from the trench sidewall. The sacrificial layer 208 can be selectively removed from the trench 222, for example, by a wet etching process, to form the gate region. Referring to Figures 2P and 2Q, in embodiments, a conformal oxide layer (e.g., silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, or a combination of such dielectrics) can be formed in the gate region using an ALD process. A metal gate can be deposited to form a metal layer (e.g., 224) corresponding to the gate plane 106 that forms the word line and the select signal line in portion 200. In one embodiment, the metal layer comprises a conformal TiN layer deposited on the conformal oxide layer using an ALD process, and a tungsten layer deposited using an ALD or CVD process to partially or completely fill the remaining gate region. Once the gate region is filled, anisotropic etching is performed to remove any material remaining in the trench 222. Returning to Figure 2A, the trench 222 can be filled with an insulating dielectric material to form a dielectric-filled isolation trench 226. In one embodiment, the insulating dielectric material includes the same material (e.g., silicon oxide) as layer 104 in Figure 2A and insulating material layer 206 in Figure 2D.

[0040] Returning to Figures 2A and 2B, the dielectric-filled isolation trench 226 isolates the gate plane 106 into strips (e.g., 228, 228a, 228b) that form the word lines and select signal lines of portion 200. As shown in Figure 1, the gate plane 106, together with the memory layer formed on the sidewalls of the channel holes and the corresponding portion of the channel layer, forms the memory cells 114 of the 3D-NAND memory device 100. The dielectric-filled groove 212 effectively divides the gate-all-around cell into two distinct cells having substantially semicircular or curved channels at each level of the gate plane 106 around the channel holes 214. This is achieved by dividing the gates of two transistors.

[0041] Figures 3A–3J schematically illustrate another example of a method for manufacturing a different type or structure of a 3D-NAND memory device, such as the 3D-NAND memory device 100 in Figure 1. Figure 3A is a cross-sectional view of a portion 300 of the 3D-NAND memory device viewed along line 3A–3A in Figure 3B. Figure 3B is a plan view of a portion 300 of the 3D-NAND memory device viewed along line 3B–3B in Figure 3A. Figures 3C, 3E, 3G, and 3I are cross-sectional views of a portion 300 of the 3D-NAND memory device viewed along line 3A–3A in Figure 3B at various stages of the manufacturing process. Figures 3D, 3F, 3H, and 3J are plan views of a portion 300 of the 3D-NAND memory device viewed along line 3B–3B in Figure 3A at various stages of the manufacturing process. A portion 300 can represent at least a portion of a stack 108 of the 3D-NAND memory device 100 in Figure 1.

[0042] As can be seen from Figure 3A, part 300 includes a substrate 302, for example, substrate 102. Substrate 302 may include one or more layers of conductive and / or nonconductive layers of varying thicknesses. Substrate 302 may also include an active layer comprising NMOS and PMOS transistors. As described with respect to Figure 1, part 300 includes alternating layers 104 of insulating material, for example, oxide, and layers 106 of conductive material. In the exemplary method of Figure 3, in 3A-3J, the conductive material includes silicon or polysilicon. Part 300 also includes a vertical NAND string 116. As described above, the vertical NAND string 116 comprises vertically stacked transistors in which a portion of the conductive material layer 106 is used as the gate of the transistor, and as described above, the conductive material layer 106 may also be called the gate plane. The gate plane 106 is located around a channel hole 314 formed through the alternating layers 104, 106. The memory layer 316 and the channel layer 318 are formed on the sidewalls of the channel hole 314. In this embodiment, the memory layer 316 includes a charge storage layer, a blocking dielectric that separates the charge storage layer from the gate plane, and a tunnel dielectric that separates the charge storage layer from the channel layer. A portion of the gate plane 106 and corresponding portions of the memory layer and channel layer form a memory cell transistor (for example, memory cell 114 in Figure 1 and 330a, 330b in Figure 3B). A portion of the gate plane 106 and corresponding portions of the channel layer, with or without the memory layer, form a selection transistor. The vertically stacked memory cell transistors and selection transistors form a vertical string 116.

[0043] Contact 120 is located at the upper end of the vertical NAND string 116. The bit line 118 is connected to contact 120. A conductive material 340 embedded in the channel hole 314 at the upper end of the vertical string 116 and electrically connected to the channel layer 318 provides a landing pad for the bit line contact 120. The topmost transistor or group of transistors of the vertical string 116 is used as a string selection transistor. The lower end of each vertical string 116 is coupled to the source line via a source line contact having the lowest transistor or group of transistors used as a source selection transistor.

[0044] Referring to Figures 3C and 3D, in the exemplary method shown in Figures 3A-3J, alternating oxide layers 304 (corresponding to layer 104) are deposited or laminated alternately with silicon or polysilicon layers 306 (corresponding to layer 106) on the substrate 302. Although not shown in Figure 3D, one or more conductive and nonconductive layers can be formed on the substrate 302 before the alternating deposition of layers 304 and 306.

[0045] Referring to Figures 3E and 3F, once the stack of layers 304, 306 is formed, multiple grooves 310 can be etched within the portion 300. In the example of Figures 3A-3J, seven grooves 310 are shown, but more or fewer grooves 310 can be included. The grooves 310 can extend longitudinally, as indicated by arrow 122 in Figure 1. In one embodiment, the grooves 310 may be etched through all of layers 304, 306 and may extend longitudinally through the entire step region 124 to separate the word lines and selection signal lines on both sides of the groove 310. In another embodiment, some grooves 310 may be etched through most of layers 304, 306, leaving some layers 304, 306 unetched at the bottom of the stack. Similarly, some grooves 310 may extend longitudinally through the step region 124, with portions of the layers 306 on both sides of the groove 310 remaining joined in the step region. Although only one groove 310 is shown in the longitudinal direction (length direction g), there may be one or more grooves 310, for example, two or three or more grooves 310, in the longitudinal direction.

[0046] In this embodiment, the groove 310 extends through all of layers 304 and 306 and has a length equal to the length of layers 304 and 308. Thus, as mentioned with respect to Figure 1, due to the stepped shape of the 3D-NAND memory device, the vertical depth and horizontal length of each groove 310 can vary. However, the groove 310 in the stepped region 124 of the 3D-memory device 100 in Figure 1 is inactive (or may contain dummy holes). In this embodiment, as described above, the arrow 122 in Figure 1 indicates the longitudinal direction of the groove 310 of the 3D-NAND memory device 100.

[0047] Referring to Figures 3G and 3H, the groove 310 can be filled with an insulating material, such as silicon oxide, to form a dielectric filling groove 312. In some other embodiments, the groove 310 does not extend through all of layers 304, 306.

[0048] Referring to Figures 3I and 3J, once the grooves 310 are filled, the channel holes 314 can be etched through the stack to partially expose the substrate 302. As can be seen from Figure 3J, the channel holes 314 are arranged in a staggered pattern, thereby enabling a higher density of memory cells when the 3D-NAND memory device is completed. In other embodiments, the channel holes 314 do not need to be staggered.

[0049] Referring to Figures 3A and 3B, the memory layer 316 and the channel layer 318 can be deposited on the walls of the channel hole 314. In embodiments, the channel layer 318 can be a conformal layer, contain amorphous, single-crystal, or polycrystalline semiconductor material, and be formed using a CVD process, an ALD process, an epitaxial growth process, or a combination thereof. In embodiments, heat treatment can be performed to convert amorphous semiconductor material to polycrystalline or single-crystal material, to convert polycrystalline semiconductor material to single-crystal material, or to change the grain size of polycrystalline semiconductor material. In one embodiment, heat treatment can be performed to convert polycrystalline semiconductor material to single-crystal material using a metal-induced crystallization process. In one embodiment, the channel material 318 may contain amorphous, single-crystal, or polycrystalline silicon or silicon-germanium material. In embodiments, the channel layer 318 may be a conformal layer and have a thickness that partially fills the channel hole 314. Subsequently, an insulating material 320, such as an oxide, can be deposited in the channel holes 314, completely or partially filling them and forming the NAND strings 116 of the 3D-NAND memory device 100 in Figure 1. Bit wires 118, for example, containing copper, can be formed on the NAND strings 116 and electrically coupled to the NAND strings via bit wire contacts 120. In embodiments, isolation trenches (not shown) can be formed between other parts 300 of the 3D-NAND memory device, such as a stack 108, and the isolation trenches can extend longitudinally as indicated by arrows 122 in Figure 1.

[0050] In the embodiments shown in Figures 3A-3J, the conductive material layer 306, for example, silicon or polysilicon, together with the memory layer 316 and channel layer 318 formed in the channel hole 314, forms the memory cells 114 of the 3D-NAND memory device 100 as shown in Figure 1. Referring to Figure 3B, the dielectric packing groove 312 divides the conductive material layer 306 into separate strips 328, 328a, and 328b, so the memory cells 114 are divided into substantially two separate parts on either side of the dielectric packing groove 312. For example, the memory cells around the channel hole 314a are effectively divided so that one side 330a of the channel hole 314a engages with the material of one strip 328a to form a first memory cell, and the other side 330b of the channel hole 314a engages with the other strip 328b to form a second memory cell. Therefore, the circular memory cell 114 of the 3D-NAND memory device 100 in Figure 1 is divided into two separate memory cells having substantially semicircular or curved channels along line 332.

[0051] Figures 4A–4Q schematically illustrate another example of a method for manufacturing a 3D-NAND memory device, such as the 3D-NAND memory device 100 in Figure 1. Figure 4A is a cross-sectional view of a portion 400 of the 3D-NAND memory device viewed along line 4A–4A in Figure 4B. Figure 4B is a plan view of a portion 400 of the 3D-NAND memory device viewed along line 4B–4B in Figure 4A. Figures 4C, 4E, 4G, 4I, 4K, 4M, and 4P are plan views of a portion 400 of the 3D-NAND memory device viewed along line 4B–4B in Figure 4A at various stages of the manufacturing process. Figures 4D, 4F, 4H, 4J, 4L, 4N, 4O, and 4Q are cross-sectional views of a portion 400 of the 3D-NAND memory device viewed along line 4A–4A in Figure 4B at various stages of the manufacturing process. The portion 400 can represent at least a part of the stack 108 of the 3D-NAND memory device 100 in Figure 1.

[0052] As can be seen from Figure 4A, part 400 includes a substrate 402, for example, substrate 102. Substrate 402 may include one or more layers of conductive and / or nonconductive layers of varying thicknesses. Substrate 402 may also include an active layer comprising NMOS transistors and PMOS transistors. Part 400 also includes a vertical NAND string 116.

[0053] As described above, the vertical NAND string 116 comprises vertically stacked transistors in which a portion of the conductive material layer 106 is used as the transistor gate, and as described above, the conductive material layer 106 is sometimes referred to as the gate plane. The gate plane 106 is located around a channel hole 414 formed through alternating layers 104, 106. The memory layer 416 and the channel layer 418 are formed on the sidewalls of the channel hole 414. In some embodiments, the memory layer 416 comprises a charge storage layer, a blocking dielectric that separates the charge storage layer from the gate plane, and a tunnel dielectric that separates the charge storage layer from the channel layer. A portion of the gate plane 106 and corresponding portions of the memory layer and channel layer form a memory cell transistor (e.g., memory cell 114 in Figure 1 and 430a, 430b in Figure 4B). A portion of the gate plane 106 and corresponding portions of the channel layer, with or without the memory layer, form a selection transistor. The vertically stacked memory cell transistors and selection transistors form the vertical string 116.

[0054] As described above, contact 120 is provided at the end of the vertical NAND string 116. Bit line 118 is connected to the vertical string 116 via contact 120. A conductive material 440 embedded in the channel hole 414 at the upper end of the vertical string 116 and electrically connected to the channel layer 318 provides a landing pad for the bit line contact 120. The uppermost transistor or group of transistors of the vertical string 116 can be used as a string selection transistor. The lower end of each vertical string 116 is coupled to the source line via a source line contact having the lowest transistor or group of transistors used as a source selection transistor.

[0055] Referring to Figures 4C and 4D, in the exemplary method shown in Figures 4A-4Q, alternating oxide layers 404 (corresponding to layer 104) are deposited or stacked alternately on a substrate 402 with a sacrificial material, such as a nitride layer 406 (corresponding to layer 106). In embodiments, the sacrificial material may include silicon nitride, silicon oxynitride, silicon carbide, amorphous silicon, or polycrystalline silicon, which can be selectively removed in a later process to provide space for forming a metallic layer corresponding to the gate plane 106 that forms the word line and selection signal line in portion 200. Referring to Figures 4E and 4F, once the stack of layers 404, 406 is formed, a number of grooves 410 can be etched into portion 400. In the example of Figures 4A-4Q, nine grooves are formed, but more or fewer grooves 410 can be included. As can be seen from Figure 4E, the grooves 410 are discontinuous, for example, the grooves 410 include gaps 408a. In the embodiments described with respect to Figures 2A-2Q and 3A-3J, the grooves 210 and 310 can be discontinuous. In the embodiments, the groove 410 can extend longitudinally as indicated by arrow 122 in Figure 1, if it is etched through all of the layers 404 and 406 and includes a gap 408a. The groove 410 can extend longitudinally, partially or entirely through the stepped region 124, as shown in Figure 1. In other embodiments, some grooves 410 can be etched through most of the layers 404 and 406, leaving some layers 404 and 406 unetched at the bottom of the stack. Referring to Figures 4G and 4H, the groove 410 can be filled with an insulating material, such as an oxide, to form a dielectric filling groove 412.

[0056] Referring to Figures 4I and 4J, once the groove 410 is filled, the channel holes can be etched through the stack to partially expose the substrate 402. As can be seen from Figure 4I, the channel holes 414 are arranged in a staggered pattern to provide a higher density NAND string arrangement.

[0057] Referring to Figures 4K and 4L, the memory layer 416 and the channel layer 418 can be deposited on the walls of the channel holes 414 in Figures 4I and 4J. As described above, the channel layer 418 can be a conformal layer, contain amorphous, single-crystal, or polycrystalline semiconductor material, and be formed using a CVD process, an ALD process, an epitaxial growth process, or a combination thereof. In embodiments, heat treatment can be performed to convert amorphous semiconductor material to polycrystalline or single-crystal material, to convert polycrystalline semiconductor material to single-crystal material, or to change the grain size of polycrystalline semiconductor material. In one embodiment, heat treatment can be performed to convert polycrystalline semiconductor material to single-crystal material using a metal-induced crystallization process. In one embodiment, the channel material 418 may contain amorphous, single-crystal, or polycrystalline silicon or silicon-germanium material. In embodiments, the channel layer 418 may be a conformal layer having a thickness that partially fills the channel holes 414 in Figures 4I and 4J. Subsequently, an insulating material 420, such as an oxide, is deposited in the channel holes 414 in Figures 4I and 4J, completely or partially filling the channel holes 414 and forming the NAND strings 116 of the 3D-NAND memory device 100 in Figure 1.

[0058] Referring to Figures 4M and 4N, the trench 422 is formed in portion 400 and, for example, etched to partially expose the substrate 402. The trench 422 extends longitudinally as indicated by arrow 122 in Figure 1 and can extend parallel to the dielectric packing groove 412 in Figures 4G and 4H. Referring to Figure 4N, the trench 422 exposes the sacrificial layer 406 in Figure 4F from the trench sidewall. The sacrificial layer 406 in Figure 4F can be selectively removed from the trench 422 to form a gate region, for example by a wet etching process.

[0059] Refer to Figures 4O and 4P. Once the sacrificial nitride is removed from portion 400, a replacement metal 424, such as tungsten, corresponding to the gate plane 106, can form the gate region through the trench 422. Before replacing the sacrificial nitride with the replacement metal 424, one or more layers of material, such as aluminum oxide or titanium nitride, may be deposited for performance and process advantages. The replacement metal 424 can be deposited through the trench 422 and into the gate region through the gap 408a, for example, by atomic layer deposition, physical deposition, chemical deposition, plasma-assisted atomic layer deposition, and plasma-enhanced chemical deposition. Arrow 432 shows an example of a path for removing the sacrificial nitride and depositing the metal 424. After filling the grooves 410 in Figures 4E and 4F with insulating material to form the dielectric packing grooves 412 in Figures 4E and 4F, the gaps 408a are the only pathway in the vertical stack for removing sacrificial nitride and depositing replacement metal. For example, without gaps 408a, the replacement metal 424 cannot be deposited in the space between adjacent dielectric packing grooves 412.

[0060] Referring to Figure 4Q, once the gate region is filled, anisotropic etching is performed to remove the material remaining in trench 422. In addition, trench 408b is etched through the stack at the location of gap 408a to isolate adjacent strips of substitution metal 424 (corresponding to the strips of gate plane 106) that function as transistor gates, word lines, and selection signal lines of the 3D-NAND memory device 100. Referring again to Figure 4B, trenches 422 and 408b, as shown in Figure 4Q, can be filled with insulating material to form dielectric-filled isolation trenches 442 and 426. The insulating material may include the same dielectric material (e.g., silicon oxide) as layer 404 in Figure 4D or layer 104 in Figure 4A.

[0061] The replacement metal 424, together with the memory layer 416 and channel layer 418 formed in the channel hole 414, forms the memory cells 114 of the 3D-NAND memory device 100 as shown in Figure 1. Referring to Figure 4B, the dielectric packing groove 412 divides the replacement metal layer 424 into separate strips 428, 428a, and 428b of the gate plane 106, so the memory cell 114 is divided into substantially two separate parts on either side of the dielectric packing groove 412. For example, the memory cell around the channel hole 414a is effectively divided so that one side 430a of the channel hole 414a engages with the metal 424 of one strip 428a to form a first memory cell, and the other side 430b of the channel hole 414a engages with another strip 428b to form a second memory cell. Thus, the circular memory cell 114 of the 3D-NAND memory device 100 in Figure 1 is divided into two separate memory cells having substantially semicircular or curved channels along the line 432.

[0062] An exemplary alternative method can be illustrated by referring to Figures 4R-4W. As can be seen from Figure 4R, the two grooves 410a and 410b do not contain a gap 408, and for example, grooves 410a and 410b are continuous. In general, in this example, all other grooves 410 are continuous.

[0063] Referring to Figure 4S, the groove 410 is filled with insulating material to form dielectric packing grooves 412, as described above. Referring to Figures 4T and 4U, the channel holes 414 and vertical channels are formed in a staggered pattern to increase memory cell density, as described above. Referring to Figures 4V and 4W, the trench 434 is etched through the continuous dielectric packing grooves. The sacrificial nitride is then removed, and the metal 424 can be deposited through the trench 434. The metal 424 can be deposited into the conductive layer 406 through the via 434 from the trench 422, for example, via atomic layer deposition, chemical vapor deposition, plasma-assisted atomic layer deposition, and plasma-enhanced chemical vapor deposition. Arrow 436 indicates an exemplary path for removing the sacrificial nitride and depositing the metal. Dielectric packing isolation trenches 442, as illustrated in Figures 4A and 4B, can be formed as needed to provide insulation between other parts 400 of the 3D-NAND memory device, such as the stack 108.

[0064] Referring to Figure 5, in another embodiment, a single vertical NAND string 116 may have only one channel hole 502, e.g., holes 214, 314, 414 (circular, elongated, or some other regular or irregular shape), and the vertical NAND string 116 may include multiple memory cells 504, e.g., memory cells 114, which can be formed for each hole on the same gate plane 506, e.g., gate plane 106. This can be done by forming physical separations between one or more material layers 508 deposited within the holes, e.g., memory layers 216, 316, 416. For example, using techniques similar to those described herein, channels can be formed and then memory cells can be formed. The memory cells can be filled with oxide, and the oxide can then be etched. The cell structure can then be etched to form multiple memory cells 504 within the channel hole 502.

[0065] Figure 6 is a flowchart of an exemplary method 600 for manufacturing a 3D-NAND memory device, for example, a 3D-NAND memory device 100. In the flowchart, the operation of method 600 is shown as separate blocks.

[0066] In block 602, a base material is provided. For example, the base material can be the same as that of base material 102.

[0067] In block 604, a first layer of the first material and a second layer of the second material are alternately deposited on the substrate to form a stack. For example, the first layer may correspond to layers 104, 206, 304, or 404, and the first material may be an oxide; the second layer may correspond to layers 106, 224, 306, or 424, and the second material may be silicon, polysilicon, or a metal such as tungsten.

[0068] In block 606, multiple grooves are formed in the stack. For example, the grooves can correspond to grooves 210, 310, or 410.

[0069] In block 608, a plurality of grooves are filled with a first material, for example, an oxide. In block 610, a plurality of channel holes are formed through a stack, for example, alternating first and second layers. For example, the channel holes may correspond to channel holes 214, 314, or 414.

[0070] In block 612, the memory layer is deposited along the walls of multiple channel holes. For example, the memory layer may include a charge storage layer, a blocking dielectric, and a tunnel dielectric.

[0071] In block 614, a channel layer is deposited on the memory layer within the channel hole. For example, silicon or polysilicon can be deposited on the memory layer within the channel hole. In block 616, a first material is deposited such that it at least partially fills the channel hole in order to form a vertical NAND string. For example, an oxide can be deposited such that it partially or completely fills the channel hole, thereby forming a vertical NAND string.

[0072] In block 618, contacts, for example, contact 120, are formed on the vertical NAND string. In block 620, bit lines, for example, bit line 118, are formed on the vertical NAND string.

[0073] While the present invention has been described in relation to specific embodiments, it should be understood that the scope of the invention is not limited to these specific embodiments. Other modifications and alterations adapted to suit specific operating requirements and environments will be apparent to those skilled in the art, and the invention is not to be considered limited to embodiments selected for disclosure purposes, but rather encompasses all modifications and alterations that do not deviate from the true spirit and scope of the invention.

[0074] This application describes embodiments having certain structural features and / or methodological actions, but it should be understood that the claims are not necessarily limited to the specific features or actions described. Rather, the specific features and actions are merely illustrative of some embodiments that fall within the scope of the claims of this application.

Claims

1. A method for manufacturing a three-dimensional NAND memory device (3D-NAND) including height, length, and width, The steps include providing a substrate and The steps include depositing a first layer of the first material on the substrate, The steps include depositing a second layer of the second material on top of the first layer to form a stack in which the first layer and the second layer are alternately stacked, The steps include forming a plurality of grooves in the stack, wherein the plurality of grooves extend along the length of the 3D-NAND memory device, The steps include filling the plurality of grooves with the first material, A step of forming a plurality of vertical holes in each of the grooves, wherein the vertical holes extend along the height of the 3D-NAND memory device, The steps include: depositing one or more conformal materials on the walls of the plurality of vertical holes to form vertical NAND strings in the plurality of grooves; The steps include depositing conductive material on the wall of the vertical NAND string, The steps include depositing a dielectric material onto the aforementioned vertical NAND string, Includes, A method wherein the second material of the second layer and the vertical NAND string define memory cells of the second layer of the 3D-NAND memory device, and the second material of the second layer defines word lines of the 3D-NAND memory device.

2. The steps include forming a plurality of pipe connection portions on the substrate before depositing the first layer of the first material and the second layer of the second material in order to form the stack, A step of depositing the first or second material onto the plurality of pipe connections, wherein the step of forming the plurality of grooves in the stack includes forming a pair of grooves on the opposite end of the plurality of pipe connections to the corresponding pipe connections, The step of forming a trench between the grooves, The steps include depositing a third material on top of the first layer before depositing the second material, The steps include removing the third material from the stack through the trench, The steps include depositing the second material into the stack via the trench to replace the third material, The steps include depositing the dielectric material in the trench, The method according to claim 1, further comprising:

3. The method according to claim 2, wherein the second material comprises tungsten.

4. The method according to claim 3, wherein the conductive material includes either silicon or polysilicon.

5. The method according to claim 2, wherein the substrate comprises either silicon or polysilicon.

6. The method according to claim 5, wherein at least one of the second material, the third material, or the conductive material includes at least one of silicon or polysilicon.

7. The method according to claim 1, wherein the vertical holes of the first groove among the plurality of grooves are arranged in a staggered pattern with respect to the vertical holes of the adjacent second groove among the plurality of grooves.

8. The step of forming the plurality of grooves in the stack includes forming the plurality of grooves in a discontinuous manner such that each of the grooves includes a gap defined therein, The aforementioned method, The steps include forming two or more trenches, The steps include depositing a third material on top of the first layer before depositing the second material, The steps include removing the third material from the stack through the two or more trenches, The steps include depositing the second material into the stack through the two or more trenches and replacing the third material, The steps include depositing the first material in the trench, The method according to claim 1, including the method described in claim 1.

9. The method according to claim 8, wherein the step of depositing the second material on the stack includes one of atomic layer deposition, chemical vapor deposition, plasma-assisted atomic layer deposition, or plasma-enhanced chemical vapor deposition.

10. The step of forming the plurality of grooves in the stack includes forming the plurality of grooves in a discontinuous manner such that each of the grooves includes a gap defined therein, The aforementioned method, The steps include forming vias in each of the aforementioned gaps, The steps include depositing a third material on top of the first layer before depositing the second material, The steps include removing the third material from the stack through the via, The steps include depositing the second material onto the stack and replacing the third material through the vias, The steps include depositing the first material in the via, The method according to claim 1, including the method described in claim 1.

11. The method according to claim 10, wherein the step of depositing the second material on the stack includes one of atomic layer deposition, chemical vapor deposition, plasma-assisted atomic layer deposition, or plasma-enhanced chemical vapor deposition.

12. A three-dimensional NAND (3D-NAND) memory device including height, length, and width, Substrate and A stack on the substrate, wherein a plurality of first layers and a plurality of second layers are arranged alternately, the plurality of first layers contain a first material, and the plurality of second layers contain a second material, and A plurality of vertical 3D-NAND strings defined in a plurality of grooves defined in the stack, wherein the vertical 3D-NAND strings extend along the height of the 3D-NAND memory device, and the grooves extend along the length of the 3D-NAND memory device, A plurality of memory cells defined in the vertical 3D-NAND string of the second layer, A plurality of word lines defined between the grooves, each of which is separated by one of the grooves from the next word line in one of the plurality of second layers, A three-dimensional NAND (3D-NAND) memory device equipped with [the specified features].

13. The 3D-NAND memory device according to claim 12, further comprising a separation trench filled with the first material.

14. The 3D-NAND memory device according to claim 13, wherein the second material comprises tungsten.

15. The 3D-NAND memory device according to claim 14, wherein the conductive material of the NAND string includes either silicon or polysilicon.

16. The 3D-NAND memory device according to claim 12, wherein the substrate comprises either silicon or polysilicon.

17. The 3D-NAND memory device according to claim 16, wherein at least one of the second material, the third material, or the conductive material includes at least one of silicon or polysilicon.

18. The 3D-NAND memory device according to claim 12, wherein the vertical channels of the first groove among the plurality of grooves are staggered with respect to the vertical 3D-NAND strings of the adjacent second groove among the plurality of grooves.

19. A method for manufacturing a three-dimensional NAND (3D-NAND) memory device, A step of depositing a first layer of the first material onto a substrate, The steps include depositing a second layer of the second material to form a stack, A step of forming a groove containing a first material in the stack, wherein the groove extends along the length of the 3D-NAND memory device, A step of forming a plurality of conductive vertical 3D-NAND strings in the groove, wherein the second material and the conductive vertical 3D-NAND strings define memory cells in the second layer for the 3D-NAND memory device, the second material in the second layer defines two word lines for the 3D-NAND memory device, and each of the word lines is separated from the next word line in the second layer by one of the grooves, The steps include forming a contact on each of the conductive vertical 3D-NAND strings, The steps include connecting each of the aforementioned contacts to a bit line, Methods that include...

20. The method according to claim 19, wherein at least one of the substrate, the second material, the third material, or the conductive material includes at least one of silicon or polysilicon.

21. A method for manufacturing a three-dimensional NAND (3D-NAND) memory device, The steps include forming a stack by alternately depositing a plurality of first layers of a first material and a plurality of second layers of a second material on a substrate, A step of forming a plurality of grooves in a stack containing a first material, wherein the grooves extend along the word line direction of the 3D-NAND memory device, and a step of dividing at least a portion of the second layer into strips extending along the word line direction, A step of etching a plurality of channel holes into the stack, wherein each of the channel holes overlaps with one of the grooves and is wider than one of the grooves in the bit line direction perpendicular to the word line direction, The steps include depositing the memory layer and the channel layer into the channel holes to form a vertical NAND string, Methods that include...

22. The method according to claim 21, wherein the step of forming the plurality of grooves includes defining a gap region between two adjacent grooves that are substantially aligned along the word line direction.

23. The method according to claim 22, wherein the channel holes etched into the stack do not overlap with the gap region.

24. A step of etching a plurality of isolation trenches into the stack, wherein the isolation trenches extend along the direction of the word line, The steps include selectively removing the second material of the second layer from the exposed side wall of the second layer of the separation trench, A step of depositing gate metal in the space revealed by the removed second material, wherein the gap region provides a path for removing the second material and depositing the gate metal, The steps include removing the material remaining in the separation trench, The steps include filling the separation trench with a dielectric material, The method according to claim 22, including the method described in claim 22.

25. The method according to claim 21, comprising the step of forming a staircase region on at least one side of the stack, wherein the plurality of grooves extend into the staircase region.

26. At least one of the grooves extends only partially into the stepped area, At least one second layer at the bottom of the stack has a first portion and a second portion opposite at least one of the grooves, The method according to claim 25, wherein the first portion and the second portion are joined via the remaining portion of the at least one second layer of the stair region.

27. The aforementioned stack has a first height, At least one of the grooves has a second height that is smaller than the first height. The method according to claim 21, wherein at least one of the second layers at the bottom of the stack is not divided by at least one of the grooves.

28. The method according to claim 21, wherein the channel holes are arranged in a staggered pattern.

29. The method according to claim 21, wherein the memory layer comprises a charge storage layer, a blocking dielectric between the channel hole sidewall and the charge storage layer, and a tunnel dielectric between the charge storage layer and the channel layer.

30. The method according to claim 29, wherein the charge storage layer includes a charge trapping layer.

31. The method according to claim 29, wherein the charge storage layer includes a floating gate.

32. The method according to claim 31, wherein the channel layer comprises polycrystalline silicon or silicon germanium.

33. A method for manufacturing a three-dimensional NAND (3D-NAND) memory device, The steps include forming a stack by alternately depositing multiple first layers of a first material and multiple second layers of a second material on a substrate, The steps include forming a plurality of grooves in the stack comprising a first material, wherein the grooves extend along the word line direction of the 3D-NAND memory device, and the gap region is defined between two adjacent grooves substantially aligned along the word line direction, A step of etching a plurality of channel holes into the stack, wherein each of the channel holes overlaps with one of the grooves and is wider than one of the grooves in the bit line direction perpendicular to the word line direction, The steps include depositing the memory layer and the channel layer into the channel holes to form a vertical NAND string, Methods that include...

34. The method according to claim 33, wherein the channel holes etched into the stack do not overlap with the gap region.

35. A step of etching a plurality of isolation trenches into the stack, wherein the isolation trenches extend along the direction of the word line, The steps include selectively removing the second material of the second layer from the exposed side wall of the second layer of the separation trench, A step of depositing gate metal in the space revealed by the removed second material, wherein the gap region provides a path for removing the second material and depositing the gate metal, The steps include removing the material remaining in the separation trench, The steps include filling the separation trench with a dielectric material, The method according to claim 33, including the method described in claim 33.

36. A method for manufacturing a U-shaped NAND string for a three-dimensional NAND (3D-NAND) memory device, The steps include providing a base material having a pipe connection portion, The steps include forming a stack by alternately depositing a plurality of first layers of the first material and a plurality of second layers of the second material on the substrate, The steps include forming first and second grooves containing the first material in the stack, wherein the first and second grooves extend along the word line direction of the 3D-NAND memory device, A step of etching first and second channel holes into the stack, wherein the pipe connection portion of the substrate is partially exposed, the first channel hole overlaps with the first groove and is wider than the first groove in the bit line direction perpendicular to the word line direction, and the second channel hole overlaps with the second groove and is wider than the second groove in the bit line direction, The steps include depositing a memory layer and a channel layer in the first and second channel holes to form a U-shaped NAND string, Methods that include...

37. A step of etching first, second, and third isolation trenches into the stack, wherein the first, second, and third isolation trenches extend along the word line direction, the first groove is located between the first and second isolation trenches, the second isolation trench is located between the first and second grooves, and the second groove is located between the second and third isolation trenches, The steps include filling the first and second separation trenches with dielectric material, The method according to claim 36, including the method described in claim 36.

38. The method according to claim 36, comprising the step of forming a staircase region on at least one side of the stack, wherein the first and second grooves extend into the staircase region.

39. At least one of the grooves extends only partially into the stepped area, At least one second layer at the bottom of the stack has a first portion and a second portion opposite to at least one of the grooves, The method according to claim 38, wherein the first portion and the second portion are joined via the remaining portion of the at least one second layer of the stair region.

40. The method according to claim 36, wherein the second material is doped polysilicon.

41. The method according to claim 36, wherein the first material is silicon oxide.

42. The method according to claim 36, wherein the memory layer includes a charge storage layer, a blocking dielectric between the second material and the charge storage layer, and a tunnel dielectric between the charge storage layer and the channel layer.

43. The method according to claim 42, wherein the charge storage layer includes a charge trapping layer.

44. The method according to claim 42, wherein the charge storage layer includes a floating gate.

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