Inspection method and system for integrated circuit substrates

Abstract

An inspection system for capturing information from a substrate using one or more sensors. In some examples, a substrate can be inspected on both sides simultaneously. In other embodiments, various measurements can be performed for overlay, features, thickness, resistance, and other parameters. These measurements can be made using various sensors, such as cameras, lasers, infrared imaging, and / or X-ray sensors. By carefully handling the substrate, the inspection system can avoid damage or contamination to the substrate while inspecting the substrate during stages of the process that are not currently inspected due to shortcomings of conventional inspection machines.

Description

[Technical Field]

[0001] (Priority Claim) This application claims the benefit of priority to U.S. Provisional Patent Application No. 63 / 385,561, filed November 30, 2022, entitled "DUAL SIDE SIMULTANEOUS INSPECTION FOR INTEGRATED CIRCUIT SUBSTRATES," the contents of which are incorporated herein by reference in their entirety.

[0002] FIELD OF THE DISCLOSURE The present disclosure relates generally to inspection methods and systems, and more particularly to automated inspection of substrates such as semiconductor substrates. [Background technology]

[0003] The manufacturing of integrated circuit boards has become more complex and robust. Processing can now be applied to both sides of a substrate, building separate layers on each side. However, traditional inspection techniques are not adept at handling integrated circuit boards with structures built on both sides. In traditional inspection systems, the first side of the substrate is placed on a stage or similar structure, and the second side is inspected using an inspection camera. Then, if the first side needs to be inspected, the substrate is flipped over and the same inspection process is repeated for the first side. Additionally, traditional inspection techniques typically cannot be used until a copper layer has been etched onto the layer being inspected, because handling the substrate without the final copper layer can lead to contamination and damage. Summary of the Invention

[0004] An inspection system for capturing information from a substrate using one or more sensors. In some examples, a substrate can be inspected on both sides simultaneously. In other embodiments, various measurements can be performed for overlay, features, thickness, resistance, and other parameters. These measurements can be made using various sensors, such as cameras, lasers, infrared imaging, and / or X-ray sensors. By carefully handling the substrate, the inspection system can avoid damage or contamination to the substrate while inspecting the substrate during stages of the process that are not currently inspected due to shortcomings of conventional inspection machines.

[0005] There is a need for an inspection technique that can safely and efficiently process inspection of both sides of a substrate (e.g., an Advanced Integrated Circuit Substrate (AICS)). The inspection technique described herein can hold a substrate panel while contacting only designated keep out zones (KOZ) on the panel so as not to damage the processing layers on either side of the substrate panel. The inspection technique described herein can also inspect both sides simultaneously using at least one sensor on each side of the panel. Furthermore, the inspection technique can be used to inspect a substrate after an intermediate processing step (i.e., before the copper layer is etched thereon) without significant risk of contamination or damage to the active areas on either side of the panel. This allows for the collection of more inspection information at intermediate processing steps than would be possible using the conventional techniques described above.

[0006] In some embodiments, a method is provided for inspecting an integrated circuit (IC) substrate, the method including receiving an IC substrate before a copper seed layer is etched on a first layer on a first side of the IC substrate and on a second layer on a second side of the IC substrate; holding the IC substrate using a holding mechanism, the holding mechanism contacting the IC substrate over one or more defined keep-out zones (KOZs); and simultaneously inspecting a first side and a second side of the substrate using a first sensor for the first side and a second sensor for the second side.

[0007] In a particular embodiment, an inspection system for double-sided inspection of an integrated circuit (IC) substrate is provided, the inspection system including: a holding mechanism for holding the IC substrate before a copper seed layer is etched on a first layer on a first side of the IC substrate and on a second layer on a second side of the IC substrate, the holding mechanism contacting the IC substrate over at least one keep-out zone (KOZ); a first sensor for inspecting the first layer on the first side of the IC substrate; and a second sensor for inspecting the second layer on the second side of the IC substrate.

[0008] In some embodiments, an inspection system for double-sided inspection is provided that includes means for holding an IC substrate before a copper seed layer is etched on a first layer on a first side of the IC substrate and on a second layer on a second side of the IC substrate, and means for substantially simultaneously inspecting the first layer and the second layer.

[0009] The various figures of the accompanying drawings are merely illustrative of exemplary embodiments of the present disclosure and should not be considered as limiting its scope. [Brief explanation of the drawings]

[0010] [Figure 1A] 1 illustrates an exemplary portion of an IC substrate panel. [Figure 1B] 1 illustrates an exemplary portion of an IC substrate panel. [Figure 2] 1 illustrates an exemplary portion of a frame having an outer frame portion. [Figure 3] 1 illustrates an exemplary portion of a frame having an outer frame portion and an inner frame portion. [Figure 4A] 1 illustrates an exemplary portion of a vertical inspection process. [Figure 4B] 1 illustrates an exemplary portion of a vertical inspection process. [Figure 5A] 1 illustrates an exemplary portion of a horizontal inspection process. [Figure 5B] 1 illustrates an exemplary portion of a horizontal inspection process. [Figure 6] 1 illustrates a flow diagram of a method for performing simultaneous double-sided inspection. [Figure 7] 1 illustrates a block diagram of an example computer system used in the inspection process. [Figure 8] 1 illustrates an exemplary portion of an inspection system. [Figure 9] 1 illustrates an exemplary layer-by-layer stack through a film stack. DETAILED DESCRIPTION OF THE INVENTION

[0011] Described herein are various inspection techniques that can safely and efficiently process the inspection of substrates (e.g., AICS). Substrate panels can be held using only designated keep-out zones (KOZs) on the panel to avoid damaging processing layers on either side of the substrate panel. Sensors can be located on each side of the panel for simultaneous inspection of both sides of the substrate, such as automatic optical inspection (AOI). In particular, the inspection techniques can be adapted to inspect substrates after intermediate processing steps (i.e., before a copper layer is etched onto the layer) without contaminating or damaging the active areas on either side of the substrate panel.

[0012] 1A and 1B illustrate an exemplary portion of an IC substrate panel 100 (e.g., an AICS). FIG. 1A shows a first side 102 of the IC substrate panel 100, and FIG. 1B illustrates an opposite second side 152 of the IC substrate panel 100. The first side 102 includes a plurality of active areas 104. The active areas 104 may include areas where layers of IC structures may be built. These layers are the focus of the inspection process, as described in further detail below. The first side 102 also includes keep-out zones 106 (KOZs). The KOZs 106 are specific locations on each side of the substrate panel that are devoid of IC structures. Thus, the KOZs 106 may be used to handle the panel during inspection. In some embodiments, the KOZs may be provided on the edges of the panel. In some embodiments, the KOZs may also be provided on interior portions of the panel. 1A, KOZ 106 are provided on the edges of the panel as well as on the inner portion, which is cross-shaped and divides the face of the panel into four active areas 104. Other configurations can also be used. For example, six, eight, or other numbers of active areas can be provided.

[0013] As described above, the IC substrate panel can have the same pattern on the opposite side. In some embodiments, the opposite second side 152 can have a different pattern of active areas and KOZ, as shown in FIG. 1B. The second side 152 includes an active area 154 and a KOZ surface 156, as shown in FIG. 1B.

[0014] For testing, an IC substrate panel (e.g., IC substrate panel 100) may be held using a KOZ. That is, a frame may be in contact with the KOZ to hold the IC substrate panel during testing, but not in contact with the active area. A frame or other holding structure may be used to hold the IC substrate panel, thereby allowing substantially simultaneous testing of both sides to be performed.

[0015] FIG. 2 illustrates an example portion of a frame 200 having an outer frame portion. As shown in FIG. 2, the frame 200 includes an outer frame portion 202 configured to contact a KOZ located at the edge of an IC substrate panel. The frame 200 may include one or more holding mechanisms, such as clamps, clips, suction cups, or electrostatic clamps, to hold the IC substrate panel. In some embodiments, the frame 200 may include a vacuum assembly to hold the IC substrate panel. The panel may be clamped to hold it from one vertical side, for example, while leaving both sides open for inspection.

[0016] 3 illustrates an example portion of a frame 300 having an outer frame portion and an inner frame portion, where the frame includes an outer frame portion 302 configured to contact a KOZ located at an edge of an IC substrate panel, and an inner frame portion 304 configured to contact a KOZ located at an inner portion of the IC substrate panel (inner frame portion 304 as described above with reference to FIG. 1A).

[0017] 4A and 4B illustrate an exemplary portion of a vertical inspection method. The vertical inspection method is configured to inspect both sides of an IC substrate panel 402 substantially simultaneously. FIG. 4A illustrates loading of an IC substrate panel 402 for inspection. In FIG. 4A, a robotic arm 404 can be used to hold a frame 406 with the IC substrate panel 402 attached at the KOZ of the IC substrate panel 402. The IC substrate panel 402 can then be held in a vertical position by the frame 406 or other holding structure for inspection. The robotic arm has a frame support that holds at least one KOZ area at the edge of the IC substrate panel to prevent contamination of the active areas on both the first and second sides of the panel. The frame support includes multiple suction cups and clamps. The holding mechanism can use a vacuum mechanism to hold one or more KOZ areas at the edge of the IC substrate panel.

[0018] 4B illustrates a method for substantially simultaneous inspection of both sides of an IC substrate panel using a vertical inspection system. A first sensor 452 may be positioned to face a first side of the IC substrate panel 402, and a second sensor 454 may be positioned to face a second side of the IC substrate panel 402. The first sensor 452 and the second sensor 454 may be configured to perform substantially simultaneous inspection of the active areas on each side of the IC substrate panel. That is, the first sensor (e.g., camera) 452 may inspect the active areas on the first side of the IC substrate panel 402, while the second sensor (e.g., camera) 454 may inspect the active areas on the second side of the IC substrate panel 402. In some embodiments, two or more cameras may be provided on each side of the IC substrate panel. The sensor(s) may further include an image sensor, such as a CMOS or CCD sensor. In some embodiments, the sensor(s) may include an infrared sensor, a laser sensor, and / or an X-ray sensor.

[0019] In one embodiment, simultaneous inspection can also be performed when the IC substrate panel is positioned horizontally. Figures 5A and 5B illustrate an exemplary portion of a horizontal inspection process. The horizontal inspection method is configured to inspect both sides of an IC substrate panel 502 substantially simultaneously. Figure 5A illustrates loading of an IC substrate panel 502 for inspection. In Figure 5A, a robotic arm 504 can be used to hold a frame 506 with the IC substrate panel 502 attached to it at the KOZ of the IC substrate panel 502. The IC substrate panel 502 can then be held in a horizontal position by the frame 406 or other holding structure for inspection.

[0020] 5B illustrates a method for substantially simultaneous inspection of both sides of an IC substrate panel using a horizontal inspection system. A first sensor 552 may be positioned to face a first side (e.g., a top side) of the IC substrate panel 502, and a second sensor 554 may be positioned to face a second side (e.g., a bottom side) of the IC substrate panel 502. The first sensor 552 and the second sensor 554 may be configured to perform substantially simultaneous inspection of the active areas of their respective sides. That is, the first sensor 552 may inspect the active areas on the first side of the IC substrate panel 502, and the second sensor 554 may inspect the active areas on the second side of the IC substrate panel 502. In some embodiments, two or more sensors may be provided on each side of the panel. The sensor(s) may include an image sensor, such as a CMOS or CCD sensor. In some embodiments, the sensor(s) may include an infrared, laser, and / or X-ray sensor.

[0021] In some embodiments, a sensor (e.g., a camera) in the inspection system (including a vertical orientation, a horizontal orientation, or any other orientation) can be moved while the IC substrate panel is held in place to perform inspection of different active areas. In some embodiments, the IC substrate panel can be moved to perform inspection of different active areas while the sensor is held in place. In some embodiments, the combination of the sensor and IC substrate panel can be moved to perform the inspection. In certain embodiments, the substrate panel can be held vertically on one side by a clamp and inspected by a sensor(s) on either side. The substrate can be moved by electric motors, for example, one precision electric motor in the x-direction and another precision electric motor in the y-direction. The electric motors can be linear motors. The camera can also be moved by electric motors in the x-, y-, and z-axes. The holding mechanism or clamp can include a calibration area used to calibrate the position of the substrate and motors relative to the sensor. Calibration markers on the substrate can also be used to calibrate the position within the substrate.

[0022] An IC substrate is generally a substrate that electrically connects an IC chip to a circuit board through a network of conductive copper traces and vias. As mentioned above, IC chip structures may now be built on both sides of the substrate. A typical process flow for manufacturing an IC substrate includes the following: 1. We provide substrates such as copper clad laminates (CCL). 2. Machine drilling the holes. 3. Seed the holes with copper (Cu) plating. 4. Dry film deposition such as photoresist (PR) deposition. 5. Developing PR. 6.Cu plating. 7. PR strips. 8.Cu etching. 9. Lamination of Ajinomoto buildup film (ABF). 10. Hardening of ABF. 11. Laser perforation. 12. Remove smear. 13.Cu plating seeding. 14. Dry film (PR) lamination. 15. Developing PR. 16.Cu plating. 17. PR Strip. 18.Cu seed etching.

[0023] These steps may be applied to each side of the substrate. Steps 9 through 18 may be repeated for a multi-layer buildup. That is, steps 9 through 18 may be repeated for each layer on each side of the substrate. For example, each side may be built with multiple layers (e.g., 12 layers on each side of a 12-2-12 AICS panel).

[0024] With conventional inspection techniques, IC substrates can typically be inspected only after step 18 of Cu etching due to the risk of damage and contamination. For example, each layer can only be inspected after step 18 is performed on the respective layer so that the layer has a Cu-etched seed layer as its top surface. However, using the inspection techniques described herein, IC substrates can be inspected multiple times before the Cu-etched seed layer is provided as the top surface of any side (after the formation of the final redistribution layer (RDL) and before the application of the next build-up layer, e.g., ABF). For example, using the inspection techniques described herein, IC substrates can be inspected after step 11 of laser drilling vias through ABF in each layer. As another example, IC substrates can also be inspected after step 15 of dry film development / lithography (PR development). Therefore, at least two additional inspections can be performed for each layer to detect possible errors during the process.

[0025] FIG. 6 illustrates a flow diagram of a method 600 for performing simultaneous double-sided inspection using the inspection techniques described herein. In operation 602, an IC substrate panel may be received by an inspection system. For example, a robotic arm may pick up the IC substrate panel and move it to the inspection system. The IC substrate panel may have IC structures built on each side. The IC substrate panel may be received before the top layer of either side has a Cu seed layer etched thereon. For example, the top layer of each side may be received after laser drilling vias through an ABF (e.g., step 11 of the process flow for manufacturing an IC substrate described above).

[0026] In operation 604, the IC substrate panel may be held using a retention mechanism, as described above, which may contact the IC substrate on one or more KOZs.

[0027] In operation 606, both sides of the IC substrate panel may be inspected substantially simultaneously using at least one camera on the first side of the IC substrate panel and at least one sensor(s) (e.g., camera, infrared sensor, laser, and / or X-ray) on the second side of the IC substrate panel. The sensor(s) on the first side and the sensor(s) on the second side may be positioned opposite each other vertically or horizontally with the substrate panel in between. The laser may be a picosecond ultrasonic laser that induces acoustic waves in the substrate that are sensed in the second laser measurement.

[0028] In operation 608, the IC substrate panel may be removed from the inspection system and may undergo further manufacturing.

[0029] In operation 610, the IC substrate panel may be received by the inspection system before the Cu seed layer is etched on each layer. For example, the top layer of each side may be received after dry film development / lithography (PR development) (e.g., step 15 of the process flow for manufacturing IC substrates described above).

[0030] In operation 612, the IC substrate panel may be held using a holding mechanism, as described above. The holding mechanism may contact the IC substrate panel at one or more KOZs. The holding mechanism holds the substrate in a horizontal or vertical position while at least one camera simultaneously inspects both sides of the substrate.

[0031] In operation 614, both sides of the IC substrate panel may be inspected substantially simultaneously using at least one camera on the first side of the IC substrate panel and at least one camera on the second side of the IC substrate.

[0032] In operation 616, the IC substrate may be removed from the inspection system and may undergo further fabrication.

[0033] In operation 618, after the Cu seed layer is etched on each top layer, the IC substrate may be received by an inspection system.

[0034] In operation 620, the IC substrate may be held using a retention mechanism, as described above. The retention mechanism may contact the IC substrate panel on one or more defined KOZs.

[0035] In operation 622, both sides of the IC substrate may be inspected substantially simultaneously using at least one camera on a first side of the IC substrate panel and at least one camera on a second side of the IC substrate panel.

[0036] These operations can then be repeated for each layer built on the substrate. For example, for an IC substrate panel with 12 layers on each side, this method can be performed 12 times, once for each layer. Each layer can then be inspected at least three times after different manufacturing steps, as described above. Compared to conventional inspection systems, which can only inspect each layer once after the Cu seed layer is etched, this inspection technique can inspect each layer multiple times, resulting in more detailed inspection.

[0037] The simultaneous inspection technique described herein offers at least two important advantages: The technique can increase throughput due to the use of at least two inspection cameras and simultaneous double-sided inspection; and, unlike conventional inspection techniques, the technique can detect defects earlier in the manufacturing process because inspection can be performed before the copper layer is etched.

[0038] The techniques shown and described herein may be performed using part or all of an inspection system such as those described above, or otherwise using a machine 700 such as that discussed below in connection with Figure 7. Figure 7 illustrates an example block diagram comprising a machine 700 on which any one or more of the techniques (e.g., methodologies) discussed herein may be performed. In various examples, machine 700 may operate as a standalone device or may be connected (e.g., networked) to other machines.

[0039] In a networked deployment, machine 700 may operate as a server machine, a client machine, or both in a server-client network environment. In one example, machine 700 may function as a peer machine in a peer-to-peer (P2P) (or other distributed) network environment. Machine 700 may be a personal computer (PC), a tablet device, a set-top box (STB), a personal digital assistant (PDA), a mobile phone, a web appliance, a network router, switch, or bridge, or any machine capable of executing instructions (sequential or otherwise) that specify actions to be taken by the machine. Furthermore, while only a single machine is illustrated, the term “machine” is intended to include any collection of machines individually or collectively executing a set (or sets) of instructions to perform any one or more of the methodologies discussed herein, such as cloud computing, software as a service (SaaS), other computer cluster configurations, etc.

[0040] Examples described herein may include or operate by logic or multiple components or mechanisms. Circuitry is a collection of circuits implemented in tangible entities including hardware (e.g., simple circuits, gates, logic, etc.). Circuitry membership may be flexible over time and the variability of the underlying hardware. Circuitry includes elements that, alone or in combination, can perform specified operations when in operation. In one example, the hardware of a circuitry may be invariably designed (e.g., hardwired) to perform specific operations. In one example, hardware comprising circuitry may include variably connected physical components (e.g., execution units, transistors, simple circuits, etc.) including computer-readable media that are physically altered (e.g., magnetically, electrically, etc., via a change in physical state or a transformation of another physical property) to encode instructions for specific operations. When connecting the physical components, the underlying electrical properties of the hardware components may be altered, for example, from insulating to conductive properties or vice versa. The instructions enable embedded hardware (e.g., an execution unit or a load mechanism) to create, via variable connections, members of circuitry within the hardware to perform portions of specific operations during operation. Thus, the computer-readable medium is communicatively coupled to other components of the circuitry when the device is operating. In one example, any of the physical components may be used in more than one member of more than one circuitry. For example, during operation, an execution unit may be used in a first circuit of a first circuitry at one time and reused by a second circuit within the first circuitry or by a third circuit within the second circuitry at a different time.

[0041] The machine 700 (e.g., a computer system) may include a hardware-based processor 701 (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a hardware processor core, or any combination thereof), a main memory 703, and a static memory 705, some or all of which may communicate with each other via an interlink 730 (e.g., a bus). The machine 700 may further include a display device 709, an input device 711 (e.g., an alphanumeric keyboard), and a user interface (UI) navigation device 713 (e.g., a mouse). In one example, the display device 709, the input device 711, and the UI navigation device 713 may include at least a portion of a touchscreen display. The machine 700 may additionally include a storage device 720 (e.g., a drive unit), a signal generating device 717 (e.g., a speaker), a network interface device 750, and one or more sensors 715, such as a global positioning system (GPS) sensor, a compass, an accelerometer, or other sensor. The machine 700 may include an output controller 719, such as a serial controller or interface (e.g., universal serial bus (USB)), a parallel controller or interface, or other wired or wireless (e.g., infrared (IR)) controller or interface, near field communication (NFC), etc., coupled to communicate with or control one or more peripheral devices (e.g., a printer, a card reader, etc.).

[0042] The storage device 720 may include a machine-readable medium on which is stored one or more sets of data structures or instructions 724 (e.g., software or firmware) that embody or are utilized by any one or more of the techniques or functions described herein. The instructions 724 may also reside, completely or at least partially, within the main memory 703, within the static memory 705, within the mass storage device 707, or within the hardware-based processor 701 during execution thereof by the machine 700. In one example, one or any combination of the hardware-based processor 701, the main memory 703, the static memory 705, or the storage device 720 may constitute a machine-readable medium.

[0043] Although the machine-readable medium is considered a single medium, the term "machine-readable medium" may include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) configured to store one or more instructions 724.

[0044] The term "machine-readable medium" may include any medium capable of storing, encoding, or carrying instructions for execution by machine 700 and causing machine 700 to perform any one or more of the techniques of this disclosure, or capable of storing, encoding, or carrying data structures used by or associated with such instructions. Non-limiting examples of machine-readable media may include solid-state memory, and optical and magnetic media. Thus, a machine-readable medium is not a transitory, propagating signal. Specific examples of large-scale machine-readable media may include semiconductor memory devices (e.g., Electrically Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM)) and non-volatile memory such as flash memory devices, magnetic or other phase-change or state-change memory circuits, magnetic disks such as internal hard disks and removable disks, magneto-optical disks, and CD-ROM and DVD-ROM disks.

[0045] The instructions 724 may further be transmitted or received over a communications network 721 using a transmission medium via a network interface device 750 utilizing any one of several transport protocols (e.g., frame relay, internet protocol (IP), transmission control protocol (TCP), user datagram protocol (UDP), hypertext transfer protocol (HTTP), etc.). Exemplary communication networks may include local area networks (LANs), wide area networks (WANs), packet data networks (e.g., the Internet), mobile phone networks (e.g., cellular networks), Plain Old Telephone (POTS) networks, and wireless data networks (e.g., the Institute of Electrical and Electronics Engineers (IEEE) 802.22 family of standards known as Wi-Fi®, the IEEE 802.26 family of standards known as WiMax®), the IEEE 802.27.4 family of standards, peer-to-peer (P2P) networks, among others. In one example, network interface device 750 may include one or more physical jacks (e.g., Ethernet, coaxial, or telephone jacks) or one or more antennas for connecting to communication network 721. In one example, the network interface device 750 may include multiple antennas for wireless communication using at least one of single-input multiple-output (SIMO), multiple-input multiple-output (MIMO), or multiple-input single-output (MISO) technologies.The term "transmission medium" is intended to include any intangible medium capable of storing, encoding, or carrying instructions for execution by machine 700, including digital or analog communication signals or other intangible media for facilitating communication of such software.

[0046] FIG. 8 illustrates an inspection system 800 used to take a substrate 402 (such as a panel) and inspect both sides simultaneously. A robotic arm 802 can be used to grasp the substrate at one end of the inspection system and transport it to an inspection area where it can be simultaneously inspected using at least two sensors positioned on both sides of the substrate. In certain embodiments, the panel can be passed from the robotic arm 802 to a holding mechanism that clamps and suctions the top surface of the substrate 402. The substrate can then be moved in the x and y directions with electric motors so that the sensors can scan across the substrate. When inspection is complete, a second robotic arm 804 can pick up the substrate and remove it from the inspection system.

[0047] In a more detailed embodiment, it is described herein that an IC substrate typically has at least 12 layers on each side, i.e., there are 24 layers in an IC substrate panel that need to be tracked. The inspection system not only allows the user to continuously track the measurement data of the layers, but the data can also be sent to a processing system for selection of final calculations based on the received measurements.

[0048] In one embodiment, the system measures laser-drilled holes on the surface of each side of an IC substrate panel during inspection. The drilled holes are inspected by at least one sensor on each side while a holding mechanism, such as a robotic arm or clamp, holds the panel in a horizontal or vertical position. The first and second sides of the substrate can be inspected simultaneously, and the X / Y positions of the drilled holes relative to the nominal positions of the structures are recorded. After recording the measurements of the drilled holes using a sensor (e.g., a camera), the measurement data can be used to calculate the resistance of the structures on the panel. The formula for calculating resistance, R, is ρL / A.

[0049] Information regarding the resistance across a substrate build is often tracked for metrology purposes. The machine 700, which is part of the inspection system 800 of FIG. 8, may transmit the tracked information to other servers and semiconductor manufacturing equipment (such as a laser drilling machine), where such tracking information can be used. In another embodiment, the inspection system 800 transmits the measurement data and resistance calculations to a stepper on the production line. The stepper uses the received information to calculate the stage and lens adjustments needed to return the overlay to its nominal position. Calculations are performed for both sides of the panel, and the calculated adjustments allow for ideal positioning of the IC substrate panel.

[0050] In an exemplary embodiment, the resistance calculation is performed using the formula R=ρL / A, as shown in Table 1 below. [Table 1] where: Via nominal copper length is 0.000500 meters Nominal resistance, no overlay drift is 0.131250 ohms Overlay drift resistance is 0.144375 ohms Delta resistance is 0.013125 ohms The percentage difference is 10 Copper ρ is 1.68E-08 The resistance is calculated using the formula R=ρL / A, where R is 0.0187 ohms.

[0051] In one embodiment, the system further includes at least one sensor on each side of the IC substrate panel. These sensors are used for inspection in the pattern to measure features on the substrate (such as drilled holes or vias). Both sides of the substrate, i.e., the first side and the second side, can be inspected simultaneously, and the X / Y positions of the drilled holes relative to the nominal positions of the structures are recorded. After recording the measurements of the drilled holes using the sensors on both sides, the measurement data can be further used to calculate the resistance of the RDL structures and via holes between multiple layers on the substrate panel.

[0052] Additionally, the captured X / Y positions and RDL structures are saved in suitable output format files on the inspection system 800. These output files can then be transferred to a server or database, which may reside within or outside the manufacturing facility. The inspection system 800 can also use information received from other manufacturing machines (such as laser drilling machines) for comparison. The inspection system can also use RDL resistance tracker information to compare the positions of holes, vias, or other features from one layer to the next. For example, the RDL resistance tracker can use captured X / Y position features from the transferred output files of both the first and second sides of a substrate panel to track the center coordinates of the X / Y positions on the front and back sides of the panel layers. The difference in pattern position between the first-side and second-side patterns increases as the number of layers and the respective substrate distortion increase. The position difference data is plotted in a heat map format to represent the raw position delta. An inspection system, such as machine 700, can also calculate the resistance of the RDL structures.

[0053] Drilled holes are inspected by at least one sensor on each side. Multiple holes and / or vias are drilled using advanced technology such as lasers. Simultaneous inspection of deformations across both sides of the panel collects X,Y coordinate data from the laser-drilled vias. This data is saved in a suitable file format and sent from machine 700 of inspection system 800 to a database to calculate systematic lithography stepper and laser-drilling X / Y position errors that control front-to-back pattern registration. Such calculations can be modeling programs that provide error information to the lithography machines.

[0054] The data modeling of both the first side ("A") and the second side ("B") of the panel can simultaneously provide inter-field systematic errors such as scaling X, Y, orthogonality, rotation between fields and intra-field systematic errors (intra-field: magnification, anamorph, rotation).

[0055] By comparing the systematic errors of the first side ("A") and the second side ("B"), the differential ("A" - "B") systematic error provides real-time stepper and laser drilling "in-line" monitoring for both systems. If the "A" - "B" systematic error exceeds a user-defined limit, the inspection system or server notifies the user of the deformation and alignment error across all of the patterned vias.

[0056] In one embodiment, the data in the inspection system 800 may then be transmitted to a server for final calculations based on the received measurements, allowing a user to continuously track the layer measurement data. The server may be a computing system such as that described in FIG.

[0057] In another embodiment, inspection system 800 using machine 700 can send the measurement data and resistance calculations to a lithography machine on the production line. The lithography machine uses the received information to calculate the stage and lens adjustments needed to return the overlay to its nominal position. Calculations are performed for both sides of the panel, and the calculated adjustments allow for ideal positioning of the IC substrate panel.

[0058] Furthermore, the RDL structure with trenches patterned in the photoresist can be placed in a plating apparatus within a manufacturing facility. The first and second sides of the panel can be plated simultaneously, with metal being deposited in the trenches. After the metal is deposited, the photoresist is removed. In one embodiment, an inspection system uses a 3D metrology sensor (such as a laser or camera system) to measure the height of the RDL structure. The sensor can be used to measure height across different points on the panel to understand the distribution across the panel. The inspection system can identify deformations to create a more uniform distribution across both sides of the panel. The measurement data can be sent to a server for the creation of a photograph or heat map of both sides of the panel with an indication of where the deformations appear. In addition to being used to create an image or heat map, the height measurement data can be used for other inspection and measurement purposes. The difference between the height measurements on each side of the panel can be recorded and tracked on the inspection system. The inspection system can also send the information to a server for calculations. This information can be used to identify problems with the plating tool setup.

[0059] The inspection system can be used to measure Ajinomoto build-up film (ABF). As mentioned above, a substrate often consists of 24 RDL layers, with 12 layers on each side. Between each RDL layer is an insulating ABF layer. Using a 3D metrology sensor (such as a laser or camera system), the thickness of the ABF layer on both sides of the panel can be measured. The measurement data can be sent to a server to create a heat map that tracks the difference in thickness of the ABF layer on both sides of the panel.

[0060] In another embodiment, after electrochemical deposition (ECD) and stripping of the resist and copper seed, inspection system 800 may inspect the copper-plated RDL layer for deformations or defects. In some embodiments, this deformation inspection may be performed simultaneously on both sides of the substrate. Physical constraints, such as RDL height data, may be collected during simultaneous first-side (“A”) and second-side (“B”) defect inspection by one of several sensors, such as a visible thickness and shape sensor (VTSS) or a 3D metrology sensor. This copper RDL height data from both the first side (“A”) and second side (“B”) of the substrate may be saved in a suitable file format and transmitted to a database on a server. The server may compare the copper-plated RDL heights on the first side (“A”) and second side (“B”), with the difference (“A” minus “B”) represented as a heat map, histogram, or the like. In certain embodiments, this may also be performed on inspection system 800. This data is reported to the ECD engineer and / or Manufacturing Execution System (MES). If the "A" - "B" systematic error exceeds a user-defined limit, the inspection system or server notifies the user of the deformation across each copper-plated RDL layer.

[0061] In yet another embodiment, a sensor is used to measure the RDL structures in height across different points on the panel to understand the distribution across the panel.

[0062] The inspection system or a separate server may create an image or heat map of both sides of the panel with an indication of where the deformations appear. The inspection system or server may identify the deformations to create a more uniform distribution on both sides of the panel. In one embodiment, apart from being used to create an image or heat map, the height measurement data may be used for other inspection and measurement purposes. The difference between the height measurements on each side of the panel may be recorded and tracked.

[0063] In some embodiments, the inspection system can record the focal Z-height of the inspection microscope from the panel during inspection of the substrate. The inspection microscope is perpendicular to the substrate surface. The captured Z-height data for each side of the substrate is saved in a suitable file format. This information can be sent to a separate server, which may include a database. The inspection system can perform a film thickness analysis to identify dZ values ​​for the front ("A") and back ("B") sides of the panel based on the difference from the nominal panel thickness microscope Z-height defined in the first RDL layer inspection. The separate server or inspection system can generate a heat map of values ​​across the substrate, providing the customer with ABF / film thickness variation. This measurement method ensures that panel deformation does not affect the accuracy of the layer thickness measurement.

[0064] The inspection system can further provide data analysis such as film thickness histograms and box plots by layer, substrate, and lot. This can be used to track key parameters for statistical process control (SPC), such as maximum wedge, total indicator runout (TIR), and edge-to-center ABF (film thickness delta), as well as for lithography stepper field size and panel layout evaluation to determine the effective substrate non-planarity per exposure. This data can be used to determine the impact of residual non-planarity on the lithography imaging process window; i.e., the difference between the stepper usable depth of focus (uDOF) and the residual substrate non-planarity (dZ) is equal to the effective process depth of focus (PDOF) per stepper field. Heat maps per exposure field can be used to highlight the impact of residual non-planarity per exposure. Correlation with yield data can provide valuable insight into opportunities for ABF / film buildup and curing process optimization.

[0065] FIG. 9 illustrates the overlay between three layers (L1, L2, and L3). A portion of FIG. 9 shows an optimal interconnect stack with little overlay error between layers. Typically, a small amount of overlay error is tolerated at each layer, but across multiple layers, this tolerable error can add up to an unacceptable total overlay or resistance. The inspection system described herein can detect problems and provide corrective error data to a separate server or other semiconductor manufacturing machines within the fabrication facility. This additional measurement and feedback loop can reduce overlay error on the substrate. Traditionally, as the number of RDL layers increases, users are presented with several limitations, including achieving smaller resolution requirements and minimizing overlay error, the latter being a particular challenge facing the RDL process.

[0066] The number of RDL interconnect layers is typically 5 to 12 per side, connected by plated through holes (PTHs). The resulting RDL stack can contain up to 24 layer-to-layer overlay errors (as already mentioned above). For AICS, overlay requirements exceed challenging layer-to-layer specifications. They are for the entire RDL stack. The total overlay is the sum of the overlay errors of all RDL layers relative to the last layer on both the first and second sides of the IC substrate panel. Cumulative overlay drift from individual RDL buildup layers can significantly increase the overall trace length, resulting in higher interconnect resistance, parasitic effects, and poor performance for high-speed and high-frequency applications. The inspection system described herein aims to address this by monitoring overlay performance data layer by layer and calculating the error through the film stack at each layer. This is critical to avoid RDLs exceeding the package's design resistance specification. The system records measurements for each overlay from the RDL to the vias across the entire substrate and can continuously sum vectors from layer to layer as the process stack increases.

[0067] An inspection system can use this inspection method and data analysis to monitor, track, and compensate for multilayer overlay drift. When the cumulative overlay error exceeds a user-defined threshold, an error signal is generated. The required overlay correction offset is calculated and sent to the lithography system at the manufacturing facility. Without the ability to monitor the total overlay error across the entire panel and layer by layer, there is no way to know if the RDL resistance meets specifications until final electronic test, which is achieved by current inspection systems and methods for testing integrated circuits.

[0068] Each of the above non-limiting aspects can stand on its own or can be combined in various permutations or combinations with one or more of the other aspects or other subject matter described in this document.

[0069] The above detailed description includes references to the accompanying drawings, which form a part of the detailed description. The drawings show, by way of illustration, specific implementations in which the invention may be practiced. These implementations are also generally referred to as "examples." Such examples may include elements in addition to those shown or described. However, the inventors also contemplate examples in which only the elements shown or described are provided. Furthermore, the inventors also contemplate examples that use any combination or permutation of the elements shown or described (or one or more aspects thereof), either with respect to the particular example (or one or more aspects thereof) or with respect to any other example (or one or more aspects thereof) shown or described herein.

[0070] In the event of a conflicting usage between this document and any document incorporated by reference, the usage in this document shall prevail.

[0071] As used herein, the terms "a" or "an" are used as is common in patent documents to include one or more than one, independent of any other instance or use of "at least one" or "one or more." As used herein, the term "or" is used to refer to a non-exclusive "or," such that "A or B" includes "A but not B," "B but not A," and "A and B," unless otherwise indicated. As used herein, the terms "including" and "in which" are used as the plain English equivalents of the respective terms "comprising" and "wherein." Also, in the following aspects, the terms "including" and "comprising" are open-ended, i.e., systems, devices, articles, compositions, formulations, or processes that include elements in addition to the elements listed after such terms in an aspect are still considered to be within the scope of that aspect. Furthermore, in the following embodiments, terms such as "first," "second," and "third" are used merely as labels and are not intended to impose numerical requirements on those objects.

[0072] The method examples described herein may be at least partially machine- or computer-implemented. Some examples may include a computer-readable or machine-readable medium encoded with instructions operable to configure an electronic device to perform the method described in the examples. Implementations of such methods may include code, such as microcode, assembly language code, higher-level language code, etc. Such code may include computer-readable instructions for implementing various methods. The code may form part of a computer program product. Further, in one example, the code may be tangibly stored on one or more volatile, non-transitory, or non-volatile tangible computer-readable media, such as during execution or at other times. Examples of these tangible computer-readable media may include, but are not limited to, hard disks, removable magnetic disks, removable optical disks (e.g., compact disks and digital video disks), magnetic cassettes, memory cards or sticks, random access memory (RAM), read-only memory (ROM), etc.

[0073] The above description is intended to be illustrative, not limiting. For example, the above examples (or one or more aspects thereof) may be used in combination with each other. Other implementations may be used, for example, by one of ordinary skill in the art, upon reviewing the above description. The Abstract is provided to enable the reader to quickly ascertain the nature of the present technical disclosure. The Abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the aspects. Also, in the above Detailed Description, various features may be grouped together to streamline the disclosure. This should not be interpreted as intending that an unclaimed disclosed feature is essential to any claim. Rather, inventive subject matter may reside in fewer than all features of a particular disclosed implementation. Thus, the following aspects are incorporated into the Detailed Description as examples or implementations, and it is contemplated that each aspect stands on its own as a separate implementation, and that such implementations can be combined with each other in various combinations or permutations.

Claims

1. 1. A method for testing an integrated circuit (IC) substrate, the method comprising: receiving an IC substrate before etching a copper seed layer on a first layer on a first side of the IC substrate and on a second layer on a second side of the IC substrate; holding the IC substrate using a retention mechanism, the retention mechanism contacting the IC substrate over one or more defined keep-out zones (KOZ); and simultaneously inspecting the first and second sides of the substrate using a first sensor for the first side and a second sensor for the second side.

2. The method of claim 1 , including inspecting vias after laser drilling them on the first layer and on the second layer.

3. The method of claim 1 , wherein the inspecting is further performed after dry film lithography on the first layer and on the second layer.

4. 2. The method of claim 1, wherein the first sensor and the second sensor are positioned on opposite sides of the IC substrate that is held vertically, with the first sensor facing the first side and the second sensor facing the second side.

5. The method of claim 1 , further comprising measuring the resistance of a structure on the substrate.

6. The method of claim 1 , further comprising measuring x-axis and y-axis positions of features on the substrate.

7. The method of claim 1 , further comprising measuring a thickness of a film on the substrate.

8. The method of claim 1 , wherein the IC substrate moves during the testing while the first sensor and the second sensor remain substantially in place.

9. The method of claim 1 , wherein the one or more KOZs are provided on an edge of the IC substrate and are devoid of active IC structures.

10. The method of claim 1 , wherein the retention mechanism includes a plurality of suction cups and clamps.

11. The method of claim 1 , wherein the holding mechanism uses a vacuum mechanism to hold the IC substrate via a plurality of suction cups.

12. 1. An inspection system for double-sided inspection of integrated circuit (IC) substrates, the inspection system comprising: a retention mechanism for retaining the IC substrate before a copper seed layer is etched on a first layer on a first side of the IC substrate and on a second layer on a second side of the IC substrate, the retention mechanism contacting the IC substrate over at least one keep-out zone (KOZ); a first sensor for inspecting the first layer on the first side of the IC substrate; and a second sensor for inspecting the second layer on the second side of the IC substrate.

13. 13. The inspection system of claim 12, wherein the first sensor and the second sensor are configured to be positioned on opposite sides of the IC substrate, with the first sensor facing the first side and the second sensor facing the second side.

14. 13. The inspection system of claim 12, wherein the first sensor is configured to inspect the first layer after laser drilling vias on the first layer, and the second sensor is configured to inspect the second layer after laser drilling vias on the second layer.

15. 13. The inspection system of claim 12, wherein the first sensor is configured to inspect the first layer after dry film lithography on the first layer, and the second sensor is configured to inspect the second layer after dry film lithography on the second layer.

16. 1. An inspection system for double-sided inspection, the inspection system comprising: means for holding the IC substrate before the copper seed layer is etched on a first layer on a first side of the IC substrate and on a second layer on a second side of the IC substrate; and means for inspecting the first layer and the second layer substantially simultaneously.

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