Suppression of High-Frequency Emissions in 10BASE-T1S Drivers by Using Multistage Notch / Band-Reject Filtering

Abstract

A method and system for reducing radiation at predetermined frequencies using delay elements and related devices is disclosed. The device includes an input terminal (102) for receiving a signal (104), a delay element (108) electrically connected to the input terminal, an output terminal (112) for providing a slew rate reduced signal (114), and a combining circuit (116) electrically connected to the delay element and the output terminal. The delay elements provide delayed signals (110) responsive to the received signal. Each of the delayed signals includes a delayed version of the received signal. The combining circuit combines the delayed signals to generate the slew rate reduced signal. The delays associated with the delay elements are selected to reduce radiation at one or more predetermined frequencies of the slew rate reduced signal compared to the received signal.

Description

[Technical Field]

[0001] (Priority Claim) This application claims the benefit of the filing date of Chinese Patent Application No. 202211564056.0, filed December 7, 2022, entitled "COMPRESSING HIGH FREQUENCY EMISSIONS IN 10BASE-T1S DRIVER BY USING MULTIPLE STAGE NOTCH / BAND STOP FILTERING," the disclosure of which is incorporated herein by reference in its entirety.

[0002] FIELD OF THE INVENTION The present disclosure relates generally to reducing emissions of one or more predetermined frequencies of a signal having a reduced slew rate compared to a received signal, and more particularly to reducing the predetermined frequency emissions using delay elements. [Background technology]

[0003] Some applications of wired local area networks (e.g., Ethernet) may have relatively stringent emissions limits across various frequencies, for example, vehicular wired local area networks may impose relatively stringent emissions limits in the Frequency Modulated (FM) broadcast band and Digital Audio Broadcasting (DAB) frequencies.

[0004] Communication technology continues to proliferate worldwide. The proliferation of communication devices increases the risk of interference between devices. As long as devices utilize the same or similar communication frequencies, interference can cause communication problems. Even harmonics outside a device's designated communication frequency range can interfere with other devices communicating in different frequency ranges. [Brief explanation of the drawings]

[0005] While the present disclosure concludes with claims that particularly point out and distinctly claim certain embodiments, the various features and advantages of embodiments within the scope of the present disclosure may be more readily ascertained from the following description when read in conjunction with the accompanying drawings. [Figure 1] 1 is a block diagram of a variable delay driver, according to various examples. [Figure 2] 2 is a schematic diagram of a variable delay driver that is an example of the variable delay driver of FIG. 1; [Figure 3] 3 is a schematic diagram of an example of a sub-driver of the variable delay driver of FIG. 1 or the variable delay driver of FIG. 2; [Figure 4] 1. FIG. 3 is a schematic diagram of another example of a sub-driver of the variable delay driver of FIG. 1 or the variable delay driver of FIG. [Figure 5] 1 is a flowchart illustrating a method for generating a signal with a reduced slew rate, in accordance with various examples. [Figure 6] 10 is a flowchart illustrating a delayed selection method, according to various examples. [Figure 7] FIG. 1 is a block diagram of a filter comprising a series combination of three virtual first-order notch filters. [Figure 8] FIG. 8 is a block diagram of a filter that is equivalent to the filter of FIG. 7. [Figure 9] 9 is a response plot of an example of the frequency response in decibels (dB) of the filter of FIG. 7 and the filter of FIG. 8. [Figure 10] 9 is a response plot of another example of the frequency response in dB of the filter of FIG. 7 and the filter of FIG. 8; [Figure 11] 1 is a block diagram of a wired local area network, in accordance with various examples. [Figure 12] 12 is a schematic diagram of a physical layer circuit, which is an example of a PHY circuit of the wired local area network of FIG. 11. [Figure 13] FIG. 1 is a block diagram of a system, according to various examples. DETAILED DESCRIPTION OF THE INVENTION

[0006] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof and which show illustrative examples in which the present disclosure may be practiced. These examples are described in sufficient detail to enable those skilled in the art to practice the present disclosure. However, other examples may be utilized, and changes in structure, materials, and processes may be made, as enabled herein, without departing from the scope of the present disclosure.

[0007] The figures presented herein are not meant to be actual illustrations of any particular method, system, device, or structure, but are merely idealized representations used to explain embodiments of the present disclosure. In some cases, similar structures or components in various figures may retain the same or similar numbering for the convenience of the reader; however, similarity in numbering does not necessarily mean that the structures or components are identical in size, composition, configuration, or any other characteristic.

[0008] The following description may include examples to assist those skilled in the art in practicing the disclosed embodiments. The use of the terms "exemplary," "example," and "for example" means that the associated description is explanatory and that the scope of the present disclosure is intended to encompass examples and legal equivalents, but the use of such terms is not intended to limit the scope of the disclosed embodiments to the specified components, steps, features, functions, etc.

[0009] It will be readily understood that the components of the embodiments, as generally described and illustrated in the figures herein, could be arranged and designed in a wide variety of different configurations. Thus, the following description of various embodiments is not intended to limit the scope of the disclosure, but is merely representative of various embodiments. While various aspects of the embodiments may be presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

[0010] Furthermore, the specific implementations shown and described are merely examples and should not be construed as the only way to implement the present disclosure, unless otherwise specified herein. Elements, circuits, and functions may be shown in block diagram form so as not to obscure the present disclosure in unnecessary detail. Conversely, the specific implementations shown and described are merely exemplary and should not be construed as the only way to implement the present disclosure, unless otherwise specified herein. Additionally, the block definitions and partitioning of logic among various blocks are illustrative of specific implementations. It will be readily apparent to one skilled in the art that the present disclosure can be implemented with numerous other partitioning solutions. For the most part, details regarding timing considerations and the like have been omitted; such details are not necessary to obtain a complete understanding of the present disclosure and are within the capabilities of those skilled in the art.

[0011] Those skilled in the art will understand that information and signals may be represented using any of a variety of different technologies and techniques. Some figures may depict a signal as a single signal for clarity of presentation and explanation. Those skilled in the art will understand that a signal may represent a bus of signals, which may have various bit widths, and that the present disclosure may be implemented with any number of data signals, including a single data signal.

[0012] The various illustrative logic blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed using a general-purpose processor, a special-purpose processor, a digital signal processor (DSP), an integrated circuit (IC), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor (which may also be referred to herein as a host processor or simply a host) may be a microprocessor, although the processor may alternatively be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. Although a general-purpose computer including a processor is considered a special-purpose computer, the general-purpose computer is for executing computing instructions (e.g., software code) associated with the embodiments of the present disclosure.

[0013] The embodiments may be described in terms of a process that is depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. While a flowchart may describe operational acts as a sequential process, many of these acts may occur in another sequence, in parallel, or substantially simultaneously. Additionally, the order of acts may be rearranged. A process may correspond to a method, a thread, a function, a procedure, a subroutine, a subprogram, other structure, or combinations thereof. Furthermore, methods disclosed herein may be implemented in hardware, software, or both. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media, including any medium that facilitates transfer of a computer program from one place to another.

[0014] Any reference to elements herein using designations such as "first," "second," etc. does not limit the quantity or order of those elements unless such limitation is expressly stated. Rather, these designations may be used herein as a convenient method of distinguishing between two or more elements or instances of an element. Thus, reference to a first element and a second element does not imply that only two elements may be used or that the first element must precede the second element in any manner. Additionally, unless otherwise specified, a set of elements may include one or more elements.

[0015] As used herein, the term "substantially" when referring to a given parameter, characteristic, or condition means and includes the extent to which one of ordinary skill in the art would understand that the given parameter, characteristic, or condition is met with slight variations, such as, for example, within acceptable manufacturing tolerances. As an example, depending on the particular parameter, characteristic, or condition that is substantially met, the parameter, characteristic, or condition may be at least 90% met, at least 95% met, or even at least 99% met.

[0016] Interference between devices, devices, and transmission lines, or between transmission lines and devices during electrical communications (e.g., wireless or wired communications) can cause failures or malfunctions in various communication environments. One example of a communication environment in which interference can pose challenges is in a vehicle. As used herein, the term “vehicle” refers to an automobile, truck, bus, ship, or aircraft. “Vehicle” can include a vehicle communication network. The complexity of a vehicle communication network can vary depending on the number of electronic devices in the network and other sources of electromagnetic radiation (e.g., but not limited to, amplitude modulated (AM) and frequency modulated (FM) radio, digital audio broadcasting (DAB), and cellular phone devices). For example, an advanced vehicle communication network can include various control modules for engine control, transmission control, safety control (e.g., anti-lock braking), and emission control. To support these modules, the automotive industry relies on various communication protocols.

[0017] One example of a protocol regulating single-pair Ethernet communication in vehicles is 10BASE-T1S or its equivalent, 10SPE, a network technology specified by IEEE 802.3cg™. Devices operating according to the 10BASE-T1S protocol must also comply with stringent radio frequency emissions tests for automotive electronic devices. Passing these stringent radio frequency emissions tests can be difficult if the frequencies of harmonic lobes for emissions from electronic devices used in vehicle networks fall within some of the most stringent frequency ranges tested in these tests. As a non-limiting example, some of the most stringent requirements of these tests may fall within the bandwidths specified for frequency modulation (FM) radio (essentially 87-108 megahertz (MHz)) and digital audio broadcasting (DAB) (essentially 1100 MHz). Rise and fall shaping (e.g., cosine rise and fall shaping) can cause radiation lobes at FM and DAB frequencies when the limits are particularly tight, which can cause problems for automotive use.

[0018] According to various examples, emissions in network communications (e.g., in the FM and DAB frequency ranges) can be compressed using a multi-pole stage driver implemented as a notch filter or band-stop filter. Driver emissions in the FM and DAB bands can be reduced by shaping the rise and fall of the signal level. Because emissions at specific frequencies or frequency ranges are reduced, this rise and fall shaping according to various examples may also be referred to herein as a “notch filter.” High-frequency emissions spectra (e.g., but not limited to, within the FM band, DAB band) with notch / band-stop filtering can be reduced to meet stringent emissions requirements for automotive products. In some examples, multi-stage driver cells can be designed with specified delays to shape the output waveform for low emissions. The terms “frequency range,” “band,” “frequency band,” and “broadcast band” are used interchangeably herein to refer to frequency ranges.

[0019] 1 is a block diagram of a variable delay driver 100 according to various examples. The variable delay driver 100 includes an input terminal 102, a plurality of delay elements 108, an output terminal 112, and a combinational circuit 116. The input terminal 102 receives a signal 104. The delay elements 108 (for example, but not limited to, arranged in a delay network) are electrically connected to the input terminal 102. The delay elements 108 provide each of a plurality of delayed signals 110 responsive to the received signal 104. Each of the delayed signals 110 includes a different delayed version of the received signal 104. The output terminal 112 provides a slew-rate reduced signal 114. The combinational circuit 116 is electrically connected to the delay elements 108 and the output terminal 112. The combinational circuit 116 combines the delayed signals 110 to generate the slew-rate reduced signal 114. The delay associated with delay element 108 is selected to reduce emissions of one or more predetermined frequencies of slew rate reduced signal 114 compared to received signal 104 .

[0020] The combinational circuit 116 includes a plurality of sub-drivers 118. The sub-drivers 118 are “sub-drivers” in the sense that the variable delay driver 100 is a driver and the sub-drivers 118 are sub-drivers for the variable delay driver 100. At least some of the sub-drivers 118 are electrically connected from each of the delay elements 108 to the output terminals 112 to drive each of the delayed signals 110 to the output terminals 112. In some examples, one of the sub-drivers 118 is electrically connected from the input terminal 102 to the output terminal 112 (not shown).

[0021] In some examples, the variable delay driver 100 includes a delay control circuit 120 electrically connected to the delay elements 108. The delay control circuit 120 provides a plurality of delay control signals 122 to the delay elements 108 to control the delay associated with the delay elements 108. Thus, in such examples, the delay elements 108 may have an electrically controllable delay associated therewith, and the electrically controllable delay of each delay element 108 is controlled in response to the delay control signal 122.

[0022] As mentioned above, emissions in network communications (e.g., in the FM and DAB frequency ranges) can be compressed using multi-pole stage drivers implemented as notch filters or band-stop filters. The sub-driver 118 can be these multi-pole stage drivers, in combination with the delay element 108, to implement a notch filter or band-stop filter. The delay associated with the delay element 108 is selected to reduce emissions at one or more predetermined frequencies of the slew-rate reduced signal 114 compared to the received signal 104. Thus, a "notch filter" is implemented because emissions at a particular frequency or frequency range are reduced. In some examples, the one or more predetermined frequencies include three predetermined frequencies. In such examples, the delay control circuit 120 can determine three different preliminary delays associated with the three predetermined frequencies for the three virtual first-order notch filters. The delay control circuit 120 can also determine eight intermediate total delays associated with concatenating the three virtual first-order notch filters together. The delay control circuit 120 may sort the eight intermediate total delays in ascending order and, for each of the eight intermediate total delays except for the lowest intermediate delay, determine seven differential delays by subtracting the intermediate total delay from the delay immediately following the intermediate total delay. The delay control circuit 120 may select a delay associated with a delay element to result in each differential delay.

[0023] 2 is a schematic diagram of a variable delay driver 200, which is an example of the variable delay driver 100 of FIG. 1. The variable delay driver 200 includes a plurality of sub-drivers 218 operably coupled in parallel between an input terminal 202 and an output terminal 212. The variable delay driver 200 also includes one or more delay elements 208 coupled between the input terminal 202 and one or more of the sub-drivers 218 to deliver a delayed version of a signal 204, shown as delayed signal 210, received at the input terminal 202 to at least two of the sub-drivers 218 at different times to control the slew rate of a slew rate reduced signal 214 at the output terminal 212. The delay elements 208 are electrically connected in series from the input terminal 202 to the last one of the delay elements 208.

[0024] The sub-drivers 218 are "sub-drivers" for the variable delay driver 200 in that the variable delay driver 200 is a driver and the sub-drivers 218 are sub-drivers for the variable delay driver 200. Each of the sub-drivers 218 and the corresponding delay elements 208 may be referred to as a "stage," where applicable (for example, without limitation, the first one of the sub-drivers 218 may not have a corresponding one of the delay elements 208 and may be electrically connected from the input terminal 202 to the output terminal 212). Thus, at least some of the sub-drivers 218 are connected between at least some of the delay elements 208 and the output terminal 212. Each stage has a specified delay associated with it. The outputs of each of the stages may be summed together by a summing circuit 224 to produce the slew rate reduced signal 214. The combined output may have a desired spectrum with low emissions in a specified frequency band.

[0025] In the example shown in FIG. 2 , each of the delay elements 208 causes each of the sub-drivers 218 to receive the assertion of signal 204 (e.g., without limitation, a transition from one logic voltage level to another) at a different time. As a result, at output terminal 212, each of the sub-drivers 218 begins driving a new received bit at a staggered time relative to the other. This staggered drive of the slew-rate reduced signal 214 results in a reduced slew rate compared to the slew rate that would result from not staggering the drive. The reduced slew rate reduces higher frequency components of the slew-rate reduced signal 214, which tend to result in EMI emissions, compared to signal 204. As a result, variable delay driver 200 results in less EMI emissions compared to a driver that does not use staggered drive. The use of stages such as variable delay driver 200 of FIG. 3 can also enable control of different delays and different current levels.

[0026] In some examples, the variable delay driver 200 includes a delay control circuit 220 electrically connected to the delay elements 208. The delay control circuit 220 provides delay control signals 222 to the delay elements 208 to control the respective delays associated with the respective delay elements 208. Thus, in such examples, the delay elements 208 may have an electrically controllable delay associated therewith, and the electrically controllable delay of each delay element 208 is controlled in response to the delay control signal 222.

[0027] FIG. 3 is a schematic diagram of a sub-driver 300, which may be an example of the sub-driver 118 of the variable delay driver 100 of FIG. 1 or the sub-driver 218 of the variable delay driver 200 of FIG. 2. As can be seen in FIG. 3, the current of the sub-driver 300 is switched by differential data appearing at input terminals DN and DP. The sub-driver 300 protects data and withstands high common-mode surges on a communication bus (e.g., but not limited to, the communication bus 1108 of FIG. 11, the communication bus 1220 of FIG. 12, or the shared transmission medium 1306 of FIG. 13). The sub-driver 300 includes a high-speed input stage 302 and a high-voltage intermediate stage 304. The high-speed input stage 302 includes a plurality of data switches, each including a high-speed transistor 306. The high-voltage intermediate stage 304 includes a plurality of high-voltage transistors 308 cascaded with the high-speed transistors 306, and a plurality of protection diodes 310 cascaded with the high-voltage transistors 308. As a result, the high-speed input stage 302 and the differential data appearing at the input terminals DN, DP are protected (e.g., the high-speed input stage 302 is protected from high common-mode surges, and the differential data is protected from corruption due to failure of the high-speed input stage 302), and the sub-driver 300 can withstand high common-mode surges on the communication bus. In some examples, the amplitude and slew rate of the output signal between the output terminals TXP, TXN are controlled by a digital-to-analog converter (DAC).

[0028] The sub-driver 300 may also include circuit components 312 including a plurality of capacitors CC (e.g., 100 nF capacitors) and a plurality of resistors RR (e.g., 25 Ω resistors) in series between the capacitors CC. As a non-limiting example, the circuit components 312 may be off-chip circuit components (e.g., separate capacitors and resistors soldered to a printed circuit board). During operation, the current I Smay pass through capacitor CC and resistor RR. In some examples, the terminal between resistor RR may be grounded (zero volts). As a result, the peak-to-peak voltage between output terminals TXP, TXN of sub-driver 300 (e.g., measured across resistor RR of circuit component 312) is Vtx(pk)=I S ×(50Ω), where RR is 25Ω. In some examples, I S can vary from 2.5 milliAmp (mA) to 15 mA. As a non-limiting example, I S is 10 mA, Vtx(pk) may be about 1 volt peak-to-peak (when the terminal across resistor RR is grounded).

[0029] Vtx(pk) is the current I S Since the amplitude of the output of the sub-driver 300 is a function of I S As a result, the sub-driver 300 can be controlled when the current I S , and one or more variable current sources 314, 316 for controlling the Vtx(pk) between the output terminals TXP and TXN. As a non-limiting example, the variable current source 314 may include an NMOS variable current source, and the variable current source 316 may include a PMOS variable current source. In some examples, the variable current sources 314, 316 may be controlled by register controllers 320, 318, respectively. The register controllers 320, 318 may output voltage signals 328, 326, respectively, corresponding to a desired voltage amplitude value of Vtx(pk) between the output terminals TXP and TXN. In one example (not shown), the output voltage signals 328, 326 may be provided to the variable current sources 314, 316, respectively, to control the variable current sources 314, 316. The variable current sources 314, 316 may generate an appropriate current I Sto achieve a desired voltage swing Vtx(pk) at the output terminals TXP, TXN. In examples where the variable current sources 314, 316 are each controlled by an analog input and the register controllers 320, 318 provide digital voltage signals 328, 326, respectively, the sub-driver 300 may include one or more digital-to-analog converters (DACs) 324, 322. The DACs 324, 322 convert the respective voltage signals 328, 326 to respective analog voltage signals 332, 330 that are provided to the variable current sources 314, 316, respectively. As a non-limiting example, the register controllers 320, 318 may control the variable current sources 314, 316 with 3-bit voltage signals 328, 326 corresponding to up to eight different voltage swing levels of Vtx(pk). In one specific, non-limiting example, the voltage signals 328, 326 may selectively indicate 250 mV, 500 mV, 750 mV, 1 V, 1.25 V, or 1.5 V.

[0030] 4 is a schematic diagram of another example of a sub-driver 400 of the variable delay driver 100 of FIG. 1 or the variable delay driver 200 of FIG. 2. The sub-driver 400 includes a pull-up current source 402 electrically connected to a power supply high voltage potential node 406 (e.g., but not limited to, a VDD node). The sub-driver 400 also includes a pull-down current source 404 electrically connected to a power supply low voltage potential node 408 (e.g., a VSS node). The sub-driver 400 includes a complementary-metal oxide semiconductor (CMOS) inverter (CMOS inverter 410) electrically connected from the pull-up current source 402 to the pull-down current source 404. The pull-up current I P is supplied by the pull-up current source 402 and the pull-down current I N is essentially the same as

[0031] CMOS inverter 410 includes a pull-up transistor QP and a pull-down transistor QN. A first terminal of pull-up transistor QP is electrically connected to the positive lead of pull-up current source 402. A second terminal of pull-up transistor QP is electrically connected to the second terminal of pull-down transistor QN. A first terminal of pull-down transistor QN is electrically connected to the negative lead of pull-down current source 404. Gate terminals of pull-up transistor QP and pull-down transistor QN are electrically connected to an input node IN of CMOS inverter 410. Second terminals of pull-up transistor QP and pull-down transistor QN are electrically connected to an output node from CMOS inverter 410.

[0032] FIG. 5 is a flowchart illustrating a method 500 for generating a slew rate reduced signal (e.g., but not limited to, slew rate reduced signal 114 of FIG. 1 or slew rate reduced signal 214 of FIG. 2 ) according to various examples. At operation 502, method 500 includes delaying a received signal (e.g., but not limited to, signal 104 of FIG. 1 or signal 204 of FIG. 2 ) to generate a delayed signal (e.g., but not limited to, delayed signal 110 of FIG. 1 or delayed signal 210 of FIG. 2 ) using a delay selected to reduce emissions of one or more predetermined frequencies of the slew rate reduced signal compared to the received signal. In some examples, delaying the received signal includes selecting a delay using control circuitry electrically connected to a delay element associated with the delay in a delay selection method 600. Further details regarding delay selection method 600 are discussed below with reference to FIG. 6 .

[0033] At operation 504, method 500 includes combining the delayed signals to generate a signal at an output terminal (e.g., but not limited to, output terminal 112 of FIG. 1 or output terminal 212 of FIG. 2) with a reduced slew rate. In some examples, combining the delayed signals includes driving the delayed signals at operation 506 by a sub-driver (e.g., but not limited to, sub-driver 118 of FIG. 1 or sub-driver 218 of FIG. 2) to a summing circuit (e.g., but not limited to, summing circuit 124 of FIG. 1 or summing circuit 224 of FIG. 2) electrically connected to the output terminal.

[0034] 6 is a flowchart illustrating a delay selection method 600, according to various examples. The delay selection method 600 is specifically designed to select a delay for a variable delay driver that includes eight sub-drivers and seven delay elements. It should be appreciated that different delay selection methods can be used with variable delay drivers that include different numbers of sub-drivers and delay elements.

[0035] In operation 602, the delay selection method 600 includes determining three different preliminary delays associated with three predetermined frequencies of three virtual first-order notch filters (702, 704, and 706 in FIG. 7). A variable delay driver including eight sub-drivers and seven delay elements can be modeled as a series combination of three first-order notch filters, each with a preliminary delay D1, D2, and D3 associated with the first-order notch filter, respectively. Further details regarding the series combination of first-order notch filters are discussed with reference to FIG. 7.

[0036] 7 is a block diagram of a filter 700 that includes a series combination of three virtual first-order notch filters 702, 704, and 706. The preliminary delay associated with virtual first-order notch filter 702 is D1, the preliminary delay associated with virtual first-order notch filter 704 is D2, and the preliminary delay associated with virtual first-order notch filter 706 is D3.

[0037] Each preliminary delay D1, D2, D3 may be determined as a function of the desired notch frequency of the variable delay driver. For example, each preliminary delay D1, D2, D3 may be determined by dividing 1 / 2 by the desired notch frequency of the variable delay driver. Thus, in some examples, the preliminary delays D1, D2, D3 may be determined as follows:

[0038]

number

[0039]

number

[0040] 6, at operation 604, the delay selection method 600 includes determining eight intermediate total delays associated with concatenating together the three virtual first-order notch filters 702, 704, and 706 (FIG. 7). The eight intermediate total delays may be determined by multiplying the expressions in parentheses in the above equation for Dout, which gives the following:

[0041]

number

[0042] At operation 606, the delay selection method 600 includes sorting the eight intermediate total delays in ascending order. For example, the eight intermediate total delays [0, D1, D2, D3, D1+D2, D2+D3, D1+D3, D1+D2+D3] may be sorted in ascending order as [0, S1, S2, S3, S4, S5, S6, S7], where S1, S2, S3, S4, S5, S6, and S7 are D1, D2, D3, D1+D2, D2+D3, D1+D3, and D1+D2+D3 ordered in ascending order. For example, S1 is the smallest of D1, D2, D3, D1+D2, D2+D3, D1+D3, and D1+D2+D3. S2 is the second smallest among D1, D2, D3, D1+D2, D2+D3, D1+D3, and D1+D2+D3, and S7 is the largest among D1, D2, D3, D1+D2, D2+D3, D1+D3, and D1+D2+D3.

[0043] In operation 608, the delay selection method 600 includes, for each of the eight intermediate total delays excluding the lowest intermediate delay, determining seven differential delays by subtracting the intermediate total delay from the delay immediately following the intermediate total delay. These seven differential delays [Delay 1, Delay 2, Delay 3, Delay 4, Delay 5, Delay 6, Delay 7] may be determined as follows:

[0044]

number

[0045] At operation 610, the delay selection method 600 includes selecting a delay associated with a delay element (e.g., without limitation, delay element 108 of FIG. 1 , delay element 208 of FIG. 2 ) to result in a differential delay [delay 1, delay 2, delay 3, delay 4, delay 5, delay 6, delay 7]. As discussed with respect to the delay selection method 600 of FIG. 5 , selecting a delay associated with a delay element (operation 610) to result in a differential delay may include selecting the delay using a delay control circuit electrically connected to the delay element associated with the delay.

[0046] Figure 8 is a block diagram of a filter 800 that is equivalent to filter 700 of Figure 7. Filter 800 includes delay elements 802, 804, 806, 808, 810, 812, and 814. The delay associated with delay element 802 is selected as differential delay Delay 1. The delay associated with delay element 804 is selected as differential delay Delay 2. The delay associated with delay element 806 is selected as differential delay Delay 3. The delay associated with delay element 808 is selected as differential delay Delay 4. The delay associated with delay element 810 is selected as differential delay Delay 5. The delay associated with delay element 812 is selected as differential delay Delay 6. Finally, the delay associated with delay element 814 is selected as differential delay Delay 7.

[0047] Figure 9 is a response plot 900 of an example frequency response 902 (in decibels (dB)) of filter 700 of Figure 7 and filter 800 of Figure 8. In the example shown in Figure 9, the desired notch frequencies were 50 MHz, 72 MHz, and 100 MHz, corresponding to preliminary delays of D1 = 10 ns, D2 = 7 ns, and D3 = 5 ns. The corresponding intermediate total delays sorted in ascending order are [0, 5, 7, 10, 12, 15, 17, and 22], which correspond to differential delays of [5, 2, 3, 2, 3, 2, 5]. Thus, the frequency response 902 shown in response plot 900 of Figure 9 is the result of using [5, 2, 3, 2, 3, 2, 5] for delay 1, delay 2, delay 3, delay 4, delay 5, delay 6, and delay 7 for delay elements 802, 804, 806, 808, 810, 812, and 814, respectively, of filter 800 of Figure 8. As can be seen in response plot 900, the notches are located at approximately 50 MHz, 72 MHz, and 100 MHz. Thus, a variable delay driver implemented similarly to filter 800 (such as, but not limited to, variable delay driver 100 of Figure 1 or variable delay driver 200 of Figure 2) in which the delays discussed above are used for the delay elements will filter emissions at 50 MHz, 72 MHz, and 100 MHz.

[0048] Figure 10 is a response plot 1000 of another example frequency response 1002 (in decibels (dB)) of filter 700 of Figure 7 and filter 800 of Figure 8. In the example shown in Figure 10, the desired notch frequencies were 50 MHz, 100 MHz, and 200 MHz, corresponding to preliminary delays of D1 = 10 ns, D2 = 5 ns, and D3 = 2.5 ns. The corresponding median total delays sorted in ascending order are [2.5, 5, 7.5, 10, 12.5, 15, 17.5, 20], which correspond to differential delays of [2.5, 2.5, 2.5, 2.5, 2.5, 2, 5]. Thus, the frequency response 1002 shown in response plot 1000 of FIG. 10 is the result of using [2.5, 2.5, 2.5, 2.5, 2.5, 2.5, 2, 5] for delay 1, delay 2, delay 3, delay 4, delay 5, delay 6, and delay 7 for delay elements 802, 804, 806, 808, 810, 812, and 814, respectively, of filter 800 of FIG. 8. As can be seen in response plot 1000, the notches are located at approximately 50 MHz, 100 MHz, and 200 MHz. Thus, a variable delay driver implemented similarly to filter 800 (such as, but not limited to, variable delay driver 100 of FIG. 1 or variable delay driver 200 of FIG. 2 ) in which the delays discussed above are used for the delay elements will filter emissions at 50 MHz, 100 MHz, and 200 MHz.

[0049] 11 is a block diagram of a portion of a wired local area network 1100 according to various examples. The wired local area network 1100 includes an endpoint 1104 operably coupled to a communication bus 1108. The communication bus 1108 includes a shared transmission medium (e.g., without limitation, a single twisted pair) of the wired local area network 1100. As used herein, the term "shared transmission medium" refers to a wired transmission medium, such as a single twisted pair, that conducts both transmit and receive signals over the same conductive structure (e.g., without limitation, a wire) for multiple endpoints similar to endpoint 1104. As a non-limiting example, all endpoints in the wired local area network 1100 may transmit and receive signals over the same shared transmission line (e.g., without limitation, a single twisted pair). The endpoint 1104 is for communication over the communication bus 1108. The endpoint 1104 functions as a node of the wired local area network 1100 while electrically connected to the communication bus 1108.

[0050] Endpoint 1104 includes physical layer circuitry 1102 (PHY circuitry 1102) operably coupled to media access control (MAC) circuitry 1106 and a communication bus 1108. PHY circuitry 1102 serves as an interface for the physical connection between MAC circuitry 1106 and communication bus 1108. In some examples, PHY circuitry 1102 includes at least a portion of Ethernet physical layer circuitry.

[0051] Wired local area network 1100 may be used in some examples in an automotive environment, as shown in Figure 13. As one non-limiting example, wired local area network 1100 may be for connecting one or more sensors in a vehicle to a computer or controller via a shared transmission medium, such as a communications bus 1108. The one or more sensors, and the computer and controller may each operate as endpoints within wired local area network 1100, such as endpoint 1104 of Figure 11.

[0052] Figure 12 is a schematic diagram of a physical layer circuit 1200, which is an example of the PHY circuit 1102 of the wired local area network 1100 of Figure 11. The PHY circuit 1200 includes a transmitter circuit including a Manchester encoder 1202, the variable delay driver 100 of Figure 1, and an interference / noise compensation circuit including a capacitor 1216 (e.g., a 100 nanoFarad (nF) capacitor) and a common mode choke 1204. The PHY circuit 1102 includes a receiver circuit 1218 including a detection circuit 1212, an interference / noise compensation circuit including a plurality of receive amplifiers 1206, 1208, 1210, and a common mode dimmer 1222, and a plurality of resistors 1214 (e.g., 10 kiloOhm (kΩ) resistors). The transmitter circuitry and the receiver circuitry 1218 are both connected to the same communication bus 1220. As a result, the communication bus 1220 can be used for both transmitting and receiving data. In some examples, the communication bus 1220 can be the shared transmission medium (e.g., without limitation, a single twisted pair (e.g., without limitation, an unshielded twisted pair, or UTP)) of a wired local area network such as the wired local area network 1100 of FIG. 11.

[0053] Variable delay driver 100 drives the signal provided to variable delay driver 100 by Manchester encoder 1202 to differential outputs TXP, TXN of variable delay driver 100. Variable delay driver 100 also controls the slew rate and amplitude (e.g., without limitation, different output swing levels) of the driver output of variable delay driver 100. Variable delay driver 100 also tolerates high interference (e.g., without limitation, common-mode interference of ±40 volts or more) and noise received at the driver output of variable delay driver 100 through communication bus 1220. Variable delay driver 100 also protects itself from high input voltages at the driver input of variable delay driver 100. In addition, variable delay driver 100 can filter EMI of predetermined frequencies (e.g., without limitation, frequencies associated with FM radio and DAB) using method 500 of FIG. 5 .

[0054] Because standards for EMI emissions in automobiles are relatively stringent, the slew rate of the driver output of variable delay driver 100 can be decreased to reduce the high-frequency content of the drive transmission signal provided at the driver output of variable delay driver 100. Reducing the high-frequency content of the drive transmission signal at the driver output can result in a reduction in the overall emissions of physical layer circuit 1200. Additionally, interference / noise immunity and input voltage protection enable variable delay driver 100 to operate in the noisy and interference-prone environment of an automobile. Additionally, filtering of frequencies such as those corresponding to FM radio and DAB makes variable delay driver 100 suitable for the automobile environment.

[0055] Because standards for EMI emissions in automobiles are relatively stringent in certain frequency ranges (e.g., without limitation, those specified for FM radio and DAB), the delay of a delay element (e.g., without limitation, delay element 108 in FIG. 1 or delay element 208 in FIG. 2) may be selected to implement a notch filter to filter a particular frequency or frequency range of interest. As a non-limiting example, the delay of the delay element may be selected to target a notch frequency of the notch filter for FM frequencies substantially in the frequency range of 87-108 MHz. As another non-limiting example, the delay of the delay element may be selected to target a notch frequency of the notch filter substantially for a frequency of 100 MHz. As another non-limiting example, the delay of the delay element may be selected to target a notch frequency of the notch filter substantially for a frequency of 72 MHz. As yet another non-limiting example, the delay of the delay element may be selected to target a notch frequency of the notch filter substantially for a frequency of 50 MHz. As another non-limiting example, the delay of the delay element may be selected to target a notch frequency of the notch filter relative to one or more operating frequencies of one or more devices operating in a vehicle, such as vehicle 1302 of Figure 13. Further details regarding the variable delay driver 100 are discussed with reference to Figures 1 and 2.

[0056] The common mode dimmer 1222 protects the sensitive receiver circuitry (e.g., the detection circuit 1212 and the receive amplifiers 1206, 1208, 1210) from interference (e.g., common mode interference) and noise received from the communication bus 1220 during bulk current injection (BCI) conditions. For example, the common mode dimmer 1222 draws enough current through the resistor 1214 to filter out dangerously high common mode interference and reduce the voltage of the signal received through the communication bus 1220 to a safe level at the receiver circuit 1218. As a non-limiting example, the common mode dimmer 1222 may keep the voltage of the signal reaching the receiver circuit 1218 lower (e.g., 3.3 V) than the high power rail of the receiver circuit 1218. The common mode dimmer 1222 enables the use of high-gain receivers (e.g., receive amplifiers 1206, 1208, 1210) and signal / pulse / collision detectors (e.g., detection circuit 1212) within the receiver circuit 1218, filtering common-mode interference signals and resulting in low jitter and low power consumption. In some examples, the common mode dimmer 1222 can be used for low-power applications.

[0057] The detection circuit 1212 may include a signal detection circuit, a reflection detection circuit, a sleep mode detection circuit, a collision detection circuit, other circuits, or a combination thereof. The detection circuit 1212 may detect received signals through the communication bus 1220. The detection circuit 1212 (for example, but not limited to, using a reflection detection circuit) may diagnose the communication bus 1220 (for example, by detecting shorts, open circuits, other problems, or a combination thereof on the communication bus 1220). The detection circuit 1212 (for example, but not limited to, using a sleep mode detection circuit) may trigger the receiver circuit 1218 to sleep or wake up in response to a sleep or wake message received over the communication bus 1220. The detection circuit 1212 (for example, but not limited to, using a collision detection circuit) may detect signal collisions on the communication bus 1220. Signal and activity detection may also be performed by the detection circuit 1212.

[0058] Common mode choke 1204 reduces (e.g., suppresses) common mode interference received over communication bus 1220 to provide additional interference / noise protection, and capacitor 1216 filters out the direct current (DC) component of the received signal from communication bus 1220.

[0059] FIG. 13 is a block diagram of a system 1300 according to various examples. The system 1300 includes a vehicle 1302, which includes a shared transmission medium 1306 of a wired local area network 1308. The wired local area network 1308 may be an example of the wired local area network 1100 of FIG. 11. The vehicle 1302 also includes endpoints 1304a-1304e electrically connected to the shared transmission medium 1306. At least one of the endpoints may be the endpoint 1104 of FIG. 11 discussed above and may include the physical layer circuit 1200 of FIG. 12. Accordingly, one or more of the endpoints 1304a-1304e may include an encoder (e.g., without limitation, the Manchester encoder 1202 of FIG. 12) to provide a signal transmitted over the shared transmission medium 1306 to the wired local area network 1308.

[0060] Additionally, one or more of the endpoints 1304a-1304e may include a variable delay driver (e.g., but not limited to, the variable delay driver 100 of FIG. 1 or the variable delay driver 200 of FIG. 2). As discussed above, the variable delay driver may include an input terminal (e.g., but not limited to, the input terminal 102 of FIG. 1 or the input terminal 202 of FIG. 2), a delay element (e.g., but not limited to, the delay element 108 of FIG. 1 or the delay element 208 of FIG. 2), a combinational circuit (e.g., but not limited to, the combinational circuit 116 of FIG. 1 or the combinational circuit 216 of FIG. 2), and an output terminal (e.g., but not limited to, the output terminal 112 of FIG. 1 or the output terminal 212 of FIG. 2). The input terminal receives a signal from the encoder. The delay elements generate a delayed signal in response to the received signal. The delay associated with each of the delay elements is selected to reduce radiation of one or more predetermined frequencies of the slew-rate-reduced signal compared to the received signal. The combining circuit combines the delayed signals to generate a signal with a reduced slew rate. The output terminal is electrically connected to the shared transmission medium. The output terminal delivers the reduced slew rate signal to the shared transmission medium 1306. [Example]

[0061] A non-exhaustive, non-limiting list of exemplary embodiments follows: Each of the exemplary embodiments listed below is not expressly and individually indicated as combinable with all other of the exemplary embodiments listed below and the embodiments discussed above. However, these exemplary embodiments are intended to be combinable with all other exemplary embodiments and the embodiments discussed above, except where it is apparent to one skilled in the art that the embodiments are not combinable.

[0062] Example 1: An apparatus comprising: input terminals for receiving a signal; delay elements electrically connected to the input terminals for providing delayed signals responsive to the received signals, each delayed signal comprising a delayed version of the received signal; output terminals for providing a slew rate reduced signal; and a combinational circuit electrically connected to the delay elements and the output terminals, the combinational circuit combining the delayed signals to generate the slew rate reduced signal, the delay associated with the delay elements selected to reduce emissions of one or more predetermined frequencies in the slew rate reduced signal as compared to the received signal.

[0063] Example 2: The apparatus of example 1, wherein the combinational circuit includes sub-drivers, at least some of the sub-drivers electrically connected to drive respective ones of the delayed signals to the output terminals.

[0064] Example 3: The apparatus of example 2, wherein one of the sub-drivers is electrically connected from the input terminal to the output terminal.

[0065] Example 4: The apparatus of example 2 or 3, wherein at least one of the sub-drivers includes a pull-up current source electrically connected to a power supply high voltage potential node, a pull-down current source electrically connected to a power supply low voltage potential node, and a complementary metal-oxide semiconductor (CMOS) inverter electrically connected from the pull-up current source to the pull-down current source.

[0066] Example 5: The apparatus of example 4, wherein the pull-up current provided by the pull-up current source is substantially the same as the pull-down current provided by the pull-down current source.

[0067] Example 6: The apparatus of any one of Examples 1 to 5, wherein the combination circuit includes a summing circuit for combining the delayed signals by summing the delayed signals.

[0068] Example 7: The apparatus of any one of Examples 1 to 6, comprising a delay control circuit electrically connected to the delay element, the delay control circuit providing a delay control signal to the delay element for controlling a delay associated with the delay element.

[0069] Example 8: The apparatus of Example 7, wherein the one or more predetermined frequencies include three predetermined frequencies, and the delay control circuit determines, for the three virtual first-order notch filters, three different preliminary delays associated with the three predetermined frequencies, determines eight intermediate total delays associated with connecting the three virtual first-order notch filters together, sorts the eight intermediate total delays in ascending order, and for each of the eight intermediate total delays except the lowest intermediate delay, determines seven delay differences by subtracting the intermediate total delay from the delay immediately following the intermediate total delay, and selects delays associated with the delay elements to be each delay difference.

[0070] Example 9: The apparatus of any one of Examples 1 to 8, wherein the delay elements are electrically connected in series.

[0071] Example 10: A method for generating a signal with a reduced slew rate, the method comprising: delaying a received signal to generate a delayed signal using a delay selected to reduce radiation of one or more predetermined frequencies of the reduced slew rate signal compared to the received signal; and combining the delayed signals to generate a reduced slew rate signal at an output terminal.

[0072] Example 11: The method of example 10, wherein combining the delayed signals includes driving, by a sub-driver, the delayed signals to a summing circuit electrically connected to the output terminal.

[0073] Example 12: The method of example 10 or 11, comprising selecting the delay using a delay control circuit electrically connected to a delay element associated with the delay.

[0074] Example 13: The method of Example 12, wherein the step of selecting a delay using a delay control circuit electrically connected to the delay elements associated with the delays includes: determining three different preliminary delays associated with three predetermined frequencies for three virtual first-order notch filters; determining eight intermediate total delays associated with connecting the three virtual first-order notch filters together; sorting the eight intermediate total delays in ascending order; and, for each of the eight intermediate total delays except the lowest intermediate delay, determining seven differential delays by subtracting the intermediate total delay from the delay immediately following the intermediate total delay; and selecting a delay associated with the delay element to be the differential delay.

[0075] Example 14: A system comprising: a shared transmission medium of a wired local area network; an encoder providing a signal to be transmitted to the wired local area network via the shared transmission medium; a variable delay driver having an input terminal for receiving a signal from the encoder; delay elements for generating a delayed signal in response to the received signal, the delay being associated with each delay element selected to reduce radiation of one or more predetermined frequencies of the slew rate reduced signal compared to the received signal; a combination circuit for combining the delayed signals to generate the slew rate reduced signal; and an output terminal electrically connected to the shared transmission medium, for delivering the slew rate reduced signal to the shared transmission medium.

[0076] Example 15: The system described in Example 14, comprising a vehicle including a shared transmission medium, the vehicle including endpoints electrically connected to the shared transmission medium, at least one of the endpoints including an encoder and a variable delay driver.

[0077] Example 16: The system of Example 15, wherein the one or more predetermined frequencies include one or more operating frequencies of one or more devices operating within the vehicle.

[0078] conclusion As used in this disclosure, the term "module" or "component" may refer to a module or component and / or a specific hardware implementation that performs the actions of a software object or routine that may be stored on and / or executed by general-purpose hardware (e.g., computer-readable media, processing device, etc.) of a computing system. In some embodiments, different components, modules, engines, and services described in this disclosure may be implemented as objects or processes (e.g., as separate threads) that execute on a computing system. While some of the systems and methods described in this disclosure are generally described as being implemented in software (stored on and / or executed on general-purpose hardware), specific hardware implementations, or a combination of software and specific hardware implementations, are also possible and contemplated.

[0079] As used in this disclosure, the term "combination" in reference to multiple elements may include a combination of all elements or any of several different subcombinations of the elements. For example, the phrase "A, B, C, D, or combinations thereof" may refer to A, B, C, or D; each combination of A, B, C, and D; and any subcombination of A, B, C, or D, such as any one of A, B, and C; A, B, and D; A, C, and D; B, C, and D; A and B; A and C; A and D; B and C; B and D; or C and D.

[0080] The terms used in this disclosure, and particularly in the appended claims (e.g., the body of the appended claims), are generally intended as "open" terms (e.g., the term "including" should be interpreted as "including, but not limited to," the term "having" should be interpreted as "having at least," the term "includes" should be interpreted as "includes, but is not limited to," etc.).

[0081] Additionally, if a specific number of introduced claim recitations is intended, such intent will be expressly recited in the claim; absent such recitation, no such intent exists. For example, as an aid to understanding, the following appended claims may include the use of the introductory phrases "at least one" and "one or more" to introduce claim recitations. However, the use of such phrases should not be construed as limiting any particular claim including such introduced claim recitations to embodiments including only one such recitation (e.g., "a" and / or "an" should be construed to mean "at least one" or "one or more"), even if the same claim includes the introductory phrase "one or more" or "at least one" and an indefinite article such as "a" or "an"); the same is true for the use of express articles used to introduce claim recitations.

[0082] Additionally, even when a specific number of introduced claim recitations are explicitly recited, those skilled in the art will recognize that such recitation should be interpreted to mean at least the recited number (e.g., the explicit recitation of "two recitations" without other modifiers means at least two recitations or more than two recitations). Furthermore, when conventions similar to "at least one of A, B, and C, etc." or "one or more of A, B, and C, etc." are used, such constructions are generally intended to include A only, B only, C only, A and B together, A and C together, B and C together, or A, B, and C together, etc.

[0083] Furthermore, any disjunction or phrase presenting two or more alternative terms, whether in the specification, claims, or drawings, should be understood to contemplate the possibility of including one of the terms, either of the terms, or both terms. For example, the phrase "A or B" should be understood to include the possibilities of "A" or "B" or "A and B."

[0084] While the present disclosure has been described herein with reference to certain illustrated embodiments, those skilled in the art will recognize and understand that the present invention is not so limited. Rather, numerous additions, deletions, and modifications may be made to the illustrated and described embodiments without departing from the scope of the invention as claimed below, along with their legal equivalents. In addition, features of one example may be combined, as contemplated by the inventors, with features of other disclosed embodiments and still fall within the scope of the present disclosure.

Claims

1. 1. An apparatus comprising: an input terminal for receiving a signal; a plurality of delay elements electrically connected to the input terminal, the plurality of delay elements providing a plurality of delayed signals responsive to a received signal, each delay signal comprising a plurality of delayed versions of the received signal; an output terminal for providing a reduced slew rate signal; a combinational circuit electrically connected to the plurality of delay elements and the output terminal, the combinational circuit combining the plurality of delayed signals to generate the reduced slew rate signal, wherein delays associated with the plurality of delay elements are selected to reduce emissions of one or more predetermined frequencies of the reduced slew rate signal as compared to the received signal.

2. 2. The apparatus of claim 1, wherein the combinational circuit includes a plurality of sub-drivers, at least some of the plurality of sub-drivers electrically connected to drive each of the plurality of delayed signals to the output terminal.

3. The apparatus of claim 2 , wherein one of the plurality of sub-drivers is electrically connected from the input terminal to the output terminal.

4. At least one of the plurality of sub-drivers a pull-up current source electrically connected to the power supply high voltage potential node; a pull-down current source electrically connected to the power supply low voltage potential node; a complementary metal-oxide-semiconductor (CMOS) inverter electrically connected from the pull-up current source to the pull-down current source.

5. 5. The apparatus of claim 4, wherein the pull-up current provided by the pull-up current source is substantially the same as the pull-down current provided by the pull-down current source.

6. 2. The apparatus of claim 1, wherein the combining circuitry includes a summing circuit for combining the delayed signals by summing the delayed signals.

7. 10. The apparatus of claim 1, further comprising: a delay control circuit electrically connected to the plurality of delay elements, the delay control circuit providing a plurality of delay control signals to the plurality of delay elements for controlling the plurality of delays associated with the plurality of delay elements.

8. the one or more predetermined frequencies include three predetermined frequencies; The delay control circuit includes: determining three different preliminary delays associated with the three predetermined frequencies for three virtual first-order notch filters; determining eight intermediate total delays associated with concatenating the three virtual first-order notch filters together; sorting the eight intermediate total delays in ascending order; for each of the eight intermediate sum delays except for the lowest intermediate delay, determining seven differential delays by subtracting the intermediate sum delay from the delay immediately following the intermediate sum delay; The apparatus of claim 7 , further comprising: selecting the delay associated with the delay element to be the respective delay difference.

9. The apparatus of claim 1 , wherein the delay elements are electrically connected in series.

10. 1. A method for generating a signal having a reduced slew rate, the method comprising: delaying the received signal to generate a plurality of delayed signals using a plurality of delays selected to reduce emissions of one or more predetermined frequencies in the reduced slew rate signal relative to the received signal; combining the plurality of delayed signals to generate the reduced slew rate signal at an output terminal.

11. The method of claim 10 , wherein combining the plurality of delayed signals comprises driving the plurality of delayed signals by a plurality of sub-drivers to a summing circuit electrically connected to the output terminal.

12. 11. The method of claim 10, comprising selecting the plurality of delays using a delay control circuit electrically connected to a plurality of delay elements associated with the plurality of delays.

13. selecting the plurality of delays using a delay control circuit electrically connected to a plurality of delay elements associated with the plurality of delays, determining three different preliminary delays associated with three predetermined frequencies for three virtual first-order notch filters; determining eight intermediate total delays associated with concatenating together the three virtual first-order notch filters; sorting the eight intermediate total delays in ascending order; for each of the eight intermediate sum delays except for the lowest intermediate delay, determining seven differential delays by subtracting the intermediate sum delay from the delay immediately following the intermediate sum delay; and selecting the delays associated with the delay elements to be the delay difference.

14. 1. A system comprising: a shared transmission medium of a wired local area network; an encoder for providing a signal for transmission over the shared transmission medium to the wired local area network; A variable delay driver comprising: an input terminal for receiving the signal from the encoder; a plurality of delay elements for generating a plurality of delayed signals in response to a received signal, a plurality of delays associated with each of the plurality of delay elements selected to reduce radiation of one or more predetermined frequencies of a slew rate reduced signal compared to the received signal; a combining circuit for combining the delayed signals to generate the reduced slew rate signal; a variable delay driver comprising: an output terminal electrically connected to the shared transmission medium, the output terminal delivering the reduced slew rate signal to the shared transmission medium.

15. 15. The system of claim 14, comprising a vehicle including the shared transmission medium, the vehicle including endpoints electrically connected to the shared transmission medium, at least one of the endpoints including the encoder and the variable delay driver.

16. The system of claim 15 , wherein the one or more predetermined frequencies include one or more operating frequencies of one or more devices operating within the vehicle.

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