Phased Array Antenna Architecture

Abstract

The wireless system architecture includes a receiver having multiple subarrays in a phased array, the multiple subarrays configured to perform carrier aggregation (CA) and multiple-input multiple-output (MIMO) signal processing and provide independent beam management for multiple radio frequency (RF) signals received at each of the multiple subarrays, and a data processor configured to receive signals from the receiver and extract information related to the wireless communication.

Description

[Technical Field]

[0001] The present disclosure relates generally to electronic devices, and more particularly to wireless communication systems, and more particularly to wireless communication devices with multiple-input multiple-output (MIMO) and carrier aggregation (CA) capabilities. [Background technology]

[0002] Wireless communication devices and technologies are becoming increasingly popular as communication systems operate at millimeter wave (mmW) frequencies and near mmW frequencies. Some communication methods use what is called multiple input multiple output (MIMO) and carrier aggregation (CA), where multiple signals at one or more frequencies are processed simultaneously.

[0003] 5G mmW communication systems may be implemented that typically use time division duplex (TDD) communication methods. For TDD systems, maintaining synchronization to prevent interference is important, which can be difficult when switching between transmit and receive modes. Guard periods are used to provide separation between transmit and receive events, with a configurable total guard time expressed as an integer number of symbols.

[0004] At the receiver in the user equipment (UE), relative frame timing alignment is an important metric. The 3rd Generation Partnership Project (3GPP) defines the maximum receive timing difference (MRTD) as the maximum relative receive timing difference that a UE must be able to handle. MRTD includes the base station relative time alignment error (TAE) and the RF propagation delay difference (ΔTprop). That is, MRTD = TAE + ΔTprop. For example, in a known 5G communication system that implements a single 5 GHz-wide downlink channel bandwidth using common beam management (CMB) to achieve carrier aggregation, MRTD can be as severe as 0.26 μsec. Other limitations and performance degradation arise from this configuration due to the extremely wide channel bandwidth. Summary of the Invention [Means for solving the problem]

[0005] Various implementations of the systems, methods, and devices within the scope of the appended claims each have several aspects, no single one of which alone provides the desirable attributes described herein. Without limiting the scope of the appended claims, some prominent features will be described herein.

[0006] The details of one or more implementations of the subject matter described herein are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages will become apparent from the description, drawings, and claims. Note that the relative dimensions of the following figures may not be drawn to scale.

[0007] One aspect of the present disclosure provides a receiving system for performing carrier aggregation (CA) and multiple-input multiple-output (MIMO) operations at millimeter-wave (mmW) frequencies, the receiving system including a phased array having a plurality of groupings, each grouping having a pair of subarray structures, each subarray structure including a plurality of phased array elements and a multiplexer, each phased array element coupled to an antenna element, each phased array element including a low-noise amplifier (LNA) and a phase shifter (PS), the plurality of groupings including a first high-band (HB) grouping and a first low-band (LB) grouping. a phased array including: a downconverter circuit selectively connected to each subarray structure in a first high band (HB) grouping and a first low band (LB) grouping, each downconverter circuit having a radio frequency (RF) amplifier, a mixer, an intermediate frequency (IF) amplifier, and a filter; and a combining circuit connected to each of the downconverter circuits selectively connected to the first high band (HB) grouping and the first low band (LB) grouping, the combining circuit configured to provide a signal from each downconverter circuit to an intermediate frequency (IF) port.

[0008] Another aspect of the present disclosure provides a method for signal processing, the method including receiving at least two radio frequency (RF) signals at a receiver; selectively phase-shifting the at least two radio frequency (RF) signals; selectively directing the at least two phase-shifted radio frequency (RF) signals to selected downconverter circuits; simultaneously downconverting the at least two RF signals to intermediate frequency (IF) signals; and connecting the at least two IF signals to at least one selected output port.

[0009] Another aspect of the present disclosure provides a device, the device including: means for receiving at least two radio frequency (RF) signals at a receiver; means for selectively phase shifting the at least two radio frequency (RF) signals; means for selectively directing the at least two phase-shifted radio frequency (RF) signals to selected downconverter circuits; means for simultaneously downconverting the at least two RF signals to intermediate frequency (IF) signals; and means for connecting the at least two IF signals to at least one selected output port.

[0010] Another aspect of the present disclosure provides a wireless system architecture that includes: a receiver having multiple subarrays in a phased array, the multiple subarrays configured to perform carrier aggregation (CA) and multiple-input multiple-output (MIMO) signal processing and provide independent beam management for multiple radio frequency (RF) signals received at each of the multiple subarrays; and a data processor configured to receive signals from the receiver and extract information related to the wireless communication.

[0011] In the figures, like reference numerals refer to like parts throughout the various figures unless otherwise indicated. For reference numerals having a letter designation, such as "102a" or "102b," the letter designation can distinguish between two like parts or elements present in the same figure. If the reference numeral is intended to encompass all parts having the same reference numeral in all figures, the letter designation for the reference numeral can be omitted. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 1 illustrates a wireless device in communication with a wireless communication system. [Figure 2A] FIG. 1 is a block diagram illustrating a wireless device in which example techniques of the present disclosure may be implemented. [Figure 2B]FIG. 1 is a block diagram illustrating a wireless device in which example techniques of the present disclosure may be implemented. [Figure 3] FIG. 1 is a schematic diagram of a subarray structure of a phased array. [Figure 4] FIG. 1 is a schematic diagram of a downconverter. [Figure 5] FIG. 2 is a schematic diagram of a signal combining circuit. [Figure 6] FIG. 1 is a schematic diagram of an exemplary embodiment of a phased array. [Figure 7] FIG. 1 is a schematic diagram of an exemplary embodiment of a phased array. [Figure 8] FIG. 1 is a schematic diagram of an exemplary embodiment of a phased array. [Figure 9] FIG. 1 is a schematic diagram of an exemplary embodiment of a phased array. [Figure 10] FIG. 1 is a schematic diagram of an exemplary embodiment of a phased array. [Figure 11] 1 is a flowchart illustrating an example of the operation of a method for signal processing. [Figure 12] FIG. 1 is a functional block diagram of an apparatus for signal processing. [Figure 13] 1 is a flowchart illustrating an example of the operation of a method for signal processing. [Figure 14] FIG. 1 is a functional block diagram of an apparatus for signal processing. DETAILED DESCRIPTION OF THE INVENTION

[0013] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0014] The communication device may include a phased array antenna system and may include receive (Rx) MIMO capabilities. For example, a 5G New Radio (NR) communication device may support multiple transmitters, multiple receivers, and be capable of communicating over multiple communication bands. In some examples, the communication device may also include carrier aggregation (CA), in which the communication device may communicate over multiple communication bands simultaneously.

[0015] 1 illustrates a wireless device 110 communicating with a wireless communication system 120. The wireless communication system 120 may be a Long Term Evolution (LTE) system, a Code Division Multiple Access (CDMA) system, a Global System for Mobile Communications (GSM) system, a Wireless Local Area Network (WLAN) system, a 5G NR (New Radio) system, or some other wireless system. The CDMA system may implement Wideband CDMA (WCDMA), CDMA 1X, Evolution Data Optimized (EVDO), Time Division Synchronous CDMA (TD-SCDMA), or some other version of CDMA. For simplicity, FIG. 1 illustrates the wireless communication system 120 including two base stations 130 and 132 and one system controller 140. In general, a wireless communication system may include any number of base stations and any set of network entities.

[0016] The wireless device 110 may also be referred to as a user equipment (UE), a mobile station, a terminal, an access terminal, a subscriber unit, a station, etc. The wireless device 110 may be a mobile phone, a smartphone, a tablet, a wireless modem, a personal digital assistant (PDA), a handheld device, a laptop computer, a smartbook, a netbook, a tablet, a cordless phone, a medical device, an automobile, a device configured to connect to one or more other devices (e.g., via the Internet of Things), a wireless local loop (WLL) station, a Bluetooth device, etc. The wireless device 110 may communicate with the wireless communication system 120. The wireless device 110 may also receive signals from a broadcast station (e.g., broadcast station 134) and / or signals from a satellite (e.g., satellites 150 in one or more global navigation satellite systems (GNSS)). The wireless device 110 may support one or more radio technologies for wireless communication, such as LTE, WCDMA, CDMA 1X, EVDO, TD-SCDMA, GSM, 802.11, 5G, etc.

[0017] Wireless device 110 may support carrier aggregation, e.g., as described in one or more LTE or 5G standards. In some embodiments, for example, a single data stream is transmitted over multiple carriers using carrier aggregation, rather than using a separate carrier for each data stream. Wireless device 110 may be capable of operating over a wide range of frequencies, e.g., in various communication bands, including those used by LTE, WiFi, 5G, or other communication bands. Wireless device 110 may also be capable of communicating directly with other wireless devices without communicating through a network.

[0018] Generally, Carrier Aggregation (CA) can be classified into two types: intra-band CA and inter-band CA. Intra-band CA refers to operation on multiple carriers in the same band. Inter-band CA refers to operation on multiple carriers in different bands.

[0019] 2A is a block diagram illustrating a wireless device 200 in which example techniques of this disclosure may be implemented. Wireless device 200 may be, for example, an embodiment of wireless device 110 shown in FIG.

[0020] FIG. 2A illustrates one embodiment of a transceiver 220 having a transmitter 230 and a receiver 250. In general, signal conditioning in the transmitter 230 and receiver 250 can be performed in one or more stages, such as amplifiers, filters, upconverters, downconverters, etc. These circuit blocks can also be arranged differently than the configuration shown in FIG. 2A. Additionally, other circuit blocks not shown in FIG. 2A, such as phase shifters as discussed further below, can also be used to condition signals in the transmitter 230 and receiver 250. Unless otherwise noted, any signals in FIG. 2A or any other diagram in the drawings can be either single-ended or differential. Some circuit blocks in FIG. 2A can also be omitted.

[0021] In the embodiment shown in FIG. 2A , wireless device 200 generally comprises a transceiver 220 and a data processor 210. Data processor 210 may include a processor 296 operatively coupled to memory 298. Memory 298 may be configured to store data and program code, generally indicated using reference numeral 299, and may typically comprise analog and / or digital processing components. Transceiver 220 includes a transmitter 230 and a receiver 250 supporting bidirectional communication. In general, wireless device 200 may include any number of transmitters and / or receivers for any number of communication systems and frequency bands. All or a portion of transceiver 220 may be implemented on one or more analog integrated circuits (ICs), RF ICs (RFICs), mixed-signal ICs, etc.

[0022] The transmitter or receiver can be implemented using a superheterodyne architecture or a direct-conversion architecture. In a superheterodyne architecture, a signal is frequency converted between radio frequency (RF) and baseband in multiple stages, e.g., for a receiver, from RF to intermediate frequency (IF) in one stage and then from IF to baseband in another stage. In a direct-conversion architecture, a signal is frequency converted between RF and baseband in one stage. The superheterodyne architecture and the direct-conversion architecture may use different circuit blocks and / or have different requirements. In the embodiment shown in FIG. 2A, the transmitter 230 and the receiver 250 are implemented using a direct-conversion architecture.

[0023] In the transmit path, data processor 210 processes data to be transmitted and provides in-phase (I) and quadrature-phase (Q) analog output signals to transmitter 230. In an exemplary embodiment, data processor 210 includes digital-to-analog converters (DACs) 214a and 214b for converting digital signals generated by data processor 210 into I and Q analog output signals, e.g., I and Q output currents, for further processing. In other embodiments, DACs 214a and 214b are included within transceiver 220, and data processor 210 provides data (e.g., for I and Q) to transceiver 220 digitally.

[0024] Within transmitter 230, lowpass filters 232a and 232b filter the I and Q analog transmit signals, respectively, to remove unwanted images caused by previous digital-to-analog conversion. Amplifiers (Amp) 234a and 234b amplify the signals from lowpass filters 232a and 232b, respectively, and provide I and Q baseband signals. An upconverter 240, having upconversion mixers 241a and 241b, upconverts the I and Q baseband signals using I and Q LO signals from a transmit (TX) local oscillator (LO) 290 and provides upconverted signals. A filter 242 filters the upconverted signal to remove unwanted images caused by frequency upconversion as well as noise within the receive frequency band. A power amplifier (PA) 244 amplifies the signal from filter 242 to obtain the desired output power level and provides the transmit RF signal. The transmit RF signal may be routed through a duplexer or switch 246 and transmitted via antenna 248, or may be sent to a separate transmit antenna that is distinct from the separate receive antenna. While the embodiments discussed herein utilize I and Q signals, those skilled in the art will understand that the transceiver components may also be configured to utilize polar modulation.

[0025] In the receive path, antenna 248 receives the communication signal and provides a received RF signal, which may be routed through duplexer or switch 246 and provided to low-noise amplifier (LNA) 252. Duplexer 246 is designed to operate with a specific RX-TX duplexer frequency separation so that the RX signal is isolated from the TX signal. Alternatively, there may be separate transmit and receive antennas as described above, in which case RX-TX isolation may be achieved through limited coupling between the two antennas. In the case of separate RX and TX antennas, the RX antenna may be directly coupled to LNA 252. To obtain the desired RF input signal, the received RF signal is amplified by LNA 252 and filtered by filter 254. Downconversion mixers 261a and 261b within downconverter 260 mix the output of filter 254 with I RX LO signals and Q RX LO signals (i.e., LO_I and LO_Q) from receive (RX) LO signal generator 280 to generate I and Q baseband signals. The I and Q baseband signals are amplified by amplifiers 262a and 262b and further filtered by lowpass filters 264a and 264b to obtain I and Q analog input signals, which are provided to data processor 210. In the illustrated exemplary embodiment, data processor 210 includes analog-to-digital converters (ADCs) 216a and 216b for converting the analog input signals to digital signals that can be further processed by data processor 210. In some embodiments, ADCs 216a and 216b are included within transceiver 220 and provide data digitally to data processor 210.

[0026] 2A , TX LO signal generator 290 generates the I TX LO signal and Q TX LO signal used for frequency upconversion, while RX LO signal generator 280 generates the I RX LO signal and Q RX LO signal used for frequency downconversion. Each LO signal is a periodic signal having a particular fundamental frequency. Phase-locked loop (PLL) 292 receives timing information from data processor 210 and generates control signals used to adjust the frequency and / or phase of the TX LO signal from LO signal generator 290. Similarly, PLL 282 receives timing information from data processor 210 and generates control signals used to adjust the frequency and / or phase of the RX LO signal from LO signal generator 280.

[0027] In an exemplary embodiment, the RX PLL 282, the TX PLL 292, the RX LO signal generator 280, and the TX LO signal generator 290 may alternatively be combined into a single LO generator circuit 295, which may include a common or shared LO signal generator circuit for providing the TX LO signal and the RX LO signal. Alternatively, separate LO generator circuits may be used to generate the TX LO signal and the RX LO signal.

[0028] Wireless device 200 may support CA and may (i) receive multiple downlink signals transmitted by one or more cells on multiple downlink carriers at different frequencies, and / or (ii) transmit multiple uplink signals on multiple uplink carriers to one or more cells.

[0029] Certain components of transceiver 220 are illustrated in FIG. 2A with respect to their functionality, and the configuration depicted in this figure may or may not represent the physical device configuration in a particular implementation. For example, as discussed above, transceiver 220 can be implemented in various integrated circuits (ICs), RF ICs (RFICs), mixed-signal ICs, etc. In some embodiments, transceiver 220 is implemented on a substrate or board, such as a printed circuit board (PCB) having various modules, chips, and / or components. For example, power amplifier 244, filter 242, and duplexer 246 may be implemented in separate modules or as individual components, while the remaining components depicted in transceiver 220 may be implemented in a single transceiver chip.

[0030] Power amplifier 244 may include one or more stages, including, for example, a driver stage, a power amplifier stage, or other components, that may be configured to amplify communication signals over one or more frequencies, within one or more frequency bands, and at one or more power levels. Depending on various factors, power amplifier 244 may be configured to operate with one or more driver stages, one or more power amplifier stages, one or more impedance matching networks, and may be configured to provide good linearity, efficiency, or a combination of good linearity and efficiency.

[0031] In an exemplary embodiment in a superheterodyne architecture, filter 242, PA 244, LNA 252, and filter 254 may be implemented separately from other components in transmitter 230 and receiver 250 and may be implemented on a millimeter-wave integrated circuit. An exemplary superheterodyne architecture is shown in FIG. 2B.

[0032] 2B is a block diagram illustrating a wireless device in which example techniques of the present disclosure may be implemented. Certain components of wireless device 200a in FIG. 2B, which may be indicated by the same reference numerals, may be configured similarly to components in wireless device 200 shown in FIG. 2A, and descriptions of identically numbered items in FIG. 2B will not be repeated.

[0033] Wireless device 200a is an example of a heterodyne (or superheterodyne) architecture in which upconverter 240 and downconverter 260 are configured to process communication signals between baseband and an intermediate frequency (IF). For example, upconverter 240 can be configured to provide an IF signal to upconverter 275. In an exemplary embodiment, upconverter 275 can include an upconversion mixer 276. A summing function 278 of upconverter 240 combines the I and Q outputs and provides the combined signal to mixer 276. This combined signal can be single-ended or differential. Mixer 276 is configured to receive the IF signal from upconverter 240 and the TX RF LO signal from TX RF LO signal generator 277, and is configured to provide an upconverted RF signal to phase shift circuit 281. While PLL 292 is shown in FIG. 2B as being shared by signal generators 290, 277, a corresponding PLL for each signal generator can also be implemented.

[0034] In an exemplary embodiment, components within phase shift circuit 281 may include one or more adjustable or variable phased array elements, receive one or more control signals from data processor 210 via connection 294, and operate the adjustable or variable phased array elements based on the received control signals.

[0035] In the exemplary embodiment, the phase shift circuit 281 includes phase shifters 283 and phased array elements 287. For ease of explanation, three phase shifters 283 and three phased array elements 287 are shown, however, the phase shift circuit 281 may include more or fewer phase shifters 283 and phased array elements 287.

[0036] Each phase shifter 283 may be configured to receive an RF transmit signal from the upconverter 275, change the phase by a certain amount, and provide the RF signal to a respective phased array element 287. Each phased array element 287 may include transmit and receive circuitry, including one or more filters, amplifiers, driver amplifiers, and power amplifiers. In some embodiments, the phase shifter 283 may be incorporated within each phased array element 287.

[0037] The output of the phase shifting circuitry 281 is provided to the antenna array 248. In an exemplary embodiment, the antenna array 248 typically includes a number of antennas corresponding to the number of phase shifters 283 and phased array elements 287, e.g., each antenna element is coupled to a respective phased array element 287. In an exemplary embodiment, the phase shifting circuitry 281 and the antenna array 248 are referred to as a phased array.

[0038] In the receive direction, the output of phase shift circuit 281 is provided to downconverter 285. In an exemplary embodiment, downconverter 285 may include a downconversion mixer 286. In an exemplary embodiment, mixer 286 downconverts the received RF signal provided by phase shift circuit 281 to an IF signal in accordance with an RX RF LO signal provided by RX RF LO signal generator 279. I / Q generation function 291 of downconverter 260 receives the IF signal from mixer 286 and generates I and Q signals in downconverter 260, which downconverts the IF signal to baseband, as described above. Although PLL 282 is shown in FIG. 2B as being shared by signal generators 280, 279, a corresponding PLL for each signal generator may also be implemented.

[0039] In some embodiments, upconverter 275, downconverter 285, and phase shift circuit 281 are implemented on a common IC. In some embodiments, summing function 278 and I / Q generation function 291 are implemented separately from mixers 276 and 286 such that mixers 276, 286 and phase shift circuit 281 are implemented on a common IC, but summing function 278 and I / Q generation function 291 are not implemented on the common IC (e.g., summing function 278 and I / Q generation function 291 are implemented in a separate IC that is coupled to the IC with mixers 276, 286). In some embodiments, LO signal generators 277, 279 are included in a common IC. In some embodiments in which the phase-shift circuitry is implemented on a common IC with 276, 286, 277, 278, 279, and / or 291, the common IC and antenna array 248 are included in a module that can be coupled to other components of transceiver 220 via a connector. In some embodiments, phase-shift circuitry 281, e.g., the chip on which phase-shift circuitry 281 is implemented, is coupled to antenna array 248 by an interconnect, or both are mounted to a substrate. For example, the components of antenna array 248 can be mounted on a substrate and coupled to an integrated circuit implementing phase-shift circuitry 281 via a flexible printed circuit board, or the integrated circuit can be mounted on the opposite side of the substrate.

[0040] In some embodiments, both the architecture shown in FIG. 2A and the architecture shown in FIG. 2B are implemented within the same device. For example, wireless device 110 or 200 may be configured to communicate with signals having frequencies below approximately 7 GHz (e.g., the FR1 frequency band) using the architecture shown in FIG. 2A and to communicate with signals having frequencies above approximately 24 GHz using the architecture shown in FIG. 2B. In a device in which both architectures are implemented, one or more components of FIGS. 2A and 2B that are identically numbered may be shared between the two architectures. For example, both signals downconverted directly from RF to baseband and signals downconverted from RF to baseband via an IF stage may be filtered by the same baseband filter 264. In other embodiments, a first version of filter 264 is included in the portion of the device that implements the architecture of FIG. 2A, and a second version of filter 264 is included in the portion of the device that implements the architecture of FIG. 2B.

[0041] FIG. 3 shows a schematic diagram 300 of a subarray structure 310 of a phased array. The subarray structure 310 may be one example of multiple subarray structures that may be arranged in a phased array circuit, such as the phase shift circuit 281 (FIG. 2B). In an exemplary embodiment, there may be eight subarray structures in the phased array. The subarray structure 310 may include multiple phased array elements having transmit and / or receive capabilities. In an exemplary embodiment, an exemplary receive phased array element 315 may include a receive circuit having a low noise amplifier (LNA) 320 and a phase shifter 340. In an exemplary embodiment, the subarray structure 310 may also include a multiplexer 330 connected to the output of each phase shifter 340. Each LNA 320 may be connected to a port 317. In receive applications, the port 317 may include one or more outputs of an antenna or antenna element. An exemplary antenna element 318 is shown for reference. The antenna element 318 may be one antenna element of a phased array of antenna elements. An antenna system in a phased array may have one or more antennas and one or more antenna elements, and may have one or more outputs. An example of an output from an antenna or antenna element 318 may be a vertically polarized (V pole) output and a horizontally polarized (H pole) output. In an exemplary embodiment, the multiplexer 330 may be configured to provide signals from two of the phase shifters 340 or all of the phase shifters 340 on selected outputs to subsequent processing circuitry, such as a frequency conversion circuit (an example of which is shown in FIG. 4 ), which may be configured to convert a radio frequency (RF) signal to a lower frequency (called an intermediate frequency (IF)), and / or a circuit for combining multiple signals being output from the multiplexer 330 (e.g., before being provided to the IF port). In another example, signals received at the multiplexer 330 are combined within the multiplexer 330, and the combined signal is selectively provided to subsequent processing circuitry, such as a frequency conversion circuit. For example, the frequency conversion circuitry may be configured to convert a 24 GHz or 39 GHz signal at port 317 to a frequency of, for example, 10 GHz. Other frequencies are possible.

[0042] FIG. 4 shows a schematic diagram 400 of a downconverter 401. The downconverter 401 may be an example of the downconverter 285 of FIG. 2B and, in an exemplary embodiment, may be configured to downconvert a communication signal from an RF signal to an IF signal. In an exemplary embodiment, the downconverter 401 may include one or more variable gain amplifiers (VGAs), with exemplary VGAs 402a and 402b shown by way of example only. The VGAs 402a and 402b may each be configured to amplify the RF signal. The downconverter 401 may also include a mixer 404, an IF VGA 406, and a filter 408. The outputs of the VGAs 402a and 402b are coupled together to an input of the mixer 404. In an exemplary embodiment, the mixer 404 may be a downconversion mixer configured to convert the RF signal to an IF signal. The IF VGA 406 may be configured to amplify the IF signal, and the filter 408 may be configured to remove unwanted artifacts from the IF signal amplified by the IF VGA 406. In an exemplary embodiment, RF VGAs 402a and 402b and IF VGA 406 may be controlled by control signals from data processor 210 (FIG. 2B) or another controller. Although examples of downconverting to IF and then processing the IF signal, and examples of an IF port are described herein, it will be understood that signals may be downconverted to baseband and the baseband signal may be subsequently processed, and that exemplary devices may include a BB port, for example, in a direct conversion architecture where mixer 404 is configured to convert between RF and baseband.

[0043] FIG. 5 shows a schematic diagram 500 of a signal combining circuit 501. In an exemplary embodiment, the combining circuit 501 may include one or more variable gain amplifiers (VGAs), with exemplary VGAs 502a and 502b shown by way of example only. The output of VGA 502b may be provided to an attenuator 504. The output of VGA 502a and the output of attenuator 504 may be provided to a matching network 506. The matching network 506 may include one or more resistive, capacitive, and inductive elements configured to provide impedance matching. The output of matching network 506 may be provided to a notch filter 508. The output of notch filter 508 may be provided to a diplexer 510 configured to separate transmit and receive signals by time, for example, to enable time division duplex (TDD) communications.

[0044] FIG. 6 shows a schematic diagram 600 of a phased array 602. In an exemplary embodiment, the phased array 602 includes eight subarray structures 310, referred to in this example as subarray structures 310a, 310b, 310c, 310d, 310e, 310f, 310g, and 310h. In an exemplary embodiment, the subarray structures 310 may include an arrangement in which the subarray structures 310c, 310d, 310g, and 310h on the right side of the figure are generally configured to process signals within a particular band, such as the low band, and the subarray structures 310a, 310b, 310e, and 310f on the left side of the figure are generally configured to process signals within a particular band, such as the high band. As used herein, the terms “high” and “low” are relative. For example, low-band signals may have a frequency of approximately 24 GHz, and high-band signals may have a frequency of approximately 42 GHz. Other frequencies are possible, with the frequencies of 24 GHz and 42 GHz being used merely as an example. Furthermore, the upper subarray structures 310a, 310b, 310c, and 310d may be configured to process horizontally polarized (H-pole) signals from their respective antennas (e.g., from 16 respective antennas in the illustrated example), and the lower subarray structures 310e, 310f, 310g, and 310h may be configured to process vertically polarized (V-pole) signals from their respective antennas (e.g., the same antennas to which the upper subarray structures 310a, 310b, 310c, and 310d are coupled). However, this example is one example of several different possible configurations.

[0045] In an exemplary embodiment, subarray structures 310a and 310b associated with the high band H pole may include a high band H pole quadrant 640, subarray structures 310c and 310d associated with the low band H pole may include a low band H pole quadrant 650, subarray structures 310e and 310f associated with the high band V pole may include a high band V pole quadrant 660, and subarray structures 310g and 310h associated with the low band V pole may include a low band V pole quadrant 670. Each of quadrants 640, 650, 660, and 670 may be further divided into two subquadrants, each with a subarray structure 310.

[0046] The phased array 602 also includes downconverters 401 associated with each subarray structure. Downconverters 401a and 401b may be associated with a high-band H-pole quadrant 640, downconverters 401c and 401d may be associated with a low-band H-pole quadrant 650, downconverters 401e and 401f may be associated with a high-band V-pole quadrant 660, and downconverters 401g and 401h may be associated with a low-band V-pole quadrant 670.

[0047] Synthesizer 612 may be configured to provide local oscillator (LO) signals to downconverters 401a, 401b, 401e, and 401f, and synthesizer 614 may be configured to provide local oscillator (LO) signals to downconverters 401c, 401d, 401g, and 401h. In an exemplary embodiment, synthesizer 612 may also be configured to provide local oscillator (LO) signals to downconverters 401c, 401d, 401g, and 401h by selective activation of a switching circuit (not shown), and synthesizer 614 may also be configured to provide local oscillator (LO) signals to downconverters 401a, 401b, 401e, and 401f by selective activation of a switching circuit (not shown).

[0048] In an exemplary embodiment, combining circuit 501a may be associated with H-pole quadrants 640 and 650, and combining circuit 501b may be associated with V-pole quadrants 660 and 670. Combiner circuit 501a may be connected to a first IF port, IF_1, and combining circuit 501b may be connected to a second IF port, IF_2.

[0049] In an exemplary embodiment, one or more signals may be received by one or more antenna elements, downconverted from RF to IF, and present on a first IF port, IF_1, and a second IF port, IF_2. The signals on these ports may be communicated via interconnects to a transceiver chip or other circuitry, such as optionally a downconverter 260 (e.g., if IF is used, as in this example, although downconverter 260 may be omitted in a direct-conversion architecture) and amplifiers and / or filters 262, 264, for further processing of the one or more signals. After being processed by these elements, data processor 210 may receive the signals and further process them to extract information related to the wireless communication.

[0050] FIG. 6 is described as having four quadrants. However, in other examples, there may not be four such quadrants. For example, in implementations where a particular antenna does not include both a V pole and an H pole, there may be fewer than four quadrants (e.g., only the top half of FIG. 6 may be implemented). Other configurations may be used in which fewer (or more) quadrants are implemented. Furthermore, while the quadrants are shown as being distributed among the four corners of a rectangle, such representation is not limiting. The quadrants may be arranged on the chip in any number of ways. They may be arranged linearly, they may be separated as shown, or they may overlap. While the specific description below describes quadrants, a "grouping" having multiple (e.g., pairs of) subarray structures may also be used to describe the illustrated circuits, such as any of 640, 650, 660, and 670.

[0051] FIG. 7 shows a schematic diagram 700 of an exemplary embodiment of a phased array 702. In FIG. 7, the phased array 702 is capable of signal processing for low-band multiple-input multiple-output (LB MIMO) using independent beam management (IBM) and is capable of signal processing for two LB signals using independent beam management (IBM) in a carrier aggregation (CA) system. An example of signal processing for two LB signals using IBM in a CA system is shown, with components in this example processing a first communication signal at a first frequency arbitrarily indicated using thick dotted lines and components in this example processing a second communication signal at a second frequency arbitrarily indicated using thick dashed lines. In an exemplary embodiment, a first RF communication signal at a first frequency (f1) is indicated using arrow 703 and a second RF communication signal at a second frequency (f2) is indicated using arrow 705. In an exemplary embodiment, the signals represented by arrows 703 and 705 may be low-band signals at different frequencies in this example.

[0052] In an exemplary embodiment, the phased array 702 may be configured such that a first RF communication signal at a first frequency (f1) 703 is received by some or all of the antenna ports on subarray structures 310d and 310h, and a second RF communication signal at a second frequency (f2) 705 is received by some or all of the antenna ports on subarray structures 310c and 310g. In the example shown in Figure 7, the first RF communication signal at the first frequency (f1) 703 is received by all of the antenna ports on subarray structures 310d and 310h, and the second RF communication signal at the second frequency (f2) 705 is received by all of the antenna ports on subarray structures 310c and 310g. However, RF communication signals may be received by fewer than all of the antenna ports on any given subarray structure by selectively enabling the LNAs 320 and phase shifters 340 on any subarray structure. For example, an RF communication signal may be received by two of four antenna ports on one or more subarrays. A first RF communication signal at a first frequency (f1) 703 from an H-pole antenna port may be provided to a downconverter 401d by a multiplexer in subarray structure 310d and processed by the downconverter 401d, and a first RF communication signal at a first frequency (f1) 703 from a V-pole antenna port may be provided to a downconverter 401h by a multiplexer in subarray structure 310h and processed by the downconverter 401h. For example, downconverter 401d and downconverter 401h may receive a local oscillator (LO) signal at the first frequency and downconvert the first RF communication signal at the first frequency (f1) 703 to a first intermediate frequency (IF1) signal 713.

[0053] A second RF communication signal at a second frequency (f2) 705 from the H-pole antenna port may be provided to downconverter 401c by a multiplexer in subarray structure 310c and processed by downconverter 401c, and a second RF communication signal at a second frequency (f2) 705 from the V-pole antenna port may be provided to downconverter 401g by a multiplexer in subarray structure 310g and processed by downconverter 401g. For example, downconverter 401c and downconverter 401g may receive a local oscillator (LO) signal at the second frequency and downconvert the second communication signal at the second frequency (f2) 705 to a second intermediate frequency (IF2) signal 715.

[0054] The output of downconverter 401d having a first communication signal at a first intermediate frequency (IF1) 713 may be provided to combining circuit 501a, and the output of downconverter 401h having a first communication signal at a first intermediate frequency (IF1) 713 may be provided to combining circuit 501b.

[0055] The output of the downconverter 401c having a second communication signal at a second intermediate frequency (IF2) 715 may be provided to the combining circuit 501a, and the output of the downconverter 401g having a second communication signal at a second intermediate frequency (IF2) 715 may be provided to the combining circuit 501b.

[0056] The output IF_1 of the combining circuit 501a may comprise intermediate frequency (IF) signals 713 and 715 corresponding to a first communication signal at a first frequency (f1) 703 and a second communication signal at a second frequency (f2) 705, respectively.

[0057] The output IF_2 of the combining circuit 501b may comprise intermediate frequency (IF) signals 713 and 715 corresponding to a first communication signal at a first frequency (f1) 703 and a second communication signal at a second frequency (f2) 705, respectively.

[0058] In an exemplary embodiment, the phase shifters in subarray structure 310d and subarray structure 310h may be configured to operate on a first RF communication signal at a first frequency (f1) 703 to generate a given beam angle at the output of subarray structure 310d and the output of subarray structure 310h, and the phase shifters in subarray structure 310c and subarray structure 310g may be configured to operate on a second RF communication signal at a second frequency (f2) 705 to generate a given beam angle at the output of subarray structure 310c and the output of subarray structure 310h. For example, to generate a given beam angle at the output of subarray structure 310d, the phase shifters 340 (FIG. 3) in subarray structure 310d would be independently and individually controlled to generate the desired beam angle. For example, the phase shift applied by each of the phase shifters in a given subarray structure, in this example 310d, may be controlled to apply the same or different phase shifts to result in the desired beam angle for the signal at the output of the subarray structure. The phase shifters 340 in all subarray structures may be similarly controlled to generate a given beam angle. In this manner, independent beam management (IBM) may be provided for a first RF communication signal at a first frequency (f1) 703 and a second RF communication signal at a second frequency (f2) 705. Furthermore, as noted above, using fewer than all of the antenna ports in a subarray may contribute to providing IBM.

[0059] In this way, two different radio frequency communication signals can be separately received and downconverted to IF to provide independent beam management (IBM) in a carrier aggregation (CA) system. In an exemplary embodiment, the phased array 702 enables independent beam management (IBM) and CA, and also allows the common beam management (CBM) MRTD requirement to be relaxed to approximately 8 μsec instead of the stringent 0.26 μsec MRTD requirement.

[0060] The example in Figure 7 illustrates L+L IBM CA operation. However, the structure of the phased array 702 is also capable of processing signals in LB MIMO operation. For example, two instances of the same frequency signal can be received separately by subarray structure 310c and subarray structure 310d and processed independently using different phase shift settings, thus providing independent beam management. Similarly, two instances of the same frequency signal can be received separately by subarray structure 310g and subarray structure 310h and processed independently using different phase shift settings.

[0061] FIG. 8 shows a schematic diagram 800 of an exemplary embodiment of a phased array 802. In FIG. 8, the phased array 802 is configured for mid / high band multiple-input multiple-output (M / HB MIMO) and configured to process two mid / high band (M / HB) signals using independent beam management (IBM). Components in this example that may process a first communication signal at a first frequency are arbitrarily indicated using thick dotted lines, and components in this example that may process a second communication signal at a second frequency are arbitrarily indicated using thick dashed lines. In the exemplary embodiment, the phased array 802 will be described in the context of processing a single signal in MIMO operation. However, the phased array 802 may also process signals having multiple frequencies. In the exemplary embodiment, a first RF communication signal at a first frequency (f1) is indicated using arrow 803. In the exemplary embodiment, the signal represented by arrow 803 may be a high band signal or a mid band signal. The processing of signal 803 is described in the following example.

[0062] In an exemplary embodiment, phased array 802 may be configured such that a first RF communication signal at a first frequency (f1) 803 is received by subarray structures 310a and 310e and by subarray structures 310b and 310f. In the example shown in Figure 8, fewer than all LNAs and phase shifters are enabled in subarray structures 310a, 310b, 310e, and 310f, and two exemplary LNAs and phase shifters are shown enabled. Fewer LNAs and phase shifters may be enabled in each subarray structure 310.

[0063] A first RF communication signal at a first frequency (f1) 803 from the H-pole antenna port may be provided to downconverter 401a by a multiplexer in subarray structure 310a and processed by downconverter 401a and downconverter 401b, and a first RF communication signal at a first frequency (f1) 803 from the V-pole antenna port may be provided to downconverter 401e by a multiplexer in subarray structure 310e and processed by downconverter 401e and downconverter 401f. For example, downconverter 401a and downconverter 401e may receive a first local oscillator (LO) signal from synthesizer 612 at a first frequency and downconvert a first RF communication signal at a first frequency (f1) 803 to a first intermediate frequency (IF1) signal 813, and downconverter 401b and downconverter 401f may receive a second local oscillator (LO) signal (the LO signal is shown as a thick solid line) from synthesizer 614 at a second frequency and downconvert the first RF communication signal at the first frequency (f1) 803 to a second intermediate frequency (IF2) signal 817.

[0064] The output of the downconverter 401a having the first communication signal 803 at the first intermediate frequency (IF1) 813 and the output of the downconverter 401b having the first communication signal 803 at the second intermediate frequency (IF2) 817 may be provided to the combining circuit 501a, and the output of the downconverter 401e having the first communication signal 803 at the first intermediate frequency (IF1) 813 and the output of the downconverter 401f having the first communication signal 803 at the second intermediate frequency (IF2) 817 may be provided to the combining circuit 501b.

[0065] The output IF_1 of the combiner circuit 501a may comprise intermediate frequency (IF) signals 813 and 817 corresponding to a first RF communication signal at a first frequency (f1) 803.

[0066] The output IF_2 of the combiner circuit 501b may comprise intermediate frequency (IF) signals 813 and 817 corresponding to the first RF communication signal at the first frequency (f1) 803.

[0067] In an exemplary embodiment, the phase shifters in subarray structure 310a, subarray structure 310b, subarray structure 310e, and subarray structure 310f may be configured to operate on a first RF communication signal at a first frequency (f1) 803, thereby providing independent beam management (IBM) for instances of the first RF communication signal at the first frequency (f1) 803. Additionally, as described above, enabling a subset of the LNAs and / or phase shifters within a subarray may contribute to providing IBM.

[0068] In this way, a single radio frequency communication signal may be separately received in a MIMO architecture and downconverted to two or more separate IF signals to provide M / HB MIMO using independent beam management (IBM). In an exemplary embodiment, the phased array 802 enables independent beam management (IBM) and also allows the MRTD requirement to be relaxed to approximately 8 μsec instead of the stringent common beam management (CBM) MRTD requirement of 0.26 μsec.

[0069] FIG. 9 shows a schematic diagram 900 of an exemplary embodiment of a phased array 902. In FIG. 9, the phased array 902 is configured for mid-+high-band carrier aggregation (M+HB CA) and configured to process two mid- / high-band (M / HB) signals using independent beam management (IBM). Components in this example that process a first RF communication signal at a first frequency are optionally shown using thick dotted lines, and components in this example that process a second RF communication signal at a second frequency are optionally shown using thick dashed lines. In an exemplary embodiment, the first RF communication signal at a first frequency (f1) is shown using arrow 903, and the second RF communication signal at a second frequency (f2) is shown using arrow 905. In an exemplary embodiment, the signals represented by arrows 903 and 905 may be high-band or mid-band signals at different frequencies in this example.

[0070] In an exemplary embodiment, phased array 902 may be configured such that a first RF communication signal at a first frequency (f1) 903 is a high-band (HB) signal and is received by subarray structures 310a and 310e, and a second RF communication signal at a second frequency (f2) 905 is a mid-band (MB) signal and is received by subarray structures 310b and 310f. In the example shown in Figure 9, fewer than all LNAs and phase shifters are enabled in subarray structures 310a, 310b, 310e, and 310f, and two exemplary LNAs and phase shifters are shown enabled. More or fewer LNAs and phase shifters may be enabled in each subarray structure 310.

[0071] A first RF communication signal at a first frequency (f1) 903 from the H-pole antenna port may be provided to downconverter 401a by a multiplexer in subarray structure 310a and processed by downconverter 401a, and a first RF communication signal at a first frequency (f1) 903 from the V-pole antenna port may be provided to downconverter 401e by a multiplexer in subarray structure 310e and processed by downconverter 401e. For example, downconverter 401a and downconverter 401e may receive a local oscillator (LO) signal at the first frequency and downconvert the first RF communication signal at the first frequency (f1) 903 to a first intermediate frequency (IF1) signal 913.

[0072] A second RF communication signal at a second frequency (f2) 905 from the H-pole antenna port may be provided to downconverter 401b by a multiplexer in subarray structure 310b and processed by downconverter 401b, and a second communication signal at a second frequency (f2) 905 from the V-pole antenna port may be provided to downconverter 401f by a multiplexer in subarray structure 310f and processed by downconverter 401f. For example, downconverter 401b and downconverter 401f may receive a local oscillator (LO) signal at the second frequency and downconvert the second RF communication signal at the second frequency (f2) 905 to a second intermediate frequency (IF2) signal 915.

[0073] The output of the downconverter 401a having a first communication signal at a first intermediate frequency (IF1) 913 may be provided to the combining circuit 501a, and the output of the downconverter 401e having a first communication signal at a first intermediate frequency (IF1) 913 may be provided to the combining circuit 501b.

[0074] The output of the downconverter 401b having a second communication signal at a second intermediate frequency (IF2) 915 may be provided to the combining circuit 501a, and the output of the downconverter 401f having a second communication signal at a second intermediate frequency (IF2) 915 may be provided to the combining circuit 501b.

[0075] The output IF_1 of the combining circuit 501a may have intermediate frequency (IF) signals 913 and 915 corresponding to a first RF communication signal at a first frequency (f1) 903 and a second RF communication signal at a second frequency (f2) 905, respectively.

[0076] The output IF_2 of the combining circuit 501b may have intermediate frequency (IF) signals 913 and 915 corresponding to a first RF communication signal at a first frequency (f1) 903 and a second RF communication signal at a second frequency (f2) 905, respectively.

[0077] In an exemplary embodiment, the phase shifters in subarray structure 310a and subarray structure 310e may be configured to operate on a first RF communication signal at a first frequency (f1) 903, and the phase shifters in subarray structure 310b and subarray structure 310f may be configured to operate on a second RF communication signal at a second frequency (f2) 905, thereby providing independent beam management (IBM) for the first RF communication signal at the first frequency (f1) 903 and the second RF communication signal at the second frequency (f2) 905.

[0078] In this way, two different radio frequency communication signals can be separately received and downconverted to IF to provide M+HB CA using independent beam management (IBM). Furthermore, as described above, enabling fewer than all of the LNAs and / or phase shifters in the subarray can contribute to providing IBM. In an exemplary embodiment, the phased array 902 enables independent beam management (IBM) and also allows the MRTD requirement to be relaxed to approximately 8 μsec instead of the stringent common beam management (CBM) MRTD requirement of 0.26 μsec.

[0079] FIG. 10 shows a schematic diagram 1000 of an exemplary embodiment of a phased array 1002. In FIG. 10, the phased array 1002 is configured for low + mid / high band carrier aggregation (L+M / H CA) and configured to simultaneously process low-band and mid / high-band (L / M / H) signals using independent beam management (IBM) and carrier aggregation (CA). Components in this example that process a first communication signal at a first frequency are optionally shown using thick dotted lines, and components in this example that process a second communication signal at a second frequency are optionally shown using thick dashed lines. In an exemplary embodiment, a first RF communication signal at a first frequency (f1) is shown using arrow 1003, and a second RF communication signal at a second frequency (f2) is shown using arrow 1005. In an exemplary embodiment, the signals represented by arrows 1003 and 1005 may be a low-band signal and a mid / high-band signal at different frequencies in this example.

[0080] In an exemplary embodiment, phased array 1002 may be configured such that a first RF communication signal at a first frequency (f1) 1003 is a low-band (LB) signal and is received by subarray structure 310c, subarray structure 310d, subarray structure 310g, and subarray structure 310h, and a second RF communication signal at a second frequency (f2) 1005 is a mid / high-band (M / HB) signal and is received by subarray structure 310a, subarray structure 310b, subarray structure 310e, and subarray structure 310f. In the example shown in Figure 8, fewer than all of the LNAs and phase shifters are enabled in subarray structures 310a, 310b, 310c, 310d, 310e, 310f, 310g, and 310h, and two exemplary LNAs and phase shifters are shown enabled. In each subarray structure 310, more or fewer LNAs and phase shifters may be enabled.

[0081] A first RF communication signal at a first frequency (f1) 1003 from the H-pole antenna port may be provided to downconverter 401 d by multiplexers in subarray structures 310 c and 310 d and processed by downconverter 401 d, and a first RF communication signal at a first frequency (f1) 1003 from the V-pole antenna port may be provided to downconverter 401 h by multiplexers in subarray structures 310 g and 310 h and processed by downconverter 401 h. For example, downconverter 401 d and downconverter 401 h may receive a local oscillator (LO) signal at the first frequency and downconvert the first RF communication signal at the first frequency (f1) 1003 to a first intermediate frequency (IF1) signal 1013.

[0082] A second RF communication signal at a second frequency (f2) 1005 from the H-pole antenna port may be provided to downconverter 401a by multiplexers in subarray structures 310a and 310b and processed by downconverter 401a, and a second RF communication signal at a second frequency (f2) 1005 from the V-pole antenna port may be provided to downconverter 401e by multiplexers in subarray structures 310e and 310f and processed by downconverter 401e. For example, downconverter 401a and downconverter 401e may receive a local oscillator (LO) signal at the second frequency and downconvert the second RF communication signal at the second frequency (f2) 1005 to a second intermediate frequency (IF2) signal 1015.

[0083] The output of downconverter 401d having a first RF communication signal at a first intermediate frequency (IF1) 1013 may be provided to combining circuit 501a, and the output of downconverter 401h having a first communication signal at a first intermediate frequency (IF1) 10013 may be provided to combining circuit 501b.

[0084] The output of the downconverter 401a having a second communication signal at a second intermediate frequency (IF2) 1015 may be provided to the combining circuit 501a, and the output of the downconverter 401e having a second communication signal at a second intermediate frequency (IF2) 1015 may be provided to the combining circuit 501b.

[0085] The output IF_1 of the combining circuit 501a may have intermediate frequency (IF) signals 1013 and 1015 corresponding to a first RF communication signal at a first frequency (f1) 1003 and a second RF communication signal at a second frequency (f2) 1005, respectively.

[0086] The output IF_2 of the combining circuit 501b may have intermediate frequency (IF) signals 1013 and 1015 corresponding to a first RF communication signal at a first frequency (f1) 1003 and a second RF communication signal at a second frequency (f2) 1005, respectively.

[0087] In an exemplary embodiment, the phase shifters in subarray structure 310c, subarray structure 310d, subarray structure 310g, and subarray structure 310h may be configured to operate on a first RF communication signal at a first frequency (f1) 1003, and the phase shifters in subarray structure 310a, subarray structure 310b, subarray structure 310e, and subarray structure 310f may be configured to operate on a second RF communication signal at a second frequency (f2) 1005, thereby providing independent beam management (IBM) for the first RF communication signal at the first frequency (f1) 1003 and the second RF communication signal at the second frequency (f2) 1005.

[0088] In this manner, two different radio frequency communication signals can be separately received and downconverted to IF to provide L+ / MH CA using independent beam management (IBM). Furthermore, as described above, enabling a subset of LNAs and / or phase shifters within a subarray can contribute to providing IBM. In an exemplary embodiment, the phased array 1002 enables independent beam management (IBM) and also allows the MRTD requirement to be relaxed to approximately 8 μsec instead of the stringent common beam management (CBM) MRTD requirement of 0.26 μsec. In FIGS. 7-10 , the data processor 210 can be coupled to the IF port (e.g., through other processing circuitry) and configured to receive the processed signals (e.g., CA, MIMO, and / or IBM signals) and further process them to extract information related to the wireless communication.

[0089] 11 is a flowchart illustrating an example of the operation of a method 1100 for signal processing. The blocks in the method 1100 may be performed in the order shown or out of the order shown, and in some embodiments may be performed at least partially in parallel.

[0090] In block 1102, a first radio frequency (RF) signal and a second RF signal are received at an RF receiver. For example, a first RF signal 703 at a first frequency may be received in subarray structure 310d on the low-band H-pole quadrant 650 by subarray structure 310h on the low-band V-pole quadrant 670, and a second RF signal 705 at a second frequency may be received in subarray structure 310c on the low-band H-pole quadrant 650 by subarray structure 310g on the low-band V-pole quadrant 670.

[0091] In block 1104, the first RF signal and the second RF signal are simultaneously downconverted to a first intermediate frequency (IF1) signal and a second IF2 signal. For example, downconverter 401d and downconverter 401h may downconvert the first RF signal 703 to a first IF signal 713, and downconverter 401c and downconverter 401g may downconvert the second RF signal 705 to a second IF signal 715.

[0092] In block 1106, the first IF signal and the second IF signal are provided on a single output port. For example, the first IF signal 713 and the second IF signal 715 may be provided simultaneously at the IF_1 port at the output of the combining circuit 501a, and the first IF signal 713 and the second IF signal 715 may be provided simultaneously at the IF_2 port at the output of the combining circuit 501b.

[0093] 12 is a functional block diagram of an apparatus for signal processing. The apparatus 1200 comprises a means 1202 for receiving a first radio frequency (RF) signal and a second RF signal. In a particular embodiment, the means 1202 for receiving the first radio frequency (RF) signal and the second RF signal may be configured to perform one or more of the functions described in operational block 1102 of method 1100 (FIG. 11). In an exemplary embodiment, the means 1202 for receiving the first RF signal and the second RF signal may comprise subarray structure 310d on the low-band H pole quadrant 650 and subarray structure 310h on the low-band V pole quadrant 670 configured to receive the first RF signal 703, and subarray structure 310c on the low-band H pole quadrant 650 and subarray structure 310g on the low-band V pole quadrant 670 configured to receive the second RF signal 705.

[0094] Apparatus 1200 also comprises means 1204 for simultaneously downconverting the first RF signal and the second RF signal to a first intermediate frequency (IF1) signal and a second IF2 signal. In a particular embodiment, means 1204 for simultaneously downconverting the first RF signal and the second RF signal to a first intermediate frequency (IF1) signal and a second IF2 signal may be configured to perform one or more of the functions described in operational block 1104 of method 1100 (FIG. 11). In an exemplary embodiment, means 1204 for simultaneously downconverting the first RF signal and the second RF signal to a first intermediate frequency (IF1) signal and a second IF2 signal may comprise downconverters 401d and 401h configured to downconvert the first RF signal 703 to a first IF signal 713, and downconverters 401c and 401g configured to downconvert the second RF signal 705 to a second IF signal 715.

[0095] Apparatus 1200 also comprises means 1206 for providing the first IF signal and the second IF signal on a single output port. In particular embodiments, means 1206 for providing the first IF signal and the second IF signal on a single output port may be configured to perform one or more of the functions described in operational block 1106 of method 1100 (FIG. 11). In an exemplary embodiment, means 1206 for providing the first IF signal and the second IF signal on a single output port may comprise circuitry configured to simultaneously provide the first IF signal 713 and the second IF signal 715 at an IF_1 port at the output of combining circuit 501a and circuitry configured to simultaneously provide the first IF signal 713 and the second IF signal 715 at an IF_2 port at the output of combining circuit 501b, e.g., combining circuit(s) 501.

[0096] 13 is a flowchart illustrating an example of the operation of a method 1300 for signal processing. The blocks in the method 1300 may be performed in the order shown or out of the order shown, and in some embodiments may be performed at least partially in parallel.

[0097] In block 1302, a first radio frequency (RF) signal is received at an RF receiver. For example, the first RF signal 803 may be received in the subarray structure 310a on the high-band H-pole quadrant 640 by the subarray structure 310e on the high-band V-pole quadrant 660, and the first RF signal 803 may be received in the subarray structure 310b on the high-band H-pole quadrant 640 by the subarray structure 310f on the high-band V-pole quadrant 660.

[0098] In block 1304, the first RF signal is simultaneously downconverted to a first intermediate frequency (IF1) signal and a second intermediate frequency (IF2) signal. For example, downconverter 401a and downconverter 401e may downconvert the first RF signal 803 to a first IF signal 813, and downconverter 401b and downconverter 401f may downconvert the first RF signal 803 to a second IF signal 817.

[0099] In block 1306, the first IF signal 813 and the second IF signal 817 are provided on a first output port and a second output port. For example, the first IF signal 813 and the second IF signal 817 may be simultaneously provided at the IF_1 port at the output of the combining circuit 501a and at the IF_2 port at the output of the combining circuit 501b.

[0100] 14 is a functional block diagram of an apparatus for signal processing. The apparatus 1400 comprises a means 1402 for receiving a first radio frequency (RF) signal at an RF receiver. In a particular embodiment, the means 1402 for receiving a first radio frequency (RF) signal at an RF receiver may be configured to perform one or more of the functions described in operational block 1302 of method 1300 (FIG. 13). In an exemplary embodiment, the means 1402 for receiving a first radio frequency (RF) signal at an RF receiver may comprise a subarray structure 310a configured to receive the first RF signal 803 on the highband H-pole quadrant 640, a subarray structure 310e configured to receive the first RF signal 803 on the highband V-pole quadrant 660, a subarray structure 310b configured to receive the first RF signal 803 on the highband H-pole quadrant 640, and a subarray structure 310f configured to receive the first signal 803 on the highband V-pole quadrant 660.

[0101] The apparatus 1400 also comprises means 1404 for simultaneously downconverting the first RF signal to a first intermediate frequency (IF1) signal and a second intermediate frequency (IF2) signal. In particular embodiments, the means 1404 for simultaneously downconverting the first RF signal to a first intermediate frequency (IF1) signal and a second intermediate frequency (IF2) signal may be configured to perform one or more of the functions described in operation block 1304 of the method 1300 (FIG. 13). In an exemplary embodiment, the means 1404 for simultaneously downconverting the first RF signal to a first intermediate frequency (IF1) signal and a second intermediate frequency (IF2) signal may comprise downconverters 401a and 401e configured to downconvert the first RF signal 803 to a first IF signal 813, and downconverters 401b and 401f configured to downconvert the first RF signal 803 to a second IF signal 817.

[0102] Apparatus 1400 also comprises means 1406 for providing the first IF1 signal and the second IF2 signal on the first output port and the second output port. In particular embodiments, means 1406 for providing the first IF1 signal and the second IF2 signal on the first output port and the second output port may be configured to perform one or more of the functions described in operational block 1306 of method 1300 (FIG. 13). In an exemplary embodiment, means 1406 for providing the first IF1 signal and the second IF2 signal on the first output port and the second output port may comprise circuitry configured to simultaneously provide the first IF1 signal 813 and the second IF2 signal 817 at an IF_1 port at the output of combining circuit 501a and circuitry configured to simultaneously provide the first IF1 signal 813 and the second IF2 signal 817 at an IF_2 port at the output of combining circuit 501b, e.g., combining circuit(s) 501.

[0103] Example implementations are described in the following numbered clauses. 1. A receiving system for performing carrier aggregation (CA) and multiple-input multiple-output (MIMO) operations at millimeter wave (mmW) frequencies, comprising: a phased array having a plurality of groupings, each grouping having a pair of subarray structures, each subarray structure having a plurality of phased array elements and a multiplexer, each phased array element coupled to an antenna element, each phased array element having a low noise amplifier (LNA) and a phase shifter (PS), the plurality of groupings including a first high band (HB) grouping and a first low band (LB) grouping; 1. A receiving system comprising: downconverter circuits selectively connected to each subarray structure in a first high band (HB) grouping and a first low band (LB) grouping, each downconverter circuit having a radio frequency (RF) amplifier, a mixer, an intermediate frequency (IF) amplifier, and a filter; and a combining circuit connected to each of the downconverter circuits selectively connected to the first high band (HB) grouping and the first low band (LB) grouping, the combining circuit configured to provide a signal from each downconverter circuit to an intermediate frequency (IF) port. 2. The system described in clause 1, further comprising a first (HB) synthesizer configured to generate a first local oscillator (LO) signal and a second (LB) synthesizer configured to generate a second local oscillator (LO) signal, wherein the first and second LO signals are configured to be provided to either of the downconverter circuits. 3. The system of clause 1 or 2, wherein each subarray structure is configured to provide independent beam management, including independent phase shifts between the subarray structures. 4. The system of clause 2 or 3, wherein the antenna elements include a split antenna array and are configured to achieve inter-band carrier aggregation (CA) and independent beamforming (IBF) for 4x4 multiple-input multiple-output (MIMO) signal processing. 5. A system described in any of clauses 2 to 4, wherein the receiving system is configured to receive at least two radio frequency signals having different frequencies in two or more subarray structures. 6. A system described in any of clauses 2 to 5, wherein the receiving system is configured to receive at least two radio frequency signals having the same frequency in two or more subarray structures. 7. The system of clause 5, wherein the receiving system is configured to simultaneously downconvert two radio frequency signals at different frequencies into corresponding first and second intermediate frequency signals, and to provide the first and second intermediate frequency signals on a single output port. 8. The system of clause 6, wherein the receiving system is configured to simultaneously downconvert two radio frequency signals at the same radio frequency to a first intermediate frequency signal and a second intermediate frequency signal, and to simultaneously provide the first intermediate frequency signal and the second intermediate frequency signal on a single output port. 9. The system of any of clauses 2-8, wherein the plurality of groupings includes four quadrants, and each antenna element has a horizontally polarized output and a vertically polarized output. 10. A system described in any of clauses 2 to 9, wherein the IF port includes at least a first output pin (IF_1), and a first intermediate frequency (IF) signal and a second IF signal are provided on the first output pin (IF_1). 11. A method for signal processing, comprising: receiving at least two radio frequency (RF) signals at a receiver; selectively phase shifting the at least two radio frequency (RF) signals; selectively directing the at least two phase-shifted radio frequency (RF) signals to selected downconverter circuits; simultaneously downconverting the at least two RF signals to intermediate frequency (IF) signals; and connecting the at least two IF signals to at least one selected output port. 12. The method of clause 11, wherein at least two radio frequency signals have different frequencies and are received at different receiver sub-array structures. 13. The method of clause 11 or 12, wherein at least two radio frequency signals have the same frequency and are received at different receiver sub-array structures. 14. The method of any of clauses 11-13, further comprising selectively routing at least two IF signals from any of the plurality of subarray structures to either the first output port or the second output port. 15. The method of any of clauses 11-14, further comprising selectively amplifying and phase shifting at least two RF signals. 16. A device comprising: means for receiving at least two radio frequency (RF) signals at a receiver; means for selectively phase shifting the at least two radio frequency (RF) signals; means for selectively directing the at least two phase-shifted radio frequency (RF) signals to selected downconverter circuits; means for simultaneously downconverting the at least two RF signals to intermediate frequency (IF) signals; and means for connecting the at least two IF signals to at least one selected output port. 17. The device of clause 16, further comprising means for receiving at least two radio frequency signals having different frequencies in different receiver sub-array structures. 18. The device of clause 16 or 17, further comprising means for receiving at least two radio frequency signals having the same frequency in different receiver sub-array structures. 19. The device of any of clauses 16-18, further comprising means for selectively routing at least two IF signals from any of a plurality of sub-array structures to either the first output port or the second output port. 20. A device according to any of clauses 16-19, further comprising means for selectively amplifying and phase shifting at least two RF signals. 21. A wireless system architecture comprising: a receiver having multiple subarrays in a phased array, the multiple subarrays configured to perform carrier aggregation (CA) and multiple-input multiple-output (MIMO) signal processing and provide independent beam management for multiple radio frequency (RF) signals received at each of the multiple subarrays; and a data processor configured to receive signals from the receiver and extract information related to the wireless communication. 22. The radio system architecture of clause 21, wherein the phased array has 16 antenna elements. 23. A radio system architecture as defined in clause 21 or 22, wherein at least two radio frequency signals are received in two or more sub-arrays and have different frequencies. 24. A radio system architecture as defined in clause 21 or 22, wherein at least two radio frequency signals are received in two or more sub-arrays and have the same frequency. 25. A radio system architecture according to any of clauses 21 to 24, wherein the architecture is configured to simultaneously downconvert two radio frequency signals at different frequencies into corresponding first and second intermediate frequency signals, and to provide the first and second intermediate frequency signals on a single output port. 26. A radio system architecture according to any of clauses 21 to 24, wherein the architecture is configured to simultaneously downconvert two radio frequency signals at the same radio frequency to a first intermediate frequency signal and a second intermediate frequency signal, and to simultaneously provide the first intermediate frequency signal and the second intermediate frequency signal on a single output port.

[0104] The circuit architectures described herein may be implemented on one or more ICs, analog ICs, RFICs, mixed-signal ICs, ASICs, printed circuit boards (PCBs), electronic devices, etc. The circuit architectures described herein may also be fabricated using various IC process technologies, such as complementary metal-oxide semiconductor (CMOS), N-channel MOS (NMOS), P-channel MOS (PMOS), bipolar junction transistor (BJT), bipolar CMOS (BiCMOS), silicon germanium (SiGe), gallium arsenide (GaAs), heterojunction bipolar transistors (HBTs), high electron mobility transistors (HEMTs), silicon-on-insulator (SOI), etc.

[0105] An apparatus implementing the circuits described herein may be a standalone device or may be part of a larger device, which may be (i) a standalone IC, (ii) a set of one or more ICs that may include memory ICs for storing data and / or instructions, (iii) an RFIC such as an RF receiver (RFR) or an RF transmitter / receiver (RTR), (iv) an ASIC such as a mobile station modem (MSM), (v) a module that may be embedded within another device, (vi) a receiver, mobile phone, wireless device, handset, or mobile unit, (vii), etc.

[0106] While selected aspects have been illustrated and described in detail, it will be understood that various substitutions and changes can be made in those aspects without departing from the spirit and scope of the invention as defined by the following claims.

Claims

1. 1. A receiving system for performing carrier aggregation (CA) and multiple-input multiple-output (MIMO) operations at millimeter wave (mmW) frequencies, comprising: a phased array having a plurality of groupings, each grouping having a pair of subarray structures, each subarray structure having a plurality of phased array elements and a multiplexer, each phased array element coupled to an antenna element, each phased array element having a low noise amplifier (LNA) and a phase shifter (PS), the plurality of groupings including a first high band (HB) grouping and a first low band (LB) grouping; a downconverter circuit selectively connected to each subarray structure in the first high-band (HB) grouping and the first low-band (LB) grouping, each downconverter circuit including a radio frequency (RF) amplifier, a mixer, an intermediate frequency (IF) amplifier, and a filter; a combining circuit connected to each of the downconverter circuits selectively connected to the first high band (HB) grouping and the first low band (LB) grouping, the combining circuit configured to provide a signal from each downconverter circuit to an intermediate frequency (IF) port.

2. a first (HB) synthesizer configured to generate a first local oscillator (LO) signal; 10. The system of claim 1, further comprising: a second (LB) synthesizer configured to generate a second local oscillator (LO) signal, the first and second LO signals configured to be provided to either of the downconverter circuits.

3. The system of claim 1 , wherein each subarray structure is configured to provide independent beam management including independent phase shifts between the subarray structures.

4. 10. The system of claim 1, wherein the antenna elements include a split antenna array and are configured to implement independent beamforming (IBF) for inter-band carrier aggregation (CA) and 4x4 multiple-input multiple-output (MIMO) signal processing.

5. The system of claim 1 , wherein the receiving system is configured to receive at least two radio frequency signals having different frequencies in two or more subarray structures.

6. The system of claim 1 , wherein the receiving system is configured to receive at least two radio frequency signals having the same frequency in two or more subarray structures.

7. 6. The system of claim 5, wherein the receiving system is configured to simultaneously downconvert the at least two radio frequency signals at different frequencies to corresponding first and second intermediate frequency signals and provide the first and second intermediate frequency signals on a single output port.

8. 7. The system of claim 6, wherein the receiving system is configured to simultaneously downconvert the at least two radio frequency signals at the same radio frequency to a first intermediate frequency signal and a second intermediate frequency signal, and to simultaneously provide the first intermediate frequency signal and the second intermediate frequency signal on a single output port.

9. The system of claim 1 , wherein the plurality of groupings include four quadrants, and each antenna element has a horizontally polarized output and a vertically polarized output.

10. 2. The system of claim 1, wherein the IF port includes at least a first output pin (IF_1), and a first intermediate frequency (IF) signal and a second IF signal are provided on the first output pin (IF_1).

11. 1. A method for signal processing, comprising: receiving at least two radio frequency (RF) signals at a receiver; selectively phase-shifting the at least two radio frequency (RF) signals; Selectively directing the at least two phase-shifted radio frequency (RF) signals to selected downconverter circuits; simultaneously downconverting the at least two RF signals to an intermediate frequency (IF) signal; and connecting the at least two IF signals to at least one selected output port.

12. The method of claim 11 , wherein the at least two radio frequency signals have different frequencies and are received at different receiver sub-array structures.

13. The method of claim 11 , wherein the at least two radio frequency signals have the same frequency and are received at different receiver sub-array structures.

14. 12. The method of claim 11, further comprising selectively routing the at least two IF signals from any of a plurality of sub-array structures to any of a first output port and a second output port.

15. The method of claim 11 , further comprising selectively amplifying and phase shifting the at least two RF signals.

16. A device, means for receiving at least two radio frequency (RF) signals at a receiver; means for selectively phase shifting the at least two radio frequency (RF) signals; means for selectively directing the at least two phase-shifted radio frequency (RF) signals to selected downconverter circuits; means for simultaneously downconverting the at least two RF signals to an intermediate frequency (IF) signal; means for connecting the at least two IF signals to at least one selected output port.

17. 17. The device of claim 16, further comprising: means for receiving the at least two radio frequency signals having different frequencies in different receiver subarray structures.

18. 17. The device of claim 16, further comprising: means for receiving the at least two radio frequency signals having the same frequency in different receiver subarray structures.

19. 17. The device of claim 16, further comprising: means for selectively routing the at least two IF signals from any of a plurality of sub-array structures to either a first output port or a second output port.

20. 17. The device of claim 16, further comprising means for selectively amplifying and phase shifting the at least two RF signals.

21. 1. A radio system architecture, comprising: a receiver having multiple subarrays in a phased array, the multiple subarrays configured to perform carrier aggregation (CA) and multiple-input multiple-output (MIMO) signal processing and to provide independent beam management for multiple radio frequency (RF) signals received at each of the multiple subarrays; a data processor configured to receive signals from the receiver and extract information related to the wireless communication.

22. 22. The wireless system architecture of claim 21, wherein the phased array has 16 antenna elements.

23. 22. The radio system architecture of claim 21, wherein at least two radio frequency signals are received at two or more sub-arrays and have different frequencies.

24. 22. The wireless system architecture of claim 21, wherein at least two radio frequency signals are received at two or more sub-arrays and have the same frequency.

25. 24. The radio system architecture of claim 23, wherein the radio system architecture is configured to simultaneously downconvert the at least two radio frequency signals at different frequencies to corresponding first and second intermediate frequency signals and provide the first and second intermediate frequency signals on a single output port.

26. 25. The radio system architecture of claim 24, wherein the radio system architecture is configured to simultaneously downconvert the at least two radio frequency signals at the same radio frequency to a first intermediate frequency signal and a second intermediate frequency signal, and to simultaneously provide the first intermediate frequency signal and the second intermediate frequency signal on a single output port.

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