Semiconductor device and manufacturing method thereof

Abstract

The semiconductor device (100) comprises a semiconductor body (10) having a top surface (11) and a bottom surface (19). A first main electrode (2) is disposed on the top surface, and a second main electrode (3) is disposed on the bottom surface. The semiconductor device comprises a gate electrode (3) and at least two trenches, namely, a first type trench (51) and a second type trench (52). The semiconductor body includes a drift region (14) disposed vertically between the top surface and the bottom surface, and at least two base regions (13a, 13b), each disposed vertically between the drift region and the top surface. The semiconductor body further includes an implantation region (12) adjacent to the first base region. The first main electrode is in electrical contact with the implantation region. A gate electrode extends into the first type trench. The second type trench is free of a gate electrode. The second type trench extends deeper into the semiconductor body than the first type trench.

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] There is a need for improved semiconductor devices, for example, semiconductor devices having improved static and / or dynamic behavior, and there is a further need to provide methods for manufacturing such semiconductor devices. Summary of the Invention [Means for solving the problem]

[0003] TECHNICAL FIELD Embodiments of the present disclosure relate to a semiconductor device and a method for manufacturing the semiconductor device. First, the present semiconductor device will be described.

[0004] According to one embodiment, the semiconductor device comprises a semiconductor body extending vertically between a top surface and a bottom surface. A first main electrode is disposed on the top surface, and a second main electrode is disposed on the bottom surface. The semiconductor device further comprises a gate electrode and at least two trenches, i.e., a first type trench and a second type trench, each extending from the top surface into the semiconductor body. The semiconductor body includes a drift region of a first conductivity type vertically disposed between the top surface and the bottom surface, and at least two base regions, i.e., a first and a second base region, each of which is of a second conductivity type and vertically disposed between the drift region and the top surface. The semiconductor body further includes an implantation region of the first conductivity type vertically spaced from the drift region by the first base region and adjacent to the first base region. The first base region, the first type trench, the second base region, and the second type trench are disposed in this order in a first lateral direction. The first main electrode is in electrical contact with the implantation region. The gate electrode extends into the first type of trench, where it is separated from the semiconductor body by a gate insulating layer. The second type of trench is devoid of a gate electrode and extends deeper into the semiconductor body than the first type of trench.

[0005] Long-term performance stability of semiconductor devices such as IGBTs requires robustness against gate insulator degradation. Gate insulator degradation can be caused by dynamic avalanche during high-current turn-off switching events. Charge carriers generated by dynamic avalanche can have enough energy to be injected into the gate insulator, altering the gate capacitance and therefore the switching characteristics of the semiconductor device (e.g., by varying the switching speed and threshold voltage). Gate insulator degradation is a design challenge, particularly for trench-structured semiconductor devices, due to the peak of avalanche generation near the gate insulator at the bottom of the trench.

[0006] Therefore, a technical challenge is to provide a semiconductor device that improves the tradeoff between long-term stability (robustness against degradation of the gate insulating layer) and static loss.

[0007] This problem is solved, inter alia, by having the second-type trenches deeper than the first-type trenches. It has been found that these kinds of second-type trenches effectively protect the first-type trenches (which are active trenches) from hot carriers generated by dynamic avalanches, thereby improving the robustness of the first-type trenches against gate dielectric degradation. Improved robustness against gate dielectric degradation can expand the design space for features that reduce static losses in semiconductor devices.

[0008] The semiconductor device described herein may be a power semiconductor device, for example configured to carry a current of at least 10 A and / or handle a voltage of at least 1000 V or at least 3000 V. The semiconductor device may be a transistor device, particularly a gate-insulated transistor device, especially an IGFET.

[0009] The semiconductor body may be based on silicon or silicon carbide. The thickness of the semiconductor body measured in the vertical direction is, for example, at least 100 μm, or at least 200 μm, and / or at most 500 μm. The top and bottom surfaces are surfaces of the semiconductor body and vertically define the semiconductor body.

[0010] The first and / or second main electrodes may include or consist of a metal. Depending on the type of semiconductor device, the first electrode may be referred to herein as an "emitter electrode" or a "source electrode," and the second main electrode may be referred to herein as a "collector electrode" or a "drain electrode."

[0011] The gate electrode may comprise a metal and / or heavily doped polysilicon. The gate electrode is in particular an insulated gate electrode, i.e., electrically insulated from the semiconductor body. This may be achieved, for example, with the aid of a gate insulating layer.

[0012] The trenches extend from the upper surface of the semiconductor body into the semiconductor body and terminate within the semiconductor body, for example, in the drift region. The depth of the trenches measured in the vertical direction may each be at least 1 μm or at least 5 μm and / or at most 20 μm or at most 10 μm. The trenches may each be elongated and may each extend laterally, the lateral direction being defined herein as the direction perpendicular to the vertical direction. The lateral direction is, in particular, a direction parallel to the main extension plane of the semiconductor body. For example, the trenches extend parallel to each other.

[0013] The first type trenches and the second type trenches may be spaced apart from each other in a first lateral direction. Each trench may extend in a second lateral direction perpendicular to the first lateral direction. The average distance between the first type trenches and the second type trenches is, for example, at least 100 nm or at least 500 nm and / or at most 2 μm. The distance between two trenches is defined herein as, for example, the pitch between the trenches, i.e., the distance between the centers of the trenches. For example, no additional trenches are arranged between the first type trenches and the second type trenches in the lateral direction.

[0014] The first type of trench is filled with a conductive material, which is separated from the semiconductor body by a gate insulating layer. The conductive material is spatially and electrically separated from the semiconductor body by the gate insulating layer. The gate insulating layer may be an oxide, such as SiO2. The gate insulating layer may have a thickness of at least 10 nm and / or at most 200 nm. For example, the gate insulating layer may have a thickness of at least 50 nm and at most 150 nm.

[0015] As used herein, "electrically isolated" particularly means that there is no electrical contact between two elements. Two electrically isolated elements are configured, for example, to be electrically biased or controlled independently of each other. This means that they are configured to be at different potentials during operation of the semiconductor device. Two electrically isolated elements may particularly be electrically insulated from each other, i.e., no current can flow between them.

[0016] The conductive material in the first type trench may be metal and / or heavily doped polysilicon. The conductive material in the first type trench is part of the gate electrode, i.e., electrically connected to the gate electrode. When two elements are electrically connected or in electrical contact, this means that these two elements are not independently electrically biasable or controllable. Therefore, they are always at the same potential. The first type trench is also referred to herein as an "active trench."

[0017] For example, the conductive material in the first type of trench extends into the semiconductor body at least to the same depth as the first base region and / or the second base region.

[0018] The second type of trench is a trench without a gate electrode, i.e., the second type of trench is a trench without a gate electrode, i.e., the second type of trench is electrically isolated from the gate electrode.

[0019] The second type of trench may also be filled with a conductive material, which may be separated from the semiconductor body by an insulating layer. However, this conductive material is electrically isolated from the gate electrode, i.e., not electrically connected to the gate electrode. The insulating layer may be the same as the gate insulating layer. Within the second type of trench, the conductive material may extend into the semiconductor body to the same depth as the first and / or second base regions. The conductive material within the second type of trench may be metal and / or heavily doped polysilicon.

[0020] For example, the conductive material in the second type of trench is electrically connected to the first main electrode, or in other words, the first main electrode may extend into the second type of trench.

[0021] Instead of being filled with a conductive material, the second type of trench may be free of a conductive material and may, for example, be filled only with an electrically insulating material.

[0022] The second type of trench is also referred to herein as an "inactive trench." The drift region of the semiconductor body is of a first conductivity type. The first conductivity type is, for example, n-type, i.e., the drift region is n-doped. The second conductivity type is opposite to the first conductivity type and may therefore be p-type. However, the reverse case, where the first conductivity type is p-type and the second conductivity type is n-type, may also be realized.

[0023] The drift region extends, for example, continuously across all of the base regions, i.e., in a top view looking toward the top surface, the drift region overlaps both of the base regions.

[0024] The first type trench is disposed between the first base region and the second base region in a first lateral direction, for example, adjacent to the first base region on one side and / or adjacent to the second base region on the other side.

[0025] The second base region may be disposed between the first type trench and the second type trench in the first lateral direction, may be adjacent to the second type trench, or may extend continuously, for example without interruption, from the first type trench to the second type trench.

[0026] The structure including the first base region and adjacent implantation structure, the first-type trench, the second base region, and the second-type trench may be repeated several times along the top surface. The structure including at least a portion (half) of the first base region with the adjacent implantation region, the first-type trench, the second base region, and the second-type trench are part of a so-called "half cell" or "transistor half cell." The semiconductor device may include several such half cells, which may be arranged one after the other in the first lateral direction. Each two adjacent half cells may be mirror-symmetric with respect to a mirror plane. The mirror plane may extend, for example, perpendicular to the first longitudinal direction. The mirror plane may cross the first base region along half of its respective extension in the first lateral direction.

[0027] The semiconductor body includes an implanted region of a first conductivity type. The implanted region is vertically spaced from the drift region by the first base region and is adjacent to the first base region. The implanted region may, for example, extend to the top surface. The implanted region may be embedded in the first base region. For example, the implanted region may be adjacent to the first type trench on the same side as the first base region is adjacent to the first type trench. Each half cell may include exactly one such implanted region. The implanted region may also be called a source region.

[0028] The injection region is in electrical contact with, for example, adjacent to, the first main electrode. During operation of the semiconductor device in a (static) transistor mode, charge carriers of a first type, for example electrons, are injected into the injection region from the first main electrode. The semiconductor device is configured such that, by applying a predetermined potential to the gate electrode, the first base region adjacent to the first-type trench is depleted, forming a path for the first-type charge carriers from the injection region to the drift region, the path extending vertically along the first-type trench.

[0029] The second base region may form a portion of the top surface, for example the entire portion of the top surface located laterally between the first type trench and the second type trench. For example, the semiconductor body is vertically disposed between the second base region and the top surface, and is free of any (implanted) region of the first conductivity type adjacent to the second base region.

[0030] The depth of the second type trench, measured in the vertical direction, may be at least 0.5 μm, or at least 1 μm, or at least 1.5 μm, or at least 2 μm greater than the depth of the first type trench. For example, the first type trench and the second type trench both extend deeper into the semiconductor body than the first and second base regions.

[0031] As described above, the semiconductor body may include some first-type trenches and some second-type trenches. Each second-type trench may be deeper than each first-type trench. In particular, all features disclosed in relation to one first-type trench and one second-type trench are also disclosed for all other (pairs of) adjacent first-type trenches and second-type trenches.

[0032] According to a further embodiment, the semiconductor device is an IGBT or RC-IGBT, ie a reverse conducting IGBT, or a MISFET, in particular a MOSFET.

[0033] According to further embodiments, the width of the second type of trench is greater than the width of the first type of trench. The width of the trench is defined herein as the average or maximum extension of the trench in a lateral direction perpendicular to the main extension direction of the trench. In particular, the width may be the extension in the first lateral direction. For example, the width of the second type of trench is at least 100 nm, at least 300 nm, or at least 500 nm greater than the width of the first type of trench.

[0034] Fabrication of such trenches having different depths and widths is particularly easy compared to fabrication of trenches of the same depth because the only required change is a modified layout in the trench mask, since the trench depth is directly related to the trench width when etching the trench, at least for some etching processes.

[0035] According to further embodiments, the minimum distance between the first type trench and the second type trench, measured in the first lateral direction, is at most three times, two times, or at most 1.5 times the width of the second type trench. By positioning the second type trench as close as possible to the first type trench, the protection of the first type trench by the second type trench can be further improved. The minimum distance is the minimum distance at which adjacent first type trenches and second type trenches approach each other. For example, the minimum distance is at most 3 μm or at most 2 μm.

[0036] According to a further embodiment, the first main electrode extends into the second-type trench, where it is separated from the semiconductor body by an electrically insulating layer. That is, the second-type trench is filled with a conductive material that is electrically connected to the first main electrode. The electrically insulating layer may comprise or consist of the same material as the gate insulating layer. For example, the electrically insulating layer in the second-type trench is formed identically to the gate insulating layer, particularly in terms of material and / or thickness.

[0037] By extending the first main electrode into the second type of trench, the first type of trench and the second type of trench can be set to different potentials during operation. Alternatively, a further electrode that is biasable / controllable independently of the gate electrode and the first main electrode may extend into the second type of trench.

[0038] According to a further embodiment, the second base region comprises at least one contact region, i.e., one or more contact regions, in which the second base region is in electrical contact with an electrode of the semiconductor device different from the gate electrode, e.g., which is controllable / biasable independently of the gate electrode.

[0039] During operation, charge carriers can be extracted from the semiconductor body through the contact region. Therefore, the contact region is sometimes referred to as an "extraction region." Such an extraction region can be advantageous during switching events, such as during transistor turn-off, because it helps rapidly reduce plasma concentration within the semiconductor body. That is, the contact region serves a plasma control function. On the other hand, when the semiconductor device is operated in diode mode, electrical contact between the electrode and the semiconductor body at the contact region provides a charge carrier path that reduces on-state losses in diode mode. Because the contact region electrically contacts an electrode different from the gate electrode, the charge carrier path is independent of the gate electrode potential. The location of the contact region in the second base region, i.e., at a location spaced apart from the first type trench, helps protect the gate insulating layer within the first type trench during switching events, further reducing avalanche potential in the region of the first type trench.

[0040] For example, an electrode to which the second base region is electrically connected at the contact region is disposed on the top surface, and the electrode may be the first main electrode or a separate electrode that can be controlled independently of the first main electrode.

[0041] The contact region belongs to the second base region and is therefore also referred to herein as the second contact region. The contact region may form part of the top surface. The second base region may be adjacent to the electrode over the entire area of ​​the contact region. In a top view of the top surface, the area of ​​the contact region is in particular smaller than the area of ​​the second base region. For example, in this top view, the area of ​​the contact region is 50% or less, or 10% or less, or 5% or less, or 1% or less of the area of ​​the second base region. In the case of several contact regions, all features disclosed for one contact region are also disclosed for the other contact regions.

[0042] According to a further embodiment, the second base region includes a plurality of contact regions. The second base region is in electrical contact with an electrode, e.g., a first main electrode, at each of these contact regions. The contact regions may be spaced apart from one another in a lateral direction, e.g., in a first and / or second lateral direction. All features disclosed in relation to one contact region of the second base region are also disclosed for all other contact regions of the second base region.

[0043] In a top view to the top surface, the contact region in the second base region may be formed as a stripe or a rectangle or a square.

[0044] For each pair of adjacent contact regions in the second base region, the two adjacent contact regions may be spaced apart from each other. In areas outside the contact regions, there is no direct electrical contact between the electrode and the second base region. In particular, outside the contact regions, the electrode is not adjacent to the second base region. For example, the multiple contact regions of the second base region are arranged in a rectangular pattern when viewed from above on the top surface. For example, when viewed from this top surface, at most 50% and / or at least 10% of the area of ​​the second base region is formed by the contact regions.

[0045] According to further embodiments, the distance between the first type trench and the second type trench measured in the first lateral direction varies as one moves along the second lateral direction, the second lateral direction being perpendicular to the first lateral direction. For example, the distance varies such that the maximum distance is at least 1.5 times or at least 2 times greater than the minimum distance. The maximum distance is the maximum distance that adjacent first type trenches and second type trenches are separated from each other.

[0046] According to further embodiments, the contact regions in the second base region are spaced apart from one another in the second lateral direction, for example, the distance between adjacent contact regions in the second lateral direction is greater than the maximum distance between the first type of trench and the second type of trench, for example at least two or at least four times greater than this maximum distance.

[0047] According to a further embodiment, the distance between the first type trench and the second type trench is greater when the contact region is disposed therebetween and less when the contact region is not disposed therebetween. For example, the distance between the first type trench and the second type trench is greatest at the position where the contact region is located in the second base region. The position of the contact region is their position along the second lateral direction.

[0048] In a top view to the top surface, each of the contact regions in the second base region may be surrounded by a second-type trench and a first-type trench. For example, in this top view, each contact region is surrounded on three sides by a second-type trench and on the remaining fourth side by a first-type trench. For example, in a top view to the top surface, the second-type trench may have a shape of a rectangular function. The maximum distance between the first-type trench and the second-type trench is reached in each rectangle of the rectangular function. In each rectangle, one contact region, for example, exactly one contact region, is disposed. Within each rectangle, the lateral distance of the second-type trench to the contact region may be at most the width of the second-type trench.

[0049] According to further embodiments, the second-type trench is disposed between two first-type trenches in the first lateral direction. All features disclosed in relation to one first-type trench are also disclosed for the other first-type trench. In particular, as described above, the structure of the first base region, the first-type trench, the second base region, and the second-type trench may be repeated several times as one moves along the first lateral direction.

[0050] According to a further embodiment, two second-type trenches are arranged between two first-type trenches in a first lateral direction. All features disclosed in relation to one second-type trench are also disclosed for the other second-type trench. For example, no further trenches are arranged between the two second-type trenches in a lateral direction.

[0051] According to further embodiments, the second type trenches are disposed between the second and third base regions in the first lateral direction. For example, each second type trench of the semiconductor device may be disposed between the second and third base regions. The second type trench may be adjacent to the third base region on an opposite side to the side adjacent to the second base region.

[0052] Like the first and second base regions, the third base region is of the second conductivity type, e.g., the doping concentration in the third base region is the same as the doping concentration in the first and / or second base regions.

[0053] The third base region can extend continuously, e.g., without interruption, from the trench of the second type to a further trench spaced apart from the trench of the second type in the first lateral direction, which further trench can be another trench of the second type.

[0054] The third base region may also form part of the top surface, for example the entire part of the top surface located laterally between two trenches that laterally define the third base region. The semiconductor body may be free of an (implanted) region of the first conductivity type disposed vertically between the third base region and the top surface and adjacent to the third base region.

[0055] According to a further embodiment, the third base region extends from the top surface into the semiconductor body at least as deep as the second type trenches. For example, the third base region extends deeper into the semiconductor body than the second type trenches. It has been found that such a design can further reduce the avalanche strength near the first type trenches.

[0056] According to a further embodiment, the third base region extends under the second type trench towards the first type trench, so that in a top view to the upper surface, the second type trench and the third base region may overlap each other.

[0057] According to a further embodiment, the third base region is arranged between two second-type trenches in the first lateral direction. The third base region may be adjacent to both second-type trenches.

[0058] According to a further embodiment, the two second-type trenches sandwiching the third base region are connected to each other at their respective longitudinal ends, i.e., their ends in the second lateral direction, so that, in a top view, the third base region is completely surrounded by a continuous trench. In other words, the second-type trenches sandwiching the third base region are formed by a single continuous trench. In a top view, the continuous trench forms a frame, e.g., a rectangular frame, around the third base region. This frame-shaped trench helps reduce hole leakage current during the on-state.

[0059] According to a further embodiment, the third base region includes at least one contact region, i.e., one or more contact regions. In the contact region, the third base region is in electrical contact with an electrode of the semiconductor device that is different from the gate electrode. This electrode may be the same electrode that is in electrical contact with the second base region in the respective (second) contact region. Thus, the electrode may in particular be the first main electrode. The contact region of the third base region, also referred to herein as the third contact region, may form part of the top surface. The third contact region may have an area smaller than that of the third base region when viewed from above on the top surface. The same relative sizes as disclosed in connection with the (second) contact region of the second base region may also apply here.

[0060] The third base region contact area provides an additional degree of freedom for optimizing charge carrier extraction during turn-off in transistor mode and / or during diode mode, for example.

[0061] According to a further embodiment, the first base region includes at least one contact region, i.e., one or more contact regions, in which the first base region is in electrical contact with an electrode of the semiconductor device that is different from the gate electrode. This electrode may be the same electrode that is in electrical contact with the second and / or third base regions in their respective contact regions. Thus, the electrode may in particular be a first main electrode.

[0062] According to a further embodiment, the drift region includes a first drift region and a second drift region arranged vertically one after the other, the first drift region and the second drift region may be adjacent to each other, and both the first drift region and the second drift region are of the first conductivity type.

[0063] According to a further embodiment, the second drift region is disposed vertically between the first drift region and the first base region, for example adjacent to the first and / or second base regions.

[0064] According to further embodiments, the second drift region has a higher doping concentration than the first drift region. For example, the average or maximum doping concentration in the second drift region is at least one order of magnitude or at least two orders of magnitude greater than the average or maximum doping concentration in the first drift region. The doping concentration can increase gradually or continuously from the first drift region to the second drift region. The second drift region is also referred to as an "enhancement region" or "enhancement layer," respectively. The enhancement layer helps to further reduce on-state losses.

[0065] The enhancement layer around the channel serves to stop the injection of second-type charge carriers, such as holes, from the bottom into the first base region. As a result, more first-type charge carriers are injected into the drift region from the top. Therefore, the higher the doping concentration of the enhancement layer, the lower the on-state losses. In IGBT designs, a blocking junction is formed between the first base region and the n-drift region. During blocking, the thickness and resistivity of the drift region (together with the buffer layer and the collector layer of the second conductivity type at the bottom) are designed so that the depletion layer does not reach the collector layer and thereby cause device failure. Therefore, it will not block if the enhancement layer doping concentration is too high. If an enhancement layer is used, the doping concentration of this layer is preferably low enough so that this layer is fully depleted during the off-state, i.e., there is a trade-off between blocking losses and on-state losses.

[0066] Next, a method for manufacturing a semiconductor device will be described. For example, the semiconductor device specified in this specification can be manufactured by this method. Therefore, all features disclosed in relation to the semiconductor device are also disclosed in relation to the method, and vice versa.

[0067] According to one embodiment, a method for manufacturing a semiconductor device includes providing a semiconductor body having a top surface and a bottom surface. Then, at least two trenches, i.e., a first type trench and a second type trench, are formed in the semiconductor body, each extending from the top surface into the semiconductor body. Furthermore, a first main electrode is formed on the top surface of the semiconductor body, and a second main electrode is formed on the bottom surface of the semiconductor body. A gate electrode is formed extending into the first type trench, where it is separated from the semiconductor body by a gate insulating layer. The second type trench is devoid of a gate electrode. The semiconductor device is formed such that the semiconductor body includes a drift region of a first conductivity type vertically disposed between the top surface and the bottom surface, and at least two base regions, i.e., first and second base regions, each of a second conductivity type, vertically disposed between the drift region and the top surface. The semiconductor body further includes an implanted region of the first conductivity type vertically spaced from the drift region by the first base region and adjacent to the first base region. The first base region, the first type trench, the second base region, and the second type trench are arranged in that order in a first lateral direction. A first main electrode is in electrical contact with the implanted region. The trenches are formed such that the second type trench extends deeper into the semiconductor body than the first type trench.

[0068] The trench may be formed in the semiconductor body before the base region and the implant region are formed, or the base region may be at least partially formed before the trench is formed.

[0069] According to a further embodiment, the trenches are formed in a common etching step using a common mask, the mask including holes in the areas where the trenches are to be formed, the holes for the second type of trench having a width greater than the holes for the first type of trench.

[0070] The width of the hole defines the width of the trench. Because the etching depth increases as the width increases (especially in the case of an anisotropic etching process), the first type trench and the second type trench are automatically formed with different depths. Therefore, a common etching step can be applied to form the first type trench and the second type trench. For example, to achieve the automatic formation of trenches with different depths, etching processes such as the Bosch-type process (a C4F8 passivation step, an O2 cleaning step, and an SF6 isotropic etching step in successive pulse cycles) or other anisotropic dry etching processes such as a mixture of SF6 and C4F8 can be used.

[0071] Hereinafter, a semiconductor device and a method for manufacturing a semiconductor device will be described based on embodiments with reference to the drawings. The accompanying drawings are included for further understanding. In the drawings, elements of the same structure and / or function may be referred to by the same reference symbols. It should be understood that the embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale. To the extent that elements or components correspond to each other in terms of their function in different drawings, their description will not be repeated for each of the following drawings. For clarity, elements may not appear with corresponding reference symbols in all drawings. [Brief explanation of the drawings]

[0072] [Figure 1] Different exemplary embodiments of a semiconductor device are shown in different figures. [Figure 2] Different exemplary embodiments of a semiconductor device are shown in different figures. [Figure 3] Different exemplary embodiments of a semiconductor device are shown in different figures. [Figure 4] Different exemplary embodiments of a semiconductor device are shown in different figures. [Figure 5] Different exemplary embodiments of a semiconductor device are shown in different figures. [Figure 6] Different exemplary embodiments of a semiconductor device are shown in different figures. [Figure 7] Different exemplary embodiments of a semiconductor device are shown in different figures. [Figure 8] Different exemplary embodiments of a semiconductor device are shown in different figures. [Figure 9] Different exemplary embodiments of a semiconductor device are shown in different figures. [Figure 10] Different exemplary embodiments of a semiconductor device are shown in different figures. [Figure 11] Different exemplary embodiments of a semiconductor device are shown in different figures. [Figure 12] Different exemplary embodiments of a semiconductor device are shown in different figures. [Figure 13] Different exemplary embodiments of a semiconductor device are shown in different figures. [Figure 14] 1 illustrates different positions in an exemplary embodiment of a method for manufacturing a semiconductor device. [Figure 15] 1 illustrates different positions in an exemplary embodiment of a method for manufacturing a semiconductor device. [Figure 16] 1 illustrates different positions in an exemplary embodiment of a method for manufacturing a semiconductor device. [Figure 17] A simulation is shown. [Figure 18] A simulation is shown. [Figure 19] A simulation is shown. DETAILED DESCRIPTION OF THE INVENTION

[0073] 1 shows a first exemplary embodiment of a semiconductor device 100 in a cross-sectional view. The semiconductor device 100 is, in this case, an RC-IGBT. It comprises a semiconductor body 10 having a top surface 11 and a bottom surface 19 located vertically opposite each other. The semiconductor body 10 is, for example, based on Si or SiC.

[0074] At the bottom surface 19, the semiconductor body 10 includes alternating first-type regions 15 and second-type regions 16. The regions 15 and 16 are in electrical contact at the bottom surface 19 with a second main electrode 3, i.e., a collector electrode 3. The collector electrode 3 may be made of, for example, a metal.

[0075] The first-type region 15 is of a first conductivity type, hereinafter referred to as n-type, and the second-type region 16 is of a second conductivity type, hereinafter referred to as p-type. The drift region 14 is disposed between the top surface 11 and the bottom surface 19. The drift region 14 is of the first conductivity type, i.e., n-type. The drift region 14 is adjacent to the first-type region 15 and the second-type region 16.

[0076] A plurality of trenches 51, 52 extend from the top surface into semiconductor body 10 and into drift region 14. Trench 51 is a first type of trench, also referred to herein as an "active trench," and trench 52 is a second type of trench, also referred to herein as an "inactive trench" or "dummy trench."

[0077] The first-type trenches 51 are filled with a conductive material that is electrically isolated from the semiconductor body 10 by an electrical insulating layer 40, referred to herein as the "gate insulating layer." Thus, there is no direct electrical contact between the semiconductor body 10 and the conductive material in the first-type trenches 51. The gate insulating layer 40 is formed of an oxide, such as SiO2. The conductive material in the first-type trenches 51 may be heavily doped polysilicon. The conductive material in the first-type trenches 51 is part of the gate electrode 4 of the semiconductor device 100.

[0078] The second type of trenches 52 are also filled with a conductive material, for example heavily doped polysilicon, that is electrically isolated from the semiconductor body 10 by the same electrically insulating layer as the gate insulating layer 40. The conductive material in the second type of trenches 52 is part of a first main electrode 2, i.e., an emitter electrode 2, disposed on the top surface 12. The first base region 13a is adjacent to and in electrical contact with the emitter electrode 2 at a first contact region 6a, also referred to as the "Rb prime region."

[0079] Semiconductor body 10 includes several base regions 13a, 13b, 13c arranged vertically between drift region 14 and top surface 11. Base regions 13a, 13b, 13c are all of a second conductivity type, i.e., p-type, and they all adjoin drift region 14 and top surface 11. First base region 13a and second base region 13b are shallower (have less vertical extension) than trenches 51, 52. Third base region 13c is deeper than trenches 51, 52, i.e., extends further into semiconductor body 10.

[0080] As can be seen in FIG. 1, the semiconductor device 100 is subdivided into a plurality of so-called half cells. One such half cell is shown in more detail in FIG. 2. A half cell is the structure between the vertical dashed lines in FIG. 2. In FIG. 1, several such half cells are arranged one after the other in a first lateral direction running from left to right. Two adjacent half cells extend perpendicular to the first lateral direction and are mirror images of each other in a plane passing through the third base region 13c (see the right vertical dashed line in FIG. 2).

[0081] 2, the half cell includes a portion (half) of the first base region 13c, a first-type trench 51, a second base region 13b, a second-type trench 52, and a portion (half) of the third base region 13c, which are arranged in this order along the first lateral direction. The half cell further includes an implantation region 12 (source region 12) of a first conductivity type, i.e., n-type, vertically disposed between the first base region 13c and the top surface 11. The implantation region 12 is adjacent to the first base region 13c and the first-type trench 51. The implantation region 12 is further adjacent to and in electrical contact with the emitter electrode 2.

[0082] The operation of the semiconductor device may be as follows. In the so-called transistor mode, the emitter electrode 2 is set to ground and the collector electrode 3 is set to a positive potential. The gate electrode 4 is set to a positive potential so that the first base region 13a is depleted at the boundary of the first-type trench 51. A conductive path is formed in the first base region 13c along the first-type trench 51. Electrons are then injected from the emitter electrode 2 into the injection region 12, move along the conductive path, and can reach the drift region 14. At the bottom surface 19, holes are injected from the collector electrode 3 through the second-type region 16 and move into the drift region 14, generating an electron-hole plasma.

[0083] When the transistor mode is turned off, the electron-hole plasma can generate an avalanche in the region of the first type trench 51. Figure 17 shows a simulation of the current I and voltage V as a function of time t during turn-off from the transistor mode. Figure 18 shows the corresponding simulated maximum avalanche generation I_max as a function of time t. Indeed, there is a very high intensity avalanche during turn-off.

[0084] Such avalanches can adversely affect the gate insulating layer 40 and the long-term performance stability of the semiconductor device 10. The second type of passive trench 52 and the third base region 13c, which extends deeper into the semiconductor body than the trenches 51, 52, have been found to help divert avalanches away from the active trenches 51.

[0085] This effect is further enhanced by having the second type trenches 52 extend deeper into the semiconductor body, i.e., have a greater vertical extension than the first type trenches 51. For example, the depth of the second type trenches 52 is at least 0.5 μm greater than the depth of the first type trenches 51.

[0086] Figure 19 shows a simulation of impact ionization along the cross section indicated by the vertical dashed line in Figure 2. Solid curves A1, A2, and A3 show impact ionization as a function of depth Y along first type trench 51, and dashed curves B1, B2, and B3 show impact ionization as a function of depth Y along second type trench 52.

[0087] Curves A1 and B1 show simulation results when the first type trench 51 and the second type trench 52 have the same depth. Curves A2 and B2 show simulation results when the second type trench 52 is 1 μm deeper than the first type trench 51. Curves A3 and B3 show simulation results when the second type trench 52 is 2 μm deeper than the first type trench 51.

[0088] As can be seen, when trenches 51 and 52 have the same depth, both trenches share the same level of impact ionization. By making second-type trench 52 deeper than first-type trench 51, the stress on gate insulating layer 40 at first-type trench 51 is significantly reduced. The peak of impact ionization at the bottom of first-type trench 51 is reduced by more than one order of magnitude when second-type trench 52 is 1 μm deeper than first-type trench 51, and by more than two orders of magnitude when second-type trench 52 is 2 μm deeper than first-type trench 51.

[0089] Figure 3 shows a further exemplary embodiment of a semiconductor device 100, in this case an IGBT. At the top surface 11, the semiconductor device 100 is identical to the semiconductor device of Figure 1. However, the bottom surface 19 is formed only by a second type region 16 (collector layer 16) of the second conductivity type.

[0090] Figure 4 shows one embodiment of a semiconductor device 100 that is a MISFET. Again, the top surface 11 is the same as in Figures 1 and 3. However, the bottom surface 19 is formed only by n-type semiconductor material.

[0091] 5, the second type of trenches 52 not only have a greater depth than the first type of trenches 51, but also a greater width measured in the first lateral direction. Trenches having different depths and, at the same time, different widths can be particularly easily manufactured.

[0092] Another exemplary embodiment of the semiconductor device 100 is shown in FIG. 6. In this case, the drift region 14 includes a first drift region 14a and a second drift region 14b. The second drift region 14b is vertically disposed between the first drift region 14a and the base regions 13a, 13b, and 13c and adjacent to them. Trenches 51 and 52 extend vertically beyond the second drift region 14b and terminate within the first drift region 14a. The doping concentration of the n-type dopant in the second drift region 14b is, for example, at least 10 times or at least 100 times greater than the doping concentration in the first drift region 14a. Such a second drift region 14b, also known as an "enhancement region" or "enhancement layer," helps to improve on-state losses.

[0093] 7 to 9 show a further exemplary embodiment of the semiconductor device 100 in different views. Here, the second base regions 13b each have second contact regions 6b through which the second base regions 13b are in electrical contact with the first main electrode 2. During turn-off of the transistor mode, at least a portion of the plasma can be extracted through these contact regions 6b such that charge carriers are effectively diverted away from the first-type trenches 51. As a result, avalanche generation near the first-type trenches 51 is further reduced.

[0094] 9 shows the semiconductor device 100 of FIG. 7 as viewed from above on the upper surface 11. The upper horizontal dashed line indicates the cross-sectional plane of the cross-sectional view of FIG. 7. The lower horizontal dashed line indicates the cross-sectional plane of the cross-sectional view of FIG.

[0095] As can be seen from FIG. 9 , the second-type trenches 52 each follow a rectangular function when moving along the second lateral direction, which is from bottom to top in FIG. 9 . In each rectangle, the distance between the second-type trench 52 and the adjacent first-type trench 51 measured in the first lateral direction has a maximum value. Within each rectangle, a contact region 6b is located, where each second base region 13b is in electrical contact with the first main electrode 2. In areas of the second base region 13b where no contact region exists, the distance between the first-type trench 51 and the adjacent second-type trench 52 reaches a minimum value. This minimum value is, for example, smaller than the width of the second-type trench 52, e.g., 200 nm or less.

[0096] 10-12 show further exemplary embodiments of the semiconductor device 100 in the same views as those described in connection with Figures 7-9. The third base region 13c also includes contact regions 6c where the third base region 13c is in electrical contact with the first main electrode 2. These contact regions 6c may also serve to divert plasma away from the first type trenches 51 during turn-off of the transistor mode.

[0097] 13 shows a further exemplary embodiment of the semiconductor device 100, here only in a top view towards the top surface 11 of the semiconductor body 10. As can be seen, the second type of trenches 52 that sandwich the third base region 13c in the first lateral direction are in fact connected at their respective longitudinal ends, so that a continuous trench completely surrounds the first base region 13c.

[0098] 14 illustrates a first position in an exemplary embodiment of a method for fabricating a semiconductor device 100. At this position, a semiconductor body 10 is provided having a top surface 11 and a bottom surface 19. The bottom surface 19 is formed by alternating first-type regions 15 and second-type regions 16. The top surface 11 is formed by a base region 13 of a second conductivity type. A drift region 14 is disposed between the bottom surface 19 and the base region 13, and the drift region 14 is of the first conductivity type.

[0099] 15 shows the locations where trenches are formed in semiconductor body 10 by etching into upper surface 11. The trenches are formed using a mask 200 that includes a plurality of holes in the areas where the trenches are to be formed. The width of the holes in second type trenches 52 is greater than the width of the holes in first type trenches 51. This results in the trenches being formed with different widths, but also with different depths.

[0100] 16 shows the position after trenches 51, 52 have been filled with a conductive material. The conductive material in trenches 51, 52 is electrically isolated from semiconductor body 10 by electrically insulating material 40 disposed in trenches 51, 52. Additionally, first base region 13a, second base region 13b, and third base region 13c are formed, for example, by ion implantation. Implanted region 12 is also formed in semiconductor body 10, for example, by ion implantation.

[0101] 1-16 represent exemplary embodiments of the improved semiconductor device and improved method for manufacturing the semiconductor device, and therefore, they do not constitute an exhaustive list of all embodiments of the improved semiconductor device and the improved method. Actual semiconductor devices and methods may differ from the illustrated embodiments, for example, with respect to the arrangement, elements, and order of method steps. [Explanation of symbols]

[0102] Reference sign 2 First main electrode 3 Second main electrode 4 gate electrode 5 Further electrodes 6a First contact area 6b Second contact area 6c Third contact area 10 Semiconductor body 11 Top side 12 Injection area 13 Base Area 13a first base region 13b Second base region 13c Third base region 14 Drift Region 14a First drift region 14b Second drift region 15 Areas of the first type 16 Second type of area 19 Bottom 40 Electrical insulating layer / gate insulating layer 51 First type trench 52 Second type trench 100 Semiconductor device 200 masks A1~A3 curve B1~B3 curve

Claims

1. A semiconductor device (100), a semiconductor body (10) extending vertically between a top surface (11) and a bottom surface (19); - a first main electrode (2) on said top face (11) and a second main electrode (3) on said bottom face (19); - a gate electrode (4), - at least two trenches, namely a trench of a first type (51) and a trench of a second type (52), each trench extending from said top surface (11) into said semiconductor body (10); said semiconductor body (10) a drift region (14) of first conductivity type vertically between said top surface (11) and said bottom surface (19); at least two base regions, namely a first base region (13a) and a second base region (13b), each of which is of a second conductivity type and which are arranged vertically between said drift region (14) and said top surface (11), said semiconductor body further comprising: - an implanted region (12) of said first conductivity type vertically spaced from said drift region (14) by said first base region (13a) and adjacent to said first base region (13a), - said first base region (13a), said first type trench (51), said second base region (13b) and said second type trench (52) are arranged in this order in a first lateral direction, - said first main electrode (2) is in electrical contact with said injection region (12); - said gate electrode (4) extends into said trenches (51) of the first type, where it is separated from said semiconductor body (10) by a gate insulating layer (40); - said second type of trench (52) is free of said gate electrode (4), - said second type of trenches (52) extend deeper into said semiconductor body (10) than said first type of trenches (51); - the second base region (13b) comprises a plurality of laterally spaced contact regions (6b), the second base region (13b) being in electrical contact with the first main electrode (2) at each of these contact regions (6b); the distance between the first type of trench (51) and the second type of trench (52), measured in the first lateral direction, varies as one moves along a second lateral direction perpendicular to the first lateral direction; the contact regions (6b) in the second base region (13b) are spaced apart from one another in the second lateral direction, - the distance between the first type trench (51) and the second type trench is greater where a contact area (6b) is arranged between them and smaller where no contact area is arranged between them.

2. The semiconductor device (100) according to claim 1, wherein the width of said second type trenches (52) is greater than the width of said first type trenches (51).

3. The semiconductor device (100) according to claim 1 or 2, wherein the minimum distance between the first type trench (51) and the second type trench (52), measured in the first lateral direction, is at most twice the width of the second type trench (52).

4. The semiconductor device (100) according to any one of claims 1 to 3, wherein the first main electrode (2) extends into the second type of trench (52), where it is separated from the semiconductor body (10) by an electrically insulating layer (40).

5. The semiconductor device (100) according to any one of the preceding claims, wherein said second type trench (52) is arranged between two first type trenches (51) in said first lateral direction.

6. The semiconductor device (100) according to claim 5, wherein in said first lateral direction, two trenches (52) of a second type are arranged between two trenches (51) of a first type.

7. the second type trench (52) is arranged in the first lateral direction between the second base region (13b) and a third base region (13c), the third base region (13c) being of the second conductivity type; The semiconductor device (100) according to any one of the preceding claims, wherein said third base region (13c) extends deeper into said semiconductor body (10) than said second type trenches (52).

8. said third base region (13c) is arranged in said first lateral direction between said two second type trenches (52); - said third base region (13c) is adjacent to said two second type trenches (52); The semiconductor device (100) according to claims 6 and 7, wherein the two second type trenches (52) are connected to each other at their respective longitudinal ends, and in a top view onto the top surface (11) the third base region (13c) is completely surrounded by a continuous trench.

9. The semiconductor device (100) according to claim 7 or 8, wherein the third base region (13c) comprises at least one contact region (6c) through which the third base region (13c) is in electrical contact with the first main electrode (2).

10. - said drift region (14) comprises a first drift region (14a) and a second drift region (14b) arranged one after the other in the vertical direction; - the second drift region (14b) is arranged vertically between the first drift region (14a) and the first base region (13a); The semiconductor device (100) according to any one of the preceding claims, wherein the second drift region (14b) has a higher doping concentration than the first drift region (14a).

11. A method for manufacturing a semiconductor device (100), comprising: - providing a semiconductor body (10) having a top surface (11) and a bottom surface (19); forming at least two trenches, namely a trench of a first type (51) and a trench of a second type (52), each trench extending from said top surface (11) into said semiconductor body (10), said method further comprising: - forming a first main electrode (2) on said top surface (11) and a second main electrode (3) on said bottom surface (19); forming a gate electrode (4), said gate electrode (4) extending into said first type trench (51), where it is separated from said semiconductor body (10) by a gate insulating layer (40); - said second type of trench (52) remains free of said gate electrode (4); said semiconductor device (100) is characterized in that said semiconductor body (10) a drift region (14) of first conductivity type vertically between said top surface (11) and said bottom surface (19); - formed to include at least two base regions, namely a first base region (13a) and a second base region (13b), each of which is of a second conductivity type and which are arranged vertically between said drift region (14) and said top surface (11), said semiconductor device further comprising: - formed to include an implanted region (12) of said first conductivity type vertically spaced from said drift region (14) by said first base region (13a) and adjacent to said first base region (13a), - said first base region (13a), said first type trench (51), said second base region (13b) and said second type trench (52) are arranged in this order in a first lateral direction, - said first main electrode (2) is in electrical contact with said injection region (12); - the trenches (51, 52) are formed such that the second type trenches (52) extend deeper into the semiconductor body (10) than the first type trenches (51); - the second base region (13b) comprises a plurality of laterally spaced contact regions (6b), the second base region (13b) being in electrical contact with the first main electrode (2) at each of these contact regions (6b); the distance between the first type of trench (51) and the second type of trench (52), measured in the first lateral direction, varies as one moves along a second lateral direction perpendicular to the first lateral direction; the contact regions (6b) in the second base region (13b) are spaced apart from one another in the second lateral direction, - the distance between the first type trench (51) and the second type trench is larger where a contact area (6b) is arranged between them and smaller where no contact area is arranged between them.

12. - said trenches (51, 52) are formed in a common etching step using a common mask (200); - said mask (200) contains holes in the areas where said trenches (51, 52) are to be formed; A method according to claim 11, wherein the holes for the second type of trench (52) have a width greater than the holes for the first type of trench (51).

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