Thin film for developing array patterns and its manufacturing process

Abstract

Thin films for developing array patterns and processes for their manufacture. The present invention relates to thin films for developing array patterns and processes for their manufacture. The thin films of the present invention have strong adhesion, improved oxidation resistance, etch compatibility with standard microfabrication techniques, and excellent electrical conductivity. Furthermore, the thin films of the present invention are stable at high temperatures in oxygen. Furthermore, the present invention relates to a simple and economical process for manufacturing thin films for developing array patterns.

Description

[Technical Field]

[0001] The present invention relates to a thin film for developing an array pattern and a manufacturing process thereof, and more particularly to a piezoelectric thin film for developing an array pattern and a manufacturing process thereof.

[0002] Definition of Terms As used herein, the following terms are generally intended to have the following defined meanings, unless the context indicates otherwise.

[0003] Lead(Pb) Zirconate(Zr) Titanate (Ti) (PZT): The term "lead(Pb) Zirconate(Zr) Titanate" has the chemical formula Pb[Zr x Ti 1-x ]O3 (0≦x≦1), commonly abbreviated as PZT, and commonly known as lead zirconate titanate. PZT is a ceramic perovskite material characterized by a pronounced piezoelectric effect, which deforms when an electric field is applied. PZT is a solid solution of lead zirconate (PbZrO3) and lead titanate (PbTiO3) compounds, with the same ABO3 perovskite crystal structure as both end components. This solid is used in several practical applications, including ultrasonic transducers and piezoelectric resonators. The material is a white to slightly off-white solid.

[0004] Microelectromechanical systems (MEMS): The term "MEMS" relates to micromechatronics and microsystems technology, particularly the technology of tiny devices with moving parts. At the nanoscale, these technologies merge into nanoelectromechanical systems (NEMS) and nanotechnology. MEMS are made up of components with sizes between 1 and 100 micrometers (0.001 and 0.1 mm); MEMS devices are typically in the 20 micrometer to 1 millimeter (0.02 and 1.0 mm) range, although arrayed components (such as digital micromirror devices) can be as large as 1000 mm. 2They can exceed this size. They typically consist of a central unit (an integrated circuit chip such as a microprocessor) that processes data, and several components (such as microsensors) that interact with the surrounding environment. Microelectromechanical systems (MEMS) is a process technology for manufacturing tiny integrated devices or systems that combine mechanical and electronic components. MEMS refers to the technology for manufacturing devices with at least some dimensions in the micrometer range. MEMS devices have the ability to sense, control, and act on a microscale while still producing effects on a macroscale.

[0005] Lift-off technology: Lift-off is a process in which a pattern is exposed onto photoresist (or other material) and a thin film (such as a metal or dielectric) is deposited over the entire surface. The photoresist (or other material) is then washed away, leaving the thin film only in the patterned areas. Lift-off is a method for patterning a target material (typically a metal) using a sacrificial layer (usually photoresist) to define the pattern. First, the sacrificial layer is applied and the pattern is formed optically. Then, the target material is deposited on top. Finally, the resist is dissolved away, lifting off the metal deposited on top, leaving only the patterned metal on the substrate.

[0006] Microfabrication: "Microfabrication" or "MEMS processing" refers to a set of techniques for additively or subtractively modifying substrate materials, generally defining the process of transforming flat, thin substrates into complex multi-material structures through the interaction of microstructures. Microfabrication refers to the process of producing tiny structures on the micrometer scale or smaller.

[0007] Face-centered cubic (FCC): The term "face-centered cubic" refers to a type of atomic arrangement found in nature. A face-centered cubic unit cell (FCC) structure consists of a cubic structure with a partial atom located at each vertex of the cube and six complete atoms located at the center of each face.

[0008] Full Width Half Maximum (FWHM): The term "Full Width Half Maximum (FWHM)" refers to the difference between two points of the independent variable where the dependent variable is half its maximum. In other words, it measures the spectral width between two points on the curve that correspond to half the maximum amplitude on the y-axis. The half width at half maximum (HWHM) is half the FWHM if the function is symmetric. When the independent variable is time, the preferred term is "Full Time Width Half Maximum (FDHM)." [Background technology]

[0009] The following background information is relevant to the present invention but is not necessarily prior art.

[0010] Traditionally, lead (Pb) zirconate titanate (Ti) (Zr) (Pb) (PZT) thin films have been commonly used in microelectromechanical systems (MEMS). The performance of PZT thin-film-based MEMS systems depends primarily on two factors: (1) the integration of functional PZT layers onto conventional silicon (Si) substrates and (2) the complex patterning of multilayer thin films using microfabrication techniques such as lithography, dry / wet etching, and micromachining. Integrating PZT thin films onto conventional silicon (Si) substrates presents a technical challenge due to the incompatibility between the two materials. PZT tends to react with the Si substrate to form a silicate phase at temperatures below 500 °C, whereas the formation of the PZT phase typically requires temperatures above 500 °C. Furthermore, the formation of pores at the interface between the PZT thin film and the substrate can cause deformation of the film surface, resulting in increased surface roughness and degradation of the thin film's electrical properties.

[0011] Generally, platinum (Pt) has been mainly used as the bottom electrode because it does not react in the PZT thin film processing temperature range, but Pt cannot be used directly on the Si substrate because it reacts with the Si substrate even at a low temperature of 400 °C. The formation of platinum silicide also causes the upper layer lead (Pb) to diffuse into the underlying Si substrate.

[0012] The patterning of platinum thin films is easily destroyed by dry / wet etching, which may lead to contamination of the platinum surface due to etching of the adhesion layer, poor platinum etch selectivity, peeling of the platinum layer, and similar problems.

[0013] Patterning of platinum thin-film heterostructures can be performed before the deposition of the piezoelectric functional layer to reduce the exposure of the piezoelectric thin-film layer to multiple microfabrication processes and prevent structural damage caused by dry and wet etching of platinum. Traditionally, lift-off techniques have been used to form patterned thin films on substrate surfaces. However, for platinized silicon thin-film heterostructures, lift-off is not an optimal process because high-temperature annealing is required after Pt / Ti deposition to achieve a stable bottom electrode structure. The lift-off technique can pose a risk of particle formation, and the Pt edge is often unclear after etching. Therefore, there is a need to develop alternative microfabrication processes for patterning metallic platinum layers.

[0014] Therefore, there is a need for the development of array-patterned thin films and processes for their manufacture to alleviate the aforementioned drawbacks or at least provide a useful alternative. Summary of the Invention [Problem to be solved by the invention]

[0015] Some of the objects of the present invention, of which at least one embodiment is sufficient to be mentioned herein, are as follows.

[0016] It is an object of the present invention to ameliorate one or more of the problems in the background or at least to provide a useful alternative.

[0017] Another object of the present invention is to provide a thin film that develops an array pattern.

[0018] It is yet another object of the present invention to provide a thin film for developing array patterns that has strong adhesion, improved oxidation resistance, etch compatibility with standard microfabrication techniques, and good electrical conductivity.

[0019] It is yet another object of the present invention to provide a thin film for developing array patterns that exhibits denser and more uniform grain growth without cracking.

[0020] It is yet another object of the present invention to provide a thin film for developing an array pattern that is stable under oxygen and high temperatures.

[0021] It is yet another object of the present invention to provide a thin film for developing an array pattern that can be patterned into an array structure by a wet etching process.

[0022] It is yet another object of the present invention to provide a simple and economical process for producing thin films for developing array patterns.

[0023] Another object of the present invention is to provide a process for developing an array pattern on a thin film.

[0024] Other objects and advantages of the present invention will become more apparent from the following description, which is not intended to limit the scope of the invention thereto. [Means for solving the problem]

[0025] The present invention relates to a thin film for developing an array pattern, which comprises at least one substrate layer, at least one insulating material layer, at least one transition metal oxide layer, and at least one metal layer, with the transition metal oxide layer sandwiched between the insulating material layer and the metal layer.

[0026] The present invention also relates to a process for manufacturing a thin film for developing an array pattern. The process includes the steps of obtaining a substrate having a predetermined thickness, cleaning the substrate to obtain a cleaned substrate, depositing at least one insulating material layer on the working surface of the cleaned substrate by thermal oxidation at a first predetermined temperature for a first predetermined time to obtain a reaction prevention layer between the substrate and the insulating material, depositing at least one transition metal layer on the working surface of the reaction prevention layer under a first predetermined deposition rate in an inert atmosphere at a second predetermined temperature for a second predetermined time to obtain an adhesion layer, and depositing at least one metal layer on the working surface of the adhesion layer under a second predetermined deposition rate in an inert atmosphere at a third predetermined temperature for a third predetermined time to obtain a functional thin film. The formed thin film is then annealed in an inert / oxygen atmosphere at a temperature range of 600°C to 800°C with a heating rate of 0.4°C / s to 1°C / s for 20 to 60 minutes to obtain an annealed thin film. The resulting annealed thin film is held for 20 to 60 minutes, then cooled to 250 to 300° C., and further cooled to 20 to 40° C. to obtain the final thin film. [Brief explanation of the drawings]

[0027] The invention will now be explained with the aid of the accompanying drawings, in which:

[0028] [Figure 1] FIG. 1 shows the operating pressure characteristics during Pt / Ti deposition by DC magnetron sputtering according to the present invention. [Figure 2] FIG. 2 shows a temperature profile for annealing a thin film according to the present invention. [Figure 3] FIG. 3 shows a schematic diagram of a large area micromachined array of thin films according to the present invention. [Figure 4] Figure 4(a) shows the X-ray diffraction characteristics of the thin film according to the present invention, and Figure 4(b) shows the X-ray diffraction distribution characteristics for the entire surface of the thin film according to the present invention. [Figure 5] FIG. 5 shows electrical resistivity mapping across a thin film according to the present invention. [Figure 6]FIG. 6(a) shows a field emission scanning electron microscope (FESEM) image of a thin film according to the present invention, and FIG. 6(b) shows a field emission scanning electron microscope (FESEM) image of a thin film according to the present invention. [Figure 7] FIG. 7(a) shows a three-dimensional (3D) atomic force microscope (AFM) topography image of a thin film according to the present invention, and FIG. 7(b) shows a two-dimensional (2D) atomic force microscope (AFM) planar image of a thin film according to the present invention. Detailed Description of the Invention

[0029] Embodiments of the present invention will now be described with reference to the accompanying drawings.

[0030] The embodiments described herein will enable those skilled in the art to fully and completely grasp the scope of the present invention. Numerous details relating to individual components may be described to fully grasp the embodiments of the present invention. It will be apparent to those skilled in the art that the details described in the embodiments cannot be construed as limiting the scope of the present invention. In some embodiments, well-known processes, well-known device structures, and well-known techniques are not described in detail.

[0031] In the present invention, the terms used are used only to describe particular embodiments and should not be construed as limiting the scope of the present invention. As used herein, nouns are intended to include plural references unless the context dictates otherwise. Terms such as "comprising," "including," "comprising," and "consisting of" are inclusive transitional terms and thus specify the presence of a function, feature, integer, step, operation, element, module, unit, or component described herein, but do not preclude the presence or addition of other functions, integers, steps, operations, elements, components, or groups of components. The specific sequence of steps disclosed in the methods and processes of the present invention should not be construed as indicating that the performance described or illustrated is necessarily essential. It should also be understood that additional or alternative steps may be used.

[0032] As used herein, the term "or" includes any combination of one or more of the associated listed members.

[0033] The terms first, second, third, etc. may be used only to distinguish one element or component, region, layer, or section from another component, region, layer, or section, and therefore should not be construed as limiting the scope of the present invention. The terms first, second, third, etc. do not imply a particular permutation or order unless expressly stated herein.

[0034] Patterning of platinum thin film heterostructures is sensitive to dry and wet etching, and is prone to problems such as surface contamination due to adhesion layer etching, low selectivity, and layer delamination.

[0035] Patterning of platinum thin-film heterostructures can be performed before the deposition of the piezoelectric functional layer to reduce the exposure of the piezoelectric thin-film layer to multiple microfabrication processes and prevent structural damage caused by dry / wet etching of platinum. However, for platinized silicon thin-film heterostructures, the lift-off technique is not an optimal process because high-temperature annealing is required after Pt / Ti deposition to obtain a stable bottom electrode structure. The lift-off technique may pose a risk of particle formation, and the Pt edge after etching is often unclear. Therefore, there is a need to develop alternative microfabrication processes for patterning metallic platinum layers.

[0036] The present invention relates to a thin film for developing an array pattern and a manufacturing process thereof, and more particularly to a piezoelectric thin film for developing an array pattern and a manufacturing process thereof.

[0037] In one aspect, the present invention provides a thin film for developing an array pattern.

[0038] The thin film is composed of at least one substrate layer, at least one insulating material layer, at least one transition metal oxide layer, and at least one metal layer, with the transition metal oxide layer sandwiched between the insulating material layer and the metal layer.

[0039] According to one embodiment of the present invention, the substrate is selected from the group consisting of silicon, sapphire (Al2O3), magnesium oxide (MgO), gallium nitride (GaN), silicon carbide (SiC). In one embodiment, the substrate is silicon.

[0040] According to one embodiment of the present invention, the thickness of the matrix layer ranges from 200 μm to 400 μm, hi one embodiment, the thickness of the matrix layer is 300 μm.

[0041] According to one embodiment of the present invention, the insulating material is selected from the group consisting of silicon dioxide (SiO2), silicon nitride (SiN). In one embodiment, the insulating material is silicon dioxide (SiO2).

[0042] According to one embodiment of the present invention, the thickness of the insulating material layer is in the range of 500 nm to 600 nm, hi one embodiment, the thickness of the insulating material layer is 550 nm.

[0043] According to one embodiment of the present invention, the transition metal oxide is at least one selected from the group consisting of titanium dioxide and zirconium oxide, hi one embodiment, the transition metal oxide is titanium dioxide.

[0044] According to one embodiment of the present invention, the thickness of the transition metal oxide layer ranges from 30 nm to 100 nm, hi one embodiment, the thickness of the transition metal oxide layer is 50 nm.

[0045] According to one embodiment of the present invention, the metal of the metal layer is at least one selected from the group consisting of platinum, iridium, ruthenium, and copper, hi one embodiment, the metal of the metal layer is platinum (Pt).

[0046] According to one embodiment of the present invention, the thickness of the metal layer is in the range of 200 nm to 300 nm, hi one embodiment, the thickness of the metal layer is 250 nm.

[0047] According to one embodiment of the present invention, the ratio of the thickness of the metal layer to the transition metal oxide ranges from 2: 1 to 10: 1. In one example, the ratio of the thickness of the metal layer to the transition metal oxide is 5:1.

[0048] According to one embodiment of the present invention, the thickness of the thin film is in the range of 200 μm to 500 μm, hi one embodiment, the thickness of the thin film is 380 μm.

[0049] According to one embodiment of the present invention, the thin film has the following characteristics: Electrical resistivity is in the range of 10μΩ-cm to 15μΩ-cm, -Full width at half maximum (FWHM) is in the range of 0.1 to 0.5, · Root mean square roughness between 2 nm and 8 nm.

[0050] In another aspect, the present invention provides a process for producing a thin film for developing an array pattern, the process comprising the steps of:

[0051] The first step in thin film fabrication is to obtain a substrate having a predetermined thickness.

[0052] According to one embodiment of the present invention, the substrate is selected from the group consisting of silicon, sapphire (Al2O3), magnesium oxide (MgO), gallium nitride (GaN), silicon carbide (SiC). In one embodiment, the substrate is silicon.

[0053] In the second step of the thin film production, the substrate is washed to obtain a washed substrate.

[0054] This washing is done by heating the substrate with an organic solvent to remove impurities.

[0055] A clean substrate surface is a prerequisite for synthesizing high-purity thin films. The purpose of substrate cleaning is to remove impurity chemicals and particles on the substrate without modifying or damaging the surface. The surface of the substrate (silicon wafer) may contain impurities such as sebum and dirty grease. This is due to the substrate's high electronegativity of approximately 1.8 eV during the substrate preparation process, which makes it easy for metal impurities to adhere to the surface.

[0056] In the third step of the thin film formation, at least one insulating material layer is deposited on the working surface of the cleaned substrate by thermal oxidation at a first predetermined temperature for a first predetermined time to obtain a layer that prevents reaction between the substrate and the insulating material.

[0057] A three-stage oxidation process (dry, wet and thermal) is applied to grow insulating material onto the substrate in a high-temperature furnace.

[0058] According to one embodiment of the present invention, the insulating material is selected from the group consisting of silicon dioxide (SiO2) and silicon nitride (SiN). In one embodiment, the insulating material is silicon dioxide (SiO2).

[0059] According to one embodiment of the present invention, the first predetermined temperature is in the range of 900° C. to 1200° C. In one example, the first predetermined temperature is 1050° C.

[0060] According to one embodiment of the present invention, the first predetermined time period ranges from 60 minutes to 180 minutes. In one embodiment, the first predetermined time period is 100 minutes.

[0061] In a fourth step of the thin film formation, at least one transition metal layer is deposited on the working surface of the reaction prevention layer in an inert atmosphere at a second predetermined temperature for a second predetermined time under a first predetermined deposition rate condition to obtain an adhesive layer of the substrate, insulating material, and transition metal oxide.

[0062] According to one embodiment of the present invention, the transition metal is at least one selected from the group consisting of titanium and zirconium, hi one embodiment, the transition metal is titanium.

[0063] According to one embodiment of the present invention, the second predetermined temperature ranges from 20° C. to 40° C. In one example, the second predetermined temperature is 25° C.

[0064] According to one embodiment of the present invention, the second predetermined time period ranges from 2 minutes to 15 minutes. In one embodiment, the second predetermined time period is 5 minutes.

[0065] According to one embodiment of the present invention, the first predetermined deposition rate is in the range of 5 nm / min to 15 nm / min, hi one example, the second predetermined deposition rate is 10 nm / min.

[0066] In the fifth stage of thin film formation, at least one type of metal layer is deposited on the working surface of the adhesion layer in an inert atmosphere at a third predetermined temperature for a third predetermined time under second predetermined deposition rate conditions to obtain a functional thin film.

[0067] According to one embodiment of the present invention, the second predetermined deposition rate ranges from 5 nm / min to 15 nm / min, hi one example, the second predetermined deposition rate is 10 nm / min.

[0068] According to one embodiment of the present invention, the metal of the metal layer is at least one selected from the group consisting of platinum, iridium, ruthenium, and copper, hi one embodiment, the metal of the metal layer is platinum (Pt).

[0069] According to one embodiment of the present invention, the third predetermined temperature ranges from 20° C. to 40° C. In one example, the third predetermined temperature is 25° C.

[0070] According to one embodiment of the present invention, the third predetermined time period ranges from 2 minutes to 15 minutes. In one embodiment, the third predetermined time period is 5 minutes.

[0071] In the sixth stage of thin film formation, the formed thin film is annealed in an inert / oxygen atmosphere at a temperature range of 600°C to 800°C at a heating rate of 0.4°C / s to 1°C / s for 20 to 60 minutes to obtain an annealed thin film.

[0072] The annealing process converts the transition metal to a transition metal oxide, controls the diffusion of Ti into the top metal layer, and promotes crystallization of the top Pt metal layer along the direction of the close-packed FCC structure.

[0073] An Ar / O2 mixed gas atmosphere is used because Ti has high diffusion properties at high temperatures. Annealing in an inert atmosphere alone causes Ti to diffuse through the top Pt layer, disrupting the interface between the Pt and the next deposited layer. Annealing in an O2 atmosphere alone stops Ti diffusion into the top layer by forming an oxide with Ti. This is because Ti has multiple oxidation forms. It is difficult to identify the oxide form, and various titanium oxides (TiO) exist within the Ti and Pt layers. x- To solve these problems, it is necessary to ensure that under low oxygen concentration conditions, Ti is oxidized only within its own layer and that oxidation does not occur within the Pt layer, so a mixed gas of Ar gas and an O2 atmosphere is used, with a higher Ar ratio than Ti.

[0074] According to one embodiment of the present invention, the inert atmosphere is selected from the group consisting of argon, helium, and neon, hi one embodiment, the inert atmosphere is argon.

[0075] In the seventh step in the formation of the thin film, the annealed thin film is maintained as is for 20 to 60 minutes, after which it is cooled to a temperature range of 250 to 300°C, and then further cooled to a temperature range of 20 to 40°C to obtain the thin film.

[0076] The thin films of the present invention exhibit unique physical properties, such as strong adhesion, oxidation resistance, etch compatibility with standard microfabrication techniques, and good electrical conductivity. Additionally, the thin films of the present invention have well-defined interfaces between underlying layers, optimal layer thicknesses, stability in oxygen, high temperature processability, and the ability to be patterned into array-like structures over large areas by wet etching techniques.

[0077] The thin films of the present invention are used in the fabrication of hydrophones, pressure sensors, accelerometers, energy harvesters, and other piezoelectric-based MEMS devices.

[0078] In another aspect, the present invention provides a process for developing an array pattern in a thin film, which is described in detail below:

[0079] In the first step of forming an array pattern on a thin film, the transition metal oxide and metal layer on the top layer of the thin film is washed, and then the thin film is heated at a temperature in the range of 110°C to 150°C for 3 to 5 minutes to obtain a washed thin film.

[0080] Developing array patterns with well-defined boundaries requires cleanliness, which removes any impurity chemicals or particles present on the surface and provides the conditions necessary for good adhesion of the overlying layer.

[0081] In the second step of developing an array pattern on the thin film, a layer of photoresist material is coated onto the cleaned thin film using a spin coating process at a rotation speed of 3000 rpm to 5000 rpm for 10 seconds to 50 seconds to obtain a thin film having a coat of photoresist material.

[0082] According to one embodiment of the present invention, the photoresist material is ethyl methoxy-1-methylacetate (AZ 4000 series).

[0083] According to one embodiment of the present invention, the thickness of the photoresist material ranges from 3 μm to 10 μm.

[0084] In the third step, which involves developing an array pattern on the thin film, the thin film coated with the photoresist material is irradiated with ultraviolet light having a wavelength of 300 nm to 500 nm through a photomask to obtain a UV-irradiated thin film.

[0085] In the fourth step of developing the array pattern on the thin film, the UV-irradiated thin film is washed with a developer for 60 to 90 seconds to remove the soluble photoresist material, and then baked at a temperature range of 110°C to 130°C for 30 to 120 seconds, and then baked at 110°C to 130°C for another 10 to 15 minutes to obtain a thin film with the developed array pattern.

[0086] According to one embodiment of the present invention, the developer (MF 20A series) consists of the following components: The ratio of water to the total amount of the solution is in the range of 97.5% by mass to 98% by mass, Tetramethylammonium hydroxide (TMAH) is present in the range of 1.9% by mass to 2.45% by mass of the total solution, and Polyglycol in an amount ranging from 0.05% to 0.1% by weight relative to the total amount of said solution.

[0087] According to one embodiment, the developer (MF 20A series) comprises the following components: 97.5% by weight of water, 2.45% by weight of tetramethylammonium hydroxide (TMAH), and 0.05% by weight of polyglycol, based on the total weight of the solution.

[0088] The thin film on which the array pattern has been developed is etched by dissolving it in a HNO3:HCl:H2O solution with a molar ratio of 7:1:8 at a temperature range of 60°C to 80°C to obtain the array pattern on the thin film.

[0089] The above description of the embodiments has been provided for illustrative purposes and is not intended to limit the scope of the present invention solely to the scope of this description. Individual components of a particular example are generally not limited to that particular example and may be interchanged. Such variations cannot be considered distinct from the present invention, and all such variations are considered to be within the scope of the present invention.

[0090] The present invention is further illustrated by the following non-limiting embodiments, which are provided for illustrative purposes only and should not be construed as limiting the scope of the present invention. The following experiments can be scaled up to industrial / commercial scale, and the results obtained can be extrapolated to industrial scale.

[0091] Experiment 1: Fabrication process of thin film for developing array pattern according to the present invention.

[0092] Preparation of washed substrate:

[0093] First, to remove surface grease and prepare for use in the Si wafer dicing process, silicon wafers (substrates) were heated and cleaned using trichloroethylene (TCE) at 80°C for 5 minutes. After heating with TCE, they were cleaned in two steps using acetone and isopropanol. The silicon wafers were heated in acetone at 80°C for 5 minutes. Because acetone tends to leave residue on the silicon wafer (substrate) surface, the silicon wafers were immediately rinsed with isopropanol. The isopropanol prevents streak formation by acetone. The silicon wafers (substrates) were then rinsed with deionized water (DI water). Because clean DI water eliminates the cleaning effect of organic solvents, DI water with a resistivity of 18 MΩ was used.

[0094] Immediately afterwards, a silicon oxide layer was intentionally formed on the silicon surface by etching using nitric acid (HNO3) at 120 °C for 5–10 minutes. This silicon oxide layer was formed to renew the surface, followed by a hydrofluoric acid immersion process. The silicon oxide layer was removed by immersing the wafer in a 100:1 H2O:HF solution at room temperature for 1 minute. The H2O:HF solution ratio was selected to control the SiO2 layer removal rate while preventing deep etching into the Si wafer. Next, the silicon wafer (substrate) was rinsed with DI water at room temperature. The silicon wafer (substrate) was then dried with nitrogen (N2) gas. During the DI water rinse and air exposure process, the substrate surface absorbs water molecules. To remove the water molecules from the surface, the substrate was heated at 140 °C for several minutes to obtain the cleaned silicon wafer (substrate). Heating at temperatures above 140 °C removes OH bonds on the surface exposed to atmospheric humidity, improving adhesion during coating.

[0095] Formation of a reactive barrier layer on the substrate and insulating material:

[0096] The insulating material layer was deposited on a cleaned silicon wafer (substrate) by thermal oxidation treatment in a high-temperature furnace at 1050° C. for 100 minutes.

[0097] SiO2 was deposited on silicon wafers using a three-stage process: dry, wet, and dry oxide deposition. Cleaned silicon wafers were placed in a furnace located within a constant-temperature zone maintained at a constant temperature of 1050 °C. To prevent shock from sudden temperature changes, the cleaned silicon wafers were slowly introduced into the furnace. To ensure a good interface between the cleaned silicon wafer and the SiO2 layer, a 15 nm SiO2 layer was first deposited using a wet oxidation process. In the dry oxidation process, approximately 30 SCCM (standard cubic centimeters) of O2 was circulated through the furnace, and a dry oxide layer was formed at a deposition rate of 2.5 nm / min.

[0098] Next, a 500 nm SiO2 wet oxide layer was deposited on the dry oxide layer using a mixture of pure oxygen gas and O2 gas separated from H2O in a bubbler at a ratio of 3:1. The deposition rate was 6 nm / min, which was faster than the dry oxidation process. By forming a dry oxide layer on top of the wet oxide layer, good interface properties were obtained. A 25 nm dry oxide layer was deposited for 10 minutes to form a reaction prevention layer between the substrate (silicon wafer) and the insulating material (silicon dioxide).

[0099] Preparation of adhesion layers for substrates, insulating materials, transition metal oxides and thin film fabrication

[0100] The transition metal layer was deposited by DC magnetron sputtering.

[0101] The substrate (silicon wafer) and insulating material (silicon dioxide) barrier layer were fixed to a 4-inch substrate holder and then placed in the vacuum chamber of a sputtering deposition system. Circular Ti (transition metal) and Pt (metal) targets (99.99% purity), each 50.8 mm in diameter and 1.6 mm thick, were attached to two cylindrical magnetrons facing each other at an off-axis angle of 15°. Prior to Ti and Pt deposition, the target surfaces were cleaned with an isopropanol solution to remove impurities.

[0102] The distance between the source and substrate was kept constant at approximately 15 cm during the deposition of Ti and Ti. Sputtering was carried out under an argon (Ar) gas (inert gas) atmosphere. Ar gas acts as a carrier gas, and secondary electrons are transported to the Ar + The target atoms are ionized and ejected toward the substrate. -3 An Ar gas pressure of 100 mbar and a DC power of 85 W were applied, and high-pressure Ar gas was introduced to form a self-sustaining plasma.

[0103] The plasma power used for Pt and Ti deposition was 200 W. The substrate rotation was maintained at 5 rpm during deposition to ensure uniformity of film thickness across the wafer. Both Ti and Pt depositions were performed at room temperature. Figure 1 shows the operating pressure characteristics during Ti and Pt deposition. Base pressure was 5 × 10 -6 After the pressure reached 2.5 × 10 mbar, Ar was introduced into the chamber to ignite the plasma. -2 The pressure is then increased to 10 × 10 mbar for the deposition of Pt and Ti. -3 mbar and 10 x 10 -3 The pressure was reduced to 1000 mbar, respectively. Ti was evaporated onto a SiO2 wafer to form an adhesion layer of substrate (Si), insulating material (SiO2), and transition metal (Ti). Then, Pt was evaporated under vacuum to obtain a thin film. Ti was evaporated for 5 minutes at a deposition rate of approximately 10 nm / min to obtain a thickness of 35 nm, and Pt was evaporated for 5 minutes to obtain a thickness of 250 nm. After Pt deposition, the samples were annealed under furnace and ex-furnace conditions. One sample was annealed inside the sputtering chamber immediately after Pt deposition without breaking the vacuum.

[0104] The thin films were annealed using a high-temperature three-zone tube furnace (manufacturer: Ants Ceramics, India) in a mixed atmosphere of inert argon gas and reactive oxygen. The temperature of the tube furnace was increased from room temperature to 650 °C at a heating rate of 0.8 °C / s to convert the Ti layer to a TiO layer. The thin films were then held at the annealing temperature for 30 minutes. The thin films were then cooled to 300 °C over 30 minutes and then allowed to cool naturally to room temperature (Figure 2). After cooling, the thin films were obtained.

[0105] Experiment 2: Process for developing array patterns in thin films according to the present invention

[0106] An array pattern with box-like structures was obtained by an optical lithography process. A 4-inch chrome-coated glass mask was used to write an array of box-like patterns using a mask writer (DWL 66 Heidelberg Instruments GmbH, Germany). A 6-μm thick photoresist material, 2-methoxy-1-methylethyl acetate (AZ Series 4562), was coated on the top layer of Pt / TiO2 using a spin coater at 4000 rpm for 40 seconds. Prior to photoresist coating, the Pt / TiO2 layer was treated with conventional organic solvent cleaning and then heated at 110 to 150 °C for 3 to 5 minutes. The photoresist material was selected to provide a barrier against Pt / TiO2 etching in the patterned areas and to provide high selectivity in the wet etching process. After collimating the mask with the top Pt / TiO2 layer, it was irradiated with UV light at a wavelength of 365 nm. The UV power intensity was 500 W, and the mask exposure energy was 18 mJ / cm. 2 The mask was then exposed to UV light for 10 to 13 seconds. The mask was then developed for 90 seconds using MF26A developer, which is composed of 97.5% water, 2.45% tetramethylammonium hydroxide (TMAH), and 0.05% polyglycol by weight, and soft-baked at 110 to 130°C for 1 minute. The developed pattern was inspected using an optical microscope and then hard-baked at 110 to 130°C for 10 to 15 minutes.

[0107] Pt wet etching was performed by immersing the thin film with the developed lithographic pattern in aqua regia. Aqua regia is a mixture of nitric and hydrochloric acids, capable of etching selected precious metals. This is because platinum's inherent inertness limits its etching in most solvents. To obtain reproducible etching results, the aqua regia solution was prepared in a 7:1:8 (HNO3:HCl:H2O) mixture. The components of the aqua regia were selected to facilitate control of the etch rate. The top Pt layer was etched at 70 °C for 5 minutes, resulting in a uniform Pt edge with excellent clarity. Next, the TiO2 layer was etched using ammonium hydroxide (NH4OH, 26%) and hydrogen peroxide (H2O2, 30%) for 60 to 90 seconds at 70 °C. After etching the Pt / TiO2 layer, the remaining photoresist material was removed by dissolving it in acetone. Excellent clarity of the developed pattern was confirmed by optical microscopy after dissolution. Figure 3 shows a schematic diagram of the array developed in the thin film.

[0108] Experiment 3: Qualitative analysis of the array pattern developed on the thin film obtained in Experiment 2 of the present invention

[0109] X-ray diffraction

[0110] The array patterns developed on the thin films obtained in Experiment 2 were investigated using a Rigaku Grazing Incidence X-ray Diffraction (GIXRD) system under the following conditions: CuKα radiation (λ = 0.15418 nm), operating voltage 40 kV, current 30 mA, and grazing angle 1°. All XRD patterns were recorded in theta-2theta mode, from 20° to 70°, with a scan rate of 2° / min and a step size of 0.01°. The XRD patterns were analyzed using X'Pert High Score Plus software and compared with the Joint Powder Diffraction Data Standard (JCPDS). X-ray diffraction patterns of the ex-furnace annealed Pt / Ti thin films were measured at five locations on the wafer; the results are shown in Figure 5.

[0111] Figure 4a shows the X-ray diffraction characteristics of the array pattern developed on the thin film, and Figure 4b shows the X-ray diffraction mapping of the entire pattern.

[0112] Based on this XRD pattern, it can be inferred that the annealed Pt thin film exhibited a very strong Pt peak at 2θ = 39.76° at every point across the wafer, with no impurity peaks observed. The XRD pattern showed only oriented Pt peaks, with no other crystal planes belonging to Pt, suggesting that the Pt was crystallized in a face-centered cubic unit cell (FCC) structure. The full width at half maximum (FWHM) of the Pt peak, calculated based on the XRD pattern, ranged from 0.25 to 0.27, indicating good crystallization of the Pt thin film. The FWHM values ​​were identical for all diffraction points, indicating high-quality, uniformly crystallized Pt thin films across the wafer.

[0113] Surface morphology: Field emission scanning electron microscope (FE-SEM)

[0114] The surface morphology of the array pattern developed on the thin film was analyzed using a Carl SUPRA-55 field emission scanning electron microscope (FE-SEM). a ) and root mean square roughness (RMS) were measured using an atomic force microscope (AFM) (Bruker Dimension Edge, USA) in tapping mode.

[0115] Figure 6(a) shows a cross-sectional image of a thin film according to the present invention taken by a field-emission scanning electron microscope (FESEM), and Figure 6(b) shows a planar FESEM image of the same thin film. It is clear from Figure 6(a) that the cross-section shows a 40 nm thick TiO2 and 200 nm thick Pt layer. The pattern developed in the thin film has a columnar grain structure and densifies along the thickness mode. The FESEM cross-sectional image of the pattern developed in the thin film clearly shows distinct interfaces between the layers. In the planar image, the pattern developed in the thin film exhibits grain growth that densifies perpendicular to the film surface. This type of growth mode is expected, as the XRD pattern shows a predominantly directional pattern along the crystal orientation.

[0116] electrical resistivity

[0117] The electrical resistivity of the platinized silicon thin films was measured at room temperature using the four-point resistivity probe method. Low altitude measurements were taken at five points on the wafer, and all points exhibited similar characteristics, as shown in Figure 6. The electrical resistivity of the platinized silicon thin films annealed in both the furnace and ex-furnace environments was in the range of 11–13 μΩ·cm, indicating a nearly uniform electrical resistivity across the entire wafer. In general, the resistivity of Pt thin films was below 50 μΩ·cm, and the resistivity of the platinized silicon thin films annealed under different conditions was all significantly below 50 μΩ·cm.

[0118] Atomic force microscope (AFM) images

[0119] The surface morphology and surface roughness of the array pattern developed on the thin film were analyzed using a non-contact tapping mode atomic force microscope (AFM). The surface roughness was scanned over a 5 μm x 5 μm area from the coating surface, and the morphological features are shown in Figure 7. In accordance with the present invention, Figure 7(a) shows a three-dimensional (3-D) atomic force microscope (AFM) topography image of the thin film, and Figure 7(b) shows a planar (2-D) AFM image of the same thin film.

[0120] The surface morphology of this thin film exhibited a smooth and dense surface, with a root-mean-square roughness of 4.84 nm and an average roughness of 3.85 nm. Based on AFM microscopy images, it was found that the thin film was crystallized without cracks and was uniformly distributed.

[0121] The present invention as described above represents several technological advances, including but not limited to the realization of an array pattern developing thin film having the following features: Strong adhesion, excellent oxidation resistance, etching compatibility with standard microfabrication techniques, and good electrical conductivity. · Exhibits denser and more uniform grain growth without cracks, Stable under oxygen and high temperatures The array structure can be patterned using a wet etching process.

[0122] moreover A manufacturing process for thin film array development with the following features: · Simple and economical.

[0123] Throughout this specification, the terms "comprise" and "constitute" and their variants "composed" or "comprising" are intended to imply the inclusion of a stated element, integer or step or group of elements, integers or steps, but not the exclusion of other elements, integers or steps or other groups of elements, integers or steps.

[0124] The use of the phrase "at least" or "at least one" suggests the use of one or more elements or ingredients or quantities, as may be used in the practice of the invention to achieve one or more desired substances or results. While several embodiments of the invention have been described, these embodiments are set forth by way of example only and are not intended to limit the scope of the invention. Formulations or modifications of the manufacture of the invention may be made by one skilled in the art upon consideration of the present invention, provided they fall within the scope of the invention. Such variations and modifications are within the intended scope of the invention.

[0125] Numerical values ​​representing different physical parameters, dimensions, and quantities are approximate, and any higher value substituted for the physical parameter, dimension, or quantity is intended to be within the scope of the present invention, unless expressly stated to the contrary in the specification.

[0126] While considerable emphasis has been placed on certain features of the present invention, various modifications can be made, and many additions can be made to the preferred embodiment without departing from the principles of the invention. Modifications to the characteristics of the present invention or the preferred embodiment will be apparent to those skilled in the art, and it should be clearly understood that the foregoing description is merely illustrative of the present invention and should not be construed as limiting.

[0127] During the prosecution of a patent application, detailed requirements for economic significance may be required. Only after the filing of this application can the applicant carry out the work disclosed in relation to the product / process / method herein. The applicant intends to disclose all details related to the contribution to economic advantage only after the expiration of the protection period of the invention.

Claims

1. A thin film for developing an array pattern, - one or more substrates in at least one layer; - at least one layer of one or more insulating materials; at least one layer of one or more transition metal oxides, and - at least one layer of one or more metals; The developing thin film has a structure in which the transition metal oxide layer is sandwiched between the insulating material layer and the metal layer.

2. A thin film as claimed in claim 1, wherein the substrate is silicon, sapphire (Al 2 O 3 ), magnesium oxide (MgO), gallium nitride (GaN), and silicon carbide (SIC).

3. A thin film as claimed in claim 1, wherein said substrate layer has a thickness in the range of 200 μm to 400 μm.

4. A thin film as claimed in claim 1, wherein the insulating material is silicon dioxide (SiO 2 ) and silicon nitride (SiN).

5. A thin film as claimed in claim 1, wherein the thickness of said insulating material layer is in the range of 500 nm to 600 nm.

6. A thin film as claimed in claim 1, wherein said transition metal oxide is at least one selected from the group consisting of titanium dioxide and zirconium oxide.

7. A thin film as claimed in claim 1, wherein the thickness of said transition metal oxide layer is in the range of 30 nm to 100 nm.

8. The thin film as claimed in claim 1, wherein the metal constituting the metal layer is at least one selected from the group consisting of platinum (Pt), iridium, ruthenium, and copper.

9. A thin film as claimed in claim 1, wherein the thickness of said metal layer is in the range of 200 nm to 300 nm.

10. A thin film as claimed in claim 1, wherein the thickness of said thin film is in the range of 200 μm to 500 μm.

11. The thin film claimed in claim 1 has the following features: - Electrical resistivity is in the range of 10μΩ-cm to 15μΩ-cm, - Full width at half maximum (FWHM) is in the range of 0.1 to 0.5, - Root mean square roughness is 2 nm to 8 nm.

12. A process for producing a thin film for developing an array pattern, said process comprising the steps of: Obtaining a substrate with a predetermined thickness, washing the substrate to obtain a washed substrate; Applying at least one layer of insulating material to the working surface of the vapor-deposition-cleaned substrate by thermal oxidation at a first predetermined temperature for a first predetermined time period to obtain a layer that prevents reaction between the substrate and the insulating material. In a fourth step of the thin film formation, a layer of at least one transition metal is deposited on the working surface of the reaction barrier layer in an inert atmosphere at a second predetermined temperature for a second predetermined time under the first predetermined deposition rate conditions to obtain an adhesive layer of the substrate, the insulating material and the transition metal oxide. Depositing at least one metal layer on the working surface of the adhesive layer in an inert atmosphere at a third predetermined temperature for a third predetermined time under second predetermined deposition rate conditions to obtain a functional thin film. Annealing the thin film in an inert / oxygen atmosphere at a temperature range of 600°C to 800°C at a heating rate of 0.4°C / s to 1°C / s for 20 to 60 minutes to obtain an annealed thin film; The annealed thin film is held for 20 to 60 minutes, then cooled to a temperature range of 250 to 300°C, and further cooled to a temperature range of 20 to 40°C to obtain the thin film.

13. The process as claimed in claim 12, wherein the substrate is silicon, sapphire (Al 2 O 3 ), magnesium oxide (MgO), gallium nitride (GaN), and silicon carbide (SIC).

14. 13. The process as claimed in claim 12, wherein said insulating material is silicon dioxide (SiO 2 ) and silicon nitride (SiN).

15. A process as claimed in claim 12, wherein said first predetermined temperature is in the range of 900°C to 1200°C and said predetermined time is in the range of 60 minutes to 180 minutes.

16. 13. The process as claimed in claim 12, wherein said transition metal is at least one selected from the group consisting of titanium and zirconium.

17. 13. The process as claimed in claim 12, wherein said inert atmosphere is at least one selected from the group consisting of argon, helium, and neon.

18. A process as claimed in claim 12, wherein said second predetermined temperature is in the range of 20°C to 40°C and said second predetermined time is in the range of 2 minutes to 15 minutes.

19. 13. The process as claimed in claim 12, wherein the first predetermined deposition rate is in the range of 5 nm / min to 15 nm / min.

20. 13. The process as claimed in claim 12, wherein said metal is at least one selected from the group consisting of platinum, iridium, ruthenium, and copper.

21. A process as claimed in claim 12, wherein said third predetermined temperature is in the range of 20°C to 40°C, and said third predetermined time is in the range of 2 minutes to 15 minutes.

22. A process as claimed in claim 12, wherein the second predetermined deposition rate is in the range of 5 nm / min to 15 nm / min.

23. 1. A process for developing an array pattern in a thin film, said process comprising the steps of: As claimed in claim 1, cleaning the top layer of transition metal oxide and metal from the thin film, and then heating it at a temperature range of 110°C to 150°C for 3 to 5 minutes to obtain a cleaned thin film; applying a layer of photoresist material to the cleaned thin film using a spin-coating process at a rotation speed of 3000 rpm to 5000 rpm for a time period of 10 seconds to 50 seconds to obtain a thin film coated with photoresist material; - Irradiating the thin film coated with the photoresist material with UV light having a wavelength of 300 nm to 500 nm through a photomask to obtain a UV-irradiated thin film; The UV-irradiated thin film is washed in a developer for 60 to 90 seconds to remove the soluble photoresist material, and then baked at a temperature range of 110°C to 130°C for 30 to 120 seconds, and then baked at 110°C to 130°C for an additional 10 to 15 minutes to obtain a thin film with a developed array pattern; The thin film on which the array pattern was developed was treated with HNO3 in a molar ratio of 7:1:8 at a temperature range of 60 to 80°C. 3 :HCl:H 2 The thin film is dissolved in an O solution and etched to obtain the above-mentioned array pattern.

24. 24. The process as claimed in claim 23, wherein said photoresist material is propylene glycol monomethyl ether acetate, PGMEA (AZ 4000 series).

25. 24. The process as claimed in claim 23, wherein the developer solution comprises: - water in an amount ranging from 97.5% to 98% by weight relative to the total amount of the solution; tetramethylammonium hydroxide (TMAH) in an amount ranging from 1.9% to 2.45% by weight relative to the total amount of the solution; - polyglycol in an amount ranging from 0.05% to 0.1% by weight relative to the total amount of said solution.

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