Semiconductor devices and methods for producing semiconductor devices - Patents.com

Abstract

The semiconductor device (100) comprises a semiconductor body (10) having a top surface (11) and a bottom surface (19). A first main electrode (2) is disposed on the top surface, and a second main electrode (3) is disposed on the bottom surface. The semiconductor device comprises a gate electrode (4) and at least two trenches, namely, a first type trench (51) and a second type trench (52). The semiconductor body comprises a drift region (14) of a first conductivity type and at least three base regions (13a, 13b, 13c), each of a second conductivity type. The semiconductor body further comprises an implanted region (12) of the first conductivity type. The first main electrode is in electrical contact with the implanted region. A gate electrode extends into the first type trench. The second type trench does not have a gate electrode. The third base region includes at least one contact area (6c) through which the third base region is in electrical contact with an electrode of the semiconductor device different from the gate electrode.

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE The present disclosure relates to semiconductor devices and methods for producing semiconductor devices. [Background technology]

[0002] There is a need for improved semiconductor devices, for example, semiconductor devices having improved static and / or dynamic behavior, and there is a further need to provide methods for producing such semiconductor devices. Summary of the Invention [Means for solving the problem]

[0003] FIELD OF THE DISCLOSURE Embodiments of the present disclosure relate to semiconductor devices and methods for producing semiconductor devices.

[0004] First, the semiconductor device is described. According to one embodiment, a semiconductor device comprises a semiconductor body extending vertically between a top surface and a bottom surface. A first main electrode is disposed on the top surface, and a second main electrode is disposed on the bottom surface. The semiconductor device further comprises a gate electrode and at least two trenches, namely, a first type trench and a second type trench, each extending from the top surface into the semiconductor body. The semiconductor body comprises a drift region of a first conductivity type disposed vertically between the top surface and the bottom surface, and at least three base regions, namely, a first base region, a second base region, and a third base region, each of which is of a second conductivity type and each of which is disposed vertically between the drift region and the top surface. The semiconductor body further comprises an implanted region of the first conductivity type vertically spaced from the drift region by the first base region and adjacent to the first base region. The first base region, the first-type trench, the second base region, the second-type trench, and the third base region are arranged in this order in a first lateral direction. A first main electrode is in electrical contact with the implanted region. A gate electrode extends into the first-type trench and is separated from the semiconductor body in the first-type trench by a gate insulating layer. The second-type trench does not have a gate electrode.

[0005] The arrangement having the second type trench, the second base region, and the third base region serves, among other things, to protect the first type trench, and particularly the gate insulating layer therein, from avalanching, for example, during a switching event.

[0006] The semiconductor device described herein may be a power semiconductor device, for example configured to carry a current of at least 10 A and / or handle a voltage of at least 1000 V or at least 3000 V. The semiconductor device may be a transistor device, particularly a gate-insulated transistor device, particularly an IGFET.

[0007] The semiconductor body may be based on silicon or silicon carbide. The thickness of the semiconductor body measured in the vertical direction is, for example, at least 100 μm or at least 200 μm and / or at most 500 μm. The top and bottom surfaces are surfaces of the semiconductor body and vertically bound the semiconductor body.

[0008] The first main electrode and / or the second main electrode may include or consist of a metal. Depending on the type of semiconductor device, the first electrode may also be referred to herein as an "emitter electrode" or a "source electrode," and the second main electrode may also be referred to herein as a "collector electrode" or a "drain electrode."

[0009] The gate electrode may comprise metal and / or heavily doped polysilicon. The gate electrode is in particular an insulated gate electrode, i.e., electrically isolated from the semiconductor body. This can be achieved, for example, by using a gate insulating layer.

[0010] The trenches extend from the upper surface of the semiconductor body into the semiconductor body and terminate within the semiconductor body, for example, in the drift region. The trenches may have the same depth measured in the vertical direction. The trench depth may be at least 1 μm or at least 5 μm and / or at most 20 μm or at most 10 μm. The trenches may each be elongated and each extend laterally, the laterally direction being defined herein as the direction perpendicular to the vertical direction. The laterally direction is, in particular, a direction parallel to the main extension plane of the semiconductor body. For example, the trenches extend parallel to each other.

[0011] The first type trenches and the second type trenches may be spaced apart from each other in a first lateral direction. Each trench may extend in a second lateral direction perpendicular to the first lateral direction. The average distance between the first type trenches and the second type trenches is, for example, at least 100 nm or at least 500 nm and / or at most 2 μm. The distance between two trenches is defined herein as, for example, the pitch between the trenches, i.e., the distance between the centers of the trenches. For example, no additional trenches are arranged between the first type trenches and the second type trenches in the lateral direction.

[0012] The first type of trench is filled with a conductive material that is spatially and electrically separated from the semiconductor body by a gate insulating layer. The gate insulating layer may be an oxide, such as SiO2. The gate insulating layer may have a thickness of at least 10 nm and / or up to 200 nm. For example, the gate insulating layer may have a thickness of at least 50 nm and at most 150 nm.

[0013] In this specification, "electrically isolated" particularly means that there is no electrical contact between two elements. Two electrically isolated elements are configured, for example, to be electrically biased or controlled independently of each other. This means that they are configured to be at different potentials during operation of the semiconductor device. Two electrically isolated elements may particularly be electrically insulated from each other, i.e., no current can flow between them.

[0014] The conductive material in the first type trench may be metal and / or heavily doped polysilicon. The conductive material in the first type trench is part of the gate electrode, i.e., it is electrically connected to the gate electrode. When two elements are electrically connected or in electrical contact, this means that the two elements are not independently electrically biasable or controllable. Therefore, they are always at the same potential. The first type trench is also referred to herein as an active trench.

[0015] For example, the conductive material in the first type of trench extends into the semiconductor body at least as deep as the first base region and / or the second base region.

[0016] The second type of trench does not have a gate electrode, i.e., the second type of trench is a gate electrode-free trench. In other words, the second type of trench is electrically isolated from the gate electrode.

[0017] The second type of trench may also be filled with a conductive material that may be separated from the semiconductor body by an insulating layer. However, this conductive material is electrically isolated from the gate electrode, i.e., not electrically connected to it. The insulating layer may be the same as the gate insulating layer. Within the second type of trench, the conductive material may extend into the semiconductor body to the same depth as the first and / or second base regions. The conductive material within the second type of trench may be metal and / or heavily doped polysilicon.

[0018] For example, the conductive material in the second type of trench is electrically connected to the first main electrode, or in other words, the first main electrode may extend into the second type of trench.

[0019] Instead of being filled with a conductive material, the second type of trench may be free of a conductive material, for example, filled only with an electrically insulating material.

[0020] The second type of trench is also referred to herein as a "non-active trench." The drift region of the semiconductor body is of a first conductivity type. The first conductivity type is, for example, n-type, i.e., the drift region is n-doped. The second conductivity type is opposite to the first conductivity type and may therefore be p-type. However, the reverse case, where the first conductivity type is p-type and the second conductivity type is n-type, may also be realized.

[0021] For example, the drift region extends continuously across all of the base regions, i.e., in a top view, the drift region overlaps all three base regions.

[0022] The first type trench is disposed in a first lateral direction between the first base region and the second base region, e.g., the first type trench is adjacent to the first base region on one side and / or the second base region on the other side.

[0023] The second base region may be disposed between the first type trench and the second type trench in the first lateral direction, may be adjacent to the second type trench, or may extend continuously, for example without interruption, from the first type trench to the second type trench.

[0024] The second type trench may be disposed between the second base region and the third base region in the first lateral direction, and may be adjacent to the third base region.

[0025] The third base region may extend continuously, e.g., uninterrupted, in the first lateral direction from the second type trench to a further trench spaced apart from the second type trench, which may be another second type trench, i.e., electrically isolated from the gate electrode or not filled with the gate electrode.

[0026] The structure including the first base region and adjacent implantation structure, first-type trench, second base region, second-type trench, and third base region may be repeated several times along the top surface. A structure including at least a portion (half) of the first base region and a portion (half) of the adjacent implantation region, first-type trench, second base region, second-type trench, and third base region may also be called a "half cell" or "transistor half cell." A semiconductor device may include several such half cells, which may be arranged in sequence in the first lateral direction. Each two adjacent half cells may be mirror-symmetric with respect to a mirror plane. The mirror plane may extend, for example, perpendicular to the first longitudinal direction. The mirror plane may intersect the first base region and / or the third base region at half their respective extension ranges in the first lateral direction.

[0027] The semiconductor body includes an implanted region of a first conductivity type. The implanted region is vertically spaced from the drift region by the first base region and is adjacent to the first base region. The implanted region may, for example, extend to the top surface. The implanted region may be embedded in the first base region. For example, the implanted region may be adjacent to the first type trench on the same side as the first base region is adjacent to the first type trench. Each half cell may include exactly one such implanted region. The implanted region is also referred to as a source region.

[0028] The injection region is in electrical contact with, e.g., adjacent to, the first main electrode. During operation of the semiconductor device in a (static) transistor mode, charge carriers of a first type, e.g., electrons, are injected into the injection region from the first main electrode. The semiconductor device is configured such that application of a specific potential to the gate electrode depletes the first base region adjacent to the first type of trench, thereby forming a path for the first type of charge carriers from the injection region toward the drift region, the path extending vertically along the first type of trench.

[0029] The second base region may form part of the top surface, for example the entire part of the top surface that is located laterally between the first type trench and the second type trench, e.g., the semiconductor body does not have any (implanted) region of the first conductivity type that is arranged vertically between the second base region and the top surface and adjacent to the second base region.

[0030] The third base region may also form part of the top surface, for example the entire part of the top surface that is located in the laterally direction between two trenches that laterally bound the third base region. The semiconductor body may be free of any (implanted) region of the first conductivity type that is arranged in the vertical direction between the third base region and the top surface and adjacent to the third base region.

[0031] According to a further embodiment, the third base region comprises at least one contact area in which the third base region is in electrical contact with an electrode of the semiconductor device different from the gate electrode, e.g., controllable / biasable independently of the gate electrode.

[0032] During operation, charge carriers can be extracted from the semiconductor body through the contact area. Therefore, the contact area is sometimes referred to as an "extraction area." Such an extraction area can be advantageous during switching events, such as during transistor turn-off, because it helps rapidly reduce plasma concentration within the semiconductor body. That is, the contact area constitutes a plasma control mechanism. On the other hand, when the semiconductor device operates in diode mode, electrical contact between the electrode in the contact area and the semiconductor body provides an additional charge carrier path that reduces on-state losses in diode mode. Because the contact area is in electrical contact with an electrode different from the gate electrode, the charge carrier path is independent of the gate electrode potential. The location of the third base region contact area, i.e., its location separated from the first-type trench by the second-type trench, helps protect the gate insulating layer within the first-type trench during switching events by reducing avalanche generation in the region of the first-type trench.

[0033] For example, an electrode to which the third base region is electrically connected in the contact area is disposed on the upper surface, and the electrode may be the first main electrode or another electrode that can be controlled independently of the first main electrode.

[0034] The contact area belongs to the third base region and is therefore also referred to herein as a third contact area. The contact area may form part of the top surface. The third base region may be adjacent to the electrode over the entire area of ​​the contact area. When viewed from above, the area of ​​the contact area is in particular smaller than the area of ​​the third base region. For example, in this top view, the area of ​​the contact area is at most 50%, or at most 10%, or at most 5%, or at most 1% of the area of ​​the third base region. In the case of several contact areas, all features disclosed for one contact area are also disclosed for the other contact areas.

[0035] According to a further embodiment, the third base region is electrically connected to the first main electrode in at least one contact area, for example, the first main electrode is adjacent to the third base region in the contact area.

[0036] According to a further embodiment, the third base region is electrically connected to an electrode in at least one contact area configured to be operated independently of the first main electrode, and thus this electrode, also referred to herein as further electrode, is configured to be at a potential that is independent of and different from the potentials of the gate electrode and the first main electrode.

[0037] According to a further embodiment, the semiconductor device is an RC-IGBT, ie a reverse-conducting IGBT (RC-IGBT), or a MISFET, in particular a MOSFET.

[0038] RC-IGBTs and MOSFETs are semiconductor devices that can operate in reverse, or diode, mode. For such devices, the contact area where the third base region is in electrical contact with the electrode, as explained above, is particularly useful.

[0039] According to a further embodiment, the second base region includes at least one contact area through which the second base region is in electrical contact with an electrode of the semiconductor device different from the gate electrode. This electrode may be the same electrode that is in electrical contact with the third base region in the respective (third) contact area. The contact area of ​​the second base region, also referred to herein as the second contact area, may form part of the top surface. The second contact area may have an area smaller than the area of ​​the second base region when viewed from the top. The same relative sizes as disclosed in connection with the (third) contact area of ​​the third base region may apply here as well.

[0040] The contact area of ​​the second base region provides an additional degree of freedom for optimizing the charge carrier extraction during turn-off in transistor mode and / or in diode mode, for example.

[0041] According to a further embodiment, the first base region includes at least one contact area through which the first base region is in electrical contact with an electrode of the semiconductor device different from the gate electrode. This electrode may also be the same electrode that is in electrical contact with the third base region in the respective (third) contact area. The contact area of ​​the first base region, also referred to herein as the first contact area, may be adjacent to the top surface and / or the implanted region.

[0042] The contact area of ​​the first base region provides another degree of freedom for optimizing the charge carrier extraction during turn-off in transistor mode and / or in diode mode, for example.

[0043] According to a further embodiment, the third base region includes a plurality of (third) contact areas. The third base region is in electrical contact with an electrode at each of these contact areas. For example, the contact areas of the third base region are spaced apart from one another in at least one lateral direction, e.g., the first lateral direction. All features disclosed in relation to one contact area of ​​the third base region are also disclosed for all other contact areas of the third base region.

[0044] The contact areas of the third base region may each be formed, for example, as a second laterally extending stripe.

[0045] Each of the two contact areas of the third base region may be spaced apart from each other. In an area outside the contact areas, there is no direct electrical contact between the electrode and the third base region. In particular, outside the contact areas, the electrode is not adjacent to the third base region. For example, the contact areas of the third base region may be arranged in a rectangular pattern when viewed from above. For example, at most 50% and / or at least 10% of the area of ​​the third base region may be formed by the contact areas when viewed from above.

[0046] In either case, the contact areas are part of the respective base regions and therefore are of the second conductivity type. In each base region, at least one contact area may be spaced apart from a trench that laterally bounds the respective base region.

[0047] According to further embodiments, the third base region extends from the top surface into the semiconductor body at least as deep as the second-type trenches and / or the first-type trenches. For example, the third base region extends deeper into the semiconductor body than the second-type trenches and / or the first-type trenches. It has been found that such a design can significantly reduce the avalanche intensity near the first-type trenches.

[0048] According to further embodiments, the first type trenches and the second type trenches have the same depth. Alternatively, the second type trenches may extend deeper into the semiconductor than the first type trenches. It has been found that such deeper second type trenches further aid in keeping avalanches away from the first type trenches.

[0049] According to a further embodiment, the third base region extends below the second type trench toward the first type trench, so that the second type trench and the third base region may overlap each other in top view.

[0050] According to further embodiments, the doping concentration of the third base region is higher in the at least one contact area than in a region laterally adjacent to the contact area, for example in the contact area the doping concentration is at least one order of magnitude higher, or at least two orders of magnitude higher, or at least three orders of magnitude higher than in a region laterally surrounding the at least one contact area.

[0051] According to a further embodiment, the semiconductor body comprises a conductive layer disposed on the top surface of the semiconductor body above the third base region. The conductive layer is electrically connected to an electrode of the semiconductor device that is different from the gate electrode. This means that the conductive layer is configured to be electrically biased / controlled independently of the gate electrode, i.e., can be set to a potential that is different from the potential of the gate electrode.

[0052] The conductive layer on the upper surface above the third base region may comprise or consist of metal and / or heavily doped polysilicon. For example, the conductive layer may be electrically connected to the first main electrode or to an electrode that is controllable / biasable independently of the first main electrode.

[0053] In top view, the conductive layer and the third base region at least partially overlap each other, i.e., in top view, the conductive layer covers at least a portion of the third base region. The conductive layer may be a continuous layer or may be formed from several segments spaced apart from each other in at least one lateral direction. The conductive layer in particular extends parallel to the top surface of the semiconductor body and / or parallel to the main extension plane.

[0054] According to a further embodiment, the conductive layer is located near the third base region such that, by electrically biasing the conductive layer, a strong capacitive coupling between the third base region and the conductive layer can be achieved, such that the free charge carriers in the third base region are influenced thereby. "Influenced" means, for example, that the free charge carriers are attracted or repelled by the conductive layer. In particular, the free charge carriers are charge carriers of a second type depending on the conductivity type of the third base region. Thus, if the third base region is p-doped, the free charge carriers may be holes.

[0055] Such a conductive layer can improve the operation of the semiconductor device. For example, during static operation, the conductive layer can repel free charge carriers in the third base region to maintain a high electron-hole plasma in the semiconductor body or shift it toward the gate electrode in the first-type trench. When switching the semiconductor device, the conductive layer can attract second-type charge carriers to draw the electron-hole plasma away from the first-type trench. This reduces the risk of damage to the gate insulating layer in the first-type trench, for example due to avalanche.

[0056] The maximum distance between the third base region and the conductive layer to achieve such strong capacitive coupling depends on several factors, such as the potential applied to the conductive layer, the material disposed vertically between the conductive layer and the semiconductor body over the lateral extent of the conductive layer, etc. For example, the maximum vertical distance between the conductive layer and the third base region is on the same order of magnitude as the thickness of the gate insulating layer.

[0057] According to a further embodiment, the conductive layer is spaced from the upper surface of the semiconductor body by an electrically insulating layer disposed vertically between the upper surface and the conductive layer. The electrically insulating layer may be made of an oxide. For example, it may be made of the same material as the gate insulating layer. For example, the electrically insulating layer may be made of SiO2.

[0058] For example, the conductive layer is separated from the top surface only by the electrically insulating layer. That is, the vertical distance between the top surface and the conductive layer is defined by the thickness of the electrically insulating layer. The electrically insulating layer may fill a majority of the space between the conductive layer and the top surface of the semiconductor body. For example, at least 70%, or at least 80%, or at least 90% of the volume between the conductive layer and the top surface is filled by the electrically insulating layer.

[0059] According to further embodiments, the thickness of the electrical insulating layer is at most 5 times, or at most 3 times, or at most 1.5 times the thickness of the gate insulating layer.

[0060] According to further embodiments, the vertical distance between the conductive layer and the third base region is at most 500 nm, or at most 300 nm, or at most 150 nm. Additionally or alternatively, the vertical distance between the conductive layer and the third base region may be at least 10 nm or at least 50 nm. This minimum distance exists at least in certain regions of the conductive layer.

[0061] According to a further embodiment, the conductive layer and the third base region are electrically isolated from each other, i.e., the semiconductor device has no (direct) electrical connection between the conductive layer and the third base region. For example, the electrically insulating layer then extends continuously and uninterruptedly between the conductive layer and the upper surface of the semiconductor body and over the entire lateral extent of the conductive layer.

[0062] According to a further embodiment, an electrical connection is formed between the conductive layer and the third base region. For example, the conductive layer is in electrical contact with the third base region at one or more contact areas of the third base region. The conductive layer may be adjacent to the third base region at these contact areas.

[0063] According to further embodiments, the conductive layer covers a large portion of the third base region in a top view. For example, in this plan view, the conductive layer covers at least 60%, at least 80%, or at least 90% of the third base region. Additionally or alternatively, in this top view, the conductive layer does not overlap the second type of trenches and / or does not overlap any of the trenches that laterally bound the third base region. In this top view, it is also possible for the conductive layer to overlap any one of the second type of trenches or the trenches that laterally bound the third base region, but not extend laterally beyond this / these trenches.

[0064] According to a further embodiment, the conductive layer is arranged in the vertical direction between the top surface of the semiconductor body and a portion of the emitter electrode, e.g., in a top view, the portion of the emitter electrode and the conductive layer overlap each other, e.g., in this top view, the portion of the emitter electrode completely covers the conductive layer.

[0065] According to further embodiments, the vertical distance between the conductive layer and the third base region is at most half, at most one-fifth, or at most one-tenth of the vertical distance between the portion of the emitter electrode and the top surface of the semiconductor body. In particular, the portion of the emitter electrode is far enough away from the third base region that it is not capacitively coupled to the third base region.

[0066] For example, the vertical distance between said portion of the emitter electrode and the top surface is at least 800 nm, or at least 1 μm, or at least 1.5 μm.

[0067] There may be an additional electrically insulating layer disposed vertically between the top surface of the semiconductor body and the portion of the emitter electrode. The thickness of this additional electrically insulating layer may define the distance between the portion of the emitter electrode and the top surface. The additional electrically insulating layer may be an oxide such as SiO2. It is also referred to herein as a "field insulating layer."

[0068] According to a further embodiment, at least one contact area of ​​the third base region and the conductive layer overlap each other in top view. For example, in the contact area, the third base region is conductively connected to the conductive layer. Alternatively, a hole may be formed through the conductive layer, through which an electrode that contacts the third base region in the contact area is guided. In the hole, the electrode may be spaced from the conductive layer, for example, by an electrically insulating layer.

[0069] Next, a method for producing a semiconductor device is described. For example, the semiconductor devices specified herein can be produced by this method. Accordingly, all features disclosed in relation to the semiconductor device are also disclosed in relation to the method, and vice versa.

[0070] According to one embodiment, a method for producing a semiconductor device includes providing a semiconductor body having a top surface and a bottom surface. Then, at least two trenches, a first type trench and a second type trench, are formed in the semiconductor body, each extending from the top surface into the semiconductor body. Furthermore, a first main electrode is formed on the top surface of the semiconductor body, and a second main electrode is formed on the bottom surface. A gate electrode is formed extending into the first type trench, where it is separated from the semiconductor body by a gate insulating layer. The second type trench remains without a gate electrode. The semiconductor device is formed such that the semiconductor body includes a drift region of a first conductivity type vertically disposed between the top surface and the bottom surface, and at least three base regions, a first base region, a second base region, and a third base region, each of which is a second conductivity type and is vertically disposed between the drift region and the top surface. The semiconductor body further includes an implanted region of a first conductivity type adjacent to the drift region and vertically spaced from the drift region by a first base region. The first base region, the first type trench, the second base region, the second type trench, and the third base region are sequentially arranged in that order in a first lateral direction. The first main electrode is in electrical contact with the implanted region.

[0071] The trench may be formed in the semiconductor body before the base region and the implant region are formed, or the base region may be at least partially formed before the trench is formed.

[0072] According to a further embodiment, the semiconductor device is formed such that the third base region includes at least one contact area, in which the third base region is in electrical contact with an electrode of the semiconductor device different from the gate electrode.

[0073] According to a further embodiment, the semiconductor device is formed such that the first base region includes at least one contact area, in which the first base region is in electrical contact with an electrode of the semiconductor device different from the gate electrode.

[0074] According to a further embodiment, the semiconductor device is formed such that the doping concentration of each base region is greater in the contact area than in regions of the respective base region laterally adjacent to the contact area. For example, the contact areas may be formed by ion implantation. Such contact areas may also be formed in the second base region.

[0075] According to a further embodiment, the contact areas are simultaneously produced by means of ion implantation using one common mask, the mask for example comprising holes in the areas where the contact areas are to be formed.

[0076] Hereinafter, a semiconductor device and a method for producing a semiconductor device based on exemplary embodiments will be described in more detail with reference to the drawings. The accompanying drawings are included to provide a further understanding. In the drawings, elements of the same structure and / or function may be referred to by the same reference numerals. It should be understood that the embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale. To the extent that elements or components correspond to each other in terms of their functions in different figures, their description will not be repeated for each of the following figures. For clarity, elements may not be labeled with corresponding reference numerals in all figures. [Brief explanation of the drawings]

[0077] [Figure 1] 1A-1C illustrate different exemplary embodiments of a semiconductor device in different views. [Figure 2] 1A-1C illustrate different exemplary embodiments of a semiconductor device in different views. [Figure 3] 1A-1C illustrate different exemplary embodiments of a semiconductor device in different views. [Figure 4] 1A-1C illustrate different exemplary embodiments of a semiconductor device in different views. [Figure 5] 1A-1C illustrate different exemplary embodiments of a semiconductor device in different views. [Figure 6] 1A-1C illustrate different exemplary embodiments of a semiconductor device in different views. [Figure 7] 1A-1C illustrate different exemplary embodiments of a semiconductor device in different views. [Figure 8] 1A-1C illustrate different exemplary embodiments of a semiconductor device in different views. [Figure 9]1A-1C illustrate different exemplary embodiments of a semiconductor device in different views. [Figure 10] 1A-1D illustrate different positions during an exemplary embodiment of a method for producing a semiconductor device. [Figure 11] 1A-1D illustrate different positions during an exemplary embodiment of a method for producing a semiconductor device. [Figure 12] 1A-1D illustrate different positions during an exemplary embodiment of a method for producing a semiconductor device. [Figure 13] 1A-1C illustrate different exemplary embodiments of a semiconductor device in different views. DETAILED DESCRIPTION OF THE INVENTION

[0078] 1 shows a first exemplary embodiment of a semiconductor device 100 in a cross-sectional view. The semiconductor device 100 is, in this case, an RC-IGBT. It comprises a semiconductor body 10 having a top surface 11 and a bottom surface 19 located vertically opposite each other. The semiconductor body 10 is, for example, based on Si or SiC.

[0079] At the bottom surface 19, the semiconductor body 10 comprises alternating first-type regions 15 and second-type regions 16. The regions 15 and 16 are in electrical contact with a second main electrode 3, i.e., a collector electrode 3, on the bottom surface 19. The collector electrode 3 is made, for example, of a metal.

[0080] The first-type region 15 is of a first conductivity type, hereinafter n-type, and the second-type region 16 is of a second conductivity type, hereinafter p-type. A drift region 14 is disposed between the top surface 11 and the bottom surface 19. The drift region 14 is of the first conductivity type, i.e., n-type. The drift region 14 is adjacent to the first-type region 15 and the second-type region 16.

[0081] A plurality of trenches 51, 52 extend from the top surface into semiconductor body 10 and into drift region 14. Trenches 51 are a first type of trench, also referred to herein as active trenches, and trenches 52 are a second type of trench, also referred to herein as inactive or dummy trenches.

[0082] The first-type trenches 51 are filled with a conductive material that is electrically isolated from the semiconductor body 10 by an electrical insulating layer 40, referred to herein as the "gate insulating layer." Thus, there is no direct electrical contact between the semiconductor body 10 and the conductive material in the first-type trenches 51. The gate insulating layer 40 is formed, for example, from an oxide such as SiO2. The conductive material in the first-type trenches 51 may be heavily doped polysilicon. The conductive material in the first-type trenches 51 is part of the gate electrode 4 of the semiconductor device 100.

[0083] The second type of trenches 52 are also filled with a conductive material, for example heavily doped polysilicon, and are electrically isolated from the semiconductor body 10 by an electrically insulating layer, which is also the same as the gate insulating layer 40. The conductive material in the second type of trenches 52 is part of the first main electrode 2, i.e., the emitter electrode 2, which is disposed on the top surface 12.

[0084] Semiconductor body 10 comprises several base regions 13a, 13b, 13c that are arranged vertically between drift region 14 and top surface 11. Base regions 13a, 13b, 13c are all of the second conductivity type, i.e., p-type, and they all adjoin drift region 14 and top surface 11. First base region 13a and second base region 13b are shallower (extend less vertically) than trenches 51, 52. Third base region 13c is deeper than trenches 51, 52, i.e., extends further into semiconductor body 10.

[0085] The first base region 13a is adjacent to and in electrical contact with the emitter electrode 2 at a first contact area 6a, also referred to as the "Rb prime area." The third base region 13c is adjacent to and in electrical contact with the emitter electrode 2 at a third contact area 6c. The functions of these contact areas 6a, 6c are further explained below.

[0086] As can be seen in FIG. 1, the semiconductor device 100 is subdivided into a plurality of so-called half-cells. One such half-cell is shown in more detail in FIG. 2. A half-cell is the structure between the vertical dashed lines in FIG. 2. In FIG. 1, several such half-cells are arranged one after the other in a first lateral direction extending from left to right. Two adjacent half-cells are mirror images of each other in a plane extending through the third base region 13c perpendicular to the first lateral direction (see the right vertical dashed line in FIG. 2).

[0087] 2, the half-cell includes a portion (half) of the first base region 13c, a first-type trench 51, a second base region 13b, a second-type trench 52, and a portion (half) of the third base region 13c, which are arranged in this order along the first lateral direction. The half-cell further includes an implantation region 12 (source region 12) of a first conductivity type, i.e., n-type, arranged vertically between the first base region 13c and the top surface 11. The implantation region 12 is adjacent to the first base region 13c and the first-type trench 51. The implantation region 12 is further adjacent to and in electrical contact with the emitter electrode 2.

[0088] The operation of the semiconductor device may be as follows. In the so-called transistor mode, the emitter electrode 2 is set to ground and the collector electrode 3 is set to a positive potential. The gate electrode 4 is set to a positive potential so that the first base region 13a is depleted at the boundary with the first-type trench 51. A conduction path is created in the first base region 13c along the first-type trench 51. Electrons can then be injected from the emitter electrode 2 into the injection region 12 and travel along the conduction path into the drift region 14. At the bottom surface 19, holes are injected from the collector electrode 3 through the second-type region 16 and also travel into the drift region 14, resulting in the generation of an electron-hole plasma.

[0089] When the transistor mode is turned off, the electron-hole plasma can generate an avalanche in the region of the first type trench 51. Such an avalanche can adversely affect the gate insulating layer 40, and consequently the long-term performance stability of the semiconductor device 10. It has been found that the second type inactive trench 52 and the third base region, which extends deeper into the semiconductor body than the trenches 51, 52, help to divert the avalanche outward from the active trenches.

[0090] This effect is further enhanced by the fact that the third base region 13c is in electrical contact with the emitter electrode 2 at the third contact area 6c, through which charge carriers, e.g. holes, can be dissipated during turn-off.

[0091] Since the semiconductor device 100 is an RC-IGBT, it can also be operated in the reverse mode, the so-called diode mode. In the diode mode, the emitter electrode 2 is at, for example, ground and the collector electrode 3 is at a negative potential. Electrons are injected from the collector electrode 3 into the first-type region 15 and, after traveling further into the semiconductor body, must recombine with holes from the emitter electrode 2.

[0092] Without the third contact area 6c of the third base region, the only path would be through the first base region 13c via the first contact area 6a. A positive gate-emitter potential increases the diode on-state loss (Vf). This is because a positive gate-emitter potential establishes a channel between the n-type implantation region 12 and the n-type drift region 14, creating an electron path. Therefore, the electron path shorts out the diode path, reducing hole injection into the first base region 13a and, as a result, reducing the plasma density.

[0093] To keep diode on-state losses low, device 100 can be operated with a negative or shorted (V=0 V) gate electrode. In this case, there is no electron path. However, this limits the usefulness of the device, as gate control drives and systems must be adapted (rather than standard) or specifically designed for the application to achieve the lowest possible losses.

[0094] In the exemplary embodiment shown in FIG. 1 and FIG. 2, a charge carrier path for diode operation is formed through the third base region 13c via the contact area 6c of the third base region 13c. Holes can be injected through the third contact area 6c. This charge carrier path is independent of the gate electrode potential, particularly because the second-type trench 52 adjacent to the third base region 13c is at the emitter potential rather than the gate potential. Therefore, operation with a conventional gate drive scheme is possible while maintaining low reverse recovery charge and Erec.

[0095] 3 shows a further exemplary embodiment of the semiconductor device 100, which is substantially the same as that of FIG. 1, but which now includes a plurality of third contact areas 6c in the third base region 13c, each of which is in electrical contact with the emitter electrode 2.

[0096] 4 shows a top view of the semiconductor device 100 of FIG. 3 on the top surface 11. As can be seen, the contact areas 6c are laterally separated from one another and arranged in a rectangular pattern. In the regions between two contact areas 6c, there is no electrical contact with the emitter electrode 2. This means that in these regions, the emitter electrode 2 is not adjacent to the third base region 13c.

[0097] In fact, the size and density of the contact regions 6c can be adjusted for optimum performance in transistor and diode modes.

[0098] 5 and 6 show a third exemplary embodiment of the semiconductor device 100, also in a cross-sectional view (FIG. 5) and a top view to the upper surface 11 (FIG. 6). In this exemplary embodiment, there is an additional second contact area 6b in the second base region 13b, which is in electrical contact with the emitter electrode 2. Each second base region 13b comprises a plurality of such second contact areas 6b (see FIG. 6). The second contact areas 6b can have a similar function to the third contact area 6c, i.e., providing a charge carrier path for the diode mode and dissipating the charge carriers when the transistor mode is turned off.

[0099] With contact area 6b in second base region 13b and contact area 6c in third base region 13c, more degrees of freedom are available for optimizing transistor and diode mode operation.

[0100] 7, the third contact area 6c in the third base region 13c is not in electrical contact with the emitter electrode 2 as in the previous exemplary embodiments, but is in electrical contact with the further electrode 5. The further electrode 5 is controllable / biasable independently from the gate electrode 4 and the emitter electrode 2. This can further help to optimize the static transistor mode and / or the turn-off behavior and / or the diode mode, as another degree of freedom is available.

[0101] 8, a conductive layer 8 is disposed on the upper surface 11 above the third base region 13c. The conductive layer 8 is spaced apart from the semiconductor body 10 by an electrically insulating layer 80, which in this case is the same as the gate insulating layer 40.

[0102] The conductive layer 8 is electrically connected to the emitter electrode 2 and is close enough to the third base region 13c to be capacitively coupled to the third base region 13c. By using the conductive layer 8, holes in the third base region 13c can be influenced, for example, attracted or repelled, by the conductive layer 8. For example, during turn-off in the transistor mode, holes are attracted by the conductive layer 8. In the diode mode, holes can be repelled by the conductive layer 8.

[0103] The conductive layer 8 may be made of heavily doped polysilicon or metal. The distance between the conductive layer 8 and the third base region 13c, which is determined by the thickness of the electrically insulating layer 80, is, for example, up to 150 nm.

[0104] In the exemplary embodiment of FIG. 9 , to improve clarity of the illustration, the gate electrode 4 and its connections to different regions of the semiconductor device 100 are not shown. Instead, a portion of the emitter electrode 2 is shown extending across the third base region 13c. This portion of the emitter electrode 2 is spaced from the top surface 11 of the semiconductor body 10 by a further electrically insulating layer 20, also referred to herein as a “field insulating layer 20.” The field insulating layer 20 may be formed of an oxide. The vertical distance between the emitter electrode 2 and the top surface 11 is determined by the thickness of the field insulating layer 20, which is much greater than the thickness of the insulating layer 80 that separates the conductive layer 8 from the top surface 11.

[0105] 10 illustrates a first position in an exemplary embodiment of a method for producing a semiconductor device 100. At this position, a semiconductor body 10 is provided having a top surface 11 and a bottom surface 19. The bottom surface 19 is formed by alternating regions 15 of a first type and regions 16 of a second type. The top surface 11 is formed by a base region 13, which is of a second conductivity type. A drift region 14 is disposed between the bottom surface 19 and the base region 13, and the drift region 14 is of the first conductivity type.

[0106] 11 shows the position after trenches 51, 52 have been formed in semiconductor body 10. Trenches 51, 52 are filled with a conductive material. The conductive material in trenches 51, 52 is electrically isolated from semiconductor body 10 by electrically insulating material 40 (gate insulating layer 40) disposed in trenches 51, 52.

[0107] Moreover, the first base region 13a, the second base region 13b and the third base region 13c are formed, for example, by ion implantation. Also, an implanted region 12 is formed in the semiconductor body 10, for example, by ion implantation.

[0108] 12 shows the locations where ions are implanted into top surface 11 using mask 200. Mask 200 has holes above first base region 13a, above second base region 13b, and above third base region 13c. Using this implant, contact areas 6a, 6b, 6c are formed in base regions 13a, 13b, 13c, having a higher doping concentration than the surrounding base regions.

[0109] 13 shows the semiconductor device 100 after the electrodes 2, 3, 4 have been applied to the semiconductor body 10. The heavily doped contact areas 6a, 6b, 6c are again electrically connected to the emitter electrode 2.

[0110] The embodiments illustrated in Figures 1-13 above represent exemplary embodiments of improved semiconductor devices and improved methods for producing semiconductor devices. As such, they do not constitute an exhaustive list of all embodiments of improved semiconductor devices and improved methods. Actual semiconductor devices and methods may differ from the illustrated embodiments, for example, in terms of the arrangement, elements, and order of method steps. [Explanation of symbols]

[0111] Reference sign 2. First main electrode / emitter electrode 3 Second main electrode / collector electrode 4 gate electrode 5 Further electrodes 6a First Contact Area 6b Second Contact Area 6c Third Contact Area 8 Electrically Conductive Layer 10 Semiconductor body 11 Top side 12 Injection area 13 Base Area 13a first base region 13b Second base region 13c Third base region 14 Drift Region 15 First Type Area 16 Second Type Area 19 Bottom 20 Electrical insulation layer / field insulation layer 40 Electrical insulating layer / gate insulating layer 51 First type trench 52 Second type trench 80 Electrical insulating layer 100 Semiconductor Devices / RC-IGBT 200 masks

Claims

1. A semiconductor device (100), comprising: a semiconductor body (10) extending vertically between a top surface (11) and a bottom surface (19); a first main electrode (2) on said top surface (11) and a second main electrode (3) on said bottom surface (19); a gate electrode (4); at least two trenches, each extending from said top surface (11) into said semiconductor body (10), namely a first type trench (51) and a second type trench (52); Equipped with The semiconductor body (10) a drift region (14) of a first conductivity type disposed vertically between the top surface (11) and the bottom surface (19); at least three base regions, namely, a first base region (13a), a second base region (13b), and a third base region (13c), each of which is of a second conductivity type and each of which is disposed between the drift region (14) and the upper surface (11) in the vertical direction; the first conductivity type implantation region (12) being vertically spaced from the drift region (14) by the first base region (13a) and adjacent to the first base region (13a); Equipped with the first base region (13 a), the first type trench (51), the second base region (13 b), the second type trench (52), and the third base region (13 c) are arranged in this order in a first lateral direction; the first main electrode (2) is in electrical contact with the injection region (12); the gate electrode (4) extends into the first type trench (51) and is separated from the semiconductor body (10) in the first type trench by a gate insulating layer (40); the second type trench (52) does not have the gate electrode (4); the third base region (13c) includes at least one contact area (6c), in which the third base region (13c) is in electrical contact with an electrode (2, 5) of the semiconductor device (100) other than the gate electrode (4); A semiconductor device (100), wherein the third base region (13c) extends from the top surface (11) into the semiconductor body (10) to a depth greater than the second type of trench (52).

2. 2. The semiconductor device (100) of claim 1, wherein the third base region (13c) is electrically connected to the first main electrode (2) in the at least one contact area (6c).

3. 2. The semiconductor device (100) of claim 1, wherein the third base region (13c) is electrically connected to an electrode (5) in the at least one contact area (6c) configured to operate independently of the first main electrode (2).

4. The semiconductor device (100) of any one of the preceding claims, wherein the semiconductor device (100) is an RC-IGBT or a MISFET.

5. 10. The semiconductor device (100) of claim 1, wherein the second base region (13b) comprises at least one contact area (6b) by which the second base region (13b) is in electrical contact with an electrode (2, 5) of the semiconductor device (100) other than the gate electrode (4).

6. 10. The semiconductor device (100) of claim 1, wherein the first base region (13 a) comprises at least one contact area (6 a) by which the first base region (13 a) is in electrical contact with an electrode (2, 5) of the semiconductor device (100) different from the gate electrode (4).

7. the third base region (13c) includes a plurality of contact areas (6c), and the third base region (13c) is in electrical contact with the electrodes (2, 5) at each of the contact areas (6c); 10. The semiconductor device (100) according to any one of the preceding claims, wherein the contact areas (6c) of the third base region (13c) are spaced apart from one another in at least one lateral direction.

8. 10. The semiconductor device (100) of claim 1, wherein the doping concentration of the third base region (13c) is higher in the at least one contact area (6c) than in regions laterally adjacent to the contact area (6c).

9. a conductive layer (8) disposed on the upper surface (11) above the third base region (13c) and electrically connected to an electrode (2, 5) of the semiconductor device (100) different from the gate electrode (4); 10. The semiconductor device (100) of claim 1, wherein the conductive layer (8) is arranged close to the third base region (13 c) such that by electrically energizing the conductive layer (8), a strong capacitive coupling between the third base region (13 c) and the conductive layer (8) can be achieved, such that free charge carriers in the third base region (13 c) are influenced thereby.

10. The conductive layer (8) is separated from the upper surface (11) by an electrically insulating layer (80) disposed between the upper surface (11) and the conductive layer (8) in the vertical direction; 10. The semiconductor device (100) of claim 9, wherein the thickness of the electrical insulating layer (80) is at most 5 times greater than the thickness of the gate insulating layer (40), and / or the vertical distance between the conductive layer (8) and the third base region (13c) is at most 500 nm.

11. 11. The semiconductor device (100) according to claim 9 or 10, wherein, in a top view on the top surface (11), the conductive layer (8) covers a large portion of the third base region (13c).

12. The conductive layer (8) is disposed vertically between the top surface (11) of the semiconductor body (10) and a portion of the emitter electrode (2); The semiconductor device (100) according to any one of claims 9 to 11, wherein a vertical distance between the conductive layer (8) and the third base region (13c) is at most half of a vertical distance between the portion of the emitter electrode (2) and the top surface (11) of the semiconductor body (10).

13. A method for producing a semiconductor device (100), comprising: Providing a semiconductor body (10) having a top surface (11) and a bottom surface (19); forming at least two trenches, namely a first type trench (51) and a second type trench (52), each extending from said top surface (11) into said semiconductor body (10); forming a first main electrode (2) on said top surface (11) and a second main electrode (3) on said bottom surface (19); forming a gate electrode (4) such that said gate electrode (4) extends into said first type trench (51), where it is separated from said semiconductor body by a gate insulating layer (40); Including, The second type of trench (52) remains free of the gate electrode (4), The semiconductor device (100) comprises the semiconductor body (10): a drift region (14) of a first conductivity type located vertically between the top surface (11) and the bottom surface (19); at least three base regions, namely, a first base region (13a), a second base region (13b), and a third base region (13c), each of which is of a second conductivity type and each of which is disposed between the drift region (14) and the upper surface (11) in the vertical direction; an implanted region (12) of the first conductivity type vertically spaced from the drift region (14) by the first base region (13 a) and adjacent to the first base region (13 a); the first base region (13 a), the first type trench (51), the second base region (13 b), the second type trench (52), and the third base region (13 c) are arranged in this order in a first lateral direction; the first main electrode (2) is in electrical contact with the injection region (12); the third base region (13c) includes at least one contact area (6c), in which the third base region (13c) is in electrical contact with an electrode (2, 5) of the semiconductor device (100) other than the gate electrode (4); The method, wherein the third base region (13c) extends from the top surface (11) into the semiconductor body (10) deeper than the second type trench (52).

14. The semiconductor device (100) is formed such that the first base region (13 a) includes at least one contact area (6 a) through which the first base region (13 a) is in electrical contact with an electrode (2, 5) of the semiconductor device (100) different from the gate electrode (4), in the contact areas (6a, 6c), the doping concentration of each of the base regions (13a, 13c) is higher than in the regions of the respective base regions (13a, 13c) laterally adjacent to the contact areas (6a, 6c); 14. The method of claim 13, wherein the contact areas (6a, 6c) are simultaneously created by using ion implantation using one common mask (200).

Images