Improvements to intra-template matching prediction mode for motion estimation

Abstract

The method and system improve prediction accuracy by implementing a blending of the intra-TMP mode with other intra-prediction modes that utilize neighboring samples. The VVC standard encoder and decoder configure one or more processors of a computing system to further improve prediction accuracy by blending the intra-TMP mode with different prediction modes, such as spatial geometric partition mode (SGPM) and combined inter- and intra-prediction (CIIP), refining the intra-TMP prediction block based on neighboring samples, such as using a position-dependent intra-prediction combining (PDPC) method, applying local illumination compensation (LIC) to refine the intra-TMP prediction block, and / or implementing multiple different sub-pixel positions, sub-pixel positions combined with multiple candidate intra-TMPs, or inversion mode in the intra-TMP.

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims the benefit of U.S. patent application Ser. No. 63 / 436,826, filed January 3, 2023, entitled "Improvements to Intra Template Matching Prediction Mode for Motion Estimation," U.S. patent application Ser. No. 63 / 449,544, filed March 2, 2023, entitled "Improvements to Intra Template Matching Prediction Mode for Motion Estimation," and U.S. patent application Ser. No. 18 / 399,650, filed December 28, 2023, entitled "Improvements to Intra Template Matching Prediction Mode for Motion Estimation," both of which are expressly incorporated herein by reference in their entireties.

[0002] FIELD OF THE DISCLOSURE This disclosure relates generally to motion prediction, and more particularly to methods and systems for implementing intra-template matching prediction modes. [Background technology]

[0003] In 2020, the Joint Video Experts Team (JVET) of the ITU-T Video Coding Experts Group (ITU-T VCEG) and the ISO / IEC Moving Picture Experts Group (ISO / IEC MPEG) published the final draft of the next-generation video codec specification, Versatile Video Coding (VVC). This specification further improves video coding performance over previous standards, such as H.264 / AVC (Advanced Video Coding) and H.265 / HEVC (High Efficiency Video Coding). JVET continues to propose additional technologies beyond the scope of the VVC standard itself, collected under the name of the Extended Compression Model (ECM).

[0004] According to the VVC standard, encoders and decoders partition image data into blocks and perform motion estimation on the luma and chroma components of the blocks by selecting one of various intra- and inter-prediction modes. Among the intra-prediction modes provided by the VVC standard, intra-template matching prediction (intra-TMP) is an intra-prediction mode that copies the best predicted block from the reconstructed portion of the current frame, where an L-shaped template matches the current template. Intra-TMP predicts by taking into account non-local spatial correlations in the current frame, but does not consider local spatial correlations between neighboring samples of the current block.

[0005] As of the time of writing, the latest draft of the ECM (announced as "Algorithm Description of Enhanced Compression Model 11 (ECM 11)" at the 32nd JVET Conference in October 2023) includes proposals for further implementation of intra prediction modes, including angular intra prediction modes other than those provided by the VVC standard. According to the ECM, intra TMP is effective not only for screen content but also for camera-captured content. However, for camera-captured content, which has richer texture than screen content, intra TMP may not achieve optimal results.

[0006] There is a need to further improve the capabilities of the Intra-TMP beyond those provided by the VVC standard and ECM. Summary of the Invention

[0007] In a first aspect, an embodiment of the present disclosure provides a computing method, including: matching a template of a current block with a template in a search area; determining integer pixel positions of a block vector of a matching block corresponding to the matched template; determining sub-pixel positions around the integer pixel positions; and deriving reconstructed values ​​of the matching block at the determined sub-pixel positions around the integer pixel positions as predicted sample values ​​of the current block.

[0008] In a second aspect, an embodiment of the present disclosure provides a computing system including: a matching module configured to match a template of a current block with a template in a search area; a determination module configured to determine integer pixel positions of a block vector of a matching block corresponding to the matched template and to determine sub-pixel positions around the integer pixel positions; and a derivation module configured to derive reconstructed values ​​of the matching block at the determined sub-pixel positions around the integer pixel positions as predicted sample values ​​of the current block. In a third aspect, an embodiment of the present disclosure provides a computing system including one or more processors; and a computer-readable storage medium communicatively coupled to the one or more processors, the computer-readable storage medium storing computer-readable instructions executable by the one or more processors that, when executed by the one or more processors, perform the computing method set forth in the first aspect. In a fourth aspect, an embodiment of the present disclosure provides a non-transitory computer-readable storage medium storing a bitstream associated with one or more images, the bitstream, when computed by a processor, causing the processor to perform the computing method of the first aspect. In a fifth aspect, an embodiment of the present disclosure provides a computer program product comprising computer program instructions, the computer program instructions enabling a computer to perform the computing method according to the first aspect. In a sixth aspect, an embodiment of the present disclosure provides a computer program product enabling a computer to perform the computing method according to the first aspect. The detailed description is set forth with reference to the accompanying drawings, in which the left-most digit of a reference number identifies the figure in which the reference number first appears. Use of the same reference number in different figures indicates similar or identical items or features. [Brief explanation of the drawings]

[0009] [Figure 1A] 1A-1C are exemplary block diagrams of an encoding process and a decoding process, respectively, according to exemplary embodiments of the present disclosure.

[0010] [Figure 1B] 1A-1C are exemplary block diagrams of an encoding process and a decoding process, respectively, according to exemplary embodiments of the present disclosure.

[0011] [Figure 2] 10 shows the reference area for IBC mode showing the available reference samples according to the CTU processing order, with each block representing a 64x64 luma sample unit.

[0012] [Figure 3A] These show the BV adjustments for horizontal and vertical flips, respectively.

[0013] [Figure 3B] These show the BV adjustments for horizontal and vertical flips, respectively.

[0014] [Figure 4A] The search area for intra-TMP is shown. [Figure 4B] 1 shows the template used in the proposed alternative intra-TMP mode.

[0015] [Figure 5] 67 angular intra-prediction modes provided by VVC are shown.

[0016] [Figure 6A] 10 shows a partitioning method for angular intra prediction modes.

[0017] [Figure 6B] 10 shows a partitioning method for angular intra prediction modes.

[0018] [Figure 7A] 10 illustrates neighboring samples used for refinement according to an exemplary embodiment of the present disclosure.

[0019] [Figure 7B] 10 illustrates interpolation of matching templates according to an exemplary embodiment of the present disclosure.

[0020] [Figure 7C] 10 illustrates interpolation of matching templates according to an exemplary embodiment of the present disclosure.

[0021] [Figure 7D] 10 illustrates interpolation of matching templates according to an exemplary embodiment of the present disclosure.

[0022] [Figure 8]1 illustrates half-pixel positions above, below, left, and right around an integer pixel position according to an exemplary embodiment of the present disclosure.

[0023] [Figure 9] 1 illustrates eight half-pixel positions surrounding an integer pixel position according to an exemplary embodiment of the present disclosure.

[0024] [Figure 10] 1 illustrates eight quarter-pixel positions and eight half-pixel positions surrounding an integer pixel position according to an exemplary embodiment of the present disclosure.

[0025] [Figure 11] 1 shows eight quarter-pixel positions, eight half-pixel positions, and eight three-quarter-pixel positions surrounding an integer pixel position according to an exemplary embodiment of the present disclosure.

[0026] [Figure 12] 8 quarter-pixel positions, 16 half-pixel positions, and 24 three-quarter-pixel positions surrounding an integer pixel position are shown in accordance with an exemplary embodiment of the present disclosure.

[0027] [Figure 13] 1 illustrates four samples used for interpolation according to an exemplary embodiment of the present disclosure.

[0028] [Figure 14] 1 illustrates an exemplary system for implementing the processes and methods described herein for implementing an intra-template matching prediction mode. DETAILED DESCRIPTION OF THE INVENTION

[0029] The systems and methods discussed herein are directed to improving prediction accuracy by implementing an intra template matching prediction mode for motion estimation, and more specifically, by implementing a blend of the intra TMP mode with other intra prediction modes that utilize neighboring samples.

[0030] In accordance with the VVC video coding standard (VVC standard) and the motion prediction described therein, a computing system includes at least one or more processors and a computer-readable storage medium communicatively coupled to the one or more processors. The computer-readable storage medium is a non-instantaneous or non-transitory computer-readable storage medium that stores computer-readable instructions, as defined below with reference to FIG. 14. At least some computer-readable instructions stored on the computer-readable storage medium are executable by the one or more processors of the computing system to configure the one or more processors to perform associated operations of the computer-readable instructions, including at least the operations of an encoder described in the VVC standard and the operations of a decoder described in the VVC standard. Some of these encoder and decoder operations according to the VVC standard are described in more detail below, but these following descriptions should not be understood as exhaustive of the encoder and decoder operations according to the VVC standard. A "VVC standard encoder" and a "VVC standard decoder" will now be used to describe corresponding computer-readable instructions stored on a computer-readable storage medium and configuring one or more processors to perform these corresponding operations (which may, by way of example, be referred to as "reference implementations" of the encoder or decoder).

[0031] It should be noted that, according to exemplary embodiments of the present disclosure, the VVC standard encoder and VVC standard decoder further include computer-readable instructions stored on a computer-readable storage medium and executable by one or more processors of a computing system to configure the one or more processors to perform operations not specified in the VVC standard. The VVC standard encoder is not limited to the operation of the reference implementation of the encoder, but should be understood to include further computer-readable instructions that configure one or more processors of a computing system to perform further operations described herein. The VVC standard decoder is not limited to the operation of the reference implementation of the decoder, but should be understood to include further computer-readable instructions that configure one or more processors of a computing system to perform further operations described herein.

[0032] 1A and 1B are exemplary block diagrams of an encoding process 100 and a decoding process 150, respectively, according to an exemplary embodiment of the present disclosure.

[0033] In encoding process 100, a VVC standard encoder configures one or more processors of a computing system to receive as input one or more input images from an image source 102. The input images include a number of pixels sampled by an image capture device, such as a photosensor array, and include an uncompressed stream of multiple color channels (e.g., RGB color channels) that store color data at the image's original resolution, with each channel using a number of bits to store the color data for each pixel of the image. The VVC standard encoder configures one or more processors of the computing system to store this uncompressed color data in a compressed form, where the color data is stored at a resolution lower than the image's original resolution and is encoded as a luma ("Y") channel and two chroma ("U" and "V") channels that are lower resolution than the luma channel.

[0034] A VVC standard encoder encodes an image (the image being encoded is referred to as the “current image” to distinguish it from other images received from the image source 102) by configuring one or more processors of a computing system to partition the original image into units and subunits according to a partition structure. The VVC standard encoder configures one or more processors of the computing system to subdivide the image into macroblocks (MBs), each having dimensions of 16×16 pixels, where the macroblocks (MBs) may be further subdivided into partitions. The VVC standard encoder configures one or more processors of the computing system to subdivide the image into coding tree units (CTUs), where the luma and chroma components of the CTUs may be further subdivided into coding tree blocks (CTBs), where the CTBs are further subdivided into coding units (CUs). Alternatively, the VVC standard encoder configures one or more processors of the computing system to subdivide the image into units of N×N pixels, where the units may then be further subdivided into subunits. For purposes of this disclosure, each of these largest subdivided units of an image may generally be referred to as a “block.”

[0035] A CU is coded using one block of luma samples and two corresponding blocks of chroma samples, and is coded using one coding tree, rather than the image being monochrome.

[0036] A VVC standard encoder configures one or more processors of a computing system to subdivide blocks into partitions having dimensions that are multiples of 4x4 pixels. For example, the dimensions of a partition of a block may be 8x4 pixels, 4x8 pixels, 8x8 pixels, 16x8 pixels, or 8x16 pixels.

[0037] By encoding color information for blocks of an image and its subdivisions rather than for pixels of the original full-resolution image, a VVC standard encoder configures one or more processors of a computing system to encode color information for an image at a lower resolution than the input image, thereby storing the color information in fewer bits than the input image.

[0038] Furthermore, a VVC standard encoder encodes an image by configuring one or more processors of a computing system to perform motion prediction on blocks of a current image. Motion prediction coding refers to storing image data of blocks of a current image (blocks of an original image before coding are called "input blocks"), rather than pixel data, using motion information and a prediction unit (PU) according to intra prediction 104 or inter prediction 106.

[0039] Motion information refers to data describing the motion of a block structure of an image or its units or sub-units, such as a motion vector or a reference to a block in a current image or a reference image. A PU may refer to a unit or sub-units corresponding to one of multiple block structures of an image, such as an MB or a CTU, in which blocks are partitioned based on image data and coded according to the VVC standard. The motion information corresponding to a PU may describe motion prediction encoded by a VVC standard encoder, as described herein.

[0040] A VVC standard encoder configures one or more processors of a computing system to code motion prediction information across each block of an image in a block-to-block coding order, e.g., a raster scan order in which the first block to be decoded is the topmost and leftmost block of the image. The block being coded is called the "current block" to distinguish it from any other block of the same image.

[0041] According to intra prediction 104, one or more processors of the computing system are configured to encode a block with reference to motion information and PUs of one or more other blocks of the same image. According to intra predictive coding, one or more processors of the computing system perform intra prediction 104 (also called spatial prediction) computation by coding the motion information of a current block based on spatially neighboring samples from blocks that are spatially neighboring the current block.

[0042] According to inter prediction 106, one or more processors of the computing system are configured to encode a block with reference to motion information and PUs of one or more other images. For the purpose of inter predictive coding, one or more processors of the computing system are configured to store one or more previously encoded and decoded images in a reference image buffer. These stored images are called reference images.

[0043] The one or more processors are configured to perform inter-prediction 106 (also called temporal prediction or motion-compensated prediction) computation by coding motion information of the current block based on samples from one or more reference images. Inter-prediction can be further computed according to uni-prediction or bi-prediction. In uni-prediction, only one motion vector pointing to one reference image is used to generate a prediction signal for the current block. In bi-prediction, two motion vectors, each pointing to a corresponding reference image, are used to generate a prediction signal for the current block.

[0044] The VVC standard encoder configures one or more processors of the computing system to code the CU to include a reference index for identifying a prediction signal of a current block for reference by a VVC standard decoder. The one or more processors of the computing system can code the CU to include an inter-prediction indicator. The inter-prediction indicator indicates List 0 prediction with reference to a first reference image list called List 0, List 1 prediction with reference to a second reference image list called List 1, or bi-prediction with reference to both reference image lists called List 0 and List 1, respectively.

[0045] If the inter prediction indicator indicates List 0 prediction or List 1 prediction, the one or more processors of the computing system are configured to code a CU that includes a reference index that points to a reference picture in a reference picture buffer referenced by List 0 or List 1, respectively. If the inter prediction indicator indicates bi-prediction, the one or more processors of the computing system are configured to code a CU that includes a first reference index that points to a first reference picture in a reference picture buffer referenced by List 0 and a second reference index that points to a second reference picture in the reference pictures referenced by List 1.

[0046] A VVC standard encoder configures one or more processors of a computing system to code each current block of an image separately and output a corresponding prediction block. According to the VVC standard, a CTU can be as large as 128x128 luma samples (and corresponding chroma samples depending on the chroma format). The CTU can be further partitioned into CUs according to a quadtree, binary tree, or ternary tree. The one or more processors of the computing system are configured to finally record coding parameter sets, such as a coding mode (intra mode or inter mode), motion information for inter-coded blocks (such as reference indexes and motion vectors), and quantized residual coefficients, in a syntax structure of a leaf node of the partition structure.

[0047] After the predicted block is output, the VVC standard encoder configures one or more processors of the computing system to transmit a set of coding parameters, such as the coding mode (i.e., intra-prediction or inter-prediction), the mode of intra-prediction or the mode of inter-prediction, and motion information, to an entropy coder 124 (described later).

[0048] The VVC standard provides semantics for recording a coding parameter set for a CU. For example, for the above coding parameter set, pred_mode_flag for the CU is set to 0 for inter-coded blocks and to 1 for intra-coded blocks, general_merge_flag for the CU is set to indicate whether merge mode is used in inter prediction of the CU, inter_affine_flag and cu_affine_type_flag for the CU are set to indicate whether affine motion compensation is used in inter prediction of the CU, mvp_l0_flag and mvp_l1_flag are set to indicate a motion vector index in list 0 or list 1, respectively, and ref_idx_l0 and ref_idx_l1 are set to indicate a reference image index in list 0 or list 1, respectively. It should be understood that the VVC standard includes semantics for recording various other information, flags, and options that are beyond the scope of this disclosure.

[0049] The VVC standard encoder further implements one or more mode decision and encoder control settings 108, including rate control settings. One or more processors of the computing system are configured to perform the mode decision by selecting an optimized prediction mode for the current block based on a rate-distortion optimization method after intra-prediction or inter-prediction.

[0050] The rate control settings configure one or more processors of a computing system to assign different quantization parameters (QPs) to different images. The magnitude of the QP determines the scale at which image information is quantized during encoding by one or more processors (described below), and thereby determines the extent to which encoding process 100 discards image information from MBs of a sequence during coding (because information falls between steps of that scale).

[0051] The VVC standard encoder further implements a subtractor 110. One or more processors of the computing system are configured to perform the subtraction operation by computing the difference between an input block and a predicted block. Based on the optimized prediction mode, the predicted block is subtracted from the input block. The difference between the input block and the predicted block is called a prediction residual, or for brevity, a "residual."

[0052] Based on the prediction residual, the VVC standard encoder further implements a transform 112. One or more processors of the computing system are configured to perform a transform operation on the residual by matrix arithmetic operations to compute an array of coefficients (which may be referred to as "residual coefficients," "transform coefficients," etc.), thereby encoding the current block as a transform block (TB). The transform coefficients may refer to coefficients that represent one of several spatial transformations, such as a diagonal flip, a vertical flip, or a rotation, that may be applied to a sub-block.

[0053] It should be understood that the coefficients may be stored as two components, a magnitude and a sign, as will be explained in more detail below.

[0054] Sub-blocks of a CU, such as PUs and TBs, can be arranged in any combination of sub-block dimensions as described above. A VVC standard encoder configures one or more processors of a computing system to subdivide a CU into a residual quadtree (RQT), which is a hierarchical structure of TBs. The RQT provides an order for motion prediction and residual coding across sub-blocks at each level of the RQT and recursively at each level below.

[0055] The VVC standard encoder further implements quantization 114. One or more processors of the computing system are configured to perform a quantization operation on the residual coefficients by matrix arithmetic operations based on the quantization matrix and the QP assigned above. Residual coefficients that fall within the interval are retained, and residual coefficients that are outside the interval step are discarded.

[0056] The VVC standard encoder further implements inverse quantization 116 and inverse transform 118. One or more processors of the computing system are configured to perform inverse quantization and inverse transform operations on the quantized residual coefficients by matrix arithmetic operations that are the inverse of the quantization and transform operations, as described above. The inverse quantization and inverse transform operations result in a reconstructed residual.

[0057] The VVC standard encoder further implements an adder 120. One or more processors of the computing system are configured to perform an addition operation by adding the predicted block and the reconstructed residual to output a reconstructed block.

[0058] The VVC standard encoder further implements a loop filter 122. One or more processors of the computing system are configured to apply a loop filter, such as a deblocking filter, a sample adaptive offset (SAO) filter, and an adaptive loop filter (ALF), to the reconstructed block, thereby outputting a filtered reconstructed block.

[0059] The VVC standard encoder further configures one or more processors of the computing system to output the filtered reconstructed blocks to a decoded picture buffer (DPB) 200. The DPB 200 stores reconstructed images that are used as reference images by one or more processors of the computing system when coding images other than the current image, as described above with respect to inter prediction.

[0060] The VVC standard encoder further implements an entropy coder 124. One or more processors of the computing system are configured to perform entropy coding, in which symbols constituting quantized residual coefficients are coded by mapping to binary strings (hereinafter "bins") according to a context-sensitive binary arithmetic codec (CABAC) that can be transmitted in an output bitstream at a compressed bit rate. The coded quantized residual coefficient symbols include absolute values ​​of the residual coefficients (hereinafter these absolute values ​​are referred to as "residual coefficient levels").

[0061] Thus, the entropy coder configures one or more processors of the computing system to code the residual coefficient levels of the block, bypass coding of the signs of the residual coefficients, record the signs of the residual coefficients in the coded block, record coding parameter sets such as the coding mode, the mode of intra prediction or the mode of inter prediction, and motion information coded in the syntax structure of the coded block (such as a picture parameter set (PPS) found in the picture header and a sequence parameter set (SPS) found in a sequence of multiple pictures), and output the coded block.

[0062] The VVC standard encoder configures one or more processors of the computing system to output a coded image comprised of coded blocks from the entropy coder 124. The coded image is output to a transmission buffer and eventually packed into a bitstream for output from the VVC standard encoder. The bitstream is written by one or more processors of the computing system to a non-instantaneous or non-transitory computer-readable storage medium of the computing system for transmission.

[0063] In the decoding process 150, the VVC standard decoder configures one or more processors of a computing system to receive as input one or more coded images from a bitstream.

[0064] The VVC standard decoder implements an entropy decoder 152. One or more processors of the computing system are configured to perform entropy decoding, in which bins are decoded by reversing the symbol-to-bin mapping according to CABAC, thereby recovering the entropy-coded quantized residual coefficients. The entropy decoder 152 outputs the quantized residual coefficients, the signs of the residual coefficients that bypassed coding, and syntax structures such as PPS and SPS.

[0065] The VVC standard decoder further implements inverse quantization 154 and inverse transform 156. One or more processors of the computing system are configured to perform inverse quantization and inverse transform operations on the decoded quantized residual coefficients by matrix arithmetic operations that are the inverse of the quantization and transform operations, as described above. The inverse quantization and inverse transform operations result in a reconstructed residual.

[0066] Furthermore, based on the coding parameter set recorded by the entropy coder 124 in syntax structures such as PPS and SPS (or alternatively received by out-of-band transmission or coded to the decoder) and the coding mode included in the coding parameter set, the VVC standard decoder determines whether to apply intra prediction 156 (i.e., spatial prediction) or motion compensated prediction 158 (i.e., temporal prediction) to the reconstructed residual.

[0067] If the coding parameter set specifies intra prediction, the VVC standard decoder configures one or more processors of the computing system to perform intra prediction 158 using the prediction information specified in the coding parameter set, which then generates a predicted signal.

[0068] If the coding parameter set specifies inter prediction, the VVC standard decoder configures one or more processors of the computing system to perform motion compensated prediction 160 using reference images from the DPB 200. This causes motion compensated prediction 160 to generate a prediction signal.

[0069] The VVC standard decoder further implements an adder 162. The adder 162 configures one or more processors of the computing system to perform an addition operation on the reconstructed residual and the prediction signal, thereby outputting a reconstructed block.

[0070] The VVC standard decoder further implements a loop filter 164. One or more processors of the computing system are configured to apply a loop filter, such as a deblocking filter, an SAO filter, and an ALF, to the reconstructed block to output a filtered reconstructed block.

[0071] The VVC standard decoder further configures one or more processors of the computing system to output the filtered reconstructed blocks to DPB 200. As described above, DPB 200 stores reconstructed images that are used as reference images by one or more processors of the computing system when coding images other than the current image, as described above with respect to motion compensated prediction.

[0072] The VVC standard decoder further configures one or more processors of the computing system to output the reconstructed image from the DPB to a user-viewable display of the computing system, such as a television display, a personal computing monitor, a smartphone display, or a tablet display.

[0073] Thus, as shown in the encoding process 100 and decoding process 150 described above, the VVC standard encoder and VVC standard decoder, respectively, implement motion predictive coding according to the VVC specification. The VVC standard encoder and VVC standard decoder, respectively, configure one or more processors of a computing system to generate a reconstructed image based on a previous reconstructed image of the DPB according to motion compensated prediction described in the VVC standard, with the previous reconstructed image serving as a reference image in the motion compensated prediction as described herein.

[0074] According to the VVC standard, the coding tree is configured to provide separate block tree structures for the luma and chroma components of the image. A CTU can contain three CTBs, including one luma CTB ("Y") and two chroma CTBs ("Cb" and "Cr").

[0075] In P slices and B slices, the luma CTB and chroma CTB of one CTU are configured to share a common coding tree structure. However, in I slices, the luma CTB and chroma CTB may be configured to have separate block tree structures. Given the coding trees configured for separate block trees, the luma CTB is partitioned into CUs by a first coding tree structure, and the chroma CTB is partitioned into chroma CUs by a second coding tree structure.

[0076] In other words, a CU in an I slice may contain coding blocks for the luma component or coding blocks for two chroma components, while a CU in a P or B slice contains coding blocks for all three color components (unless the video is monochrome).

[0077] According to the VVC standard, the luma component can be predicted in several intra prediction modes, including planar intra prediction mode, DC intra prediction mode, angular intra prediction mode, multiple reference line (MRL) prediction mode, intra sub-partition (ISP) mode, and matrix-based intra prediction (MIP) mode, which are described in more detail below.

[0078] Angular intra prediction is a directional intra prediction method that has been extended from previous implementations in the HEVC standard. To capture arbitrary edge directions that appear in natural video, the VVC standard extends the number of angular intra prediction modes from 33 (used in HEVC) to 65.

[0079] Furthermore, according to the VVC standard, an intra block copy (IBC) mode is implemented as a block-level coding mode. Here, a VVC standard encoder configures one or more processors of a computing system to perform block matching (BM) to find the best block vector (or motion vector) for each CU. The block vector indicates the displacement from the current block to a reference block already reconstructed in the current image. The luma block vectors of an IBC-coded CU are integer precision. The chroma block vectors are also rounded to integer precision.

[0080] When combined with adaptive motion vector resolution (AMVR), IBC mode can switch between 1-pixel and 4-pixel motion vector precision. IBC-coded CUs are treated as a third prediction mode other than intra or inter prediction modes. IBC mode can be applied to CUs whose width and height are both less than or equal to 64 luma samples.

[0081] On the encoder side, hash-based motion estimation is performed for IBC. The encoder performs an RD check for blocks whose width or height is less than or equal to 16 luma samples. In non-merge mode, a block vector search is first performed using a hash-based search. If the hash search does not return any valid candidates, a block-matching-based local search is performed.

[0082] In hash-based search, hash key matching (32-bit CRC) between the current block and the reference block is extended to all allowed block sizes. The hash key calculation for each location in the current image is based on 4x4 sub-blocks. For larger-sized current blocks, if the hash keys of all 4x4 sub-blocks match the hash key at the corresponding reference location, the hash key is deemed to match the hash key of the reference block. If the hash keys of multiple reference blocks are found to match the hash key of the current block, the block vector cost of each of the matching reference blocks is calculated, and the reference block with the smallest cost is selected.

[0083] In a block matching search, the search range is set to cover both the previous and current CTUs.

[0084] IBC mode is signaled in the bitstream with a CU-level flag and can be signaled as IBC adaptive motion vector prediction (AMVP) mode or IBC skip / merge mode as follows:

[0085] IBC skip / merge mode: A merge candidate index is signaled to indicate which block vector in the list from neighboring candidate IBC coded blocks is used to predict the current block. The merge list consists of spatial, HMVP, and pairwise candidates.

[0086] IBC AMVP mode: Block vector differences are coded in the same way as motion vector differences. The block vector prediction method uses two candidates as predictors, one from the left neighboring block and one from the above neighboring block (if IBC coded). If neither neighboring block is available, a default block vector is used as the predictor. A flag is signaled indicating the index of the block vector predictor.

[0087] To reduce memory consumption and decoder complexity, IBC in VVC only allows reconstruction of parts of a predefined region, including the region of the current CTU and some regions of the left CTU. Figure 2 shows the reference region of the IBC mode, showing the available reference samples according to the CTU processing order, where each block represents a 64x64 luma sample unit.

[0088] Depending on the position of the current coding CU in the current CTU, the following applies:

[0089] If the current block is in the top-left 64x64 block of the current CTU, then using CPR mode, in addition to the already reconstructed samples in the current CTU, it may also point to reference samples in the bottom-right 64x64 block of the left CTU. Using CPR mode, the current block may also point to reference samples in the bottom-left 64x64 block of the left CTU and reference samples in the top-right 64x64 block of the left CTU.

[0090] If the current block is in the top-right 64x64 block of the current CTU, in addition to the already reconstructed samples in the current CTU using CPR mode, the current block may also point to reference samples in the bottom-left 64x64 block and bottom-right 64x64 block of the left CTU if the luma position (0,64) for the current CTU has not yet been reconstructed. Otherwise, the current block may also point to reference samples in the bottom-right 64x64 block of the left CTU.

[0091] If the current block is in the bottom-left 64x64 block of the current CTU, using CPR mode, in addition to the already reconstructed samples in the current CTU, if the luma position (64,0) for the current CTU has not yet been reconstructed, the current block may also point to reference samples in the top-right 64x64 block and bottom-right 64x64 block of the left CTU. Otherwise, using CPR mode, the current block may also point to reference samples in the bottom-right 64x64 block of the left CTU.

[0092] If the current block is in the bottom right 64x64 block of the current CTU, the CPR mode can be used to point only to already reconstructed samples in the current CTU.

[0093] The above restrictions allow the IBC mode to be implemented using local on-chip memory for hardware implementations.

[0094] Furthermore, ECM allows the application of the Reconstruction-Reordering IBC (RR-IBC) mode to IBC-coded blocks. When RR-IBC is applied, the samples in the reconstructed block are inverted according to the inversion type of the current block. On the encoder side, the original block is inverted before motion search and residual calculation, while the predicted block is derived without inversion. On the decoder side, the reconstructed block is inverted back, thereby restoring the original block.

[0095] Two inversion methods are supported for RR-IBC coded blocks: horizontal and vertical flipping. First, for IBC AMVP coded blocks, a syntax flag is signaled to indicate whether the reconstruction is inverted. If it is inverted, another flag specifying the inversion type is further signaled. For IBC merges, the inversion type is inherited from neighboring blocks without syntax signaling. Considering horizontal or vertical symmetry, the current block and the reference block are usually aligned horizontally or vertically. Therefore, if horizontal flipping is applied, the vertical component of BV is not signaled and is inferred to be equal to 0. Similarly, if vertical flipping is applied, the horizontal component of BV is not signaled and is inferred to be equal to 0.

[0096] To better utilize the symmetry, we apply an inversion-aware BV adjustment approach to refine the block vector candidates. For example, as shown in Figures 3A and 3B, n ,y n ) and (x c ,y c ) represent the coordinates of the center samples of the neighboring blocks and the current block, respectively, and BV n and BV c represent the BVs of the neighboring block and the current block, respectively. If the neighboring block is coded with horizontal flip, then BV c The horizontal components of the BV are not directly inherited from the neighboring blocks, but are n The horizontal component of (BV n h ) plus the motion shift, i.e., BV c h =2(x n -x c )+BV n h Similarly, if the neighboring blocks are coded with vertical flip, BV c The vertical component of BV n The vertical component (BV n v ) plus the motion shift, i.e., BV cv =2(y n -y c )+BV n v .

[0097] Furthermore, the VVC standard and ECM also provide an intra-template matching prediction (intra-TMP) mode. Here, a VVC standard encoder configures one or more processors of a computing system to derive a best prediction block from the reconstructed portion of the current frame where an L-shaped template matches the current template. For a predefined search range, the encoder searches the reconstructed portion of the current frame for a template that is most similar to the current template, determines a matching block based on the matched template, and uses the matching block as the prediction block. The encoder then signals the use of this mode, and the same prediction operation is performed at the decoder side.

[0098] A prediction signal is generated by matching a template of the current block, i.e., an L-shaped causal neighboring block of the current block, with another template in a predefined search area. In some disclosed embodiments, the predefined search area consists of the following, as shown in FIG. 4A: R1: Current CTU R2: CTU in the upper left R3: CTU above R4: CTU on the left

[0099] The template of the current block is matched with the templates in the searched region by comparing a cost function. The sum of absolute differences (SAD) is used as the cost function. Within each search region, the decoder searches for the template with the smallest SAD relative to the template of the current block, and uses the block corresponding to the matched template (the "matching block") as the predicted block.

[0100] The dimensions of the global range (SearchRange_w, SearchRange_h) are set to have a constant number of SAD comparisons per pixel, proportional to the block dimensions (i, h), i.e.

number

[0101] To speed up template matching, the search region (R1 to R4) is subsampled by a factor of 2. This reduces the template matching search by a factor of 4. After the best match is found, a refinement process is performed in which another template matching search is performed around the best match with a reduced search range. The refined search range is defined as min(w,h) / 2, where w and h are the width and height of the current CU.

[0102] Furthermore, a multi-candidate intra-TMP method has been proposed for the VVC standard and ECM. Typically, there are several blocks similar to the current block, each with a comparable template matching cost. Therefore, instead of selecting only one matching block with the smallest SAD, intra-TMP can alternatively be implemented using multiple prediction block candidates. A candidate list is created, and the candidate matching blocks are ranked in ascending order of their template matching cost. An index is then signaled in the bitstream to indicate which prediction block candidate is actually used for the current block.

[0103] Alternatively, according to the intra-TMP fusion method proposed for the VVC standard and ECM, N candidate matching blocks corresponding to the N smallest template matching costs are fused to derive a prediction block for the current block.

[0104] Alternatively, according to the intra-TMP filter method proposed for the VVC standard and ECM, a linear filter model is applied to intra-TMP prediction. The six-tap linear filter consists of five spatial luma samples in the matching block and a bias term. The filter coefficients are derived for each block using a regression based on the minimized MSE of the samples between the matching template and the current template.

[0105] As an alternative to or in addition to the intra-TMP mode based on L-shaped templates (left and upper templates), we propose an intra-TMP mode that uses only the left template and an intra-TMP mode that uses only the upper template, as shown in Figure 4B, respectively.

[0106] However, the predicted sample values ​​of intra-TMP coded blocks may be less accurate due to the following limitations:

[0107] Intra-TMP only considers the non-local spatial correlation of the current frame for prediction, but does not consider the local spatial correlation of neighboring samples of the current block.

[0108] The lighting may change even within the same frame.

[0109] In ECM, Intra TMP is effective not only for screen content but also for camera-captured content. For camera-captured content that is richer in texture than screen content, the restriction of Intra TMP to integer pixel positions may not achieve optimal results.

[0110] Therefore, exemplary embodiments of the present disclosure provide for the fusion of intra-TMP modes with other intra-prediction modes that utilize neighboring samples to improve prediction accuracy. According to exemplary embodiments of the present disclosure, intra-TMP modes are fused with different prediction modes, such as spatial geometric partition mode (SGPM) and combined inter- and intra-prediction (CIIP). According to further exemplary embodiments of the present disclosure, intra-TMP prediction blocks are refined based on neighboring samples, such as by using a position-dependent intra-prediction combining (PDPC) method. According to further exemplary embodiments of the present disclosure, LIC is applied to refine intra-TMP prediction blocks. According to further exemplary embodiments of the present disclosure, sub-pixel positioning is implemented in intra-TMP to further improve prediction accuracy.

[0111] According to an exemplary embodiment of the present disclosure, the intra-TMP mode is fused with the intra-prediction modes, which are valid for the luma component in VVC: planar, DC, angular intra-prediction mode, multiple reference line (MRL) prediction mode, intra-subpartition (ISP) mode, and matrix-based intra-prediction (MIP) mode.

[0112] Angular intra prediction is a directional intra prediction method supported by HEVC and also part of VVC. To capture arbitrary edge directions that appear in natural video, the number of angular intra prediction modes in VVC is extended from 33 (as used in HEVC) to 65. The new angular intra prediction modes, not found in HEVC, are indicated by dotted arrows in Figure 5.

[0113] Similar to HEVC, VVC also supports two non-angular intra prediction modes: DC mode and planar mode. In DC intra prediction mode, the average sample value of reference samples for a block is used to generate the prediction. VVC calculates the average using only reference samples along the long sides of rectangular blocks, while for square blocks, reference samples from both the left and top are used. In planar mode, the predicted sample value is obtained as a weighted average of four reference sample values, where the reference samples used are those in the same row or column as the current sample and those in the bottom-left and top-right positions relative to the block.

[0114] In VVC, the position-dependent intra-prediction combining (PDPC) method further modifies the intra-prediction results of DC, planar, and some angle modes. PDPC is applied to intra-modes without signaling, including planar, DC, intra-angles below horizontal, and intra-angles above vertical and below index 80.

[0115] The prediction sample pred(x',y') is predicted using a linear combination of the intra prediction mode (DC, planar, angular) and the reference sample according to the following equation:

number

[0116] The PDPC process for DC and planar modes is the same. In angular modes, if the current angular mode is HOR_IDX or VER_IDX, the left or upper reference sample is not used, respectively. The PDPC weights and scale factors depend on the prediction mode and block size. PDPC is applied to blocks with both width and height equal to or greater than 4.

[0117] In MRL mode, in addition to the directly adjacent lines of nearby samples, one of the two non-adjacent reference lines may contain input for intra prediction in VVC.

[0118] Depending on the block size, ISP divides a luma intra-predicted block vertically or horizontally into two or four sub-partitions, where prediction and transform coding operations are performed independently in each sub-partition, but the intra-prediction mode is shared among all sub-partitions.

[0119] Furthermore, MIP is a new intra prediction technique added to VVC. To predict a sample of a block of width W and height H, MIP takes as input H reconstructed neighbor boundary samples in one row to the left of the block and W reconstructed neighbor boundary samples in one row above the block. The generation of the prediction signal is based on three steps: downsampling of the reference samples, matrix-vector multiplication, and upsampling of the result by linear interpolation.

[0120] ECM further proposes luma intra-prediction modes, including decoder-side intra-mode derivation (DIMD) and template-based intra-mode derivation (TIMD). When DIMD is applied, two intra-prediction modes from 65 angular modes are derived from nearby reconstructed samples, and these two predictors are combined with the planar mode predictor using weights derived from gradients. When TIMD is applied, for each intra-prediction mode in the list, the SATD between the template predicted sample and the reconstructed sample is calculated. The first two intra-prediction modes with the smallest SATD are selected and combined with weights derived from the SATD.

[0121] According to an exemplary embodiment of the present disclosure, a VVC standard encoder and a VVC standard decoder configure one or more processors of a computing system to generate a motion prediction by blending a prediction of an intra-TMP mode with a prediction of another intra-prediction mode (which may be any intra-prediction mode as described above), as follows:

number

[0122] pred intra The intra prediction mode for generating (i, j) may be a predefined intra prediction mode. For example, the intra prediction mode is a planar mode. For another example, the intra prediction mode is a DC mode. For another example, the intra prediction mode is an angle mode derived using a DIMD method, i.e., derived from gradient information of neighboring samples. For another example, the intra prediction mode is an intra prediction mode derived using a TIMD method, i.e., derived from a template.

[0123] pred intraThe intra-prediction mode for generating (i, j) may be indicated by a syntax element signaled in the bitstream. For example, for a block indicated to be predicted by blending intra-TMP mode with another intra-prediction mode, an intra-prediction mode list may be constructed that includes several intra-prediction modes among planar mode, DC mode, and 65 angular modes. An index is signaled in the bitstream to indicate which intra-prediction mode is selected.

[0124] The two weights w0 and w1 may be two predefined values. For example, the value of w0 may be equal to 0.5, and the value of w1 may be equal to 0.5. The two weights w0 and w1 may be determined based on the intra prediction modes of neighboring blocks. For example, if the neighboring blocks contain more blocks coded in intra TMP mode, the value of w0 is larger, and if the neighboring blocks contain fewer blocks coded in intra TMP mode, the value of w1 is larger. The two weights w0 and w1 may also be indicated by a syntax element signaled in the bitstream. For example, a list of two weights is constructed, and the index of the selected weight is signaled in the bitstream.

[0125] The use of the fusion of the intra TMP mode and another intra prediction mode for a block may be indicated by a flag signaled in the bitstream. Specifically, if a flag indicating that the intra TMP mode is used for prediction for a block exists in the bitstream, another flag indicating whether to fuse with another intra prediction mode is further signaled in the bitstream. In some embodiments, there is no additional flag indicating fusion. That is, if a flag indicating that the intra TMP mode is used for prediction for a block exists in the bitstream, it is always fused with another intra prediction mode.

[0126] In some embodiments, the template matching process is also modified for blocks predicted by combining intra-TMP mode and another intra-prediction mode. In the original intra-TMP template matching, the SAD value between the reconstruction value of the template of the current block and the reconstruction value of the matched template is calculated to find a matching block. In contrast, according to an exemplary embodiment of the present invention, for blocks predicted by the fusion mode, an intra-prediction mode is used, and the template of the current block is predicted by its neighboring samples, and the predicted sample values ​​of the template also affect the template matching process. As an example, when performing template matching, the reconstruction value of the matched template is fused with the predicted sample values ​​of the template of the current block obtained using the intra-prediction mode, and then the SAD value between the fused value and the reconstructed value of the template of the current block is calculated to perform template matching. As another example, when performing template matching, the reconstruction value of the template of the current block is subtracted from the predicted sample values ​​obtained using the intra-prediction mode, and then the SAD value between the modified value and the reconstructed value of the matched template is calculated to perform template matching.

[0127] According to an exemplary embodiment of the present disclosure, a VVC standard encoder and a VVC standard decoder configure one or more processors of a computing system to combine intra-TMP mode and spatial geometric partition mode (SGPM). VVC supports SGPM mode for inter prediction. Geometric partition mode is signaled using a CU-level flag as a type of merge mode; other merge modes include normal merge mode, MMVD mode, CIIP mode, and sub-block merge mode. Geometric partition mode supports a total of 64 partitions for each possible CU size.

[0128] When this mode is used, a CU is split into two parts by a geometrically positioned line. The position of the split line is mathematically derived from the angle and offset parameters of a particular partition. Each part of the geometric partition in a CU is inter-predicted using its own motion. Only uni-prediction is allowed for each partition, i.e., each part has one motion vector and one reference index. Uni-prediction motion constraints are applied to ensure that only two motion-compensated predictions are required for each CU, just like in traditional bi-prediction. After predicting each part of the geometric partition, the sample values ​​along the edge of the geometric partition are adjusted using a blending process with adaptive weights. This is the prediction signal for the entire CU, and as with other prediction modes, the transformation and quantization processes are applied to the entire CU.

[0129] ECM adopts a spatial GPM method, which utilizes geometric partition mode (GPM) for intra prediction. This new intra-coding tool partitions a coding block into two parts and generates two corresponding intra-prediction modes. To efficiently represent the partitions and associated prediction information in the bitstream, this method uses a template-reordered candidate list, where each candidate in the list includes a combination of a partition mode and two intra-prediction modes, and only the candidate index is signaled.

[0130] For each partition mode, the VVC standard encoder and decoder derive an IPM list for each part. The size of the IPM list is 3. The IPM list is derived for TIMD mode, DIMD mode, and intra mode of neighboring blocks. The possible combinations of one geometric partition mode and two intra prediction modes are ranked in ascending order based on the SAD between template prediction and reconstruction. The weight in the template is 1 or 0 depending on the partition mode. The size of the template is set equal to 1, i.e., the height of the upper template part is 1 and the width of the left template part is 1. The length of the candidate list of combinations is set equal to 16.

[0131] According to an exemplary embodiment of the present disclosure, a VVC standard encoder and a VVC standard decoder configure one or more processors of a computing system to include an intra-TMP mode in the IPM list of the SGPM, thereby enabling the intra-TMP mode to be merged with another intra-prediction mode in a geometrically partitioned block.

[0132] As an example, the intra-TMP mode is always included in the IPM list of the SGPM. For example, the number of intra-prediction modes in the IPM list is expanded from 3 to 4, with the first three modes constructed in the original way and the fourth mode set to the intra-TMP mode.

[0133] As another example, if at least one neighboring block is coded in intra-TMP mode, then the intra-TMP mode is included in the IPM list of the SGPM.

[0134] As another example, if at least one neighboring block is coded in intra-TMP mode and the block vector of the neighboring block is used to predict the current block, the intra-TMP mode is included in the IPM list of the SGPM. Specifically, when constructing the IPM list in the SGPM for the current block, the neighboring blocks are traversed in a specific order, and a block vector indicating the location of the matching block of the first traversed intra-TMP coded neighboring block is stored. Then, when predicting the current block in intra-TMP mode, another block vector for the current block is searched for using the stored block vector instead of performing template matching.

[0135] According to an exemplary embodiment of the present disclosure, a VVC standard encoder and a VVC standard decoder configure one or more processors of a computing system to combine the intra-TMP mode with the combined inter and intra prediction mode (CIIP). According to VVC, when a CU is coded in merge mode, if the CU contains at least 64 luma samples (i.e., the product of the CU width and CU height is 64 or greater) and both the CU width and CU height are less than 128 luma samples, an additional flag is signaled indicating whether the combined inter and intra prediction mode (CIIP) is applied to the current CU. As the name suggests, CIIP prediction combines inter and intra prediction signals. The inter prediction signal in CIIP mode P_inter is derived using the same inter prediction process as applied in normal merge mode, and the intra prediction signal P_intra is derived after the normal intra prediction process in plane mode. Then, the intra and inter prediction signals are combined using a weighted average, where the weights are calculated according to the coding modes of the upper and left neighboring blocks, as follows:

[0136] If the neighboring block above is available and intra-coded, set isIntraTop to 1; otherwise, set isIntraTop to 0.

[0137] If the left neighboring block is available and intra-coded, set isIntraLeft to 1; otherwise, set isIntraLeft to 0.

[0138] If (isIntraLeft+isIntraTop) is equal to 2, set wt to 3.

[0139] Otherwise, if (isIntraLeft+isIntraTop) is equal to 1, set wt to 2.

[0140] Otherwise, set wt to 1.

[0141] The CIIP forecast is computed as follows:

number

[0142] According to the ECM, the CIIP uses a TIMD derivation method to derive the intra prediction mode: the intra prediction mode with the smallest SATD value in the TIMD mode list is selected and mapped to one of the 67 regular intra prediction modes.

[0143] It is also proposed to modify the weights when the derived intra prediction mode is an angular mode. In the nearly horizontal mode (2≦angular mode index<34), the current block is divided vertically as shown in Figure 6A, and in the nearly vertical mode (34≦angular mode index≦66), the current block is divided horizontally as shown in Figure 6B.

[0144] The (wIntra, wInter) of different sub-blocks are shown in Table 1 below. [Table 1]

[0145] According to an exemplary embodiment of the present disclosure, a VVC standard encoder and a VVC standard decoder configure one or more processors of a computing system to include an intra-TMP mode in a CIIP mode. CIIP prediction can combine an inter-prediction signal and an intra-prediction signal. As an example, CIIP prediction can also combine an intra-TMP prediction signal with another intra-prediction signal. As another example, CIIP prediction can also combine an intra-TMP prediction signal with an inter-prediction signal.

[0146] Furthermore, according to an exemplary embodiment of the present disclosure, a VVC standard encoder and a VVC standard decoder configure one or more processors of a computing system to refine predicted sample values ​​for intra-TMP mode by neighboring samples. For a block coded in intra-TMP mode, each sample in the block may be refined using the reconstructed value of its corresponding upper neighboring sample and its corresponding left neighboring sample, as shown in Figure 7A. For example, the predicted sample values ​​may be refined using the same method as PDPC for planar mode.

[0147] The use of refinement by neighboring samples for a block coded in intra-TMP mode is indicated by a flag signaled in the bitstream. Specifically, if a flag indicating that intra-TMP mode is used for prediction for a block is present in the bitstream, another flag indicating whether to refine by neighboring samples is further signaled in the bitstream. In some embodiments, there is no additional flag indicating refinement. That is, if a flag indicating that intra-TMP mode is used for prediction for a block is present in the bitstream, refinement is always performed by neighboring samples.

[0148] Furthermore, LIC is an inter-prediction technique that models the local illumination variation between the current block and its predicted block as a function of the local illumination variation between the current block template and the reference block template. The function parameters are represented by a scale α and an offset β, and compensate for illumination changes according to the linear equation α*p[x]+β, where p[x] is the reference sample pointed to by the MV at location x on the reference image. When wraparound motion compensation is enabled, the MV should be clipped to account for the wraparound offset. Because α and β can be derived based on the current block template and the reference block template, no signaling overhead is required for them, except for the LIC flag signaled for AMVP mode to indicate the use of LIC.

[0149] For uni-predictive inter CUs, local illumination compensation is used with the following modifications:

[0150] Intra-neighborhood samples can be used to derive LIC parameters,

[0151] LIC is not possible for blocks with less than 32 luma samples.

[0152] For both the non-subblock mode and the affine mode, the derivation of the LIC parameters is performed based on the template block samples corresponding to the current CU, rather than the partial template block samples corresponding to the first upper-left 16x16 unit; and

[0153] The samples of the reference block template are generated using MC and block MV without rounding the block MV to integer pixel positions.

[0154] According to an exemplary embodiment of the present disclosure, a VVC standard encoder and a VVC standard decoder configure one or more processors of a computing system to perform LIC on predicted sample values ​​of a block coded in intra-TMP mode. Specifically, when a block predicted in intra-TMP mode finds a matching block through template matching, a linear model is first constructed between the matched template and the template of the current block, and then the linear model is applied to the reconstructed samples in the matching block to generate predicted sample values ​​of the current block, instead of directly copying from the matching block.

[0155] The use of LIC for a block coded in intra-TMP mode is indicated by a flag signaled in the bitstream. Specifically, if a flag indicating that intra-TMP mode is used for prediction for a block is present in the bitstream, another flag indicating whether LIC should be performed is also signaled in the bitstream. In some embodiments, there is no additional flag indicating the performance of LIC. That is, if a flag indicating that intra-TMP mode is used for prediction for a block is present in the bitstream, LIC is always performed. In some embodiments, an implicit method is used to determine whether LIC should be performed for a block coded in intra-TMP mode. This determination can be made using information about the template. For example, if there is a large difference between the mean value of the template for the current block and the mean value of the template for the matching block, LIC is performed; otherwise, LIC is not performed.

[0156] In some embodiments, when LIC is performed on a block predicted by intra-TMP mode, the template matching process is also modified. First, a linear model is constructed between the template of the current block and the matched template. Next, the reconstructed value of the matched template is modified using the linear model. Finally, the SAD value between the modified value and the reconstructed value of the template of the current block is calculated, and template matching is performed.

[0157] According to exemplary embodiments of the present disclosure, a VVC standard encoder and a VVC standard decoder configure one or more processors of a computing system to implement sub-pixel positions around integer pixel positions, or in other words, fractional pixel positions around integer pixel positions, in an intra-TMP. As an example, but not limited to, half-pixel positions (i.e., half-pixel positions) around integer pixel positions can be implemented in an intra-TMP. As another example, but not limited to, quarter-pixel positions (i.e., quarter-pixel positions) around integer pixel positions can be implemented in an intra-TMP. As yet another example, sub-pixel positions with greater granularity around integer pixel positions can be implemented in an intra-TMP.

[0158] Currently, Intra-TMP only supports integer pixel accuracy. Template matching determines the location of a block vector that indicates the location of the matching block with integer pixel accuracy. Then, the reconstructed values ​​of the integer pixel locations indicated by the block vector are directly copied to the corresponding locations of the current block as the predicted sample values ​​of the current block.

[0159] According to the present disclosure, it should be understood that sub-pixel positions around integer pixel positions supported by intra-TMP modes can be expressed according to coordinates along horizontal and vertical axes in the format (x,y) (i.e., without reference to the integer pixel position), or alternatively, can be decomposed into two components: precision and direction. Sub-pixel precision should be understood as the magnitude of a sub-position's shift from the integer pixel position, and this shift is further decomposed into a horizontal precision offset component and a vertical precision offset component, which are then expressed in the format (o1,o2). The horizontal precision offset component describes the sub-pixel position's horizontal offset from the optimal integer pixel position. The vertical precision offset component describes the sub-pixel position's vertical offset from the optimal integer pixel position. Both the horizontal precision offset and the vertical precision offset can be expressed as absolute sub-pixel values ​​(there are no negative values) or as sub-pixel values ​​along a positive or negative axis centered around the optimal integer pixel position.

[0160] The direction of a "sub-pixel position surrounding an integer pixel position" should be understood as one of any number of different directions of offset from the integer pixel position, which may include the eight cardinal directions, and may further include additional intermediate directions between the cardinal directions as described below.

[0161] According to one embodiment, a VVC standard encoder and a VVC standard decoder configure one or more processors of a computing system to determine an optimal integer pixel position of a matching block according to intra-TMP template matching, and then configure the one or more processors to determine whether to refer to sub-pixel positions around the integer pixel position for the intra-TMP according to template matching of the integer pixel position against half-pixel positions around the integer pixel position.

[0162] According to another embodiment, a VVC standard encoder and a VVC standard decoder configure one or more processors of a computing system to determine an optimal integer pixel position of a matching block according to intra-TMP template matching, and then configure the one or more processors to determine whether to refer to sub-pixel positions surrounding the integer pixel position for the intra-TMP according to syntax elements signaled in the bitstream.

[0163] The template matching process for intra-TMP is configured in substantially the same way by a VVC standard encoder and a VVC standard decoder. However, the VVC standard encoder further configures signaling of syntax elements, and the VVC standard decoder further configures these syntax elements. The VVC standard encoder further configures one or more processors of the computing system to predict the current block using the integer pixel position and a set of sub-pixel positions surrounding the integer pixel position after the intra-TMP template matching determines the best matching block at the integer pixel position. As an example, template matching is performed at four half-pixel positions above, below, left, and right of the integer pixel position, respectively, to determine the best prediction. Next, a flag indicating whether the integer pixel position or the sub-pixel position is to be used is signaled in the bitstream. If the flag indicates that a sub-pixel position is to be used, another syntax element indicating which of the set of possible sub-pixel positions surrounding the integer pixel position is to be selected is further signaled.

[0164] When predicting at integer pixel positions, the reconstructed values ​​of the matching blocks are copied to the corresponding positions of the current block as predicted sample values. When predicting at sub-pixel positions around the integer pixel positions, the matching blocks at the integer pixel positions are offset according to the sub-pixel positions, and the predicted sample values ​​of the current block are obtained by interpolating the matching blocks at the sub-pixel positions around the integer pixel positions.

[0165] The VVC standard decoder further configures one or more processors of the computing system to determine, for blocks coded in intra-TMP mode, whether to refer to integer pixel positions or sub-pixel positions by a flag signaled in the bitstream, and which sub-pixel positions around the integer pixel positions are used is determined by syntax elements signaled in the bitstream.

[0166] According to another embodiment, a VVC standard encoder and a VVC standard decoder configure one or more processors of a computing system to determine an optimal integer pixel position of a matching block by template matching, and further configure the one or more processors to determine whether to refer to sub-pixel positions surrounding the integer pixel position for intra-TMP according to a flag signaled in the bitstream and according to the template.

[0167] The VVC standard encoder further configures one or more processors of the computing system to predict the current block using the integer pixel position and a set of sub-pixel positions around the integer pixel position after determining a matching block at the optimal integer pixel position through template matching of the intra-TMP. As an example, template matching is performed at each of four half-pixel positions above, below, left, and right of the integer pixel position to determine the optimal prediction. Then, a flag indicating whether the integer pixel position or the sub-pixel position is used is signaled in the bitstream.

[0168] The VVC standard decoder further configures one or more processors of the computing system to determine, for blocks coded in intra-TMP mode, whether to refer to integer pixel or sub-pixel locations via a flag signaled in the bitstream, with the coordinates of half-pixel locations being determined in the same manner by templates in both the encoder and the decoder.

[0169] According to some embodiments, a high-level syntax structure flag is signaled to indicate whether sub-pixel positioning is supported in the intra-TMP. For example, a flag can be signaled in the SPS syntax structure found in the sequence of multiple images, as described above. Based on this high-level flag, sub-pixel positioning can be enabled only in certain cases. For example, for camera-captured content, this flag is set to true, and the intra-TMP is configured to support sub-pixel positioning for camera-captured content, but for screen content, this flag is set to false, and the intra-TMP is configured not to support sub-pixel positioning for screen content.

[0170] After the optimal integer pixel position matching block is determined by template matching of the intra-TMP and the sub-pixel positions surrounding the integer pixel position are referenced (regardless of how the one or more processors decide to reference the sub-pixel positions), the one or more processors continue performing template matching at the set of sub-pixel positions surrounding the integer pixel position. As an example, template matching is performed at four half-pixel positions above, below, left, and right of the integer pixel position. Figure 8 shows the half-pixel positions above, below, left, and right of the integer pixel position.

[0171] When performing template matching on sub-pixel positions surrounding an integer pixel position, for each of a set of sub-pixel positions surrounding the integer pixel position, an interpolation filter is used to interpolate the matched template, and the SAD between the interpolated matched template and each of the set of sub-pixel positions surrounding the integer pixel position is calculated.

[0172] Interpolating the matched template should be understood as taking each sample of the matched template and inputting that sample and several neighboring samples into an interpolation filter to output a corresponding interpolated sample. In other words, all samples of the matched template and several neighboring samples are input into an interpolation filter, which outputs an interpolated sample for the entire matched template.

[0173] This disclosure does not specifically limit the type and number of taps of the interpolation filter used in the matched template interpolation.

[0174] In any direction (up, down, left, right) of the matched template, 0 to 2 rows of neighboring samples can be input to the interpolation filter. Additionally, neighboring samples can be biased in the direction of an offset from integer pixel positions to sub-pixel positions.

[0175] As an example, the matched template of Figure 7B can be interpolated as follows: For sub-pixel positions offset to the left of the integer pixel position, for a 4-tap interpolation filter, samples a through n shown in Figure 7B are input to the interpolation filter, and to output each individual sample, the left-biased neighboring samples of that individual sample are input to the interpolation filter. That is, to output sample c', left-biased samples a, b, c, and d are input to the interpolation filter; to output sample d', left-biased samples b, c, d, and e are input to the interpolation filter; to output sample m', left-biased samples k, l, m, and n are input to the interpolation filter, etc.

[0176] As another example, the matched template of Figure 7C can be interpolated as follows: For sub-pixel positions offset to the right of the integer pixel position, for a 4-tap interpolation filter, samples a through n shown in Figure 7C are input to the interpolation filter, and to output each individual sample, the right-biased neighboring samples of that individual sample are input to the interpolation filter. That is, to output sample b', right-biased samples a, b, c, and d are input to the interpolation filter; to output sample c', right-biased samples b, c, d, and e are input to the interpolation filter; to output sample l', right-biased samples k, l, m, and n are input to the interpolation filter, etc.

[0177] As another example, the matched template in Figure 7D can be interpolated as follows: At sub-pixel positions offset to the upper left of the integer pixel positions, for a 4-tap interpolation filter, samples a to ai shown in Figure 7D are first input to the horizontal interpolation filter, and to output each individual sample, a sample adjacent to the left bias of the individual sample is input to the interpolation filter, which then outputs samples c' to a', which are then input to the vertical interpolation filter, and to output each individual sample, a sample adjacent to the up bias of the individual sample is input to the interpolation filter.

[0178] In other words, to output sample c', left-biased samples a, b, c, and d are input to the interpolation filter, to output sample j', left-biased samples h, i, j, and k are input to the interpolation filter, to output sample q', left-biased samples o, p, q, and r are input to the interpolation filter, to output sample x', left-biased samples v, w, x, and y are input to the interpolation filter, etc. Then, to output sample q', top-biased samples c', j', q', and x' are input to the interpolation filter.

[0179] If at least one of the SAD values ​​of the set of sub-pixel positions surrounding the integer pixel position is smaller than the SAD value of the optimal integer pixel position, the sub-pixel position is used. Among the set of sub-pixel positions surrounding the integer pixel position, the sub-pixel position with the smallest SAD value is determined for motion prediction. During prediction, the matching blocks at the integer pixel position are offset according to the determined sub-pixel positions, and the predicted sample values ​​of the current block are obtained by interpolating the matching blocks at the determined sub-pixel positions surrounding the integer pixel position.

[0180] According to some embodiments, the sub-pixel locations may be eight locations relative to the optimal integer pixel location, i.e., an upper half-pixel location, a lower half-pixel location, a left half-pixel location, a right half-pixel location, an upper left half-pixel location, an upper right half-pixel location, a lower left half-pixel location, and a lower right half-pixel location relative to the optimal integer pixel location, as shown in FIG. 9 . For the four diagonal half-pixel locations, interpolation may be performed in the horizontal and vertical directions, respectively. For example, horizontal interpolation may be performed first, followed by vertical interpolation. For another example, vertical interpolation may be performed first, followed by horizontal interpolation.

[0181] In terms of precision and direction, each of the eight positions above is offset by a half-pixel position from the optimal integer-pixel position, and each is offset in a different one of eight directions from the optimal integer-pixel position.

[0182] According to some embodiments, intra-TMP can consider not only half-pixel positions but also other sub-pixel positions such as quarter-pixel positions, eighth-pixel positions, and sixteenth-pixel positions, etc. The interpolation filter coefficients may be different for different levels of precision.

[0183] According to further embodiments, multiple combinations of sub-pixel position accuracy can be implemented in the intra-TMP, i.e., different combinations of sub-pixel accuracy and orientation can be supported in the intra-TMP.

[0184] Intra-TMP can support a combination of two sub-pixel accuracy levels and eight directions. As an example, half-pixel accuracy and quarter-pixel accuracy are supported, with eight directions supported for each accuracy level, as shown in Figure 10, which shows a total of 16 sub-pixel positions in eight directions. Blue circles indicate integer-pixel positions, gray circles indicate neighboring integer-pixel positions, red circles indicate half-pixel accuracy positions in eight directions, and yellow circles indicate quarter-pixel accuracy positions in eight directions.

[0185] Alternatively, intra-TMP can support a combination of three sub-pixel accuracy levels and eight directions. As an example, half-pixel accuracy, quarter-pixel accuracy, and three-quarter-pixel accuracy levels are supported, with eight directions supported for each accuracy level, as shown in Figure 11, which shows a total of 24 sub-pixel positions in eight directions. Blue circles indicate integer-pixel positions, gray circles indicate neighboring integer-pixel positions, red circles indicate half-pixel accuracy positions in eight directions, yellow circles indicate quarter-pixel accuracy positions in eight directions, and green circles indicate three-quarter-pixel accuracy positions in eight directions.

[0186] Alternatively, intra-TMP can support three sub-pixel accuracy combinations with up to 24 directions, with sub-pixel granularity supporting additional directions beyond the eight cardinal directions. As an example, half-pixel, quarter-pixel, and three-quarter-pixel accuracy are supported. As shown in Figure 12 (showing 48 sub-pixel positions), quarter-pixel accuracy supports eight directions, half-pixel accuracy supports a larger granularity of 16 directions, and three-quarter-pixel accuracy supports an even larger granularity of 24 directions. Blue circles indicate integer-pixel positions, gray circles indicate neighboring integer-pixel positions, red circles indicate half-pixel accuracy positions in 16 directions, yellow circles indicate quarter-pixel accuracy positions in eight directions, and green circles indicate three-quarter-pixel accuracy positions in 24 directions.

[0187] 11 and 12 further show each sub-pixel location having its coordinate location resolved into horizontal and vertical offset components (o1, o2) (using absolute values) as described above, without showing the directional components mentioned above. As shown in FIG. 11, those sub-pixel locations in the cardinal direction from the optimal integer pixel location have integer-pixel precision along one of the two offsets, while those sub-pixel locations in the ordinal direction from the optimal integer pixel location have sub-pixel precision along both offsets, where both sub-pixel precisions have the same magnitude. As shown in FIG. 12, additional sub-pixel locations are located intermediate between the cardinal and ordinal directions, and these intermediate sub-pixel locations have different sub-pixel precisions along both offsets.

[0188] The proposed multiple sub-pixel accuracy and directional decomposition can be combined with the previous embodiments.

[0189] In some embodiments, both the sub-pixel accuracy and the direction are derived by template matching, which is configured substantially similarly by the VVC standard encoder and the VVC standard decoder. As an example, when the intra-TMP is implemented with 1 / 2 pixel accuracy, 1 / 4 pixel accuracy and 3 / 4 pixel accuracy in eight directions are supported (as shown in FIG. 11 ). After the optimal integer pixel position of the matching block is determined by template matching according to the intra-TMP, it is further determined whether to refer to sub-pixel positions around the integer pixel position and which sub-pixel position (with which accuracy and in which direction) to use according to the template. That is, the position with the smallest template SAD value is used.

[0190] In some embodiments, both sub-pixel precision and direction are indicated by syntax elements signaled in the bitstream. First, a flag is signaled indicating whether to reference the optimal integer pixel location derived by template matching or to reference sub-pixel locations surrounding the integer pixel location. If the flag indicates that one of the sub-pixel locations is to be used, one or more syntax elements are further signaled indicating which of the sub-pixel locations surrounding the integer pixel location are to be used. As an example, the sub-pixel location is signaled by one syntax element. As another example, first, the selected precision is signaled by a syntax element, and then the selected direction is signaled by another syntax element. As yet another example, first, the selected direction is signaled by a syntax element, and then the selected precision is signaled by another syntax element. Each of the above syntax elements may be signaled by fixed-length coding, truncated unary coding, truncated binary coding, or exponential-Golomb coding, or any other binarization coding method.

[0191] In some embodiments, the sub-pixel precision is indicated by a syntax element signaled in the bitstream, the direction is not signaled in the bitstream, and the encoder and decoder are each configured to derive the direction by template matching. That is, if the flag indicates that one of the sub-pixel positions is to be used, a syntax element is further signaled indicating which sub-pixel precision to select. Template matching is then performed on the directions supported by the selected precision, and the direction with the smallest SAD value is selected.

[0192] In some embodiments, the direction is indicated by a syntax element signaled in the bitstream, the sub-pixel precision is not signaled in the bitstream, and the encoder and decoder are each configured to derive the sub-pixel precision by template matching. That is, if the flag indicates that one of the sub-pixel positions is to be used, a syntax element is further signaled indicating which direction to select. Template matching is then performed in the directions with the supported precisions, and the precision with the smallest SAD value is selected.

[0193] In some embodiments, subpixel precision is indicated by a syntax element signaled in the bitstream, the direction is not signaled in the bitstream, and the direction is derived by a syntax element signaled in the bitstream and a template matching method. That is, if the flag indicates that one of the subpixel positions is to be used, a syntax element indicating which subpixel precision is selected is further signaled. Next, the supported directions may be classified into C categories, and another syntax element indicating which category of direction is selected is further signaled. The value of C must be smaller than the number of supported directions, and each category must have at least one direction. If there is more than one direction for a selected category of direction, template matching is performed on these directions at the selected precision, and the direction with the smallest SAD value is selected.

[0194] As an example, if intra-TMP is implemented with half-pixel precision and supports eight directions with quarter-pixel and three-quarter-pixel precision (as shown in Figure 11), a syntax element is signaled to indicate which of the three sub-pixel precisions is selected. Furthermore, the eight directions can be classified into four categories: {up, down}, {left, right}, {upper-left, lower-right}, and {upper-right, lower-left} (i.e., each two opposite directions fall into the same category), and another syntax element is signaled to indicate which category of directions is selected. For each of the two opposite directions in this category, one direction is selected by performing template matching at the selected precision.

[0195] In some embodiments, when selecting a direction in a category by template matching, template matching can be performed on the direction in the category at a fixed precision rather than a selected precision. As an example, when selecting a direction in a category by template matching, template matching is performed at a half-pixel precision, regardless of the selected precision.

[0196] In some embodiments, for each intra-TMP coded block, once one of the sub-pixel locations is selected, the order of the sub-pixel location list is reordered using template matching.

[0197] As an example, all sub-pixel positions are sorted by template matching based on the SAD value. Then, a sub-pixel position list is constructed using the best N positions, and an index indicating which sub-pixel position to select for predicting the current block is signaled. The value of N can be any positive integer less than or equal to the number of supported sub-pixel positions. For example, for the supported sub-pixel positions according to FIG. 11, N is less than or equal to 24.

[0198] As another example, only sub-pixel precisions are sorted by template matching based on SAD values. The direction can be determined by a syntax element, and then the sub-pixel precisions in this direction are sorted by template matching based on SAD values, and a sub-pixel precision list is constructed using the best P precisions, and an index indicating which sub-pixel precision is selected is signaled. The value of P can be any positive integer less than or equal to the number of sub-pixel precisions supported in this direction. For example, for the supported sub-pixel positions according to Figure 11, P is less than or equal to 3.

[0199] As yet another example, only sub-pixel directions are sorted by template matching based on SAD values. The precision is determined by a syntax element signaled in the bitstream, and then the sub-pixel directions at this precision are sorted by template matching based on SAD values. The best D direction is used to construct a sub-pixel direction list, and an index indicating which sub-pixel direction is selected is signaled. The value of D can be any positive integer less than or equal to the number of sub-pixel directions supported at this precision. For example, for the supported sub-pixel positions associated with FIG. 11, D is less than or equal to 8. In some embodiments, the same sub-pixel direction list can be used for each precision, and the list can be derived for a particular precision. For example, for the supported sub-pixel positions associated with FIG. 11, a sub-pixel direction list can be constructed for ½-pixel precision and used for ¼-pixel precision and ¾-pixel precision.

[0200] All the above indices can be signaled by fixed length coding, truncated unary coding, truncated binary coding, or exponential-Golomb coding, or other binarization coding methods.

[0201] In some embodiments, the template matching cost is the sum of absolute translation differences (SATD), whereby the SAD cost function described above is replaced by a SATD cost function.

[0202] This disclosure does not specifically limit the type and number of taps of the interpolation filter used for half-pixel interpolation.

[0203] For horizontal half-pixel interpolation, as an example, a 2-tap interpolation filter

[3232] may be used. As another example, a 4-tap DCT-IF interpolation filter [-4 36 36 -4] may be used. As another example, a 4-tap DCT-IF interpolation filter [-16 144 144 -16] may be used. As another example, a 4-tap weak DCT-IF interpolation filter [-5 37 37 -5] may be used. As another example, a 4-tap Gaussian interpolation filter [8 24 24 8] may be used. As another example, a 6-tap flat DCT-IF interpolation filter [3 9 20 20 9 3] may be used. As another example, a 6-tap DCT-IF interpolation filter [12 -44 160 160 -44 12] may be used. As another example, an 8-tap DCT-IF interpolation filter [-4 16 -44 160 160 -44 16 -4] may be used. As another example, a 12-tap DCT-IF interpolation filter [-2 6 -13 25 -50 162 162 -50 25 -13 6 -2] may be used. For vertical half-pixel interpolation, the interpolation filter is the transpose of the interpolation filter for the horizontal half-pixel interpolation filter.

[0204] For horizontal quarter-pixel interpolation in the right direction (when the quarter-pixel position is to the right of the optimal integer-pixel position), as an example, a 2-tap bilinear interpolation filter

[4816] may be used. As another example, a 4-tap DCT-IF interpolation filter [-16 216 64 -8] may be used. As another example, a 6-tap DCT-IF interpolation filter [12 -40 232 68 -20 4] may be used. As another example, an 8-tap DCT-IF interpolation filter [-4 16 -40 323 68 -20 4 0] may be used. As another example, a 12-tap DCT-IF interpolation filter [-2 5 -11 21 -43 230 75 -29 15 -8 4 -1] may be used. For horizontal quarter-pixel interpolation in the left direction (when the quarter-pixel position is to the left of the optimal integer-pixel position), the interpolation filter is the horizontal transpose of the interpolation filter for horizontal quarter-pixels in the right direction. For vertical quarter-pixel interpolation in the upward direction (when the quarter-pixel position is above the best integer-pixel position), the interpolation filter is the transpose of the interpolation filter for horizontal quarter-pixel interpolation in the left direction. For vertical quarter-pixel interpolation in the downward direction (when the quarter-pixel position is below the best integer-pixel position), the interpolation filter is the transpose of the interpolation filter for horizontal quarter-pixel interpolation in the right direction.

[0205] For horizontal 3 / 4 pixel interpolation, the interpolation filter is the horizontal inverse of the interpolation filter for horizontal 1 / 4 pixel interpolation, and for vertical 3 / 4 pixel interpolation, the interpolation filter is the vertical inverse of the interpolation filter for horizontal 1 / 4 pixel interpolation.

[0206] Interpolation is performed using neighboring samples adjacent to the current block. According to some embodiments, when sub-pixel interpolation is performed on a matching block (as defined above with reference to the intra-TMP technique) and at least one sample outside the matching block is input to the interpolation filter, the input sample outside the matching block is padded by copying the nearest reconstructed sample in the matching block. As an example, as shown in FIG. 13, a half-pixel position is used, and the half-pixel position is between sample b and sample c. A 4-tap interpolation filter is used for interpolation, and input sample a, input sample b, input sample c, and input sample d are input to the interpolation filter, respectively. Since input sample d is outside the matching block, input sample c, which is the nearest reconstructed sample to input sample d in the matching block, is used for padding, i.e., the value of input sample c is copied to input sample d.

[0207] According to some embodiments, padding is performed on input samples outside the matching block only if they are unavailable during the interpolation process. If the matching block is at the boundary of an image, slice, or tile, neighboring samples on one entire side may not exist. Furthermore, even if the upper and left neighboring samples are coded or decoded before the matching block, the right and lower neighboring samples may not be coded or decoded before the current coding block according to the raster scan order. Other possible coding orders may vary the availability of neighboring samples across the top, left, right, or bottom edge. Therefore, in this disclosure, neighboring samples along an edge that are not present or have not been coded or decoded are referred to as "unavailable." For example, as shown in FIG. 13, if input sample d is available, there is no padding. If input sample d is unavailable, padding is performed by copying input sample c.

[0208] According to some embodiments, when determining the half-pixel position, other half-pixel positions than those immediately adjacent to the best integer pixel are also considered, for example, all sub-pixel positions within a region surrounding the best integer pixel may be considered, the extent of said region being related to the width and height of the current block.

[0209] As an example, all half-pixel locations within two integer pixels of the best integer-pixel location obtained by template matching are supported, thus 1 / 2 pixel and 3 / 2 pixel locations are supported.

[0210] In some embodiments, integer pixel positions within a region surrounding the optimal integer pixel position may also be considered, in some embodiments, a syntax element is first signaled to indicate which integer pixel position within the region surrounding the optimal integer pixel position is selected, and then another syntax element is further signaled to indicate which sub-pixel positions around the integer pixel position are used.

[0211] The proposed sub-pixel location based intra-TMP can be combined with other intra-TMP tools.

[0212] In some embodiments, when combined with multi-candidate intra-TMP, the sub-pixel position-based intra-TMP and the multi-candidate intra-TMP are treated as two separate schemes. That is, the multi-candidate index is signaled only if integer-pixel positions are used. Alternatively, a flag indicating whether the multi-candidate method is used is signaled first, and the sub-pixel position-based intra-TMP scheme can be used only if the multi-candidate scheme is not used.

[0213] In some embodiments, when combined with a multi-candidate intra-TMP, when a multi-candidate intra-TMP is used, after signaling the multi-candidate index, sub-pixel position-related parameters indicating the sub-pixel positions are further signaled or derived by template matching.

[0214] In some embodiments, when combined with intra-TMP fusion, intra-TMP based on sub-pixel position and intra-TMP fusion are treated as two separate schemes: the fusion method is signaled only when integer pixel positions are used, and the intra-TMP method based on sub-pixel position is signaled only when intra-TMP fusion is not used.

[0215] In some embodiments, when combined with intra-TMP fusion, sub-pixel position-related parameters indicating the sub-pixel position of each matching block used in the fusion method are signaled or derived by template matching, and in some embodiments, the same sub-pixel positions are used for all matching blocks used in the fusion method.

[0216] In some embodiments, when combined with intra-TMP filters, the intra-TMP based on sub-pixel positions and the intra-TMP filter are treated as two separate schemes: the filter method is signaled only when integer pixel positions are used, and the intra-TMP method based on sub-pixel positions is signaled only when intra-TMP filters are not used.

[0217] In some embodiments, when combined with an intra-TMP filter, when an intra-TMP filter is used, sub-pixel position-related parameters indicating the sub-pixel positions are further signaled or derived by template matching. In some embodiments, the filter process is performed after the sub-pixel position interpolation, and in some embodiments, the filter process is performed before the sub-pixel position interpolation.

[0218] In some embodiments, when combined with left template intra-TMP only or top template intra-TMP only, sub-pixel position based intra-TMP and multi-mode intra-TMP are treated as two separate schemes: left template intra-TMP only or top template intra-TMP only are signaled only when integer pixel positions are used, or the sub-pixel position based intra-TMP method is signaled only when L-template intra-TMP is used.

[0219] In some embodiments, when combined with only the intra-TMP of the left template or only the intra-TMP of the upper template, sub-pixel position related parameters indicating the sub-pixel positions are further signaled or derived by template matching in the case of only the intra-TMP of the left template or only the intra-TMP of the upper template.

[0220] In some embodiments, the methods described above for Intra-TMP can be used with IBC.

[0221] According to an exemplary embodiment of the present disclosure, the VVC standard encoder and VVC standard decoder configure one or more processors of a computing system to execute the intra-TMP mode according to one of two inversion modes: horizontal inversion mode and vertical inversion mode.

[0222] In horizontal flip mode, only the upper template is used when performing template matching. Before performing template matching, the upper template of the current block is first horizontally flipped, and then the template matching process is performed to find the template that matches with the horizontally flipped upper template. After that, the corresponding matching block is horizontally flipped and used as the predicted sample value of the current block.

[0223] In vertical flip mode, only the left template is used when performing template matching. Before performing template matching, the left template of the current block is first vertically flipped, and then the template matching process is performed to find a template that matches the vertically flipped left template. After that, the corresponding matching block is vertically flipped and used as the predicted sample value of the current block.

[0224] According to another embodiment, a different inversion method is implemented as follows.

[0225] In the horizontal flip mode, only the upper template is used when performing template matching. Before performing template matching, the upper template of the current block is first horizontally flipped, and then the template matching process is performed to search for a template that matches the horizontally flipped upper template. The VVC standard encoder further configures one or more processors of the computing system to horizontally flip the original values ​​of the current block before calculating the residual between the original values ​​of the current block and the predicted sample values. After reconstructing the current block, the reconstructed values ​​are horizontally flipped.

[0226] In vertical flip mode, only the left template is used when performing template matching. Before performing template matching, the left template of the current block is first vertically flipped, and then the template matching process is performed to find a template that matches the vertically flipped left template. The VVC standard encoder further configures one or more processors of the computing system to vertically flip the original values ​​of the current block before calculating the residual between the original values ​​of the current block and the predicted sample values. After reconstructing the current block, the reconstructed values ​​are vertically flipped.

[0227] The flipping performance for blocks coded in intra-TMP mode is indicated by a flag signaled in the bitstream. Specifically, if a flag indicating that intra-TMP mode is used for prediction for a block is present in the bitstream, another flag is further signaled in the bitstream indicating whether to perform flipping. Then, another flag is signaled indicating whether horizontal or vertical flipping is selected.

[0228] Those skilled in the art will understand that all of the above aspects of the present disclosure may be implemented simultaneously in any combination thereof, and that all aspects of the present disclosure may be implemented in combination as yet another embodiment of the present disclosure.

[0229] FIG. 14 illustrates an example system 1400 for implementing the above-described processes and methods for implementing intra-template matching prediction modes.

[0230] The techniques and mechanisms described herein may be implemented by multiple instances of system 1400, as well as other computing devices, systems, and / or environments. System 1400 shown in FIG. 14 is merely an example system and is not intended to suggest any limitation regarding the scope of use or functionality of any computing device utilized to perform the processes and / or procedures described above. Other well-known computing devices, systems, environments, and / or configurations that may be suitable for use with the above embodiments include, but are not limited to, personal computers, server computers, handheld or laptop devices, multiprocessor systems, microprocessor-based systems, set-top boxes, game consoles, programmable consumer electronics, network PCs, minicomputers, mainframe computers, distributed computing environments that include any of the above systems or devices, implementations using field programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs), and the like.

[0231] System 140 may include one or more processors 1402 and a system memory 1404 communicatively coupled to processor 1402. Processor 1402 may execute one or more modules and / or processes to cause processor 1402 to perform various functions. In some embodiments, processor 1402 may include a central processing unit (CPU), a graphics processing unit (GPU), both a CPU and a GPU, or other processing units or components known in the art. Additionally, each processor 1402 has its own local memory that may also store program modules, program data, and / or one or more operating systems.

[0232] Depending on the exact configuration and type of system 1400, system memory 1404 may be volatile, such as RAM, non-volatile, such as ROM, flash memory, a mini-hard drive, a memory card, or a combination thereof. System memory 1404 may include one or more computer-executable modules 1406 that are executable by processor 1402.

[0233] The modules 1406 include, but are not limited to, one or more of an encoder 1408 and a decoder 1410 .

[0234] The encoder 1408 may be a VVC standard encoder that implements any, some, or all aspects of the exemplary embodiments of the present disclosure as described above and is executable by the processor 1402 to configure the processor 1402 to perform the operations described above.

[0235] The decoder 1410 may be a VVC standard decoder that implements any, some, or all aspects of the exemplary embodiments of the present disclosure as described above and is executable by the processor 1402 to configure the processor 1402 to perform the operations described above.

[0236] System 1400 may further include an input / output (I / O) interface 1440 for receiving image source data and bitstream data and outputting reconstructed images to a reference image buffer or DPB and / or a display buffer. System 1400 may also include a communications module 1450 that enables system 1400 to communicate with other devices (not shown) over a network (not shown). The network may include wired media, such as the Internet, a wired network, or a direct-wired connection, and wireless media, such as acoustic, radio frequency (RF), infrared, and other wireless media.

[0237] In some embodiments, matching a template of the current block with a template in the search area; determining integer pixel locations of block vectors of matching blocks corresponding to the matched template; determining sub-pixel locations surrounding said integer pixel locations; and deriving reconstructed values ​​of the matching block at the determined sub-pixel positions surrounding the integer pixel position as predicted sample values ​​of the current block.

[0238] In one implementation, the step of deriving the reconstructed values ​​of the matching blocks at the determined sub-pixel positions around the integer pixel positions as the predicted sample values ​​of the current block comprises: Deriving the reconstructed value of the matching block at the determined sub-pixel location by applying an interpolation filter.

[0239] In one implementation, the step of deriving the reconstructed value of the matching block at the determined sub-pixel location by applying the interpolation filter comprises: Interpolating the reconstructed values ​​of the matching blocks at half-pixel positions by applying a 4-tap DCT-IF interpolation filter [-16 144 144 -16].

[0240] In one implementation, the step of deriving the reconstructed value of the matching block at the determined sub-pixel location by applying the interpolation filter comprises: Interpolating the reconstructed values ​​of the matching blocks at quarter-pixel positions by applying a 4-tap DCT-IF interpolation filter [-16 216 64 -8].

[0241] In one implementation, the computing method comprises: The method further includes padding unavailable input samples by copying the closest reconstructed samples in the matching block.

[0242] In one implementation, the sub-pixel locations around the integer pixel locations include precision and direction; the precision includes a magnitude of the offset from the integer pixel position; The direction comprises one of a plurality of cardinal directions from the integer pixel position.

[0243] In one implementation, the set of sub-pixel positions surrounding an integer pixel position includes 24 combinations of precisions each selected from three sub-pixel precisions and directions each selected from eight cardinal directions.

[0244] In one implementation, the three sub-pixel precisions include 1 / 4 pixel precision, 1 / 2 pixel precision, and 3 / 4 pixel precision.

[0245] In one implementation, the computing method comprises: The method further includes template matching the integer pixel location and the surrounding sub-pixel locations by interpolating the matched template for each sub-pixel location.

[0246] In one implementation, the computing method comprises: The method further includes transmitting a first flag in the bitstream that indicates that sub-pixel positions surrounding the integer pixel position are to be referenced for intra-template matching prediction (intra-TMP).

[0247] In one implementation, the computing method comprises: The method further includes transmitting a second flag in the bitstream that indicates one of a set of sub-pixel positions surrounding the integer pixel position.

[0248] In one implementation, the step of transmitting in the bitstream the second flag indicating one of the set of sub-pixel positions surrounding the integer pixel position comprises: transmitting the one of the set of sub-pixel locations in a syntax element of the bitstream.

[0249] In one implementation, the step of transmitting in the bitstream the second flag indicating one of the set of sub-pixel positions surrounding the integer pixel position comprises: transmitting in a first syntax element of the bitstream the precision of the one of the set of sub-pixel locations; transmitting the orientation of the one of the set of sub-pixel locations in a second syntax element of the bitstream following the first syntax element.

[0250] In one implementation, the step of transmitting in the bitstream the second flag indicating one of the set of sub-pixel positions surrounding the integer pixel position comprises: transmitting the orientation of the one of the set of sub-pixel locations in a first syntax element of the bitstream; transmitting the precision of the one of the set of sub-pixel locations in a second syntax element of the bitstream following the first syntax element.

[0251] In one implementation, the step of transmitting in the bitstream the second flag indicating one of the set of sub-pixel positions surrounding the integer pixel position comprises: transmitting the one of the set of sub-pixel locations according to a binarization coding selected from one of fixed length coding, truncated unary coding, truncated binary coding, and exponential-Golomb coding.

[0252] In one implementation, the computing method comprises: further comprising reading a first flag from the bitstream; deriving the reconstructed values ​​of the matching blocks at the determined sub-pixel positions around the integer pixel position as the predicted sample values ​​of the current block, The method includes interpolating, based on the first flag, the reconstructed values ​​of the matching block at the determined sub-pixel positions around the integer pixel position as predicted sample values ​​of the current block.

[0253] In one implementation, the computing method comprises: further comprising the step of reading a second flag from the bitstream; The step of determining the sub-pixel locations surrounding the integer pixel locations comprises: determining the sub-pixel positions around the integer pixel position based on the second flag indicating the sub-pixel positions around the integer pixel position;

[0254] In some embodiments, a matching module configured to match a template of the current block with a template in the search area; a determination module configured to determine integer pixel positions of a block vector of a matching block corresponding to the matched template and to determine sub-pixel positions surrounding the integer pixel positions; a derivation module configured to derive reconstructed values ​​of the matching block at the determined sub-pixel positions surrounding the integer pixel position as predicted sample values ​​of the current block.

[0255] In one implementation, the derivation module is configured to derive the reconstructed value of the matching block at the determined sub-pixel location by applying an interpolation filter.

[0256] In one implementation, the derivation module is configured to interpolate the reconstructed values ​​of the matching block at half-pixel positions by applying a 4-tap DCT-IF interpolation filter [-16 144 144 -16].

[0257] In one implementation, the derivation module is configured to interpolate the reconstructed values ​​of the matching block at quarter-pixel positions by applying a 4-tap DCT-IF interpolation filter [-16 216 64 -8].

[0258] In one implementation, the computing system: The method further includes a patching module that pads unavailable input samples by copying the closest reconstructed samples in the matching block.

[0259] In one implementation, the sub-pixel locations around the integer pixel locations include precision and direction; the precision includes a magnitude of the offset from the integer pixel position; The direction comprises one of a plurality of cardinal directions from the integer pixel position.

[0260] In one implementation, the set of sub-pixel positions surrounding an integer pixel position includes 24 combinations of precisions each selected from three sub-pixel precisions and directions each selected from eight cardinal directions.

[0261] In one implementation, the three sub-pixel precisions include 1 / 4 pixel precision, 1 / 2 pixel precision, and 3 / 4 pixel precision.

[0262] In one implementation, the computing system: The system further includes a template matching module configured to template match the integer pixel location and its surrounding sub-pixel locations by interpolating the matched template for each sub-pixel location.

[0263] In one implementation, the computing system: The device further includes a transmitting module configured to transmit a first flag in a bitstream indicating reference to sub-pixel positions surrounding the integer pixel position for intra-template matching prediction (intra-TMP).

[0264] In one implementation, the transmission module is further configured to transmit in the bitstream a second flag indicating one of a set of sub-pixel positions surrounding the integer pixel position.

[0265] In one implementation, the transmission module is further configured to transmit the one of the set of sub-pixel locations in a syntax element of the bitstream.

[0266] In one implementation, the transmission module is configured to transmit the precision of the one of the set of sub-pixel locations in a first syntax element of the bitstream and to transmit the direction of the one of the set of sub-pixel locations in a second syntax element of the bitstream following the first syntax element.

[0267] In one implementation, the transmission module is configured to transmit a direction of the one of the set of sub-pixel locations in a first syntax element of the bitstream and to transmit a precision of the one of the set of sub-pixel locations in a second syntax element of the bitstream following the first syntax element.

[0268] In one implementation, the transmission module is configured to transmit the one of the set of sub-pixel locations according to a binarization coding selected from fixed length coding, truncated unary coding, truncated binary coding, and exponential-Golomb coding.

[0269] In one implementation, the computing system: further comprising a read module for reading a first flag from the bitstream; The derivation module is configured to interpolate, based on the first flag, the reconstructed values ​​of the matching block at the determined sub-pixel positions around the integer pixel position as predicted sample values ​​of the current block.

[0270] In one implementation, the computing system: further comprising a read module for reading a second flag from the bitstream; The derivation module is configured to determine the sub-pixel positions surrounding the integer pixel position based on the second flag indicating the sub-pixel positions surrounding the integer pixel position.

[0271] In some embodiments, one or more processors; and a computer-readable storage medium communicatively coupled to the one or more processors, the computer-readable storage medium storing computer-readable instructions executable by the one or more processors and that, when executed by the one or more processors, perform a computing method according to an embodiment of the computing method described above.

[0272] In some embodiments, a non-transitory computer-readable storage medium is provided that stores a bitstream associated with one or more images, said bitstream being computed by a processor to cause said processor to perform a computing method according to any of the computing method embodiments described above.

[0273] In some embodiments, a computer program product is provided that includes computer program instructions that enable a computer to perform a computing method according to the computing method embodiments described above.

[0274] In some embodiments, a computer program is provided that enables a computer to perform a computing method according to the computing method embodiments described above.

[0275] Some or all of the operations of the above methods may be performed by executing computer-readable instructions stored on a computer-readable storage medium, as defined below. The term "computer-readable instructions," as used in the description and claims, includes routines, applications, application modules, program modules, programs, components, data structures, algorithms, etc. The computer-readable instructions may be implemented in a variety of system configurations, including single-processor or multi-processor systems, minicomputers, mainframe computers, personal computers, handheld computing devices, microprocessor-based and programmable consumer electronics, combinations thereof, and the like.

[0276] The computer-readable storage medium may include volatile memory (such as random access memory (RAM)) and / or non-volatile memory (such as read-only memory (ROM), flash memory, etc.). The computer-readable storage medium may also include additional removable and / or non-removable storage including, but not limited to, flash memory, magnetic storage, optical storage, and / or tape storage that may provide non-volatile storage of computer-readable instructions, data structures, program modules, and the like.

[0277] Non-instantaneous or non-transitory computer-readable storage media is an example of a computer-readable medium. Computer-readable media includes at least two types of computer-readable media: computer-readable storage media and communication media. Computer-readable storage media includes volatile and non-volatile, removable and non-removable media implemented in any process or technology for storing information such as computer-readable instructions, data structures, program modules, or other data. Computer-readable storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disc read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassette, magnetic tape, magnetic disk storage or other magnetic storage device, or any other non-transmission medium that can be used to store information and access it by a computing device. In contrast, communication media may embody computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transmission mechanism. As used herein, computer-readable storage media is not to be construed as instantaneous signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission medium (such as light pulses through fiber optic cable), or electrical signals propagating through wires.

[0278] Computer-readable instructions stored on one or more non-instantaneous or non-transitory computer-readable storage media, when executed by one or more processors, may perform the operations described above with reference to Figures 1A-10. Generally, computer-readable instructions include routines, programs, objects, components, data structures, etc. that perform particular functions or implement particular abstract data types. The order in which the operations are described is not intended to be construed as a limitation, and any number of the described operations can be combined in any order and / or in parallel to implement a process.

[0279] Although the subject matter has been described in language specific to structural features and / or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described. Rather, the specific features and acts are disclosed as example forms of implementing the claims.

Claims

1. matching a template of the current block with a template in the search area; determining integer pixel locations of block vectors of matching blocks corresponding to the matched template; determining sub-pixel locations surrounding said integer pixel locations; and deriving reconstructed values ​​of the matching block at the determined sub-pixel positions surrounding the integer pixel position as predicted sample values ​​of the current block.

2. deriving the reconstructed values ​​of the matching blocks at the determined sub-pixel positions around the integer pixel position as the predicted sample values ​​of the current block, The computing method of claim 1 , comprising applying an interpolation filter to derive the reconstructed value of the matching block at the determined sub-pixel location.

3. deriving the reconstructed value of the matching block at the determined sub-pixel location by applying the interpolation filter, 3. The computing method of claim 2, comprising the step of interpolating the reconstructed values ​​of the matching blocks at half-pixel positions by applying a 4-tap DCT-IF interpolation filter [-16 144 144 -16].

4. deriving the reconstructed value of the matching block at the determined sub-pixel location by applying the interpolation filter, 3. The computing method of claim 2, comprising the step of interpolating the reconstructed values ​​of the matching blocks at quarter-pixel positions by applying a 4-tap DCT-IF interpolation filter [-16 216 64 -8].

5. A computing method according to any one of claims 2 to 4, further comprising padding unavailable input samples by copying the nearest reconstructed sample in the matching block.

6. the sub-pixel locations surrounding the integer pixel locations include precision and direction; the precision includes a magnitude of the offset from the integer pixel position; The computing method of any preceding claim, wherein the direction comprises one of a plurality of cardinal directions from the integer pixel position.

7. 7. The computing method of claim 6, wherein the set of sub-pixel positions surrounding the integer pixel position includes 24 combinations of precisions each selected from three sub-pixel precisions and directions each selected from eight cardinal directions.

8. The computing method of claim 7 , wherein the three sub-pixel precisions include ¼ pixel precision, ½ pixel precision, and ¾ pixel precision.

9. 9. The computing method of claim 1, further comprising template matching the integer pixel location and its surrounding sub-pixel locations by interpolating the matched template for each sub-pixel location.

10. 10. The computing method of claim 1, further comprising transmitting in the bitstream a first flag indicating reference to sub-pixel positions surrounding an integer pixel position for intra-template matching prediction (intra-TMP).

11. 11. The computing method of claim 10, further comprising transmitting in the bitstream a second flag indicating one of a set of sub-pixel positions surrounding the integer pixel position.

12. transmitting in the bitstream the second flag indicating one of the set of sub-pixel positions surrounding the integer pixel position, 12. The computing method of claim 11, comprising transmitting the one of the set of sub-pixel locations in a syntax element of the bitstream.

13. transmitting in the bitstream the second flag indicating one of the set of sub-pixel positions surrounding the integer pixel position, transmitting in a first syntax element of the bitstream the precision of the one of the set of sub-pixel locations; and transmitting the orientation of the one of the set of sub-pixel locations in a second syntax element of the bitstream following the first syntax element.

14. transmitting in the bitstream the second flag indicating one of the set of sub-pixel positions surrounding the integer pixel position, transmitting, in a first syntax element of the bitstream, a direction of the one of the set of sub-pixel locations; and transmitting the precision of the one of the set of sub-pixel locations in a second syntax element of the bitstream following the first syntax element.

15. transmitting in the bitstream the second flag indicating one of the set of sub-pixel positions surrounding the integer pixel position, 12. The computing method of claim 11, comprising transmitting the one of the set of sub-pixel locations according to a binarization coding selected from one of fixed length coding, truncated unary coding, truncated binary coding, and exponential-Golomb coding.

16. further comprising the step of reading a first flag from the bitstream; deriving the reconstructed values ​​of the matching blocks at the determined sub-pixel positions around the integer pixel position as the predicted sample values ​​of the current block, 2. The computing method of claim 1, further comprising: interpolating, based on the first flag, the reconstructed values ​​of the matching blocks at the determined sub-pixel positions surrounding the integer pixel position as predicted sample values ​​of the current block.

17. further comprising the step of reading a second flag from the bitstream; The step of determining the sub-pixel locations surrounding the integer pixel locations comprises:

17. The computing method of claim 16, comprising determining the sub-pixel positions surrounding the integer pixel location based on the second flag indicating the sub-pixel positions surrounding the integer pixel location.

18. a matching module configured to match a template of the current block with a template in the search area; a determination module configured to determine integer pixel positions of a block vector of a matching block corresponding to the matched template and to determine sub-pixel positions surrounding the integer pixel positions; a derivation module configured to derive reconstructed values ​​of the matching block at the determined sub-pixel positions surrounding the integer pixel position as predicted sample values ​​of the current block.

19. 20. The computing system of claim 18, wherein the derivation module is configured to derive the reconstructed value of the matching block at the determined sub-pixel location by applying an interpolation filter.

20. 20. The computing system of claim 19, wherein the derivation module is configured to interpolate the reconstructed values ​​of the matching blocks at half-pixel positions by applying a 4-tap DCT-IF interpolation filter [-16 144 144 -16].

21. 20. The computing system of claim 19, wherein the derivation module is configured to interpolate the reconstructed values ​​of the matching blocks at quarter-pixel positions by applying a 4-tap DCT-IF interpolation filter [-16 216 64 -8].

22. 22. The computing system of claim 19, further comprising a patching module for padding unavailable input samples by copying the closest reconstructed samples in the matching block.

23. the sub-pixel locations surrounding the integer pixel locations include precision and direction; the precision includes a magnitude of the offset from the integer pixel position; The computing system of any one of claims 18 to 22, wherein the direction comprises one of a plurality of cardinal directions from the integer pixel position.

24. 24. The computing system of claim 23, wherein the set of sub-pixel positions surrounding the integer pixel position includes 24 combinations of precisions each selected from three sub-pixel precisions and directions each selected from eight cardinal directions.

25. 25. The computing system of claim 24, wherein the three sub-pixel precisions include 1 / 4 pixel precision, 1 / 2 pixel precision, and 3 / 4 pixel precision.

26. 26. The computing system of claim 18, further comprising a template matching module configured to template match the integer pixel location and its surrounding sub-pixel locations by interpolating the matched template for each sub-pixel location.

27. 27. The computing system of claim 18, further comprising a transmission module configured to transmit in a bitstream a first flag indicating reference to sub-pixel positions surrounding an integer pixel position for intra-template matching prediction (intra-TMP).

28. 28. The computing system of claim 27, wherein the transmitting module is further configured to transmit in the bitstream a second flag indicating one of a set of sub-pixel positions surrounding the integer pixel position.

29. 30. The computing system of claim 28, wherein the transmission module is further configured to transmit the one of the set of sub-pixel locations in a syntax element of the bitstream.

30. 29. The computing system of claim 28, wherein the transmit module is configured to transmit a precision of the one of the set of sub-pixel locations in a first syntax element of the bitstream and a direction of the one of the set of sub-pixel locations in a second syntax element of the bitstream following the first syntax element.

31. 29. The computing system of claim 28, wherein the transmission module is configured to transmit a direction of the one of the set of sub-pixel locations in a first syntax element of the bitstream and to transmit a precision of the one of the set of sub-pixel locations in a second syntax element of the bitstream following the first syntax element.

32. 29. The computing system of claim 28, wherein the transmission module is configured to transmit the one of the set of sub-pixel locations according to a binarization coding selected from one of fixed length coding, truncated unary coding, truncated binary coding, and exponential-Golomb coding.

33. further comprising a read module for reading the first flag from the bitstream; 20. The computing system of claim 18, wherein the derivation module is configured to interpolate, based on the first flag, the reconstructed values ​​of the matching blocks at the determined sub-pixel positions surrounding the integer pixel position as predicted sample values ​​of the current block.

34. a read module for reading a second flag from the bitstream; 34. The computing system of claim 33, wherein the derivation module is configured to determine the sub-pixel positions surrounding the integer pixel location based on the second flag indicating the sub-pixel positions surrounding the integer pixel location.

35. one or more processors; and a computer-readable storage medium communicatively coupled to the one or more processors, the computer-readable storage medium storing computer-readable instructions executable by the one or more processors and that, when executed by the one or more processors, perform the computing method of any one of claims 1 to 17.

36. 18. A non-transitory computer readable storage medium storing a bitstream associated with one or more images, the bitstream, when computed by a processor, causing the processor to perform the computing method of any one of claims 1 to 17.

37. A computer program product comprising computer program instructions, said computer program instructions enabling a computer to carry out the computing method of any one of claims 1 to 17.

38. A computer program enabling a computer to carry out the computing method according to any one of claims 1 to 17.

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