Method and apparatus for improving differential amplifiers

Abstract

The illustrated device is a differential amplifier (220) having an inverting input (-) coupled to a first input (208) through a first resistor (216), a non-inverting input (+) coupled to a second input (204) through a second resistor (212), and a first supply input (V) coupled to the first input through a third resistor (228) and to the second input through a fourth resistor (224). REF1 ) and a second supply input (V REF2 ), a differential amplifier including a non-inverting output (+) and an inverting output (-), a first transistor (256) including a first control terminal coupled to the non-inverting output and a first current terminal coupled to the inverting input, and a second transistor (248) including a second control terminal coupled to the inverting output and a second current terminal coupled to the non-inverting input.

Description

[Technical Field]

[0001] This application relates generally to differential amplifiers, and more particularly to methods and apparatus for improving differential amplifiers. [Background technology]

[0002] In-line current sensing is typically accomplished by determining a voltage difference across a resistor placed in the circuit element where the current measurement is performed. The controller circuit element divides the voltage difference across the resistor by the resistance of the resistor to determine the current flowing through the resistor. For example, in-line current sensing includes a resistor having a relatively small resistance and a differential amplifier. The differential amplifier is coupled to the relatively small resistor by a first reference input and a second reference input. The differential amplifier converts the voltage difference across the relatively small resistor from a differential voltage at a common-mode voltage to a single-ended voltage referenced to a common potential (e.g., ground). For example, if the first reference input is 60.005 volts (V), the second reference input is 60 volts (V), and the differential amplifier is configured to amplify the output with a gain of 1, the output of the differential amplifier is 5 millivolts (mV). In such an example, the controller circuitry may apply Ohm's Law to calculate that the current through the relatively small resistor is 5 amps (A) when the resistance of the relatively small resistor is 1 milliohm (mΩ). Summary of the Invention

[0003] Regarding a method and apparatus for reducing common-mode rejection in a differential amplifier, an exemplary apparatus includes a differential amplifier including an inverting input coupled to a first input through a first resistor, a non-inverting input coupled to a second input through a second resistor, a first supply input coupled to the first input through a third resistor and to the second input through a fourth resistor, a second supply input coupled to a current source, a non-inverting output, and an inverting output, a first transistor including a first control terminal and a first current terminal, and a second transistor including a second control terminal and a second current terminal, wherein the first control terminal is coupled to the non-inverting output, the first current terminal is coupled to the inverting input, the second control terminal is coupled to the inverting output, and the second current terminal is coupled to the non-inverting input. [Brief explanation of the drawings]

[0004] [Figure 1] FIG. 1 is a schematic diagram of an example motor driver configured to power an example motor based on a voltage output of an example differential amplifier.

[0005] [Figure 2] 2 is a schematic diagram of the differential amplifier of FIG. 1, including an input stage and a differential-to-single-ended converter stage.

[0006] [Figure 3] 1 is a cross-sectional view of an example portion of a semiconductor device including an n-type buried layer configured to form an internal capacitance.

[0007] [Figure 4] 4 is a voltage versus time graph illustrating an example operation of the differential amplifier of FIGS. 1 and 2 including the n-type buried layer of FIG. 3 configured to reduce disturbances to the voltage output of the differential amplifier following a sudden change in common mode voltage.

[0008] [Figure 5]3 is an illustrative magnitude versus time graph illustrating an example operation of the differential amplifier of FIGS. 1 and 2 configured to reduce variations in offset voltage as the common mode voltage changes.

[0009] [Figure 6] 3 is a flowchart illustrating example operations that may be performed to configure the common mode range of the differential amplifier of FIGS. 1 and 2.

[0010] Use of the same reference numbers or other reference designators in the drawings indicates the same or similar (functional and / or structural) features. DETAILED DESCRIPTION OF THE INVENTION

[0011] The drawings are not necessarily drawn to scale. While the drawings show layers with clear lines and boundaries, some or all of these lines and / or boundaries may be idealized. In reality, boundaries and / or lines may not be observable, may be blended, and / or may be irregular.

[0012] Applications requiring current measurement may include a series resistor at the location where the current is measured. For example, a series resistor (also referred to as an "in-line" resistor) may be incorporated into the supply path to a motor so that the current supplied to the motor from the supply source can be measured. Such applications measure the voltage difference across the resistor to determine the current flowing through the resistor. For example, Ohm's Law allows an application to calculate the current flowing through a resistor by dividing the voltage drop across the resistor by the resistor's resistance. Such a current sensing method is sometimes referred to as "in-line current sensing." One exemplary implementation of in-line current sensing includes a resistor (e.g., having a relatively small resistance) and a differential amplifier. The relatively small resistor is placed between two points where the current is measured. The relatively small resistor has a resistance that is configured to be relatively small, thereby reducing any voltage difference resulting from the addition of the resistance.

[0013] The differential amplifier includes a first reference input and a second reference input coupled to a relatively small resistor. In some examples, the differential amplifier has a configurable gain, so that a voltage difference can be amplified by the configured gain. The differential amplifier generates an output voltage approximately equal to the voltage difference between the first reference input and the second reference input multiplied by the gain. For example, if the first reference input is 20 volts (V), the second reference input is 15 volts (V), and the differential amplifier has a gain of 2, the output voltage of the differential amplifier is 10 volts (V).

[0014] The differential amplifier is configured to reject common-mode voltages from the reference inputs. The common-mode voltage is an offset voltage common to both reference inputs. For example, a differential amplifier with a first reference input coupled to 60 volts (V) and a second reference input coupled to 65 volts (V) rejects common-mode voltages of approximately 60 volts (V). The differential amplifier can accurately determine the voltage difference between the reference inputs if both reference inputs are within the common-mode range of the differential amplifier. The common-mode range of a differential amplifier is the range of potentials (voltages) that can be coupled to the reference inputs. For example, a differential amplifier with a common-mode range of minus 16 volts (V) (-16V) to plus 80 volts (V) (+80V) can couple the reference input to any voltage between minus 16 volts (V) and plus 80 volts (V). In some applications, such as manufacturing and automotive, differential amplifiers with a relatively large common-mode range are required to perform in-line current sensing. One way to increase the common-mode range of a differential amplifier is to increase the voltage supply. However, increasing the voltage supply to the differential amplifier increases cost and complexity.

[0015] Some differential amplifiers have relatively large common-mode voltages with relatively small common-mode rejection ratios (CMRRs). CMRR is the ratio of the change in voltage difference at the reference input to a change in common-mode voltage. CMRR characterizes the ratio of the gain resulting from a change in common mode to the gain resulting from a change in differential voltage at the reference input. For example, a differential amplifier may generate a voltage output of approximately zero volts (V) when both reference inputs are coupled to a common potential (e.g., ground), but generate a voltage output of 100 millivolts (mV) when both reference inputs are coupled to 100 volts (V). A relatively small CMRR indicates that the offset error associated with the voltage output increases as the common-mode voltage increases. A differential amplifier is accurate over a wide range of common-mode voltages if it has a relatively high CMRR. In applications such as current sensing, a relatively small CMRR reduces the accuracy of the voltage measurement represented by the output of the differential amplifier. One way to minimize inaccuracies resulting from a relatively low CMRR while maintaining a relatively high common-mode range is to include trim circuitry configured to modify circuitry including the differential amplifier to reduce gain resulting from common-mode variations, although such methods increase the size and complexity of the system-on-chip (SoC).

[0016] Examples described herein include exemplary differential amplifiers configured to support a relatively wide common-mode range, achieve wide bandwidth, and achieve a relatively small voltage offset for the voltage output. In some described examples, the differential amplifier includes input stage circuitry and a differential-to-single-ended converter stage. The input stage circuitry uses a single amplifier and transistors to convert a differential voltage from a first reference input and a second reference input into a differential current to implement current feedback. The differential current is converted by the differential-to-single-ended converter stage into a voltage output representing the voltage difference between the reference inputs relative to a common potential.

[0017] In some of the described examples, the input stage includes a fully differential amplifier and current feedback, thereby creating a closed-loop system that converts a voltage differential input to a differential current output. The fully differential amplifier uses the reference input as a voltage source, allowing a single amplifier to support both negative and positive voltages in the common-mode range. In some described examples, an n-type buried layer (also referred to as an "n-buried layer") is placed between the buried oxide and p-type region of the semiconductor device of the fully differential amplifier to reduce settling time following relatively large common-mode transients.

[0018] 1 is a schematic diagram of an example motor driver 100 configured to provide power to an example motor 110. In the example of FIG. 1, motor driver 100 includes example controller circuitry 120, a first example transistor 130, a second example transistor 140, an example resistor 150, and an example difference amplifier 160. Motor driver 100 provides power to motor 110 based on the duration that controller circuitry 120 turns on transistors 130 and / or 140. Motor driver 100 uses resistor 150 and difference amplifier 160 to calculate the current provided to motor 110.

[0019] 1, controller circuitry 120 is coupled to a first transistor 130, a second transistor 140, and a differential amplifier 160. Controller circuitry 120 provides power to motor 110 by controlling transistors 130 and 140. Controller circuitry 120 varies the amount of power provided to motor 110 by varying the duration that transistors 130 and / or 140 are turned on (e.g., conducting) or off (e.g., non-conducting). Controller circuitry 120 controls the voltage output (V DIFF ) to the resistance of resistor 150 (R S) to determine the magnitude of the current supplied to motor 110. For example, if the voltage output of differential amplifier 160 is 1 millivolt (mV) and the resistance of resistor 150 is 10 milliohms (mΩ), the calculated current flowing through resistor 150 is 100 milliamps (mA).

[0020] The first transistor 130 is coupled to the controller circuitry 120, the second transistor 140, the resistor 150, and a first reference potential (VDD). When turned on by the controller circuitry 120, the first transistor 130 can pass current from the first reference potential toward the resistor 1cc50, and when turned off by the controller circuitry 120, the first transistor 130 prevents current from passing from the first reference potential toward the resistor 150 and / or the second transistor 140. The first transistor 130 is a p-channel metal-oxide-semiconductor field-effect transistor (MOSFET). Alternatively, the first transistor 130 may be a PNP bipolar junction transistor (BJT), an n-channel field-effect transistor (FET), an n-channel insulated-gate bipolar transistor (IGBT), an n-channel junction field-effect transistor (JFET), an n-channel MOSFET, a p-channel IGBT, a p-channel JFET, or an NPN BJT.

[0021] The second transistor 140 is coupled to the controller circuitry 120, the first transistor 130, the resistor 150, and a second reference potential (VSS) (e.g., a common potential such as ground). When turned on by the controller circuitry 120, the second transistor 140 can pass current from the resistor 150 toward the second reference potential, and when turned off by the controller circuitry 120, the second transistor 140 prevents current from passing through the first transistor 130 and / or the resistor 150. The second transistor 140 is an n-channel MOSFET. Alternatively, the second transistor 140 may be a PNP BJT, an n-channel FET, an n-channel IGBT, an n-channel JFET, a p-channel MOSFET, a p-channel FET, a p-channel IGBT, a p-channel JFET, or an NPN BJT.

[0022] The resistor 150 is coupled to the motor 110, the first transistor 130, the second transistor 140, and the differential amplifier 160. The resistor 150 has a resistance (R S ) The current flowing through resistor 150 can be calculated by applying Ohm's law, such as dividing the voltage difference across resistor 150 by the resistance.

[0023] The differential amplifier 160 is coupled to the motor 110, the controller circuitry 120, the first transistor 130, the second transistor 140, and the resistor 150. In the example of FIG. 1 , the differential amplifier 160 includes an exemplary input stage 170 and an exemplary differential-to-single-ended stage 180. The differential amplifier 160 converts the voltage difference across the resistor 150 into a voltage output (V DIFF )

[0024] The input stage 170 receives a first reference input (V IN+ ) to the first transistor 130, the second transistor 140, and the resistor 150. The input stage 170 has a second reference input (V IN- ) to motor 110 and resistor 150. Input stage 170 converts the differential voltage of the first and second reference inputs into a differential current. Input stage 170 is sometimes referred to as a "transconductance stage." Input stage 170 includes circuit elements configured to increase the common-mode range, increase the CMRR, reduce the voltage offset, and reduce the settling time of differential amplifier 160. An exemplary implementation of input stage 170 is described below in conjunction with FIG. 2. Input stage 170 provides the differential current to differential-to-single-ended stage 180.

[0025] The differential-to-single-ended stage 180 is coupled to the controller circuitry 120 and the input stage 170. The differential-to-single-ended stage 180 converts the differential current from the input stage 170 into a single-ended voltage that is referenced to a common potential (e.g., ground) at a first reference input (V IN+ ) and the second reference input (V IN-) (e.g., across resistor 150). Differential-to-single-ended stage 180 is sometimes referred to as a "transimpedance stage." An example implementation of differential-to-single-ended stage 180 is described below with reference to FIG. 2. Differential-to-single-ended stage 180 provides an output voltage to controller circuitry 120.

[0026] 2 is a schematic diagram of the differential amplifier 160 of FIG. 1, including the input stage 170 of FIG. 1 and the differential-to-single-ended stage 180 of FIG. 1. The differential amplifier 160 provides a voltage output (V DIFF ) 200, the gain of the amplifier is connected to the first reference input (V IN+ ) 204 and the second reference input (V IN- ) 208. Reference inputs 204 and 208 are sometimes referred to as reference terminals, such as a first reference terminal and a second reference terminal. Input stage 170 increases the common-mode range of differential amplifier 160 using a feedback loop that forces circuit elements (such as input stage 170) to track the common mode of reference inputs 204 and 208. Input stage 170 improves the accuracy of differential amplifier 160 by increasing CMRR and reducing offset voltage using current feedback. Differential-to-single-ended stage 180 converts the differential current output of input stage 170 to a single-ended voltage so that the voltage difference between voltage output 200 and a common potential (e.g., ground) is approximately equal to the voltage difference between reference inputs 204 and 208.

[0027] 2 , input stage 170 includes first example resistor 212, second example resistor 216, example fully differential amplifier 220, third example resistor 224, fourth example resistor 228, first example transistor 232, example current source 236, example voltage source 240, example charge pump 244, second example transistor 248, third example transistor 252, fourth example transistor 256, and fifth example transistor 260. Input stage 170 is coupled to differential-to-single-ended stage 180 and reference inputs 204 and 208. Reference inputs 204 and 208 are operable to be coupled to resistors 212 and 216. Input stage 170 generates a differential current based on a voltage difference between reference inputs 204 and 208. Input stage 170 provides the differential current to differential-to-single-ended stage 180.

[0028] The first resistor 212 is coupled to the first reference input 204, the fully differential amplifier 220, the third resistor 224, and the second transistor 248. The first resistor 212 has a first resistance (R1). The first resistor 212 allows the second transistor 248 to source a current from the first reference input 204. The first resistor 212 supplies the fully differential amplifier 220 with a voltage equal to the first reference input 204 minus a voltage difference (e.g., a voltage drop) across the resistor 212. The voltage difference across the first resistor 212 is equal to the first resistance multiplied by the magnitude of the current sourced by the second transistor 248. For example, if the first resistor is 1 kiloohm (kΩ) and the second transistor 248 is sourcing 1 milliamp (mA), the first resistor 212 will supply a voltage to the fully differential amplifier 220 equal to the first reference input 204 minus 1 volt (V).

[0029] The second resistor 216 is coupled to the second reference input 208, the fully differential amplifier 220, the fourth resistor 228, and the fourth transistor 256. The second resistor 216 has a resistance equal to the first resistance of the first resistor 212. The second resistor 216 allows the fourth transistor 256 to source a current from the second reference input 208. The second resistor 216 provides the fully differential amplifier 220 with a voltage equal to the second reference input 208 minus the voltage difference across the second resistor 216. The voltage difference across the second resistor 216 is equal to the first resistance multiplied by the magnitude of the current that the fourth transistor 256 is sourcing. For example, if the first resistor is 1 kiloohm (kΩ) and the fourth transistor 256 is sourcing 1 milliamp (mA), the second resistor 216 will supply a voltage to the fully differential amplifier 220 equal to the second reference input 208 minus 1 volt (V).

[0030] The fully differential amplifier 220 is coupled at its non-inverting input (+) to a first resistor 212. The fully differential amplifier 220 is coupled at its inverting input (-) to a second resistor 216. The fully differential amplifier 220 is coupled at its first source input (V REF1 ) to resistors 224 and 228. The fully differential amplifier 220 has a second source input (V REF2) to transistors 232, 252, and 260. The source inputs of fully differential amplifier 220 are sometimes referred to as supply inputs, such as a first supply input and a second supply input. Fully differential amplifier 220 includes internal circuitry (not shown) that creates an internal feedback loop that regulates the voltage difference between the first and second source inputs. For example, fully differential amplifier 220 may include circuitry for regulating a 2.5 volt (V) difference between the first and second source inputs. The regulated voltage difference between the source inputs allows fully differential amplifier 220 to track the common-mode voltage of reference inputs 204 and 208. The regulated voltage difference allows fully differential amplifier 220 to adjust for variations in the common mode of the reference input. A differential amplifier that uses the common mode of its inverting and non-inverting inputs to adjust its supply inputs is sometimes referred to as a "floating differential amplifier."

[0031] The fully differential amplifier 220 can be fabricated to reduce common-mode transient step disturbances by adding an n-buried layer between the buried oxide layer and the p-doped layer (e.g., as shown in FIG. 3). Common-mode transient step disturbances occur when the voltage output 200 fluctuates in response to an abrupt change in the common-mode voltage of the reference inputs 204 and 208 (e.g., a rising or falling edge of a pulse-width modulated signal). In the example of FIG. 2, a common-mode transient step disturbance can occur when an abrupt change in the common mode of the reference input alters the regulated potential difference between the source inputs. The n-buried layer coupled to the first source input can isolate the second source input, which is coupled to the p-doped region, from a common potential (e.g., ground).

[0032] In some implementations, a p-doped layer is adjacent to the buried oxide and coupled to the second source input, thereby creating an internal capacitance between the second source input and a reference coupled to the substrate layer. Such internal capacitance between the second source input and the reference coupled to the substrate layer causes fluctuations in the second source input rather than the first source input. The addition of the n-buried layer creates an internal capacitance between the first source input and the reference coupled to the substrate layer, thereby isolating the p-doped region from creating capacitance with the substrate layer. This isolation by the n-buried layer reduces disruptions to the regulated potential difference caused by sudden fluctuations in the potential difference of the source input.

[0033] An example semiconductor device including the addition of an n-buried layer is illustrated in connection with Figure 3 and described in more detail below. Advantageously, the n-buried layer creates a capacitance between the first source input and the substrate layer that can cause the second source input to swing along with the first source input during relatively large swings in the common-mode voltage of the reference inputs 204 and 208.

[0034] The fully differential amplifier 220 is coupled at its inverting output (−) to a second transistor 248. The fully differential amplifier 220 is coupled at its non-inverting output (+) to a fourth transistor 256. The inverting and non-inverting outputs of the fully differential amplifier 220 comprise a differential output. A fully differential amplifier is an amplifier with differential inputs and outputs, such as inverting and non-inverting inputs, or inverting and non-inverting outputs. The fully differential amplifier 220 controls the transistors 248 and 256 based on the voltages provided to the non-inverting and inverting inputs by resistors 212 and 216. By turning on transistors 248 and / or 256, the fully differential amplifier 220 configures the voltages at the non-inverting and inverting inputs to be approximately equal to one another, so that, for example, the transistors 248 and 256 can source current from the resistors 212 and 216. This configuration is a method of current feedback.

[0035] In such a configuration, fully differential amplifier 220 sources different amounts of current to transistors 248 and 256 via resistors 212 and 216, thereby modifying the voltages at the inverting and non-inverting inputs of fully differential amplifier 220. Fully differential amplifier 220 adjusts the amount of current sourced by transistors 248 and 256 when there is a voltage difference between the inverting and non-inverting inputs, such as when reference inputs 204 and 208 are different. For example, a voltage difference between reference inputs 204 and 208 causes fully differential amplifier 220 to modify the amount of current being sourced by transistors 248 and 256. In such an example, first resistor 212 reduces the voltage at the non-inverting input of fully differential amplifier 220 by a first voltage, and second resistor 216 reduces the voltage at the inverting input of fully differential amplifier 220 by a second voltage.

[0036] The fully differential amplifier 220 is considered to be in a settled state when the first voltage and the second voltage set the non-inverting and inverting inputs of the fully differential amplifier 220 approximately equal to one another. Advantageously, a current feedback loop is created by modifying transistors 248 and 256 to source modified amounts of current to set the inverting and non-inverting inputs equal to one another. Advantageously, the current feedback loop of input stage 170 allows the fully differential amplifier to adjust for a wide range of voltages supplied to the reference inputs 204 and 208.

[0037] The voltage difference induced across resistors 212 and 216 by turning on transistors 248 and / or 256 represents the voltage difference between reference inputs 204 and 208. The current flowing through transistors 248 and / or 256 is a differential current that represents the voltage difference between reference inputs 204 and 208. Advantageously, fully differential amplifier 220 uses current feedback from transistors 248 and 256 to induce a voltage difference across resistors 212 and 216 that represents the voltage difference between the reference inputs as a differential current.

[0038] A third resistor 224 is coupled to the first reference input 204, the first resistor 212, and the fully differential amplifier 220. The third resistor 224 allows the first source input of the fully differential amplifier 220 to source current from the first reference input 204. The third resistor 224 facilitates providing a voltage to the first source input of the fully differential amplifier 220 equal to the voltage at the first reference input 204 minus the voltage difference resulting from the current being sourced by the fully differential amplifier 220. The voltage difference across the third resistor 224 is equal to the first resistance times approximately half the magnitude of the current being sourced by the fully differential amplifier 220.

[0039] A fourth resistor 228 is coupled to the second reference input 208, the second resistor 216, and the fully differential amplifier 220. The fourth resistor 228 allows the first source input of the fully differential amplifier 220 to source current from the second reference input. The fourth resistor 228 facilitates providing the first source input of the fully differential amplifier 220 with a voltage equal to the voltage at the second reference input 208 minus the voltage difference resulting from the current being sourced by the fully differential amplifier 220. The voltage difference across the fourth resistor 228 is equal to the first resistance times approximately half the magnitude of the current being sourced by the fully differential amplifier 220.

[0040] The voltage at the first source input of fully differential amplifier 220, resulting from resistors 224 and 228, varies with the common-mode voltage of reference inputs 204 and 208. With this configuration, the source input of fully differential amplifier 220 can be adjusted with respect to the common mode of reference inputs 204 and 208. Thus, by coupling the first source input of fully differential amplifier 220 to reference inputs 204 and 208 by resistors 224 and 228, fully differential amplifier 220 can share the common-mode voltage of reference inputs 204 and 208.

[0041] The drain of the first transistor 232 is coupled to the fully differential amplifier 220 and the transistors 252 and 260. The drain and / or source may be referred to as a current terminal. The source of the first transistor 232 is coupled to a current source 236. The gate of the first transistor 232 is coupled to a voltage source 240. The gate may be referred to as a control terminal or control input. The first transistor 232 sources current to or from the second source input of the fully differential amplifier 220. The first transistor 232 is configured to be always on. The first transistor 232 includes a relatively large impedance at its drain, such that when turned on, a voltage difference may occur between the drain and the source while current may flow from the drain to the source. The transistor 232 may be implemented by a power transistor, a high-voltage transistor, and / or a drain extension transistor. Advantageously, the voltage at the second source input of the fully differential amplifier 220 may be different from the common-mode voltage of the source. The first transistor 232 is an n-channel MOSFET. Alternatively, the first transistor 232 may be a PNP BJT, an n-channel FET, an n-channel IGBT, an n-channel JFET, a p-channel MOSFET, a p-channel FET, a p-channel IGBT, a p-channel JFET, or an NPN BJT.

[0042] Current source 236 is coupled to first transistor 232, voltage source 240, and charge pump 244. Current source 236 provides a set magnitude of current from first transistor 232 to charge pump 244. Current source 236 is configured to sink a bias current from a second source input of fully differential amplifier 220 to charge pump 244. Fully differential amplifier 220 provides the current sunk by current source 236 by increasing the amount of current provided by resistors 224 and 228 from reference inputs 204 and 208. The additional current sourced from reference inputs 204 and 208 through resistors 224 and 228 to supply current source 236 sets the voltage of the first source input of fully differential amplifier 220 relative to the common-mode voltage of reference inputs 204 and 208.

[0043] As the common-mode voltage of reference inputs 204 and 208 varies, the bias current continues to set the voltage of the first source input by creating a potential difference across resistors 224 and 228. For example, as the common-mode voltage of reference inputs 204 and 208 decreases, the bias current of current source 236 causes fully differential amplifier 220 to decrease the voltage of the first source input by continuing to source bias current through resistors 224 and 228. In such an example, the second source input is set to the reduced voltage of the first source input minus a fixed potential difference. The bias current creates an internal feedback loop in fully differential amplifier 220 that creates a fixed potential difference between the source inputs, modifying the voltage of the second source input as the first source input is set by the bias current. Advantageously, current source 236 uses fully differential amplifier 220 to source bias current, ensuring that the fixed potential difference between the source inputs of fully differential amplifier 220 remains fixed while the common mode of reference inputs 204 and 208 varies.

[0044] The current source 240 is coupled to the first transistor 232, the current source 236, and the charge pump 244. The voltage source 240 generates a set potential difference between the charge pump 244 and the gate of the first transistor 232. The set potential difference of the voltage source 240 is configured to turn on the first transistor 232. Advantageously, the voltage source 240 ensures that the first transistor 232 remains on, such as by enabling a potential difference between the second source input of the fully differential amplifier 220 and the charge pump 244.

[0045] Charge pump 244 is coupled to differential-to-single-ended stage 180, current source 236, and voltage source 240. Charge pump 244 may be a direct current (DC)-to-DC converter that may use current to generate a negative voltage. Charge pump 244 uses current from current source 236 and current through resistors 264 and 268 to generate a low common-mode voltage (V REF3) Advantageously, charge pump 244 may ensure that the common-mode range of differential amplifier 160 includes voltages below zero volts (e.g., ground).

[0046] The source of the second transistor 248 is coupled to the first resistor 212 and the fully differential amplifier 220. The drain of the second transistor 248 is connected to the source of the third transistor 252, and the gate of the second transistor 248 is connected to the inverting output of the fully differential amplifier 220. When the second transistor 248 is turned on, it sources current through the first resistor 212. When the second transistor 248 is turned off, it does not source current. The second transistor 248 enables the fully differential amplifier 220 to reduce the voltage at its non-inverting input by turning on the second transistor 248, as described above in connection with the fully differential amplifier 220. The second transistor 248 is a p-channel MOSFET. Alternatively, the second transistor 248 may be a PNP BJT, an n-channel FET, an n-channel IGBT, an n-channel JFET, an n-channel MOSFET, a p-channel FET, a p-channel IGBT, a p-channel JFET, or an NPN BJT.

[0047] The drain of the third transistor 252 is coupled to the differential-to-single-ended stage 180 (specifically, the non-inverting input of the amplifier 272), and the gate of the third transistor 252 is coupled to the fully differential amplifier 220. The third transistor 252 is configured to source current from the second transistor 248 when turned on and not source current when turned off. The third transistor 252 has a relatively large impedance at its drain, such that a voltage difference may occur between the drain and source when turned on, while current may flow from the source to the drain. Such a transistor may be implemented by a power transistor, a high-voltage transistor, and / or a drain extension transistor. The third transistor 252 is a p-channel MOSFET. Alternatively, the third transistor 252 may be a PNP BJT, an n-channel FET, an n-channel IGBT, an n-channel MOSFET, a p-channel FET, a p-channel IGBT, or an NPN BJT.

[0048] A source of the fourth transistor 256 is coupled to the second resistor 216 and the fully differential amplifier 220, and a drain of the fourth transistor 256 is coupled to a fifth transistor 260. A gate of the fourth transistor 256 is coupled to the non-inverting output of the fully differential amplifier 220. The fourth transistor 256 may cause the fully differential amplifier 220 to reduce the voltage at the inverting input by turning on the fourth transistor 256, as described above in connection with the fully differential amplifier 220.

[0049] The source of the fifth transistor 260 is coupled to the drain of the fourth transistor 256, and the drain of the fifth transistor 260 is coupled to the differential-to-single-ended stage 180 (specifically, the inverting input of the amplifier 272). The gate of the fifth transistor 260 is coupled to the fully differential amplifier 220. The fifth transistor 260 is configured to source current from the fourth transistor 256 when turned on. When turned off, the fifth transistor 260 prevents the source input from sourcing current. The fifth transistor 260 has a relatively large impedance at its drain, such that when turned on, a voltage difference may occur between the drain and source while current may flow from the source to the drain. The fifth transistor 260 is a p-channel MOSFET. Alternatively, the fifth transistor 260 may be a PNP BJT, an n-channel FET, an n-channel IGBT, an n-channel JFET, an n-channel MOSFET, a p-channel FET, a p-channel IGBT, a p-channel JFET, or an NPN BJT.

[0050] Advantageously, transistors 252 and 260 provide a differential current output for input stage 170. Advantageously, the differential current output of transistors 252 and 260 may produce a lower voltage at the drains of transistors 252 and 260 than the voltage provided at their sources. Advantageously, the potential voltage difference between the source and drain of transistors 252 and 260 increases the common-mode range of differential amplifier 160. Input stage 170 provides a differential current output to differential-to-single-ended stage 180.

[0051] 2, differential-to-single-ended stage 180 includes a fifth example resistor 264, a sixth example resistor 268, an example amplifier 272, a seventh example resistor 276, and an eighth example resistor 280. Differential-to-single-ended stage 180 generates voltage output 200 by converting the differential current output of input stage 170 to a single-ended voltage for voltage output 200.

[0052] The fifth resistor 264 is coupled to the charge pump 244, the third transistor 252, the amplifier 272, and the seventh resistor 276. The fifth resistor 264 has a second resistance (R2). The fifth resistor 264 generates a voltage drop equal to the resistance of the fifth resistor 264 multiplied by the current sourced by the third transistor 252, thereby providing a first intermediate voltage output (V OUT+ ) is configured to generate.

[0053] The sixth resistor 268 is coupled to the charge pump 244, the fifth transistor 260, the amplifier 272, and the eighth resistor 280. The sixth resistor 268 has a resistance equal to the resistance of the fifth resistor 264. The sixth resistor 268 generates a voltage drop equal to the resistance of the sixth resistor 268 multiplied by the current sourced by the fifth transistor 260, thereby providing a second intermediate voltage output (V OUT- ) is configured to generate.

[0054] The non-inverting input (+) of amplifier 272 is coupled to the drain of third transistor 252, fifth resistor 264, and seventh resistor 276. The inverting input (−) of amplifier 272 is coupled to the drain of fifth transistor 260, sixth resistor 268, and eighth resistor 280. The output of amplifier 272 is coupled to eighth resistor 280 and voltage output 200. Amplifier 272 induces a current through eighth resistor 280 by modifying the voltage of the amplifier output. Amplifier 272 modifies the voltage of the amplifier output to set the voltage of the inverting input equal to the voltage of the non-inverting input. Amplifier 272 sets voltage output 200 based on the amplifier output, which sets the voltages of the inverting and non-inverting inputs of amplifier 272 approximately equal.

[0055] A seventh resistor 276 couples the amplifier 272 to the reference voltage input (V REF4 ) The seventh resistor 276 has a third resistance (R3). Resistors 264 and 276 form a voltage divider that can offset the voltage output 200 by a DC offset.

[0056] An eighth resistor 280 is coupled to the amplifier 272 and the voltage output 200. The eighth resistor 280 is coupled between the inverting input of the amplifier 272 and the amplifier output of the amplifier 272. The eighth resistor 280 has a resistance equal to the resistance of the seventh resistor 276. Advantageously, the eighth resistor 280 enables the closed-loop gain of the amplifier 272. The gain of the difference amplifier 160 is approximately equal to the resistance of the resistors 276 and 280 divided by the resistance of the resistors 212 and 216. Advantageously, the resistors 212, 216, 276, and 280 may be configured to amplify the voltage difference between the reference inputs 204 and 208.

[0057] In some examples, resistors 212 and 268 set the closed-loop gain of amplifier front end 170 .

[0058] To allow the differential amplifier 160 of FIGS. 1 and 2 to support an increased common-mode range, manufacturers may need to fabricate the fully differential amplifier 220 using semiconductor process technology that supports relatively high-voltage circuit components. One exemplary method is referred to as a silicon-on-insulator (SOI) process. The SOI process involves placing an insulating layer, such as a buried oxide, between a substrate and a doped (e.g., p-type) semiconductor layer (e.g., an epitaxial layer, although an epitaxial silicon layer can be used if the substrate is a monocrystalline silicon layer) that surrounds the semiconductor implementation of the circuit elements. The buried oxide isolates the substrate from the p-doped regions, thereby allowing the substrate to be coupled to a common potential (e.g., ground) that is substantially lower than the voltage coupled to the p-doped regions. In some applications, such as the fully differential amplifier 220, a relatively large potential difference can be established between the substrate and the p-doped regions, enabling a relatively wide operating range.

[0059] However, the substrate and p-doped region, using buried oxide as a dielectric material, act as an internal capacitance between the potentials coupled to the p-doped region and the substrate. This internal capacitance results in a long settling time for relatively rapid changes in the voltage coupled to the p-doped region, such as the rising edge of a pulse-width modulation (PWM) signal. In the example of fully differential amplifier 220, this internal capacitance from such an SOI process prevents the voltage at the second source input from changing at the same rate as the first source input. The difference in the speed of the source inputs causes fluctuations in the regulated potential difference, preventing differential amplifier 160 from generating an accurate voltage output 200 until fully differential amplifier 220 settles. As mentioned above, implementations using alternative SOI processes can result in settling times following relatively large voltage transients at reference inputs 204 and 208. In applications such as automotive and manufacturing, where PWM signals are often used to control devices, significant timing issues can arise during in-line current sensing.

[0060] 3 is an illustration of process and / or device structure improvements to an example semiconductor device 300 configured to reduce common-mode transient step disturbances. The example illustrated is a fully differential amplifier 220 of FIG. 2, in which the second source input (V REF2) from a common potential (eg, ground). In the example of FIG. 3 , the semiconductor device 300 includes an example substrate 302, an example buried oxide layer 304, an example n-buried layer 306, a first example p-type layer 308, a second example p-type well 310, a first example terminal 312 (e.g., contacts and overlying first level metal structures), a first example n-doped region 314 (e.g., heavily doped region for forming source / drain regions), a second example terminal 316 (e.g., contacts and overlying first level metal structures), a first example insulator 318 (e.g., including a gate insulating layer, gate sidewalls, and insulating cap on the gate structure), a first example polysilicon region 320 (e.g., a doped polysilicon region used to form a gate, which may or may not be suicided), a second example n-doped region 322 (e.g., heavily doped region for forming source / drain regions), a third example terminal 316 (e.g., contacts and overlying first level metal structures), a second example n-doped region 324 (e.g., heavily doped region for forming source / drain regions), a third example terminal 318 (e.g., including a gate insulating layer, gate sidewalls, and insulating cap on the gate structure), a first example polysilicon region 320 (e.g., a doped polysilicon region used to form a gate, which may or may not be suicided), a second example n-doped region 322 (e.g., heavily doped region for forming source / drain regions), a third example terminal 318 (e.g., including a gate insulating layer, gate sidewalls, and insulating cap on the gate structure), a third example polysilicon region 320 (e.g., a doped polysilicon region used to form a gate, which may or may not be suicided), a fourth example n-doped region 324 (e.g., heavily do 324 (e.g., contacts and overlying first level metal structures), a third example n-doped well 326, a fourth example terminal 328 (e.g., contacts and overlying first level metal structures), a third example p-doped region 330 (e.g., heavily doped region for forming source / drain regions), a fifth example terminal 332 (e.g., contacts and overlying first level metal structures), a second example insulator 334 (e.g., including a gate insulation layer, gate sidewalls, and an insulating cap on the gate structure), a second example polysilicon region 336 (e.g., a doped polysilicon region used to form a gate, which may or may not be suicided), a fourth example p-doped region 338 (e.g., heavily doped region for forming source / drain regions), and a sixth example terminal 340 (e.g., contacts and overlying first level metal structures).

[0061] 3, the semiconductor device 300 includes an n-buried layer 306 between a buried oxide 304 and a first p-doped layer 308. The n-buried layer 306 is connected to a first source input (V REF1) (e.g., VDD), and a first internal capacitance 342 (shown for clarity) may be created between the first source input and a common potential (e.g., ground (GND)) coupled to the substrate layer 302. The n-buried layer 306 also creates a second internal capacitance 344 (shown for clarity) between the n-buried layer 306 and the p-doped regions 308 and 310. The first internal capacitance 342 prevents fluctuations in the regulated potential difference of the fully differential amplifier 220 by resisting relatively large changes in the common-mode voltage on both source inputs of the fully differential amplifier 220, where the regulated potential difference is shown as a regulated source 346 for clarity. Advantageously, the addition of the n-buried layer 306 shortens the settling time of the fully differential amplifier 220 when relatively large common-mode transients are applied to the reference inputs 204 and 208. Advantageously, the n-buried layer 306 reduces common mode transient step disturbances by resisting sudden changes in voltage at the source inputs of the fully differential amplifier 220, preventing fluctuations in the regulated supply 346.

[0062] Substrate layer 302 is coupled to a common potential (e.g., ground). Buried oxide layer 304 is coupled between substrate layer 302 and n-buried layer 306. Buried oxide layer 304 is a dielectric material (e.g., a silicon dioxide layer) configured to electrically insulate n-buried layer 306 from substrate layer 302, resulting in first internal capacitance 342.

[0063] The n-buried layer 306 abuts regions 308, 310, and 326. The n-buried layer 306 is connected to the first source input (V REF1) Layers 302, 304, and 306 create a first internal capacitance 342 configured to be coupled between a first source input of fully differential amplifier 220 and a common potential coupled to substrate layer 302. First internal capacitance 342 reduces the settling time of fully differential amplifier 220 by resisting voltage fluctuations across regulated supply 346 in response to common-mode transients on reference inputs 204 and 208. An exemplary operation of first internal capacitance 342 with respect to a common-mode transient is illustrated in connection with FIG.

[0064] The n-buried layer 306 (and layer 308) may be formed by growing an epitaxial silicon layer on the buried oxide layer 304 (which may be formed as a continuous silicon dioxide layer such as used for SOI, with selective openings filled with doped silicon to form a connection to the substrate 302, or the buried oxide 304 may be selectively grown in areas above the substrate 302) and the exposed portions of the substrate 302. The n-buried layer 306 may be in-situ doped during epitaxial silicon growth or may be doped (e.g., by ion implantation or other doping methods). If the buried layer 306 is in-situ doped with an n-type dopant, then layer 308 may also include an n-type dopant. Thus, a p-type dopant implant is performed in a dose sufficient to make layer 308 p-type. Subsequently, a selective implantation step is performed with a heavier p-type dopant to form region 310, and a heavier n-type dopant is used to form region 326. An insulating region 350 is selectively formed on the upper surface of epitaxial layer 308. The insulating region 350 may be a selectively grown silicon dioxide region and may be used to act as a mask for subsequent dopant implantation and / or silicidation steps.

[0065] A gate structure is formed by forming a thin insulating layer (such as a grown silicon dioxide or oxynitride layer) on layer 308. A polysilicon layer is then formed on the thin insulating layer. After selectively etching the polysilicon and portions of the underlying thin insulating layer, gate sidewalls are formed (e.g., by blanket depositing a silicon dioxide or oxynitride layer and selectively etching that layer). The polysilicon structures are then doped with n-type or p-type dopants (to form structures 320 and 334), and the top surfaces of these structures may be silicided (not shown) to reduce their contact resistance. A capping insulator is formed on structures 320 and 334 to complete the formation of insulators 318 and 334. N-type dopants are selectively implanted into well 310 (using insulating region 350 and insulator 318 as a mask) at a concentration sufficient to form source / drain regions 314 and 322. Similarly, p-type dopants are selectively implanted into well 326 (using insulating region 350 and insulator 334 as a mask) at a concentration sufficient to form source / drain regions 330 and 338. Source / drain regions 314, 322, 330, and 338 may be selectively silicided to reduce their contact resistance. Next, insulating layer 352 is formed over the entire surface. Insulating layer 352 may include multiple layers of insulating material (e.g., silicon dioxide, silicon nitride, silicon oxynitride, doped silicon dioxide, etc.). After openings are formed in insulating layer 352, a conductive material (e.g., one or more layers of tungsten, titanium, tantalum, aluminum, copper, nitrides of any of the above, or mixtures or stacks of any of the above) is deposited in the openings to form conductive contacts. A first metal layer (such as tungsten, titanium, tantalum, aluminum, copper, any of the nitrides mentioned above, or one or more layers of any of the mixtures or stacks mentioned above) is formed (such as by evaporation or sputtering) and selectively removed (such as by etching or chemical-mechanical polishing as used in damascene processes) to form contacts 312, 316, 324, 328, 332, 340 and substrate contacts.

[0066] 3, regions 310, 314, 320, and 322, terminals 312, 316, and 324, and first insulator 318 form an n-channel MOSFET. While one n-channel MOSFET is illustrated in connection with semiconductor device 300, fully differential amplifier 220 may include multiple n-channel MOSFETs with p-doped regions, such as second p-doped region 310, coupled to a second source input of fully differential amplifier 220. n-buried layer 306 and second p-doped region 310 form (at least in part) a second internal capacitance 344. Second internal capacitance 344 is configured to be coupled between the first and second source inputs of fully differential amplifier 220. Internal capacitances 342 and 344 are configured to prevent transients in the common-mode voltage from altering a regulated supply 346 of fully differential amplifier 220. For example, when the control circuitry 120 in FIG. 1 turns on the first transistor 130, the common mode of the differential amplifier 160 may suddenly increase from a common potential to a relatively high voltage. In such an example, the first internal capacitance 342 resists a sudden change in voltage to the first source input of the fully differential amplifier 220, thereby preventing a sudden fluctuation in the second source input by regulating the potential difference. Advantageously, the n-buried layer 306 reduces disturbances across the regulated supply 346 by isolating the first p-doped layer 308 from the substrate 302. Such isolation prevents the first p-doped layer 308 and the substrate 302 from creating a magnitude of internal capacitance that could cause fluctuations in the second source input of the fully differential amplifier 220. In some examples, multiple n-channel MOSFETs may be formed in the well 310 or other wells (such as the well 310) in the layer 308. In some instances, the n-channel MOSFETs may have the same structure, while others may have different structures.

[0067] 3, regions 326, 330, 336, and 338, terminals 328, 332, and 340, and second insulator 334 comprise p-channel MOSFETs. Although one p-channel MOSFET is illustrated in connection with semiconductor device 300, fully differential amplifier 220 includes multiple p-channel MOSFETs with n-doped regions, such as third n-doped region 326, coupled to a first source input of fully differential amplifier 220. In some examples, multiple p-channel MOSFETs may be formed in well 326 or other wells (such as well 326) in layer 308. In some examples, the p-channel MOSFETs may have the same structure, and others may have different structures.

[0068] In the example of FIG. 3 , semiconductor device 300 illustrates a portion of fully differential amplifier 220. A regulated supply 346 is coupled between the source inputs of fully differential amplifier 220. Regulated supply 346 allows fully differential amplifier 220 to continue to use the common mode of reference inputs 204 and 208 as a power source. For example, regulated supply 346 may be configured to provide approximately 2.5 volts (V) to ensure that the second source input of fully differential amplifier 220 is approximately 2.5 volts (V) lower than the first source input. By regulating the second source input to track the first source input, regulated supply 346 reduces the duration that fully differential amplifier 220 is out of its operating region due to variations in the common mode of reference inputs 204 and 208.

[0069] Advantageously, first internal capacitance 342 is created between layers having a potential difference equal to or greater than that of regulated supply 346. First internal capacitance 342 reduces the settling time of fully differential amplifier 220 by reducing the effect of relatively large transients in the common-mode voltage of reference inputs 204 and 208 on regulated supply 346. Advantageously, n-buried layer 306 isolates first p-doped region 308 from the common potential coupled to substrate layer 302. Advantageously, n-buried layer 306 reduces the settling time of differential amplifier 160 of FIGS. 1 and 2 by ensuring that the potential difference across regulated supply 346 remains approximately equal to the designed potential difference during relatively large input transients. An example of the effect of first internal capacitance 342 is illustrated and described hereinafter in connection with FIG. 4.

[0070] FIG. 4 illustrates an example operation of the differential amplifier 160 of FIGS. 1 and 2 including the n-buried layer 306 of FIG. 3 configured to reduce disturbances in the voltage output 200 of FIG. 2 due to relatively large common-mode transients. The example of FIG. 4 includes a first timing diagram 400 (of a regulated voltage 405) to illustrate an example operation of the regulated source 346 of the fully differential amplifier 220 when the n-buried layer 306 is not located between the buried oxide layer 304 and the first p-doped region 308. The regulated voltage 405 represents the effect on the operation of the differential amplifier 160 when the fully differential amplifier is implemented in the configuration of FIG. 2 without the benefit of the n-buried layer 306. The first timing diagram 400 illustrates the disturbances in the regulated source 346 when the common-mode voltage increases and decreases suddenly. Such abrupt changes in common mode may be referred to as transients.

[0071] The example of FIG. 4 includes a second timing diagram 410 to illustrate a regulated voltage 415, which is the regulated potential difference across the regulated source 346, when the fully differential amplifier 220 includes an n-buried layer 306 between the buried oxide layer 304 and the first p-doped region 308, such as to form the first internal capacitance 342 of FIG. 3. The regulated voltage 415 includes much smaller voltage spikes than the voltage 405 due to the addition of the n-buried layer 306 in the implementation of the fully differential amplifier 220. The second timing diagram 410 illustrates disturbances in the example potential difference across the regulated source 346 when the common-mode voltage suddenly increases and decreases. Advantageously, the first p-doped region 308 is isolated from the substrate layer 302 by the addition of the n-buried layer 306, thereby reducing the magnitude of disturbances caused by sudden fluctuations in the common-mode voltage of the reference inputs 204 and 208 of FIG. 2.

[0072] 4 includes a third timing diagram 420 configured to illustrate a common-mode voltage 425 of the reference inputs 204 and 208. Such common-mode voltage 425 represents the common-mode voltage of the reference inputs 204 and 208 powering the fully differential amplifier 220 over an exemplary period of time during which the absolute voltage values ​​of the reference inputs 204 and 208 increase and decrease rapidly.

[0073] At a first time 430, the common-mode voltage 425 increases from a relatively low voltage (approximately −10 volts (V)) to a relatively high voltage (approximately 110 volts (V)). For example, the controller circuitry 120 of FIG. 1 turns on the first transistor 130 and turns off the second transistor 140. The increase in the common-mode voltage 425 at the first time 430 may be referred to as a rising edge. As the common-mode voltage 425 increases at the first time 430, the regulated voltage 405 increases sharply by approximately 1.5 volts (V). The change in the regulated voltage 405 occurs in response to the first source input of the fully differential amplifier 220, which does not have an n-buried layer 306, being coupled to the relatively high common-mode voltage while the second source input resists the relatively high potential of the common-mode voltage 425. During the first time 430, as the common-mode voltage 425 increases, the regulated voltage 415 fluctuates by approximately 300 millivolts (mV). During the first time 430, the first internal capacitance 342 due to the addition of the n-buried layer 306 reduces the voltage increase across the regulated supply 346. Following the first time 430, the regulated voltages 405 and 415 begin to settle as the common-mode voltage 425 remains at a relatively high voltage.

[0074] At the second time 435, the regulated voltage 415 settles to a voltage of the regulated source 346 that is approximately equal to the voltage before the first time 430. At the second time 435, the regulated voltage 405 continues to settle at a voltage higher than the voltage of the regulated source 346 before the first time 430. At the second time 435, the fully differential amplifier 220, including the n buried layer 306, begins to operate in normal operation so that the voltage output 200 of the difference amplifier 160 can be accurate.

[0075] At a third time 440, the regulated voltage 405 settles to the voltage of the regulated source 346, which is approximately equal to the voltage before the first time 430. At the third time 440, the fully differential amplifier without the n-buried layer (in the configuration of the differential amplifier 160) begins to operate in normal operation, resulting in an accurate voltage output 200. Advantageously, the isolation of the substrate layer 302 and the first p-doped region 308 by the n-buried layer 306 reduces the time between the sudden increase in the common-mode voltage 425 and the differential amplifier 160 providing an accurate voltage for the voltage output 200.

[0076] At a fourth time 445, the common-mode voltage 425 decreases from a relatively high voltage (approximately +110 volts (V)) to a relatively low voltage (approximately −10 volts (V)). For example, the controller circuitry 120 turns off the first transistor 130 and turns on the second transistor 140. The decrease in the common-mode voltage 425 at the fourth time 445 may be referred to as a falling edge. As the common-mode voltage 425 decreases at the fourth time 445, the regulated voltage 405 rapidly decreases by approximately 3 volts (V). The change in the regulated voltage 405 occurs in response to the first source input of the fully differential amplifier 220, which does not have an n-buried layer 306, being coupled to a relatively low common-mode voltage while the second source input resists the relatively low potential of the common-mode voltage 425. During the fourth time 445, the regulated voltage 415 fluctuates by approximately 100 millivolts (mV) as the common-mode voltage 425 decreases. During the fourth time 445, the first internal capacitance 342 due to the addition of the n-buried layer 306 resists and reduces the voltage decrease across the regulated supply 346. Following the fourth time 445, the regulated voltages 405 and 415 begin to settle as the common-mode voltage 425 remains a relatively low voltage.

[0077] At a fifth time 450, the regulated voltage 415 settles to the voltage of the regulated source 346, which is approximately equal to the voltage between times 435 and 445. At the fifth time 450, the regulated voltage 405 continues to settle at a voltage lower than the voltage of the regulated source 346 between times 440 and 445. At the fifth time 450, the fully differential amplifier 220, including the n buried layer 306, begins to operate in normal operation so that the voltage output 200 of the difference amplifier 160 can be accurate.

[0078] At a sixth time 455, the regulated voltage 405 settles to the voltage of the regulated source 346, which is approximately equal to the voltage between times 440 and 445. At the sixth time 455, the fully differential amplifier without the n-buried layer 306 begins to operate normally in the configuration of the difference amplifier 160, so that the voltage output 200 can be accurate. Advantageously, by isolating the substrate layer 302 from the first p-doped region 308 with the n-buried layer 306, the time between the sudden increase in the common-mode voltage 425 and when the difference amplifier 160 provides the correct voltage for the voltage output 200 is reduced.

[0079] 5 illustrates an example operation of the differential amplifier 160 of FIGS. 1 and 2 including the n-buried layer 306 of FIG. 3, illustrating the variation in offset as the common-mode voltage changes. The example of FIG. 5 includes a first timing diagram 500 configured to illustrate an example input current 510 over time. The input current 510 is the current supplied to the differential amplifier 160 at the reference inputs 204 and 208 of FIG. 2.

[0080] The example of Figure 5 includes a second timing diagram 520 to illustrate an example common-mode voltage 530 over time. The common-mode voltage 530 represents the common-mode voltage at the reference inputs 204 and 208. The example of Figure 5 includes a third timing diagram 540 to illustrate an example output voltage 550 over time. The output voltage 550 represents the voltage output 200 of Figure 2.

[0081] At a first time 560, the common-mode voltage 530 begins to decrease from approximately 110 volts (V). The decrease in common-mode voltage 530 causes the output voltage 550 to fluctuate in response to the fully differential amplifier 220 using the common mode of the reference inputs 204 and 208 as a power source. Advantageously, the current feedback of the fully differential amplifier 220 allows the fluctuation in the output voltage 550 to settle to approximately the same voltage as before the fluctuation at the first time 560, such as to prevent an offset voltage on the voltage output 200.

[0082] At a second time 570, the common-mode voltage 530 settles to approximately minus 5 volts (V). Between times 560 and 570, the common-mode voltage 530 decreases from approximately 110 volts (V) to approximately minus 5 volts (V). An example of a single-amplifier differential amplifier with voltage feedback creates an offset voltage on the output voltage 550, which reduces the CMRR and, consequently, accuracy as the common mode of the input increases. A relatively low CMRR reduces the accuracy of the differential amplifier and can limit the common-mode range of some differential amplifiers. However, the differential amplifier 160 uses current feedback in the fully differential amplifier 220 to reduce the voltage offset on the output voltage 550, thereby increasing the CMRR and resulting in a relatively large common-mode range over which the voltage output 200 is accurate. Advantageously, input stage 170 of FIGS. 1 and 2 implements current feedback using transistors 248 and 256 of FIG. 2 to increase CMRR and reduce offset voltage from approximately 110 volts (V) to approximately minus 5 volts (V).

[0083] At a third time 580, the common-mode voltage 530 increases from approximately minus 5 volts (V) at the second time 570 to approximately zero volts, which may be referred to as a common potential (e.g., ground). Advantageously, the input current 510 and the output voltage 550 remain substantially unchanged in response to the increase in common-mode voltage 530 between times 570 and 580.

[0084] 6 is a flow chart illustrating an example method of operation 600 that may be performed to configure the common-mode range of the differential amplifier 160 of FIGS. 1 and 2. The method of operation 600 may be implemented and / or performed by a designer, manufacturer, processor circuitry, etc. The method of operation 600 of FIG. 6 begins at block 620. In block 620, the source input (V REF1 and V REF2 ) is selected. As discussed above in connection with FIG. 2 and fully differential amplifier 220, the regulated potential difference is a characteristic of fully differential amplifier 220. Specifically, the regulated potential difference results from a feedback loop internal to fully differential amplifier 220. Method of operation 600 proceeds to block 640.

[0085] In block 640, drain extension transistors that include a desired maximum voltage difference are selected. For example, transistors 232, 252, and 260 in FIG. 2 are selected to be drain extension transistors designed to allow a maximum voltage difference of approximately 120 volts (V) between their sources and drains. The maximum voltage difference is a characteristic of transistors 232, 252, and 260 and may be related to their internal impedances. The voltage difference between the drain and source of transistors 232, 252, and 260 sets the common-mode range of differential amplifier 160. For example, a maximum voltage difference of 120 volts (V) may allow the source of first transistor 232 to be coupled to a voltage that is 120 volts (V) lower than the voltage coupled to the drain of first transistor 232. Advantageously, increasing the maximum voltage difference of the drain extension transistors increases the common-mode range of the differential amplifier. Operational method 600 proceeds to block 660.

[0086] In block 660, the charge pump 244 of Figure 2 is configured to a negative potential. The negative potential generated by the charge pump 244 is the minimum common-mode voltage that can be represented by the differential amplifier 160. However, the potential difference across the current source 236 of Figure 2 may increase the minimum common-mode voltage that can be represented by the differential amplifier 160. The operational method 600 proceeds to end.

[0087] The common-mode range of the differential amplifier 160 is limited to a minimum common-mode voltage (V) approximately equal to the voltage produced by the charge pump 244 plus the voltage difference across the current source 236. MIN The common-mode range of the differential amplifier 160 has a maximum common-mode voltage (V ) that is approximately equal to the minimum common-mode voltage plus the maximum potential difference between the drain extension transistors (such as transistors 232, 252, and 260) and the fixed potential difference at the source inputs of the fully differential amplifier 220. MAX ) Advantageously, the common-mode range of the differential amplifier 160 can be increased by selecting drain extension transistors with a relatively large maximum voltage difference between their drains and sources.

[0088] Although an example method has been described with reference to the flowchart illustrated in Figure 6, many other methods of setting the common-mode range of differential amplifier 160 may alternatively be used in this description. For example, the order of execution of these blocks may be changed, and / or some of the described blocks may be modified, eliminated, or combined. Similarly, additional operations may be included in the manufacturing process before, between, or after the blocks shown in the illustrated example.

[0089] In this description, the term "and / or" (when used in the form A, B, and / or C, etc.) refers to any combination or subset of A, B, and C. For example, (a) A only, (b) B only, (c) C only, (d) A with B, (e) A with C, (f) B with C, (g) A with B and C, etc. Also, as used herein, the phrase "at least one of A or B" (or "at least one of A and B") refers to an implementation that includes any of (a) at least one A, (b) at least one B, and (c) at least one A and at least one B.

[0090] The term "coupled" is used throughout this specification. This term may encompass a connection, communication, or signal path that enables a functional relationship consistent with this description. For example, in a first example, device A is coupled to device B when device A provides a signal to control device B to perform a certain action, or in a second example, device A is coupled to device B via an intervening component C such that device B is controlled by device A via a control signal provided by device A, where intervening component C does not substantially change the functional relationship between device A and device B.

[0091] A device that is "configured" to perform a task or function may be configured (e.g., programmed and / or hardwired) to perform that function by a manufacturer at the time of manufacture and / or may be configurable (or reconfigurable) by a user after manufacture to perform that function and / or other additional or alternative functions. Such configuration may be achieved by firmware and / or software programming of the device, by the construction and / or layout of the hardware components and interconnections of the device, or by a combination thereof.

[0092] As used herein, the terms "terminal," "node," "interconnect," "pin," and "lead" are used interchangeably and, unless otherwise noted, are used generally to refer to an interconnection between, or termination of, a device element, circuit element, integrated circuit, device, or other electronic or semiconductor component.

[0093] A circuit or device described herein as including certain components may instead be adapted to be coupled to those components to form the described circuit element or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more sources (such as voltage and / or current sources) may instead include only the semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package) and may be adapted to be coupled to at least some of the passive elements and / or sources to form the described structure, either during or after manufacture, for example, by an end user and / or a third party.

[0094] Although particular transistors are described herein, other transistors (or equivalent devices) may be used instead with little or no modification to the remaining circuit elements. For example, metal-oxide-silicon FETs ("MOSFETs") (e.g., n-channel MOSFETs, nMOSFETs, or p-channel MOSFETs, pMOSFETs), bipolar junction transistors (BJTs, e.g., NPN or PNP), insulated-gate bipolar transistors (IGBTs), and / or junction field-effect transistors (JFETs) may be used in place of or in combination with the devices described herein. The transistors may be depletion-mode devices, drain-extension devices, enhancement-mode devices, natural transistors, or other types of device structures. Additionally, the devices may be implemented in / on silicon substrates (Si), silicon carbide substrates (SiC), gallium nitride substrates (GaN), or gallium arsenide substrates (GaAs).

[0095] Circuits described herein are reconfigurable to include replaced components that provide functionality at least partially similar to that available prior to the component replacement. Components illustrated as resistors, unless otherwise noted, generally represent any one or more elements coupled in series and / or parallel to provide the amount of impedance represented by the illustrated resistor. For example, a resistor or capacitor illustrated and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in parallel between the same nodes. For example, a resistor or capacitor illustrated and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in series between the same two nodes as a single resistor or capacitor. While some elements of the illustrated examples may be included in an integrated circuit and other elements may be external to the integrated circuit, in other examples, additional or fewer features may be incorporated into the integrated circuit. Also, some or all of the features illustrated as being external to the integrated circuit may be included within the integrated circuit, and / or some of the features illustrated as being internal to the integrated circuit may be incorporated external to the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits (1) integrated within / on a semiconductor substrate, (2) integrated within a single semiconductor package, (3) integrated within the same module, and / or (4) integrated within / on the same printed circuit board.

[0096] Use of the term "ground" in the above description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection applicable or appropriate to the teachings of the present description. Unless otherwise specified, "about," "approximately," or "substantially" preceding a value means ±10 percent of the stated value, or, if the value is zero, a reasonable range of values ​​around zero.

[0097] Modifications in the described embodiments are possible and other embodiments are possible within the scope of the claims.

Claims

1. 1. An apparatus comprising: a differential amplifier; a first transistor including a first control terminal and a first current terminal; a second transistor including a second control terminal and a second current terminal; Including, The differential amplifier an inverting input coupled to the first input through a first resistor; a non-inverting input coupled to the second input through a second resistor; a first supply input coupled to the first input through a third resistor and to the second input through a fourth resistor; a second supply input coupled to the current source; a non-inverting output; Inverted output, Including, the first control terminal of the first transistor is coupled to the non-inverting output and the first current terminal is coupled to the inverting input; the second control terminal of the second transistor is coupled to the inverting output and the second current terminal is coupled to the non-inverting input; Device.

2. 2. The apparatus of claim 1, wherein the first transistor further comprises a third current terminal and the second transistor further comprises a fourth current terminal; The apparatus further comprises: a third transistor including a third control terminal and a fifth current terminal, the third control terminal coupled to the second supply input and the fifth current terminal coupled to the third current terminal; a fourth transistor including a fourth control terminal and a sixth current terminal, the fourth control terminal coupled to the second supply input and the sixth current terminal coupled to the fourth current terminal; 1. An apparatus comprising:

3. 2. The apparatus of claim 1, wherein the first transistor further comprises a third current terminal and the second transistor further comprises a fourth current terminal; The apparatus further comprises: a charge pump; a fifth resistor configured to be coupled between the third current terminal and the charge pump; a sixth resistor configured to be coupled between the fourth current terminal and the charge pump; 1. An apparatus comprising:

4. 2. The apparatus of claim 1, further comprising a third transistor including a third current terminal and a fourth current terminal, the third current terminal coupled to the second supply input and the fourth current terminal coupled to the current source.

5. 10. The apparatus of claim 1, The differential amplifier further comprises: a substrate layer; an n-type buried layer coupled to the first supply input; a buried oxide layer coupled between the substrate layer and the n-type buried layer; 1. An apparatus comprising:

6. 6. The apparatus of claim 5, wherein the n-type buried layer is configured to be coupled to the first supply input.

7. 2. The apparatus of claim 1, wherein the differential amplifier is a first differential amplifier, the first transistor further includes a third current terminal, the second transistor further includes a fourth current terminal, and the apparatus further includes a second differential amplifier configured to be coupled to the third current terminal and the fourth current terminal.

8. A device, A first input; A second input; and an input stage coupled to the first input and the second input; a differential to single-ended converter; Including, the input stage: a first transistor including a first control terminal, a first current terminal, and a second current terminal; a second transistor including a second control terminal, a third current terminal, and a fourth current terminal; 1. A differential amplifier, comprising: a coupled supply input; an inverting input coupled to the first current terminal; a non-inverting input coupled to the third current terminal; a first output coupled to the first control terminal; a second output coupled to the second control terminal; the differential amplifier, a first resistor coupled between the supply input and the first input; a second resistor coupled between the supply input and the second input; a third resistor coupled between the inverting input and the first input; a fourth resistor coupled between the non-inverting input and the second input; Including, the differential-to-single-ended converter is coupled to the second current terminal and the fourth current terminal; device.

9. 9. The device of claim 8, wherein the supply input is a first supply voltage and the differential amplifier further includes a second supply input; the input stage further comprising: a third transistor including a third control terminal and a fifth current terminal, the third control terminal coupled to the second supply input and the fifth current terminal coupled to the second current terminal; a fourth transistor including a fourth control terminal and a sixth current terminal, the fourth control terminal coupled to the second supply input and the sixth current terminal coupled to the fourth current terminal; 1. An apparatus comprising:

10. 9. The device of claim 8, a charge pump; a fifth resistor configured to be coupled between the second current terminal and the charge pump; a sixth resistor configured to be coupled between the fourth current terminal and the charge pump; 1. An apparatus comprising:

11. 9. The device of claim 8, wherein the supply input is a first supply input and the differential amplifier further comprises a second supply input; The device further includes a third transistor including a fifth current terminal and a sixth current terminal, the fifth current terminal coupled to the second supply input and the sixth current terminal coupled to a current source.

12. 9. The device of claim 8, The differential amplifier further comprises: a substrate layer; an n-type buried layer coupled to the supply input; a buried oxide layer coupled between the substrate layer and the n-type buried layer; Including, the device.

13. 13. The device of claim 12, wherein the n-type buried layer is configured to be coupled to the first input by the first resistor and to the second input by the second resistor.

14. 9. The device of claim 8, wherein the differential amplifier is a first differential amplifier, the first transistor further includes a fifth current terminal, and the second transistor further includes a sixth current terminal; The device further includes a second differential amplifier configured to be coupled to the fifth current terminal and the sixth current terminal.

15. 1. A differential amplifier having a first reference terminal operable to be coupled to a first terminal of a first resistor and a second reference terminal operable to be coupled to a second terminal of the first resistor, the differential amplifier comprising: an input stage coupled to the first reference terminal and the second reference terminal, the input stage comprising: a floating differential amplifier coupled to the first reference terminal and the second reference terminal, the floating differential amplifier configured to convert a differential voltage across the first resistor to a differential output; a first transistor coupled to the floating differential amplifier, the first transistor being controlled by the differential output and configured to pass a first current from the first reference terminal; a second transistor coupled to the floating differential amplifier, the second transistor controlled by the differential output and configured to pass a second current from the second reference terminal; a second resistor configured to create a first intermediate voltage drop based on the first current; a third resistor configured to create a second intermediate voltage drop based on the second current; the input stage including: a differential amplifier configured to convert a differential voltage based on a difference between the first intermediate voltage and the second intermediate voltage into a single-ended voltage; a differential amplifier including:

16. 16. A differential amplifier according to claim 15, a third transistor configured to pass current from the first transistor and enable a voltage difference between a first current terminal and a second current terminal, the third transistor having the first current terminal coupled to the first intermediate voltage; a fourth transistor configured to pass current from the second transistor and enable a voltage difference between a third current terminal and a fourth current terminal, the third current terminal being coupled to the second intermediate voltage; and a differential amplifier further comprising:

17. 16. The differential amplifier of claim 15, further comprising a charge pump coupled to the second resistor and the third resistor, the charge pump configured to increase a common-mode range of the floating differential amplifier.

18. 20. The differential amplifier of claim 17, further comprising a current source coupled to the floating differential amplifier by a third transistor, the current source configured to reduce a settling time of the floating differential amplifier.

19. 16. A differential amplifier according to claim 15, the floating differential amplifier further comprising: a substrate layer; an n-type buried layer configured to be coupled to the first reference terminal by a fourth resistor; a buried oxide layer coupled between the substrate layer and the n-type buried layer; a differential amplifier,

20. 20. The differential amplifier of claim 19, wherein the n-type buried layer is configured to be coupled to the first reference terminal by the fourth resistor and to the second reference terminal by a fifth resistor.

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