Method, device, system and computer-readable storage medium for retrieving alignment markers

Abstract

This application relates to the field of communications technology and discloses an alignment marker search method, an apparatus, a system, and a computer-readable storage medium. The method includes: a first module receiving a first data stream, the first data stream being obtained by multiplexing multiple second data streams at a reference granularity, where any second data stream includes an AM and data from at least one FEC codeword, the reference granularity being a number of bits corresponding to n symbols included in the FEC codeword; acquiring a first data segment from a first position within the first data stream at the reference granularity; and performing an AM search on the first data segment. In this method, the reference granularity is a number of bits corresponding to n symbols. Therefore, when a burst bit error occurs in the first data stream, the number of symbols affected by the burst bit error is small. Compared to a data stream obtained through bit multiplexing, the first data stream in this method has higher resistance to burst bit errors.

Description

[Technical Field]

[0001] This application claims priority to Chinese Patent Application No. 202310032473.9, entitled "Method, Apparatus, System and Computer-Readable Storage Medium for Searching for Aligned Markers," filed on January 10, 2023, the entire contents of which are incorporated herein by reference.

[0002] Technical Field The present application relates to the field of communication technology, and in particular to an aligned marker search method and apparatus, system, and computer-readable storage medium. [Background technology]

[0003] With the development of communication technology, the speed of Ethernet interfaces is continuously increasing. Since the rate of an Ethernet interface is much higher than the rate of a single lane connected to the Ethernet interface, multi-lane parallel transmission of data streams transmitted through the Ethernet interface becomes a manner of implementing adaptation between the lane rate and the Ethernet interface rate.

[0004] Skew is likely to occur when transmitting data streams over multiple lanes. Therefore, the data stream transmitter must insert an alignment marker (AM) into the data streams transmitted over multiple lanes, so that the data stream receiver can search for the AM and align the data streams transmitted over multiple lanes based on the AM, thereby accurately acquiring the data. Summary of the Invention [Problem to be solved by the invention]

[0005] The present application provides an aligned marker search method and apparatus, a system, and a computer-readable storage medium for performing an AM search on a data stream. [Means for solving the problem]

[0006] According to a first aspect, there is provided an alignment marker search method, which includes: a first module receiving a first data stream transmitted by a second module, the first data stream being obtained by multiplexing multiple second data streams at a reference granularity, where any second data stream includes an AM and data from at least one forward error correction (FEC) codeword, where the reference granularity is the number of bits corresponding to n symbols included in the FEC codeword, where n is a positive integer; the first module then obtaining a first data segment from a first position within the first data stream at the reference granularity and performing an AM search on the first data segment, where the first position is an arbitrary position within the first data stream.

[0007] In this method, a first data stream is obtained by multiplexing multiple second data streams with a reference granularity of the number of bits corresponding to n symbols included in an FEC codeword. Therefore, when a burst bit error occurs in the first data stream, the number of symbols affected by the burst bit error is small. If the first data stream is obtained by performing bit multiplexing on multiple second data streams and the bit multiplexing is performed on the multiple data streams with a granularity of 1 bit, the burst bit error will affect multiple symbols, and as a result, the number of symbols affected by the burst bit error will be large. Therefore, compared to performing an AM search on a data stream obtained through bit multiplexing, the method provided in this application has higher tolerance to burst bit errors.

[0008] In one possible implementation, obtaining a first data segment from a first position within the first data stream at the reference granularity includes demultiplexing the first data stream from the first position within the first data stream at the reference granularity to obtain the first data segment. Thus, when the first position is a boundary for performing multiplexing, the data included in the first data segment may be from the same second data stream, and then an AM search may be performed on the first data segment. For example, the AM search may be performed on the first data segment using an AM search method specified in the Institute of Electrical and Electronics Engineers (IEEE) 802.3 standard.

[0009] In one possible implementation, acquiring a first data segment from a first position in the first data stream at a reference granularity includes: acquiring a first number of bits from the first position in the first data stream at intervals of a first number of bits; and acquiring the first data segment based on multiple groups of the acquired first number of bits, where the first number is determined based on the reference granularity. Compared to the method of acquiring the first data segment through demultiplexing, in this implementation, the first data stream does not need to be demultiplexed, and the first data segment may be directly acquired by acquiring bits from the first data stream at intervals of the first number, thereby improving the efficiency of acquiring the first data segment. Additionally, in this method, the first data segment may be acquired through demultiplexing, or the first data segment may be acquired by directly acquiring bits from the first data stream. The method of acquiring the first data segment is flexible.

[0010] In one possible implementation, the method includes: obtaining a second data segment from a second position in the first data stream at a reference granularity based on the absence of an AM in the first data segment; and performing an AM search on the second data segment, where the second position is different from the first position. In other words, if an AM is not found in the first data segment, it means that the first position is not a boundary for performing multiplexing. In this case, the second data segment may be obtained from another position, i.e., the second position, in the first data stream, and an AM search is performed in the second data segment.

[0011] In one possible implementation, the second position is a second number of bits after the first position, or the second position is a third number of reference symbols after the first position, the type of reference symbols is determined based on a modulation scheme corresponding to the second data stream, and the second number is different from the number of bits corresponding to the third number of reference symbols. The method for determining the second position is flexible.

[0012] In one possible implementation, the AM includes a common marker (CM) field, and the CM field is used to perform an AM search on the first data segment. When an AM search is performed based on the CM field, if the CM field is found, the AM is considered to be found, thereby improving the efficiency of the AM search.

[0013] In one possible implementation, the FEC codewords are Reed-Solomon (RS) codewords.

[0014] According to a second aspect, there is provided an alignment marker search method. The method includes: a second module acquiring a first data stream, the first data stream being acquired by multiplexing a plurality of second data streams at a reference granularity, where any second data stream includes an AM and data from at least one FEC codeword, where the reference granularity is a number of bits corresponding to n symbols included in the FEC codeword, where n is a positive integer; the second module then transmits the first data stream to a first module, causing the first module to acquire a first data segment from a first position within the first data stream at the reference granularity and perform an AM search on the first data segment, where the first position is an arbitrary position within the first data stream.

[0015] In this method, the number of bits corresponding to n symbols included in an FEC codeword is used as a reference granularity, and multiple second data streams are multiplexed to obtain a first data stream. Therefore, when a burst bit error occurs in the first data stream, the number of symbols affected by the burst bit error is small. If a method of performing bit multiplexing on multiple second data streams is used to obtain a first data stream, the bit multiplexing is performed on the multiple data streams at a 1-bit granularity, so a burst bit error affects multiple symbols, and as a result, the number of symbols affected by the burst bit error is large. Therefore, compared to a data stream obtained through bit multiplexing, the first data stream obtained according to this method has higher resistance to burst bit errors.

[0016] According to a third aspect, there is provided an alignment marker search device, the device being used in a first module, the device comprising: an acquisition unit configured to receive a first data stream transmitted by a second module, the first data stream being acquired by multiplexing a plurality of second data streams at a reference granularity, any second data stream including AM and data from at least one FEC codeword, the reference granularity being a number of bits corresponding to n symbols included in the FEC codeword, n being a positive integer; the acquiring unit is further configured to acquire a first data segment from a first position within the first data stream at a reference granularity, the first position being an arbitrary position within the first data stream; a search unit configured to perform an AM search on the first data segment; Includes:

[0017] In one possible implementation, the acquiring unit is configured to demultiplex the first data stream from a first position within the first data stream at the reference granularity to acquire a first data segment.

[0018] In one possible implementation, the acquisition unit is configured to acquire a first number of bits at intervals of the first number of bits from a first position in the first data stream, and acquire a first data segment based on multiple groups of the acquired first number of bits, where the first number is determined based on a reference granularity.

[0019] In one possible implementation, the search unit is further configured to: retrieve a second data segment from a second position in the first data stream at a reference granularity based on the AM not being found in the first data segment, the second position being different from the first position; and perform an AM search on the second data segment.

[0020] In one possible implementation, the second position is a second number of bits after the first position, or the second position is a third number of reference symbols after the first position, the type of reference symbols being determined based on a modulation scheme corresponding to the second data stream, and the second number is different from the number of bits corresponding to the third number of reference symbols.

[0021] In one possible implementation, the AM includes a CM field, and the CM field is used to perform an AM search on the first data segment.

[0022] In one possible implementation, the FEC codewords are RS codewords.

[0023] According to a fourth aspect, there is provided an apparatus for retrieving aligned markers, the apparatus being used in a second module, the apparatus comprising: an acquisition unit configured to acquire a first data stream, the first data stream being acquired by multiplexing a plurality of second data streams at a reference granularity, any second data stream including AM and data from at least one FEC codeword, the reference granularity being a number of bits corresponding to n symbols included in the FEC codeword, where n is a positive integer; and a transmitting unit configured to transmit a first data stream to a first module, and cause the first module to retrieve a first data segment from a first position in the first data stream at a reference granularity, the first position being any position in the first data stream, and perform an AM search on the first data segment.

[0024] According to a fifth aspect, there is provided a communication system, the system including a first module and a second module, the first module configured to perform the aligned marker search method according to any one of the first aspect, and the second module configured to perform the aligned marker search method according to the second aspect.

[0025] According to a sixth aspect, there is provided a computer system. The computer system includes a processor, the processor including a first module or a second module. When the processor includes the first module, the computer system performs the alignment marker search method according to any one of the first aspects when the processor executes program instructions or code; or when the processor includes the second module, the computer system performs the alignment marker search method according to the second aspect when the processor executes program instructions or code. For example, the computer system further includes a memory configured to store the program instructions or code.

[0026] According to a seventh aspect, there is provided a computer-readable storage medium. The computer-readable storage medium stores at least one program instruction or code, the program instruction or code being executable by a computer, the computer including a first module or a second module. When the computer includes the first module, the program instruction or code, when executed by the computer, causes the computer to perform the alignment marker search method according to any one of the first aspects; or when the computer includes the second module, the program instruction or code, when executed by the computer, causes the computer to perform the alignment marker search method according to the second aspect.

[0027] According to an eighth aspect, there is provided a communication device. The device includes a transceiver, a memory, and a processor. The transceiver, the memory, and the processor communicate with each other through an internal connection path. The memory is configured to store instructions. The processor is configured to execute the instructions stored in the memory to control the transceiver to receive / transmit signals. The processor includes a first module or a second module. If the processor includes the first module, executing the instructions stored in the memory causes the processor to perform the alignment marker search method according to any one of the first aspects. If the processor includes the second module, executing the instructions stored in the memory causes the processor to perform the alignment marker search method according to the second aspect.

[0028] For example, there may be one or more processors and there may be one or more memories.

[0029] For example, the memory and processor may be integrated together, or the memory and processor are located separately.

[0030] In a particular implementation process, the memory may be a non-transitory memory, such as a read-only memory (ROM). The memory and the processor may be integrated on the same chip or may be separately located on different chips. The type of memory and the manner in which the memory and the processor are located are not limited in this application.

[0031] According to a ninth aspect, there is provided a computer program product, the computer program product comprising computer program instructions or code, the computer program instructions or code being executed by a computer, the computer comprising a first module or a second module, wherein if the computer comprises the first module, the computer program instructions or code, when executed by the computer, causes the computer to perform the alignment marker search method according to any one of the first aspects; or, if the computer comprises the second module, the computer program instructions or code, when executed by the computer, causes the computer to perform the alignment marker search method according to the second aspect.

[0032] According to a tenth aspect, there is provided a chip. The chip includes a processor, the processor including a first module or a second module, and the processor is configured to execute program instructions or code. When the processor includes the first module, a device including the chip performs the alignment marker search method according to any one of the first aspects; or when the processor includes the second module, a device including the chip performs the alignment marker search method according to the second aspect.

[0033] For example, the chip further includes an input interface, an output interface, and a memory, wherein the input interface, the output interface, the processor, and the memory are connected through interconnection paths, and the memory is configured to store program instructions or codes.

[0034] It should be understood that the beneficial effects achieved by the technical solutions of the third to tenth aspects of the present application and possible implementations corresponding to the third to tenth aspects refer to the technical effects of the first and second aspects and possible implementations corresponding to the first and second aspects, and the details will not be described again in this specification. [Brief explanation of the drawings]

[0035] [Figure 1] 1 is a diagram of an implementation scenario of the aligned marker search method according to an embodiment of the present application;

[0036] [Figure 2] 1 is a flowchart of a method for searching for alignment markers according to an embodiment of the present application.

[0037] [Figure 3] FIG. 10 is a diagram illustrating multiplexing a second data stream to obtain a first data stream according to an embodiment of the present application.

[0038] [Figure 4] FIG. 2 is a diagram of a first position according to an embodiment of the present application.

[0039] [Figure 5] FIG. 10 is a diagram of obtaining multiple groups of a first number of bits according to an embodiment of the present application.

[0040] [Figure 6] 1 is a diagram of the structure of an alignment marker retrieval device according to an embodiment of the present application;

[0041] [Figure 7] FIG. 10 is a diagram of the structure of another alignment marker retrieval device according to an embodiment of the present application.

[0042] [Figure 8] 1 is a diagram of a computer system architecture according to an embodiment of the present application;

[0043] [Figure 9] FIG. 10 is a diagram of another computer system architecture according to an embodiment of the present application. DETAILED DESCRIPTION OF THE INVENTION

[0044] The terms used in the implementation of the present application are only used to describe the embodiments of the present application and are not intended to limit the present application. The following describes the embodiments of the present application with reference to the accompanying drawings.

[0045] As communication technology develops, the rate of an Ethernet interface may increase faster than the rate of a single lane connected to the Ethernet interface. For example, a 10 Gigabit Ethernet (GE) interface is connected to a single 10 gigabits per second (Gbps) lane, a 100GE interface is connected to four 25Gbps lanes, and a 400GE interface is connected to sixteen 25Gbps lanes or eight 50Gbps lanes. A lane may also be a physical coding sublayer (PCS) lane. As the rate of an Ethernet interface increases from 10GE to 400GE, the rate of a single lane increases from 10Gbps to 25Gbps. s It can be seen that the data rate increases to 50 Gbps or 50 Gbps. In this case, the transmission of the data stream sent through the Ethernet interface may be performed in multi-lane parallel transmission mode. If the Ethernet interface is connected to multiple lanes, the data stream may be transmitted in parallel through the multiple lanes.

[0046] When data streams are transmitted in parallel through multiple lanes, the skew of the data streams on different lanes may be different. Therefore, a data stream transmitter inserts AMs into the data streams transmitted through multiple lanes, and a data stream receiver searches for AMs in the data streams received from the multiple lanes to obtain the positions of the AMs inserted into the data streams transmitted through the lanes. Therefore, after obtaining the positions of the AMs, the data stream receiver aligns (including alignment lock and deskew) the data streams transmitted through multiple lanes based on the positions of the AMs, and further decodes the data streams transmitted by the transmitter to the receiver through multiple lanes. The content of the AMs is not changed during transmission. However, in a data stream, a specific bit sequence of the AMs may be disturbed due to processes such as bit multiplexing or symbol multiplexing. The bit sequence is sometimes called a bit pattern.

[0047] When a data stream is transmitted through a physical link, the rate of the physical link used to transmit the data stream may be higher than the rate of the PCS lane. For example, the rate of a single PCS lane may be 25 Gbps, and the rate of the physical link used to transmit the data stream may be 50 Gbps or 100 Gbps. In this case, when the data stream on the PCS lane is transmitted through the physical link, the data streams transmitted through multiple PCS lanes need to be aggregated, and the data stream obtained through the aggregation is transmitted through the physical link. The data stream receiver may obtain the data stream transmitted through the PCS lane based on the data stream obtained through the aggregation, and then perform AM search on the data stream transmitted through the PCS lane.

[0048] An embodiment of the present application provides an aligned marker search method. This method is applicable to performing an AM search on a data stream obtained through aggregation. FIG. 1 is a diagram of an implementation scenario of the aligned marker search method according to an embodiment of the present application. Please refer to FIG. 1. The implementation scenario includes a first module 101 and a second module 102, where the first module 101 and the second module 102 are communicatively connected. For example, the first module 101 and the second module 102 are communicatively connected through multiple physical links. For example, the first module 101 is included in a first device, and the second module 102 is included in a second device; or the first module 101 and the second module 102 may be included in the same device. The device where either or both of the first module 101 and the second module 102 are located may be a network device or another device that includes an Ethernet interface or complies with the IEEE 802.3 standard. In addition, the implementation scenario shown in FIG. 1 may further include another module. This is not limited to the embodiments of the present application.

[0049] The alignment marker search method provided in this embodiment of the present application can be shown in Figure 2. The following describes the alignment marker search method provided in this embodiment of the present application with reference to the implementation scenario shown in Figure 1. As shown in Figure 2, the method includes, but is not limited to, S201 and S202.

[0050] S201: A second module acquires a first data stream, where the first data stream is acquired by multiplexing a plurality of second data streams at a reference granularity, where any second data stream includes AM and data from at least one FEC codeword, where the reference granularity is a number of bits corresponding to n symbols included in the FEC codeword, where n is a positive integer.

[0051] When multiplexing multiple second data streams to obtain a first data stream, the second module performs the multiplexing with a reference granularity of the number of bits corresponding to one or more symbols of an FEC codeword, i.e., n may be greater than or equal to 1. In some embodiments, n may be greater than or equal to 2. m m may be a positive integer greater than or equal to 1. For example, n is 2, 4, 8, or 16. The FEC codewords may be Reed-Solomon (RS) codewords. In this embodiment of the present application, n may be determined based on the number of FEC codewords corresponding to the second data stream. For example, for any second data stream, the second data stream includes data from two FEC codewords. In other words, the number of FEC codewords corresponding to the second data stream is 2. In this case, n is greater than or equal to 2.

[0052] For example, for any second data stream among the plurality of second data streams, the AM included in the second data stream corresponds to the lane transmitting the second data stream. For example, the second data stream is a data stream transmitted through a PCS lane, and the AM included in the second data stream has a one-to-one correspondence with the sequence number of the PCS lane transmitting the second data stream. When eight PCS lanes are used to transmit multiple second data streams in parallel, the correspondence between the AM included in the second data stream and the sequence number of the PCS lane transmitting the second data stream may be as shown in Table 1. [Table 1]

[0053] As shown in Table 1, the eight PCS lanes are PCS lane 0 to PCS lane 7, with sequence numbers 0 to 7, respectively. The AM corresponding to any PCS lane includes a CM field, a unique marker (UM) field, and a unique pad (UP) field. CM0 to CM5 in the AMs corresponding to all PCS lanes have the same value. For example, in Table 1, the value of CM0 in each AM is 0x9A, the value of CM1 in each AM is 0x4A, the value of CM2 in each AM is 0x26, the value of CM3 in each AM is 0x65, the value of CM4 in each AM is 0xB5, and the value of CM5 in each AM is 0xD9. The values ​​of UM0 to UM5 in the AM corresponding to each PCS lane uniquely correspond to the PCS lane, and the values ​​of UP0 to UP2 may also uniquely correspond to each PCS lane. For example, the values ​​of UM0 in the AM for PCS lanes 0 through 7 are 0xB3, 0x5A, 0x3E, 0x86, 0x2A, 0x12, 0x42, and 0xD6, respectively. The values ​​of UP0 in the AM for PCS lanes 0 through 7 are 0x05, 0x04, 0x46, 0x5A, 0xE1, 0xF2, 0x3D, and 0x22, respectively. For example, the values ​​of UP0 through UP2 are padding data unrelated to the AM locking mechanism. The contents of Table 1 are intended to illustrate the correspondence between PCS lanes and AMs and the contents contained in the AMs, and are not used to limit the PCS lane numbering scheme.

[0054] When 16 PCS lanes are used to transmit multiple second data streams in parallel, the correspondence between the AMs included in the second data streams and the sequence numbers of the PCS lanes transmitting the second data streams may be shown in Tables 2 and 3. [Table 2] [Table 3]

[0055] As shown in Tables 2 and 3, the 16 PCS lanes are PCS lane 0 to PCS lane 15, with sequence numbers 0 to 15, respectively. The principle of the correspondence between PCS lanes and AMs is the same as that shown in Table 1. The details will not be explained again in this specification. In addition, the contents of Tables 2 and 3 are intended to explain the correspondence between PCS lanes and AMs and the contents contained in the AMs, and are not used to limit the numbering scheme of PCS lanes.

[0056] Referring to Tables 1 to 3, CM0 to CM5, UM0 to UM5, and UP0 and UP2 may each include 8 bits, and therefore one AM may include 120 bits. The 120 bits may come from multiple FEC codewords. For example, if a symbol of an FEC codeword includes 10 bits, the 120-bit AM is allocated to multiple FEC codewords in 10-bit increments. Of course, the AM may include additional bits other than the 120 bits. For example, the AM may further include padding, which is used to adjust the number of bits included in the AM to a specified number. The number of bits included in the AM is not limited in the embodiments of the present application.

[0057] Note that the eight groups of AMs shown in Table 1 are specific to a 200GE interface. If there is an interface of another rate, different AMs may be used. For ease of design, for multiple PCS lanes connected to an interface, the CM fields in the AMs corresponding to the PCS lanes may be the same, for example, as shown in Tables 1 to 3, but the UMs may be different. In addition, Tables 2 and 3 are specific to a 400GE interface. If 16 lanes are used for an interface of another rate, the AMs may be different. Tables 1 to 3 above are merely illustrative examples and do not limit the various cases of correspondence between AMs and PCS lanes to which the present application is applicable. In addition, Table 1 is used as an example to describe AMs corresponding to PCS lanes connected to a 200GE interface. Tables 2 and 3 are used as examples to describe AMs corresponding to PCS lanes connected to a 400GE interface. For interfaces of another rate, the AMs may differ from the contents of Tables 1 to 3. For example, the AMs may not include a UP field.

[0058] FIG. 3 illustrates multiplexing a second data stream to obtain a first data stream according to an embodiment of the present application. As shown in FIG. 3, two second data streams are transmitted over PCS lane 0 and PCS lane 1, respectively. Each of the two second data streams includes an AM and a data portion from an FEC codeword. When the second data stream is transmitted over PCS lane 0, the AM used is AM0. When the second data stream is transmitted over PCS lane 1, the AM used is AM1. For example, a symbol of an FEC codeword includes 10 bits, and n is equal to 4, i.e., the reference granularity is 40 bits. AM0 and AM1 are each divided into three parts for multiplexing, and the data portions in the second data streams from the FEC codeword are also multiplexed at the reference granularity to obtain the first data stream.

[0059] For example, in this embodiment of the present application, when multiple second data streams are multiplexed, deskewing is first performed on the multiple second data streams, and then the multiple second data streams obtained through deskewing are multiplexed. When deskewing is performed on the multiple second data streams, it is not necessary to perform full deskewing on the multiple second data streams. Specifically, as long as deskewing is performed on the multiple second data streams up to the reference granularity for multiplexing, it is not necessary to completely align the multiple second data streams based on the AMs within the multiple second data streams. That is, as long as the multiple second data streams can be multiplexed at the reference granularity, the AM of one second data stream may be aligned with the data portion of the other second data stream. As shown in FIG. 3 , AM1 is aligned with the data portion of the second data stream transmitted through PCS lane 0 and is not aligned with AM0.

[0060] S202: The second module transmits a first data stream to the first module.

[0061] The manner in which the second module transmits the first data stream to the first module is not limited in the embodiments of the present application. For example, the second module transmits the first data stream to the first module through a physical link. The first module may obtain a first data segment from a first position in the first data stream with a reference granularity and perform an AM search on the first data segment, where the first position is any position in the first data stream. For the process in which the first module obtains the first data segment and performs an AM search on the first data segment, see S203 to S205. Details are not described in this specification.

[0062] In the method provided in this embodiment of the present application, the number of bits corresponding to n symbols included in the FEC codeword is used as the reference granularity, and multiple second data streams are multiplexed to obtain a first data stream. Therefore, when a burst bit error occurs in the first data stream, the number of symbols affected by the burst bit error is small. If a method of performing bit multiplexing on multiple second data streams is used to obtain a first data stream, the bit multiplexing is performed on the multiple data streams at a 1-bit granularity, so a burst bit error affects multiple symbols, and as a result, the number of symbols affected by the burst bit error is large. Therefore, compared to a data stream obtained through bit multiplexing, the first data stream obtained according to this method has higher resistance to burst bit errors.

[0063] The above uses the second module side as an example to describe the alignment marker search method provided in this embodiment of the present application. Below, the first module side is used as an example to describe this method. As shown in Figure 2, this method includes, but is not limited to, S203 to S205.

[0064] S203: The first module receives the first data stream transmitted by the second module.

[0065] The manner in which the first module receives the first data stream transmitted by the second module is not limited in the embodiments of the present application, as long as the manner corresponds to the manner in which the second module transmits the first data stream to the first module. The first data stream is obtained by multiplexing multiple second data streams at a reference granularity, where any second data stream includes AM and data from at least one FEC codeword, and the reference granularity is the amount of bits corresponding to n symbols included in the FEC codeword, where n is a positive integer.

[0066] S204: The first module obtains a first data segment from a first position in the first data stream at a reference granularity, where the first position is an arbitrary position in the first data stream.

[0067] In one possible implementation, the first module performs an operation of obtaining a first data segment from a first position in the first data stream at a reference granularity in accordance with the following method 1 or method 2.

[0068] Method 1: Demultiplexing a first data stream from a first position within the first data stream at a reference granularity to obtain a first data segment.

[0069] In the method 1, the first module may demultiplex the first data stream at the same granularity as the reference granularity for multiplexing, starting from any position within the first data stream. Therefore, when the first position is the boundary for performing multiplexing, the data included in the first data segment may be from the same second data stream.

[0070] FIG. 4 is a diagram of a first position according to an embodiment of the present application. Please refer to FIG. 4. If the first position is position A or position B within the first data stream, positions A and B are not boundaries for performing multiplexing. Therefore, the acquired first data segment includes not only data of the second data stream transmitted through PCS Lane 0 but also data of the second data stream transmitted through PCS Lane 1. In other words, the data included in the first data segment originates from two second data streams. If the first position is position C within the first data stream, position C is a boundary for performing multiplexing. Therefore, the acquired first data segment includes only data of the second data stream transmitted through PCS Lane 0 or only data of the second data stream transmitted through PCS Lane 1. In other words, the data included in the first data segment originates from the same second data stream. In this embodiment of the present application, when the first data segment is acquired by demultiplexing the first data stream, an AM search may then be performed on the first data segment. For example, an AM search may be performed on the first data segment using an AM search method specified in the IEEE 802.3 standard.

[0071] Method 2: Acquire a first number of bits at intervals of the first number of bits from a first position in a first data stream, and acquire a first data segment based on multiple groups of the acquired first number of bits, where the first number is determined based on a reference granularity.

[0072] Compared with the method of obtaining the first data segment through demultiplexing in Scheme 1, in Scheme 2, the first data stream is not demultiplexed, and the first data segment is directly obtained by obtaining bits from the first data stream at intervals of a first number, thereby improving the efficiency of obtaining the first data segment. In this embodiment of the present application, the first number is equal to the number of bits corresponding to the reference granularity. For example, if a symbol of an FEC codeword contains 10 bits, n×10 consecutive bits are obtained at intervals of n×10 consecutive bits in the first data stream, and then the first data segment is obtained based on multiple groups of the obtained n×10 bits.

[0073] FIG. 5 is a diagram illustrating acquiring multiple groups of a first number of bits. Referring to FIG. 5, if the first module uses position D as the first position, the first module acquires the first number of bits at intervals of the first number of bits in the first data stream, starting from position D. If the first module uses position E as the first position, the first module acquires the first number of bits at intervals of the first number of bits in the first data stream, starting from position E. Position E is one bit after position D.

[0074] S205: The first module performs an AM search on the first data segment.

[0075] For example, a CM field included in an AM is used to perform an AM search on the first data segment, thereby reducing the amount of data required to perform the AM search and increasing the efficiency of the AM search. The CM field may include CM0 to CM5 in Tables 1 to 3. In this embodiment of the present application, for any second data stream, an AM corresponding to a PCS lane transmitting the second data stream may be inserted into the second data stream at certain intervals. When an AM search is performed based on the CM field, if a CM field is found, the AM is considered to have been found. In this embodiment of the present application, for any second data stream, an AM corresponding to a PCS lane transmitting the second data stream may be repeatedly inserted into the second data stream at a reference interval. In this case, if a CM field is found p times consecutively in the first data segment at the reference interval for inserting an AM, the AM is considered to have been found. For inserting If an AM is found p times consecutively in the first data segment within the reference interval, the AM lock is successful. Here, p may be a positive integer equal to or greater than 2. The method of searching for the CM field is not limited to the embodiment of the present application. For example, each CM field includes two nibbles, and CM0 to CM5 include a total of 12 nibbles. If 9 of the 12 nibbles can be found in the first data segment, it is determined that the CM field has been found.

[0076] In one possible implementation, the first module may alternatively perform an AM search on the first data segment based on multiple fields in the AM. For example, the first module may perform an AM search on the first data segment based on the CM field and the UM field in the AM. In other words, in addition to searching for the CM field, the first module may also search for the UM field. Therefore, if both the CM field and the UM field are found in the first data segment, the AM is considered to be found in the first data segment. The manner of searching for the UM field is not limited in this embodiment. For example, each UM field includes two nibbles, and UM0 to UM5 include a total of 12 nibbles. If 9 of the 12 nibbles can be found in the first data segment, the UM field is determined to be found.

[0077] In one possible implementation, the method further includes the steps of: obtaining a second data segment from a second position in the first data stream at a reference granularity based on the absence of an AM in the first data segment, the second position being different from the first position; and performing an AM search on the second data segment. In other words, if an AM is not found in the first data segment, it means that the first position is not a boundary for performing multiplexing. In this case, the second data segment may be obtained from another position, i.e., the second position, in the first data stream, and the AM search is performed in the second data segment. The principle of performing the AM search in the second data segment is the same as in S205. Details will not be described again in this specification. For example, if an AM is not found after the reference length bits, it is determined that an AM is not found in the first data segment. The reference length may be determined based on experience or practical requirements. For example, the reference length is five times the AM insertion interval.

[0078] The second position may be a second number of bits after the first position, or may be a third number of reference symbols after the first position, where the type of reference symbol is determined based on a modulation scheme corresponding to the second data stream, and the second number is different from the number of bits corresponding to the third number of reference symbols. The modulation scheme corresponding to the second data stream may be 4-level pulse amplitude modulation (PAM4), whereby the reference symbol may be a PAM4 symbol. Alternatively, the modulation scheme corresponding to the second data stream may be 3-level pulse amplitude modulation (PAM3), whereby the reference symbol may be a PAM3 symbol. Alternatively, the modulation scheme corresponding to the second data stream may be 5-level pulse amplitude modulation (PAM5), whereby the reference symbol may be a PAM5 symbol. Alternatively, the modulation scheme corresponding to the second data stream may be 6-level pulse amplitude modulation (PAM6), whereby the reference symbols may be PAM6 symbols. Alternatively, the modulation scheme corresponding to the second data stream may be 8-level pulse amplitude modulation (PAM8), whereby the reference symbols may be PAM8 symbols. Alternatively, the modulation scheme corresponding to the second data stream may be 16-level pulse amplitude modulation (PAM16), whereby the reference symbols may be PAM16 symbols. Alternatively, the modulation scheme corresponding to the second data stream may be 16-level pulse amplitude modulation (PAM16), whereby the reference symbols may be PAM16 symbols. Modulation method is quadrature amplitude modulation (QAM), whereby the reference symbols may be QAM symbols.

[0079] For example, if the AM is not found in the second data segment, the first module may continue to change the location, retrieve the data segment from the changed location in the first data stream, and perform an AM search on the retrieved data segment. The first module cyclically performs the process of changing the location, retrieving the data segment, and performing an AM search on the data segment until the AM is found in the data segment.

[0080] Because the multiplexing granularity is fixed, the multiplexing boundary appears periodically. Therefore, when the position is changed, the position can be one bit after position A or x*n*10 bits + 1 bits after position A, where x is a positive integer greater than or equal to 1. For example, as shown in FIG. 4, if position A is the first position and the first module does not find an AM in the first data segment, the first module may use position B, which is one bit after position A, as the second position to obtain a second data segment and perform an AM search on the obtained second data segment. If the first module does not find an AM in the second data segment, the first module may use position C, which is one bit after position B, as the third position, to obtain a third data segment from position C in the first data stream at the standard granularity and perform an AM search on the third data segment. In another example, as shown in FIG. 5, when position D is the first position and the first module does not find an AM in the first data segment, the first module may use position E, which is one bit after position D, as the second position to obtain a second data segment and perform an AM search on the obtained second data segment.

[0081] In addition, if multiple first data segments are obtained when the first data segment is obtained through demultiplexing, an AM search may be performed for each of the first data segments. If AM lock for any of the multiple first data segments fails, it is determined that the first position is not a boundary for performing multiplexing, and the first module performs an operation of obtaining a second data segment from a second position in the first data stream at the reference granularity and performing an AM search for the second data segment.

[0082] The method provided in this embodiment of the present application is applicable to performing an AM search on a first data stream. In this method, the first data stream is obtained by multiplexing multiple second data streams with a reference granularity of the number of bits corresponding to n symbols included in an FEC codeword. Therefore, when a burst bit error occurs in the first data stream, the number of symbols affected by the burst bit error is small. If the first data stream is obtained by performing bit multiplexing on multiple second data streams and the bit multiplexing is performed on the multiple data streams with a granularity of 1 bit, the burst bit error will affect multiple symbols, and as a result, the number of symbols affected by the burst bit error will be large. Therefore, compared to performing an AM search on a data stream obtained through bit multiplexing, the method provided in this embodiment of the present application has higher tolerance to burst bit errors.

[0083] An embodiment of the present application further provides an alignment marker search device. Figure 6 is a diagram of the structure of an alignment marker search device according to an embodiment of the present application. Based on the multiple units shown in Figure 6, the alignment marker search device shown in Figure 6 can perform all or part of the operations performed by the first module. It should be understood that the device may include more additional units than the units shown, or may omit some of the units shown. This is not limited in the embodiment of the present application. As shown in Figure 6, the device includes: an acquiring unit 601 configured to receive a first data stream transmitted by a second module, the first data stream being acquired by multiplexing a plurality of second data streams at a reference granularity, any second data stream including AM and data from at least one FEC codeword, the reference granularity being a number of bits corresponding to n symbols included in the FEC codeword, n being a positive integer; The acquiring unit 601 is further configured to acquire a first data segment from a first position in the first data stream at a reference granularity, the first position being an arbitrary position in the first data stream; a search unit 602 configured to perform an AM search on the first data segment; Includes:

[0084] In one possible implementation, the acquiring unit 601 is configured to demultiplex the first data stream from a first position within the first data stream at a reference granularity to acquire a first data segment.

[0085] In one possible implementation, the acquisition unit 601 is configured to acquire a first number of bits at intervals of a first number of bits from a first position in the first data stream, and acquire a first data segment based on multiple groups of the acquired first number of bits, where the first number is determined based on a reference granularity.

[0086] In one possible implementation, the search unit 602 is further configured to, based on not finding the AM in the first data segment, retrieve a second data segment from a second location in the first data stream at the reference granularity, the second location being different from the first location, and perform an AM search on the second data segment.

[0087] In one possible implementation, the second position is a second number of bits after the first position, or the second position is a third number of reference symbols after the first position, the type of reference symbols being determined based on a modulation scheme corresponding to the second data stream, and the second number is different from the number of bits corresponding to the third number of reference symbols.

[0088] In one possible implementation, the AM includes a CM field, and the CM field is used to perform an AM search on the first data segment.

[0089] In one possible implementation, the FEC codewords are RS codewords.

[0090] The device provided in this embodiment of the present application is applicable to performing an AM search on a first data stream. In the device, the first data stream is obtained by multiplexing multiple second data streams with a reference granularity of the number of bits corresponding to n symbols included in an FEC codeword. Therefore, when a burst bit error occurs in the first data stream, the number of symbols affected by the burst bit error is small. If the first data stream is obtained by performing bit multiplexing on multiple second data streams, and the bit multiplexing is performed on the multiple data streams with a granularity of 1 bit, the burst bit error will affect multiple symbols, and as a result, the number of symbols affected by the burst bit error will be large. Therefore, compared to performing an AM search on a data stream obtained through bit multiplexing, the device has higher tolerance to burst bit errors.

[0091] 7 is a diagram of the structure of another alignment marker search device according to an embodiment of the present application. Based on the multiple units shown in FIG. 7, the alignment marker search device shown in FIG. 7 can perform all or part of the operations performed by the second module. It should be understood that the device may include more additional units than the units shown, or may omit some of the units shown. This is not limited in the embodiment of the present application. As shown in FIG. 7, the device includes: an acquisition unit 701 configured to acquire a first data stream, the first data stream being acquired by multiplexing a plurality of second data streams at a reference granularity, where any second data stream includes AM and data from at least one FEC codeword, the reference granularity being a number of bits corresponding to n symbols included in the FEC codeword, where n is a positive integer; and a transmitting unit 702 configured to transmit a first data stream to a first module and cause the first module to retrieve a first data segment from a first position in the first data stream at a reference granularity, the first position being any position in the first data stream, and perform an AM search on the first data segment.

[0092] In the device provided in this embodiment of the present application, the number of bits corresponding to n symbols included in an FEC codeword is used as a reference granularity, and multiple second data streams are multiplexed to obtain a first data stream. Therefore, when a burst bit error occurs in the first data stream, the number of symbols affected by the burst bit error is small. If a method of performing bit multiplexing on multiple second data streams is used to obtain a first data stream, the bit multiplexing is performed on the multiple data streams at a 1-bit granularity, so a burst bit error affects multiple symbols, and as a result, the number of symbols affected by the burst bit error is large. Therefore, compared to a data stream obtained through bit multiplexing, the first data stream obtained by this device has strong resistance to burst bit errors.

[0093] It should be understood that when the apparatus provided in Figures 6 and 7 implements the functions of the apparatus, the division of the above-mentioned functional units is only used as an example for explanation. In actual application, the above-mentioned functions may be allocated to different functional units for implementation based on needs. That is, the internal structure of the device is divided into different functional units for implementing all or part of the above-mentioned functions. In addition, the apparatus provided in the above-mentioned embodiments belongs to the same concept as the method embodiment. For the specific implementation process thereof, please refer to the method embodiment. The details will not be described again in this specification.

[0094] 8 is a diagram of the structure of a computer system according to an embodiment of the present application. For example, as shown in FIG. 8, the computer system is computer system 2000. Computer system 2000 may be a network device, which may be a routing device or a switching device. Computer system 2000 shown in FIG. 8 is configured to perform operations associated with the first module or the second module in the alignment marker search method shown in FIG. 2. Computer system 2000 may be, for example, a server, and computer system 2000 may be implemented using a general-purpose bus architecture.

[0095] As shown in FIG. 8, the computer system 2000 includes at least one processor 2001, memory 2003, and at least one communication interface 2004.

[0096] The processor 2001 may be, for example, a central processing unit (CPU), a digital signal processor (DSP), a network processor (NP), a graphics processing unit (GPU), a neural-network processing unit (NPU), a data processing unit (DPU), a microprocessor, or one or more integrated circuits configured to implement the solutions of the present application. For example, the processor 2001 may include an application-specific integrated circuit (ASIC), a programmable logic device (PLD) or another programmable logic device, a transistor logic device, a hardware component, or any combination thereof. The PLD may be, for example, a complex programmable logic device (CPLD), a field programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof. The processor may implement or execute various logic blocks, modules, and circuits described with reference to the disclosed subject matter in the embodiments of the present application. Alternatively, the processor may be a combination of processors that implement computing functions, such as a combination of one or more microprocessors, or a combination of a DSP and a microprocessor.

[0097] Optionally, the computer system 2000 further includes a bus. The bus is configured to transmit information between components of the computer system 2000. The bus may be a peripheral component interconnect (PCI) bus, an extended industry standard architecture (EISA) bus, or the like. The bus may be classified into an address bus, a data bus, a control bus, or the like. For ease of representation, only one thick line is used to represent a bus in FIG. 8, but this does not imply that only one bus or only one type of bus is present.

[0098] Memory 2003 may be, for example, but is not limited to, read-only memory (ROM) or another type of static storage device capable of storing static information and instructions, random access memory (RAM) or another type of dynamic storage device capable of storing information and instructions, electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compact discs, laser discs, optical discs, digital versatile discs, Blu-ray discs, etc.), disk storage media or other magnetic storage devices, or any other medium that can be used to carry or store program code, expected in the form of instructions or data structures, and that can be accessed by a computer. For example, memory 2003 exists independently and is connected to processor 2001 through a bus. Alternatively, memory 2003 and processor 2001 may be integrated together.

[0099] The communication interface 2004 is any device, such as a transceiver, configured to communicate with other devices or communication networks. The communication network may be an Ethernet, a radio access network (RAN), a wireless local area network (WLAN), or the like. The communication interface 2004 may include a wired communication interface or may further include a wireless communication interface. Specifically, the communication interface 2004 may be an Ethernet interface, a fast Ethernet (FE) interface, a gigabit Ethernet (GE) interface, an asynchronous transfer mode (ATM) interface, a WLAN interface, a cellular network communication interface, or a combination thereof. The Ethernet interface may be an optical interface, an electrical interface, or a combination thereof. In this embodiment of the present application, the communication interface 2004 may be used by the computer system 2000 to communicate with another device.

[0100] In a specific implementation, in one embodiment, the processor 2001 may include one or more CPUs, such as CPU0 and CPU1 shown in FIG. 8. Each of the processors may be a single-core (single-CPU) processor or a multi-core (multi-CPU) processor. A processor herein may be one or more devices, circuits, and / or processing cores configured to process data (e.g., computer program instructions).

[0101] Among specific implementations, in one embodiment, computer system 2000 may include multiple processors, such as processor 2001 and processor 2005 shown in FIG. 8. Each processor may be a single-core processor (single CPU) or a multi-core processor (multiple CPUs). A processor herein may be one or more devices, circuits, and / or processing cores configured to process data (e.g., computer program instructions).

[0102] During specific implementation, in one embodiment, the computer system 2000 may further include an output device and an input device. The output device communicates with the processor 2001 and may display information in multiple ways. For example, the output device may be a liquid crystal display (LCD), a light emitting diode (LED) display device, a cathode ray tube (CRT) display device, or a projector. The input device communicates with the processor 2001 and may receive user input in multiple ways. For example, the input device may be a mouse, a keyboard, a touchscreen device, or a sensing device.

[0103] In some embodiments, the memory 2003 is configured to store program code 2010 for performing the solutions of the present application, and the processor 2001 may execute the program code 2010 stored in the memory 2003. The program code 2010 may include one or more software modules. Optionally, the processor 2001 may also store program code or instructions for performing the solutions of the present application.

[0104] In a specific embodiment, the computer system 2000 in this embodiment of the present application may include the first module in the method embodiment described above. The processor 2001 in the computer system 2000 reads the program code 2010 in the memory 2003 or the program code or instructions stored in the processor 2001 to cause the computer system 2000 shown in FIG. 8 to perform all or a part of the operations performed by the first module.

[0105] In a specific embodiment, the computer system 2000 in this embodiment of the present application may include the second module in the method embodiment described above. The processor 2001 in the computer system 2000 reads the program code 2010 in the memory 2003 or the program code or instructions stored in the processor 2001 to cause the computer system 2000 shown in FIG. 8 to perform all or a part of the operations performed by the second module.

[0106] The computer system 2000 may further correspond to the devices shown in Figures 6 and 7. Each functional unit in the devices shown in Figures 6 and 7 is implemented by using software in the computer system 2000. In other words, the functional units included in the devices shown in Figures 6 and 7 are generated after the processor 2001 of the computer system 2000 reads the program code 2010 stored in the memory 2003.

[0107] The steps in the alignment marker search method shown in FIG. 2 can be completed by using integrated logic circuits in hardware within the processor of the computer system 2000 or by using instructions in the form of software. The steps of the method disclosed with reference to the embodiments of the present application can be performed directly by the hardware processor, or by using a combination of hardware and software modules within the processor. The software modules can be located in a storage medium well-established in the art, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, or registers. The storage medium is located in the memory, and the processor reads the information in the memory and completes the steps in the aforementioned method in combination with the processor's hardware. To avoid repetition, the details will not be described again here.

[0108] FIG. 9 is a diagram of the structure of another computer system according to an embodiment of the present application. The computer system is configured to perform operations related to the first or second module in the alignment marker search method shown in FIG. 2. For example, the computer system is a server. Servers can vary greatly due to different configurations or performance. The computer system may include one or more processors 901 and one or more memories 902. The one or more memories 902 store at least one computer program, which is loaded and executed by the one or more processors 901. For example, the processor 901 is a CPU. Of course, the computer system may further include components such as a wired or wireless network interface, a keyboard, and an input / output interface for input / output. The computer system may further include other components configured to implement device functions. Details will not be described herein.

[0109] An embodiment of the present application further provides a computer system. The computer system includes a processor. The processor includes a first module or a second module. The processor is configured to retrieve instructions stored in the memory from the memory and execute the instructions. When the processor includes the first module, the computer system implements the alignment marker search method performed by the first module. When the processor includes the second module, the computer system implements the alignment marker search method performed by the second module.

[0110] In one possible implementation, the computer system further includes an input interface, an output interface, and the memory, wherein the input interface, the output interface, the processor, and the memory are connected through an internal connection path.

[0111] An embodiment of the present application further provides a communication system. The communication system includes a first module and a second module. The first module is configured to execute the method performed by the first module shown in Figure 2, and the second module is configured to execute the method performed by the second module shown in Figure 2. For functions of the first module and the second module of the communication system, please refer to the related description shown in Figure 2. Details will not be described again in this specification.

[0112] An embodiment of the present application further provides a communication device. The device includes a transceiver, a memory, and a processor. The transceiver, the memory, and the processor communicate with each other through an internal connection path. The memory is configured to store instructions. The processor is configured to execute the instructions stored in the memory to control the transceiver to receive / transmit signals. The processor includes a first module or a second module. If the processor includes the first module, executing the instructions stored in the memory causes the processor to perform an alignment marker search method performed by the first module. If the processor includes the second module, executing the instructions stored in the memory causes the processor to perform an alignment marker search method performed by the second module.

[0113] It is understood that the processor may be a CPU, or may be another general-purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component, etc. The general-purpose processor may be a microprocessor, any conventional processor, etc. It is noted that the processor may also be a processor supporting the advanced reduced instruction set computer machine (advanced RISC machine, ARM) architecture.

[0114] Additionally, in optional embodiments, the memory may include read-only memory and random access memory to provide instructions and data for the processor. The memory may further include non-volatile random access memory. For example, the memory may further store information regarding device type.

[0115] The memory may be volatile or nonvolatile, or may include both volatile and nonvolatile memory. Nonvolatile memory may be ROM, programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory may be RAM, used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchlink dynamic random access memory (SLDRAM), and direct Rambus random access memory (DR RAM).

[0116] An embodiment of the present application further provides a computer-readable storage medium. The computer-readable storage medium stores at least one program instruction or code, and the program instruction or code is executed by a computer, the computer including a first module or a second module. When the computer includes the first module, the program instruction or code, when executed by the computer, causes the computer to perform the alignment marker search method performed by the first module. When the computer includes the second module, the program instruction or code, when executed by the computer, causes the computer to perform the alignment marker search method performed by the second module.

[0117] An embodiment of the present application further provides a computer program product. The computer program product includes computer program instructions or code that are executed by a computer, the computer including a first module and a second module. When the computer includes the first module, the computer program instructions or code, when executed by the computer, cause the computer to perform the alignment marker search method performed by the first module. When the computer includes the second module, the computer program instructions or code, when executed by the computer, cause the computer to perform the alignment marker search method performed by the second module.

[0118] An embodiment of the present application further provides a chip including a processor. The processor includes a first module or a second module. The processor is configured to execute program instructions or codes. When the processor includes the first module, a device including the chip executes the alignment marker search method executed by the first module. When the processor includes the second module, a device including the chip executes the alignment marker search method executed by the second module.

[0119] For example, the chip further includes an input interface, an output interface, and a memory, wherein the input interface, the output interface, the processor, and the memory are connected through interconnection paths, and the memory includes program instructions or codes.

[0120] All or part of the foregoing embodiments may be implemented using software, hardware, firmware, or any combination thereof. When software is used to implement an embodiment, all or part of the embodiment may be implemented in the form of a computer program product. A computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the procedures or functions described herein are generated. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or another programmable device. The computer instructions may be stored on a computer-readable storage medium or transmitted from a computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from a website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, or digital subscriber line) or wireless (e.g., infrared, radio, microwave, etc.) methods. The computer-readable storage medium may be any available medium accessible by a computer, or a data storage device, such as a server or data center, that integrates one or more available media. The available media may be magnetic media (e.g., floppy disks, hard disks, or magnetic tapes), optical media (e.g., digital video discs (DVDs)), or semiconductor media (e.g., solid-state drives (SSDs)).

[0121] In the above-described embodiments, the unit of transmission rate is Gb / s, which may be abbreviated as G. For example, a rate of 400 Gb / s may be abbreviated as 400 G.

[0122] In order to clearly describe the compatibility of hardware and software, the steps and configurations of the embodiments are generally described in terms of functions in the above description. Whether a function is performed by hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art may use different methods to implement the described functions for each specific application, but such implementation should not be considered as going beyond the scope of the present application.

[0123] The computer program code used to implement the methods of the embodiments of the present application may be written in one or more programming languages. The computer program code may be provided to a processor of a general-purpose computer, a special-purpose computer, or another programmable alignment marker retrieval device, so that when the program code is executed by the computer or another programmable alignment marker retrieval device, the functions / operations specified in the flowcharts and / or block diagrams are implemented. The program code may run entirely on the computer, partially on the computer, as a stand-alone software package, partially on the computer and partially on a remote computer, or entirely on a remote computer or server.

[0124] In the context of the embodiments of the present application, computer program code or associated data may be carried on any suitable carrier, thereby enabling a device, apparatus, or processor to perform the various types of processes and operations described above. Examples of carriers include signals, computer-readable media, etc. Examples of signals may include electrical signals, optical signals, radio signals, audio signals, or other forms of propagated signals such as carrier waves and infrared signals.

[0125] For the sake of convenience, those skilled in the art can clearly understand that the detailed operation processes of the aforementioned systems, devices and modules may refer to the corresponding processes in the aforementioned method embodiments, and the details will not be described again in this specification.

[0126] In some embodiments provided herein, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. For example, the described device embodiments are merely examples. For example, the division of modules is merely a division of logical functions, and other division modes may exist in actual applications. For example, multiple modules or components may be combined or integrated into another system, or some features may be ignored or not implemented. In addition, the shown or described mutual couplings or direct couplings or communication connections may be indirect couplings or communication connections implemented by some interfaces, devices, or modules, or may be electrical, mechanical, or other forms of connection.

[0127] Modules described as separate parts may or may not be physically separate, and parts denoted as modules may or may not be physical modules, specifically, may be located in one location or distributed over multiple network modules, and some or all of the modules may be selected based on actual requirements for realizing the objectives of the solutions of the embodiments of the present application.

[0128] In addition, the functional modules in the embodiments of the present application may be integrated into one processing module, or each module may exist physically alone, or two or more modules may be integrated into one module. The integrated modules may be implemented in the form of hardware or in the form of software functional modules.

[0129] In this application, terms such as "first" and "second" are used to distinguish between the same item or similar items having essentially the same function. It should be understood that there is no logical or temporal order dependency between "first," "second," and "nth," and that the number and execution order are not limited. In the following description, terms such as "first" and "second" are used to describe various elements, but it should be further understood that these elements should not be limited by these terms. These terms are used merely to distinguish one element from another. For example, a first module may be referred to as a second module, and similarly, a second module may be referred to as a first module, without departing from the scope of various described examples.

[0130] It should be further understood that in the embodiments of the present application, the sequence numbers of the processes do not mean the execution order, and the execution order of the processes should be determined based on the functions and internal logic of the processes, and should not be construed as any limitation on the implementation process of the embodiments of the present application.

[0131] As used herein, the term "at least one" means one or more, and the term "plurality" as used herein means two or more. For example, a plurality of code blocks means two or more code blocks. The terms "system" and "network" are often used interchangeably herein.

[0132] It should be understood that the terminology used in the description of the various examples herein is intended to describe particular examples only and is not intended to constitute a limitation. The singular terms "one" ("a" and "an") and "the" used in the description of the various examples and the appended claims are also intended to include the plural forms unless the context clearly dictates otherwise.

[0133] It will be further understood that the term "comprising" (also referred to as "including," "comprises," and / or "comprises") as used herein specifies the presence of stated features, integers, steps, operations, elements, and / or components, and does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or components thereof.

[0134] It should also be understood that, depending on the context, the phrase "upon determining..." or "upon detecting [the stated condition or event]" may be interpreted to mean "once determining..." or "in response to determining..." or "once detecting [the stated condition or event]" or "in response to detecting [the stated condition or event]."

[0135] It should be understood that determining B based on A does not mean that B is determined based only on A; B may alternatively be determined based on A and / or other information.

[0136] It should be further understood that references throughout this specification to "an embodiment," "one embodiment," and "one possible implementation" mean that a particular feature, structure, or characteristic associated with that embodiment or implementation is included in at least one embodiment of the present application. Thus, the appearances of "an embodiment," "in one embodiment," or "one possible implementation" throughout this specification do not necessarily refer to the same embodiment. In addition, these particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

Claims

1. 1. A method for locating aligned markers, the method comprising: receiving, by a first module, a first data stream transmitted by a second module, the first data stream being obtained by multiplexing a plurality of second data streams at a reference granularity, any second data stream including an alignment marker AM and data from at least one forward error correction (FEC) codeword, the reference granularity being a number of bits corresponding to n symbols included in the FEC codeword, where n is a positive integer; obtaining a first data segment at the reference granularity from a first position in the first data stream, the first position being an arbitrary position in the first data stream; performing an AM search on the first data segment; A method comprising:

2. Obtaining a first data segment at the reference granularity from a first position in the first data stream includes: demultiplexing the first data stream at the reference granularity from the first position in the first data stream to obtain the first data segment; The method of claim 1.

3. Obtaining a first data segment at the reference granularity from a first position in the first data stream includes: acquiring a first number of bits at intervals of a first number of bits from the first position in the first data stream, and acquiring the first data segment based on a plurality of groups of the acquired first number of bits, wherein the first number of bits is determined based on the reference granularity. The method of claim 1.

4. The method further comprises: obtaining a second data segment at the reference granularity from a second location in the first data stream based on the absence of an AM in the first data segment, the second location being different from the first location; performing an AM search on the second data segment; 4. The method of claim 1, comprising:

5. the second position is a second number of bits after the first position, or the second position is a third number of reference symbols after the first position; the type of the reference symbol is determined based on a modulation scheme corresponding to the second data stream, and the second number of bits is different from the number of bits corresponding to the third number of reference symbols; The method of claim 4.

6. 6. The method of claim 1, wherein the AM includes a common marker CM field, the CM field being used to perform an AM search on the first data segment.

7. The method of claim 1 , wherein the FEC codewords are Reed-Solomon RS codewords.

8. 1. A method for locating aligned markers, the method comprising: acquiring, by a second module, a first data stream, the first data stream being acquired by multiplexing a plurality of second data streams at a reference granularity, any second data stream including an alignment marker AM and data from at least one forward error correction (FEC) codeword, the reference granularity being a number of bits corresponding to n symbols included in the FEC codeword, where n is a positive integer; sending the first data stream to a first module, causing the first module to obtain a first data segment at the reference granularity from a first position in the first data stream, and perform an AM search on the first data segment, wherein the first position is an arbitrary position in the first data stream; A method comprising:

9. An apparatus for retrieving aligned markers, the apparatus being used in a first module, the apparatus comprising: an acquisition unit configured to receive a first data stream transmitted by a second module, the first data stream being acquired by multiplexing a plurality of second data streams at a reference granularity, any second data stream including an alignment marker AM and data from at least one forward error correction (FEC) codeword, the reference granularity being a number of bits corresponding to n symbols included in the FEC codeword, n being a positive integer; an acquisition unit, the acquisition unit being further configured to acquire a first data segment at the reference granularity from a first position in the first data stream, the first position being an arbitrary position in the first data stream; a search unit configured to perform an AM search on the first data segment; An apparatus having:

10. 10. The apparatus of claim 9, wherein the acquisition unit is configured to demultiplex the first data stream at the reference granularity from the first position in the first data stream to acquire the first data segment.

11. 10. The apparatus of claim 9, wherein the acquisition unit is configured to acquire a first number of bits at intervals of a first number of bits from the first position in the first data stream, and acquire the first data segment based on multiple groups of the acquired first number of bits, and the first number of bits is determined based on the reference granularity.

12. 12. The apparatus of claim 9, wherein the search unit is further configured to: obtain a second data segment at the reference granularity from a second position in the first data stream, the second position being different from the first position, based on no AM being found in the first data segment; and perform an AM search on the second data segment.

13. 13. The apparatus of claim 12, wherein the second position is a second number of bits after the first position, or the second position is a third number of reference symbols after the first position, a type of the reference symbol is determined based on a modulation scheme corresponding to the second data stream, and the second number of bits is different from a number of bits corresponding to the third number of reference symbols.

14. 14. The apparatus of claim 9, wherein the AM includes a common marker CM field, the CM field being used to perform an AM search on the first data segment.

15. 15. Apparatus according to any one of claims 9 to 14, wherein the FEC codewords are Reed-Solomon RS codewords.

16. An apparatus for retrieving aligned markers, the apparatus being used in a second module, the apparatus comprising: an acquisition unit configured to acquire a first data stream, the first data stream being acquired by multiplexing a plurality of second data streams at a reference granularity, any second data stream including an alignment marker AM and data from at least one forward error correction (FEC) codeword, the reference granularity being a number of bits corresponding to n symbols included in the FEC codeword, where n is a positive integer; a transmitting unit configured to transmit the first data stream to a first module and cause the first module to perform the steps of: obtaining a first data segment at the reference granularity from a first position in the first data stream, the first position being an arbitrary position in the first data stream; and performing an AM search on the first data segment; An apparatus having:

17. 10. A communication system comprising a first module and a second module, the first module configured to perform the method of any one of claims 1 to 7, and the second module configured to perform the method of claim 8.

18. A computer system, the computer system having a processor, the processor having a first module or a second module, wherein if the processor has the first module, when the processor executes program instructions or code, the computer system performs the method of any one of claims 1 to 7; or if the processor has the second module, when the processor executes program instructions or code, the computer system performs the method of claim 8.

19. 20. The computer system of claim 18, further comprising a memory, said memory configured to store said program instructions or said code.

20. 10. A computer-readable storage medium storing at least one program instruction or code, the program instruction or code being executed by a computer, the computer having a first module or a second module, wherein if the computer has the first module, the program instruction or code, when executed by the computer, causes the computer to perform the method of any one of claims 1 to 7; or if the computer has the second module, the program instruction or code, when executed by the computer, causes the computer to perform the method of claim 8.

21. 10. A computer program product comprising computer program instructions or code that are executed by a computer, the computer having a first module or a second module, wherein if the computer has the first module, the computer program instructions or code, when executed by the computer, cause the computer to perform the method of any one of claims 1 to 7; or if the computer has the second module, the computer program instructions or code, when executed by the computer, cause the computer to perform the method of claim 8.

22. A chip, the chip having a processor, the processor having a first module or a second module, the processor being configured to execute program instructions or code, wherein if the processor has the first module, a device having the chip performs the method of any one of claims 1 to 7; or if the processor has the second module, a device having the chip performs the method of claim 8.

23. 23. The chip of claim 22, further comprising an input interface, an output interface, and a memory, wherein the input interface, the output interface, the processor, and the memory are connected through internal connection paths, and the memory contains the program instructions or the code.

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