Method for multi-layer die stacking by die-to-wafer bonding

Abstract

[0009] Embodiments of methods for die stacking are described herein. In some embodiments, a method for die stacking by die-wafer bonding includes bonding a plurality of first dies to a substrate by a hybrid bonding process, performing a selective silicon (Si) thinning process to reduce thicknesses of the bonded plurality of first dies to form a plurality of thinned first dies, passivating the plurality of thinned first dies to form a plurality of passivated thinned first dies to protect the plurality of thinned first dies, filling gaps between adjacent dies of the plurality of thinned first dies with a first filler material, wherein the plurality of passivated thinned first dies and the first filler material together form a first layer, and forming a plurality of first conductive vias through the first layer to the substrate.

Description

[Technical Field]

[0001] SUMMARY OF THE INVENTION Embodiments of the present disclosure generally relate to methods for processing substrates. [Background technology]

[0002] Conventional multi-layer die stacking, for example in memory applications, is performed using flip-chip techniques. Such a process involves attaching a semiconductor die bond pad-side down to a substrate or carrier. Electrical connections are made through conductive bumps on the die bond pads. After the die is attached, the separation distance between the die and the substrate is typically filled with a non-conductive adhesive called underfill. The underfill provides stress relief between the die and the carrier, provides robustness, and protects the component from moisture ingress. Summary of the Invention [Problem to be solved by the invention]

[0003] However, the vertical height of the conductive bumps and the underfill process limit the number of stacks of memory or other devices that can be formed while maintaining a maximum form factor (<770 micrometers). Accordingly, the present inventors have described herein embodiments of methods for improving device capacity. [Means for solving the problem]

[0004]

[0006] In some embodiments, a die-to-wafer bonding die stacking method includes: bonding a plurality of first dies to a substrate by a hybrid bonding process; performing a selective silicon (Si) thinning process to reduce thicknesses of the bonded plurality of first dies to form a plurality of thinned first dies; passivating the plurality of thinned first dies to form a plurality of passivated thinned first dies to protect the plurality of thinned first dies; filling gaps between adjacent dies of the plurality of thinned first dies with a first filler material, wherein the plurality of passivated thinned first dies and the first filler material together form a first layer; and forming a plurality of first conductive vias through the first layer to the substrate.

[0005] In some embodiments, a non-transitory computer-readable medium includes instructions that, when executed by one or more processors, perform a method for die stacking by die-wafer bonding, the method including: bonding a plurality of first dies to a substrate by a hybrid bonding process; performing a selective silicon (Si) thinning process to reduce thicknesses of the bonded plurality of first dies to form a plurality of thinned first dies; passivating the plurality of thinned first dies to form a plurality of passivated thinned first dies to protect the plurality of thinned first dies; filling gaps between adjacent dies of the plurality of thinned first dies with a first fill material, wherein the plurality of passivated thinned first dies and the first fill material together form a first layer; and forming a plurality of first conductive vias through the first layer to the substrate.

[0006] In some embodiments, a method for die stacking by die-wafer bonding includes forming a plurality of stacked layers on a substrate, wherein forming each stacked layer of the plurality of stacked layers includes bonding a plurality of dies to a lower layer by a hybrid bonding process, wherein the lower layer is the substrate or one of the plurality of stacked layers; performing a selective silicon (Si) thinning process to reduce thicknesses of the bonded plurality of dies to form a plurality of thinned dies; passivating the plurality of thinned dies to protect the plurality of thinned dies; filling gaps between adjacent dies of the plurality of thinned dies with a filler material; and forming a plurality of conductive vias extending through at least one of the filler material or the plurality of thinned dies and through the plurality of stacked layers.

[0007] Other and additional embodiments of the present disclosure are described below.

[0008] Embodiments of the present disclosure, briefly outlined above and discussed in more detail below, can be understood by reference to exemplary embodiments of the present disclosure illustrated in the accompanying drawings. However, the accompanying drawings depict only typical embodiments of the present disclosure and, therefore, should not be considered limiting in scope, as the present disclosure may embrace other embodiments that are equally effective. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a flow diagram of a method for die stacking by die-to-wafer bonding, in accordance with at least some embodiments of the present disclosure. [Figure 2A] 1 is a schematic cross-sectional side view of multiple dies coupled to a substrate in accordance with at least some embodiments of the present disclosure. [Figure 2B] FIG. 1 is a schematic cross-sectional side view of multiple thinned dies after a selective silicon (Si) thinning process, in accordance with at least some embodiments of the present disclosure. [Figure 2C]1 is a schematic cross-sectional side view of multiple passivated thinned dies with gaps between adjacent dies filled with a filler material, in accordance with at least some embodiments of the present disclosure. [Figure 2D] FIG. 1 is a schematic cross-sectional side view of a planarized first layer, according to at least some embodiments of the present disclosure. [Figure 2E] 1 is a schematic cross-sectional side view of multiple dies bonded to a substrate having bonding and landing pads, in accordance with at least some embodiments of the present disclosure. [Figure 3A] FIG. 1 is a schematic cross-sectional side view of a plurality of conductive vias formed through a plurality of passivated thinned dies by a through-silicon-via (TSV) process, in accordance with at least some embodiments of the present disclosure. [Figure 3B] FIG. 1 is a schematic cross-sectional side view of multiple stacked layers on a substrate, each of the stacked layers including multiple conductive vias formed through multiple passivated thinned dies by a through-silicon via (TSV) process, in accordance with at least some embodiments of the present disclosure. [Figure 4A] FIG. 1 is a schematic cross-sectional side view of a plurality of conductive vias formed through a plurality of passivated thinned dies by a through-dielectric-via (TDV) process, in accordance with at least some embodiments of the present disclosure. [Figure 4B] 1 is a schematic cross-sectional side view of a plurality of bond pads electrically coupled to a plurality of conductive vias, in accordance with at least some embodiments of the present disclosure. [Figure 4C] FIG. 1 is a schematic cross-sectional side view of multiple stacked layers on a substrate, each of the stacked layers including multiple conductive vias formed through a fill material by a dielectric through via (TDV) process, according to at least some embodiments of the present disclosure. [Figure 5]FIG. 1 is a schematic isometric view of a multi-chamber processing tool configured to at least partially perform a method for die stacking by die-wafer bonding according to at least some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0010] To facilitate understanding, the same reference numerals have been used, where possible, to designate identical elements common to the figures. The figures are not drawn to scale and may be simplified for clarity. Elements and features of one embodiment may be beneficially incorporated in other embodiments without additional description.

[0011] Described herein are embodiments of methods for die stacking. The methods described herein use direct hybrid bonding and eliminate the use of conductive bumps and underfill layers during die stacking. Such methods advantageously reduce the vertical height of each die layer, allowing more dies to be stacked while maintaining a fixed maximum form factor of <770 micrometers, consistent with typical silicon wafer thickness. The dies may include one or more integrated circuit (IC) devices. A non-limiting example of an IC device is a memory IC or memory. Thus, the reduced vertical height of each die layer advantageously increases the memory capacity of the stack. Without the use of an underfill layer, the die stack may advantageously have improved stress, improved form factor, and improved heat dissipation for the memory stack.

[0012] FIG. 1 illustrates a flow diagram of a method 100 of die stacking by die-wafer bonding, according to at least some embodiments of the present disclosure. At 102, the method 100 includes bonding a plurality of first dies (e.g., a plurality of first dies 210) to a substrate (e.g., a substrate 202) by a hybrid bonding process, as shown in FIG. 2A. The plurality of dies may be bonded device-side down to the substrate. Bonding the plurality of first dies to the substrate may be performed in a bonding chamber (e.g., a bonder chamber 540). FIG. 2A illustrates a schematic cross-sectional side view of a plurality of first dies 210 bonded to a substrate 202, according to at least some embodiments of the present disclosure. The substrate 202 may include a dielectric layer 204 disposed on a silicon layer 206.

[0013] In some embodiments, the substrate 202 includes one or more bonding pads 208, which may be disposed within the dielectric layer 204, may be aligned with the positions of the plurality of first dies 210, or may be formed on the top surface 218 of the substrate 202. In some embodiments, the one or more bonding pads 208 are made of a conductive material. In some embodiments, the substrate 202 includes one or more bonding pads 208, which may be disposed within the dielectric layer 204 at positions not aligned with the positions of the plurality of first dies 210, or may be formed on the top surface 218 of the substrate 202.

[0014] 2E , the substrate 202 includes one or more landing pads 208B, which may be disposed in the dielectric layer 204 at positions misaligned with the first dies 210 and may be covered with a dielectric material, such as one or more bonding pads 208, and may be formed near the top surface 218 of the substrate 202. The one or more landing pads 208B may be made of a conductive material. The use of one or more landing pads 208B made of a conductive material covered with one or more bonding pads 208 made of a dielectric material advantageously prevents the conductive material from being exposed during subsequent processes (e.g., a silicon thinning process), which could contaminate a process chamber in which the subsequent processes are performed.

[0015] The plurality of first dies 210 are bonded to the substrate 202 by a suitable hybrid bonding process. A hybrid bonding process is generally a process that connects dies using small copper-to-copper connections as opposed to bumps. In some embodiments, the plurality of first dies 210 comprises a silicon layer 212 bonded to a dielectric layer 214. The silicon layer 212 generally includes transistors, such as transistors for front-end-of-line (FEOL) logic or memory functions. The dielectric layer 214 includes back-end interconnects with at least one or more bonding pads 216, which provide connectivity to transistors located in other ones of the stacked dies. In some embodiments, the one or more bonding pads 216 provide connectivity to active transistors forming memory cells. In some embodiments, the one or more bonding pads 216 are aligned with corresponding ones of the one or more bonding pads 208 of the substrate 202. In some embodiments, the thickness of the silicon layer 212 of the plurality of first dies 210 is greater than the thickness of the dielectric layer 214 before bonding to the substrate 202. Such a thickness of the silicon layer 212 advantageously provides a stronger and more reliable bond. In some embodiments, the plurality of first dies 210 have a thickness of about 40 to about 150 micrometers.

[0016] At 104, the method 100 includes performing a selective silicon (Si) thinning process to reduce the thickness of the bonded plurality of first dies to form a plurality of thinned first dies (e.g., a plurality of thinned first dies 210A). The selective Si thinning process includes reducing the thickness of the silicon layer 212. In some embodiments, reducing the thickness of the plurality of first dies includes thinning the plurality of first dies to a thickness of about 2 to about 12 microns. This thinning process may be performed in an etch chamber or other suitable tool, such as a combination of grinding and chemical-mechanical polishing tools.

[0017] 2B shows a schematic cross-sectional side view of multiple thinned first dies 210A after a selective silicon (Si) thinning process, in accordance with at least some embodiments of the present disclosure. In some embodiments, the thinned silicon layer 212A has a thickness that is less than the thickness of the dielectric layer 214.

[0018] At 106, the method 100 includes passivating the plurality of thinned first dies to form a plurality of passivated thinned first dies (e.g., passivated plurality of first dies 210B) as shown in FIG. 2C to protect the plurality of thinned first dies. In some embodiments, the plurality of thinned first dies are passivated with a nitride layer (e.g., nitride layer 224), such as a silicon nitride (SiN) or silicon carbonitride (SiCN) layer. This passivating process may be performed in a suitable deposition chamber, such as a chemical vapor deposition (CVD) chamber. At 108, the method 100 includes filling gaps between adjacent dies of the plurality of thinned first dies with a first fill material (e.g., first fill material 230), as shown in FIG. 2C. The first fill material may be deposited in a suitable deposition chamber, such as a CVD chamber. In some embodiments, the passivation process and the first fill material deposition process are performed in the same chamber. The plurality of passivated thinned first dies and the first filler material together form a first layer (eg, first layer 240).

[0019] FIG. 2C illustrates a schematic cross-sectional side view of a plurality of passivated first dies 210B with a first fill material 230 filling gaps between adjacent dies, in accordance with at least some embodiments of the present disclosure. The first fill material 230 may generally comprise a dielectric material. In some embodiments, the first fill material 230 comprises an organic dielectric material, such as an epoxy mold compound or a polymer. In some embodiments, the first fill material 230 comprises an inorganic material, such as a combination of silicon nitride (SiN) and silicon dioxide (SiO). In some embodiments, the first fill material 230 consists essentially of silicon oxide. In some embodiments, the first fill material 230 consists essentially of an epoxy mold compound or a polymer. In some embodiments, the first fill material 230 covers the plurality of passivated first dies 210B such that there is a thin layer of the first fill material 230 vertically above the plurality of passivated first dies 210B.

[0020] In some embodiments, method 100 includes planarizing the first layer with a suitable planarization process. In some embodiments, the planarization process is a chemical mechanical planarization (CMP) process. FIG. 2D shows a schematic cross-sectional side view of planarized first layer 240A in accordance with at least some embodiments of the present disclosure. In some embodiments, first fill material 230 is planarized so that a small amount of first fill material 230 covers passivated plurality of first dies 210B, as shown in FIG. 2D . In some embodiments, first fill material 230 is planarized so that a top surface of first fill material 230 is flush with a top surface of passivated plurality of first dies 210B. In some embodiments, first fill material 230 and passivated plurality of first dies 210B are planarized, and after planarization, a top surface of first fill material 230 is flush with a top surface of passivated plurality of first dies 210B.

[0021] At 110, method 100 includes forming a plurality of first conductive vias (e.g., a plurality of first conductive vias 310) through the first layer to the substrate. In some embodiments, forming the plurality of first conductive vias is performed as a through-silicon via (TSV) process in which the first conductive vias extend through the plurality of first dies, as shown in FIG. 3A . In some embodiments, forming the plurality of first conductive vias is performed as a through-dielectric via (TDV) process in which the first conductive vias extend through the first fill material but not through the plurality of first dies (i.e., extend outside the plurality of first dies), as shown in FIG. 4A . In some embodiments, the plurality of first vias may be formed in an etch chamber. In some embodiments, for example, when forming the plurality of first vias by a TSV process, the plurality of first vias may be formed in a chemical vapor deposition (CVD) chamber to form a liner oxide. The plurality of first conductive vias may be formed in a physical vapor deposition (PVD) chamber to deposit a barrier metal and a copper seed in the plurality of first vias prior to copper plating to fill the plurality of vias.

[0022] In some embodiments, the method 100 includes forming bond pads (e.g., bond pads 420) electrically coupled to the plurality of conductive vias. In some embodiments, the bond pads 420 are formed by etching the top surface 410 of the first layer 240, 240A and depositing a conductive material. Forming the bond pads 420 facilitates electrical connection between the first layer 240, 240A and one or more bonding pads 208 or one or more landing pads 208B of the substrate 202.

[0023] Figure 3A shows a schematic cross-sectional side view of a plurality of conductive vias 310 formed through a plurality of passivated first dies 210B by a through-silicon via (TSV) process, in accordance with at least some embodiments of the present disclosure. Figure 4A shows a schematic cross-sectional side view of a plurality of conductive vias 310 formed through a plurality of passivated thinned dies by a through-dielectric via (TDV) process, in accordance with at least some embodiments of the present disclosure. Figure 4B shows a schematic cross-sectional side view of a plurality of bond pads (e.g., bond pad 420) electrically coupled to the plurality of conductive vias, in accordance with at least some embodiments of the present disclosure. The plurality of conductive vias 310 may include one or more vias extending from each bond pad of the plurality of bond pads 420.

[0024] Forming the conductive vias 310 with a TSV process advantageously requires minimal design changes, such as minimal design changes to an existing TSV formation process flow. However, forming the conductive vias 310 with a TDV process improves the yield of stacked dies. For example, if the conductive vias 310 extend outside the dies, there is more space within the first dies for additional devices, such as additional memory cells.

[0025] Method 100 may be repeated one or more times to form multiple stacked layers (e.g., multiple stacked layers 330) on substrate 202. For example, method 100 may include bonding multiple second dies to first layer 240A via a hybrid bonding process. Method 100 may also include performing a selective silicon (Si) thinning process to reduce thicknesses of the bonded multiple second dies to form multiple thinned second dies.

[0026] Method 100 may further include passivating the plurality of thinned second dies to form a plurality of passivated thinned second dies (e.g., passivated thinned second dies 210B′) to protect the plurality of thinned second dies. In some embodiments, method 100 includes filling gaps between adjacent dies of the plurality of thinned second dies with a second fill material (e.g., second fill material 230′) comprising a material similar to the first fill material. The plurality of passivated thinned second dies and the second fill material together form a second layer (e.g., second layer 242A). In some embodiments, method 100 includes forming a plurality of second conductive vias (e.g., plurality of second conductive vias 310′) through the second layer. The plurality of second conductive vias are generally aligned with the plurality of first conductive vias. In some embodiments, a plurality of second conductive vias may be formed through the passivated thinned second die, as shown in Figure 3B. In some embodiments, a plurality of second conductive vias may be formed through the second fill material 230', as shown in Figure 4C.

[0027] FIG. 3B further illustrates a third layer 244A disposed on the second layer 242A, the third layer 244A having a plurality of third conductive vias 310″ extending through a plurality of passivated thinned third dies 210B″. FIG. 4C further illustrates a third layer 244A disposed on the second layer 242A, the third layer 244A having a plurality of third conductive vias 310″ extending through a third fill material 230″. Thus, multiple layers having multiple dies may be stacked on top of each other to form multiple stacked layers up to the maximum form factor. For example, each stacked layer of the multiple stacked layers may include bonding multiple dies to a lower layer by a hybrid bonding process, where the lower layer is the substrate 202 or one of the multiple stacked layers (e.g., the first layer 240A, the second layer 242A, the third layer 244A, etc.).

[0028] 5 illustrates a schematic top view of a multi-chamber processing tool configured to at least partially perform a method for die stacking with die-to-wafer bonding according to at least some embodiments of the present disclosure. The multi-chamber processing tool 500 generally includes an Equipment Front End Module (EFEM) 502 and multiple AMMs 510 coupled in series to the EFEM 502. The multiple AMMs 510 are configured to shuttle one or more types of substrates 512 from the EFEM 502 through the multi-chamber processing tool 500 and perform one or more processing steps on the one or more types of substrates 512. Each of the multiple AMMs 510 generally includes a transfer chamber 516 and one or more process chambers 506 coupled to the transfer chamber 516 for performing one or more processing steps. To advantageously provide modular expandability and customization of the multi-chamber processing tool 500, the multiple AMMs 510 are coupled to one another by their respective transfer chambers 516. As shown in FIG. 1, the plurality of AMMs 510 includes three AMMs, a first AMM 510a coupled to the EFEM 502, a second AMM 510b coupled to the first AMM 510a, and a third AMM 510c coupled to the second AMM 510b.

[0029] The EFEM 502 includes a plurality of load ports 514 for receiving one or more types of substrates 512. In some embodiments, the one or more types of substrates 512 include 200 mm wafers, 300 mm wafers, 450 mm wafers, tape frame substrates, carrier substrates, silicon substrates, glass substrates, etc. An EFEM robot 504 is disposed within the EFEM 502 and is configured to transport the substrates 512 between the plurality of load ports 514.

[0030] The one or more process chambers 506 may be sealingly engaged with a transfer chamber 516. The transfer chamber 516 typically operates at atmospheric pressure, but may be configured to operate at vacuum pressure. The transfer chamber 516 includes a buffer 520 configured to hold one or more types of substrates 512. In some embodiments, the buffer 520 is disposed within the interior volume of the transfer chamber 516, which advantageously reduces the overall footprint of the tool. The transfer chamber may include a transfer robot 526 disposed within the transfer chamber and configured to transport substrates 512 between the one or more process chambers 506 and the buffer 520.

[0031] The one or more process chambers 506 may include atmospheric pressure chambers configured to operate under atmospheric pressure and vacuum chambers configured to operate under vacuum pressure. Examples of atmospheric pressure chambers may generally include wet cleaning chambers, radiation chambers, heating chambers, metrology chambers, bonding chambers, etc. Examples of vacuum chambers may include plasma chambers. If desired, atmospheric pressure chambers of the type discussed above may also be configured to operate under vacuum. The one or more process chambers 506 may also be any process chambers or modules necessary to perform bonding processes, dicing processes, cleaning processes, plating processes, etc.

[0032] In some embodiments, one or more process chambers 506 of each AMM of the plurality of AMMs 510 include at least one of a wet cleaning chamber 522, a plasma chamber 530, a degassing chamber 532, a radiation chamber 534, or a bonder chamber 540, such that the multi-chamber processing tool 500 includes at least one wet cleaning chamber 522, at least one plasma chamber 530, at least one degassing chamber 532, at least one radiation chamber 534, and at least one bonder chamber 540.

[0033] The bonder chamber 540 is configured to transfer and bond, for example, to transfer and bond a plurality of first dies 210 to a substrate 202. The bonder chamber 140 may generally include a first support 542 for supporting one of the substrates 202 and a second support 544 for supporting a second substrate, for example, a substrate having a plurality of dies 210 bonded to the substrate 202.

[0034] A controller 580 controls the multi-chamber processing tool 500 described herein. The controller 580 may use direct control of the multi-chamber processing tool 500 or, alternatively, may control a computer (or controller) associated with the multi-chamber processing tool 500. In operation, the controller 580 enables data collection and feedback from the multi-chamber processing tool 500 to optimize performance of the multi-chamber processing tool 500. The controller 580 generally includes a central processing unit (CPU) 582, memory 584, and support circuits 586. The CPU 582 may be any form of general-purpose computer processor that can be used in an industrial environment. The support circuits 586 are conventionally coupled to the CPU 582 and may include cache, clock circuits, input / output subsystems, power supplies, etc. The memory 584 may store software routines, such as methods described below, that, when executed by the CPU 582, may transform the CPU 582 into a special-purpose computer (controller 580). The software routines may also be stored and / or executed by a second controller (not shown) located remotely from the multi-chamber processing tool 500 .

[0035] Memory 584 takes the form of a computer-readable storage medium containing instructions that, when executed by CPU 582, facilitate the operation of semiconductor processes and equipment. The instructions in memory 584 take the form of a program product, such as a program that implements the methods of the present principles. The program code may conform to any one of several different programming languages. In one example, the present disclosure may be embodied as a program product stored on a computer-readable storage medium for use with a computer system. The program in the program product defines the functions of aspects (including the methods described herein). Exemplary computer-readable storage media include, but are not limited to, non-writable storage media having information permanently stored thereon (e.g., a read-only memory device in a computer, such as a CD-ROM disk readable by a CD-ROM drive, flash memory, a ROM chip, or any type of solid-state non-volatile semiconductor memory), and writable storage media having changeable information stored thereon (e.g., a floppy disk or hard disk drive in a diskette drive, or any type of solid-state random-access semiconductor memory). Such computer-readable storage media, when containing computer-readable instructions that direct the functions of the methods described herein, are aspects of the present disclosure.

[0036] While the forgoing is directed to embodiments of the present disclosure, other and further embodiments of the present disclosure may be devised without departing from the basic scope thereof.

Claims

1. 1. A method of die stacking by die-to-wafer bonding, comprising: bonding a plurality of first dies to a substrate by a hybrid bonding process; performing a selective silicon (Si) thinning process to reduce thicknesses of the bonded first dies to form a plurality of thinned first dies; passivating the plurality of thinned first dies to form a plurality of passivated thinned first dies to protect the plurality of thinned first dies; filling gaps between adjacent dies of the plurality of thinned first dies with a first filler material, the plurality of passivated thinned first dies and the first filler material together forming a first layer; forming a plurality of first conductive vias through the first layer to the substrate; A method comprising:

2. The method of claim 1 , further comprising planarizing the first layer before forming the plurality of first conductive vias.

3. 10. The method of claim 1, wherein forming the plurality of first conductive vias is performed as a through-silicon via (TSV) process, wherein the first conductive vias extend through the plurality of first dies.

4. 10. The method of claim 1, wherein forming the plurality of first conductive vias is performed as a through-dielectric-via (TDV) process, wherein the first conductive vias extend through the first fill material and do not extend through the plurality of first dies.

5. 10. The method of claim 1, wherein reducing the thickness of the plurality of first dies comprises thinning the plurality of first dies to a thickness of about 2 to about 12 microns.

6. The method of any of claims 1 to 5, wherein the first fill material consists essentially of silicon oxide, silicon dioxide, an epoxy molding compound, or a polymer.

7. The method according to any one of claims 1 to 5, wherein the plurality of thinned first dies are passivated by a layer of silicon nitride (SiN) or silicon carbonitride (SiCN).

8. bonding a plurality of second dies to the first layer by a hybrid bonding process; performing a selective silicon (Si) thinning process to reduce thicknesses of the bonded second dies to form a plurality of thinned second dies; passivating the plurality of thinned second dies to form a plurality of passivated thinned second dies to protect the plurality of thinned second dies; filling gaps between adjacent dies of the plurality of thinned second dies with a second filler material, the plurality of passivated thinned second dies and the second filler material together forming a second layer; forming a plurality of second conductive vias through the second layer, the plurality of second conductive vias aligned with the plurality of first conductive vias; The method of any one of claims 1 to 5, further comprising:

9. 6. The method of claim 1, wherein passivating the plurality of thinned first dies is performed in a chemical vapor deposition (CVD) chamber, and bonding the plurality of first dies is performed in a bonding chamber.

10. A non-transitory computer readable medium comprising instructions that, when executed by one or more processors, perform the method of any of claims 1 to 5.

11. 11. The non-transitory computer-readable medium of claim 10, wherein the first fill material consists essentially of silicon oxide, silicon dioxide, an epoxy molding compound, or a polymer.

12. 11. The non-transitory computer-readable medium of claim 10, wherein the plurality of thinned first dies are passivated with a layer of silicon nitride (SiN) or silicon carbonitride (SiCN).

13. 11. The non-transitory computer-readable medium of claim 10, wherein passivating the plurality of thinned first dies is performed in a chemical vapor deposition (CVD) chamber and bonding the plurality of first dies is performed in a bonding chamber.

14. bonding a plurality of second dies to the first layer by a hybrid bonding process; performing a selective silicon (Si) thinning process to reduce thicknesses of the bonded second dies to form a plurality of thinned second dies; passivating the plurality of thinned second dies to form a plurality of passivated thinned second dies to protect the plurality of thinned second dies; filling gaps between adjacent ones of the plurality of thinned second dies with a second filler material including an organic dielectric material, the plurality of passivated thinned second dies and the second filler material together forming a second layer; forming a plurality of second conductive vias through the second layer, the plurality of second conductive vias aligned with the plurality of first conductive vias; The non-transitory computer-readable medium of claim 10 further comprising:

15. 1. A method of die stacking by die-to-wafer bonding, comprising: A method comprising forming a plurality of stacked layers on a substrate, wherein forming each stacked layer of the plurality of stacked layers comprises the method of any one of claims 1 to 5.

16. 16. The method of claim 15, wherein the first fill material consists essentially of silicon oxide, silicon dioxide, an epoxy molding compound, or a polymer.

17. 16. The method of claim 15, wherein the plurality of thinned first dies are passivated with a layer of silicon nitride (SiN) or silicon carbonitride (SiCN).

18. 20. The method of claim 17, further comprising forming bond pads electrically coupled to the plurality of conductive vias.

19. The method of claim 15 , wherein the plurality of first dies comprises memory cells.

20. 16. The method of claim 15, wherein the plurality of first dies have a thickness of about 40 to about 150 micrometers, and the plurality of thinned dies have a thickness of about 2 to about 12 micrometers.

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