Circuit board and semiconductor package including same

Abstract

A circuit board according to an embodiment includes an insulating layer including a first layer including a first filler and a second layer arranged on the first layer, a pad portion arranged on the second layer of the insulating layer, and a metal layer arranged on the pad portion, wherein the pad portion includes a first portion that horizontally overlaps the first filler of the first layer and a second portion that does not horizontally overlap the first filler of the first layer.

Description

[Technical Field]

[0001] The embodiments relate to a circuit board and a semiconductor package including the same. [Background technology]

[0002] As the performance of electrical and electronic products continues to improve, technologies are being proposed and researched to accommodate more semiconductor elements on a semiconductor package substrate with limited size. However, because a typical semiconductor package is designed to mount only one semiconductor element, there is a limit to how much performance can be achieved.

[0003] Recently, semiconductor packages have been developed that use multiple substrates to arrange multiple semiconductor devices. These semiconductor packages have a structure in which multiple semiconductor devices are connected to each other horizontally and / or vertically on the substrate. This allows for efficient use of the mounting area of ​​the semiconductor devices, and allows for high-speed signal transmission via short signal transmission paths between the semiconductor devices.

[0004] In addition, semiconductor packages applied to products that provide the Internet of Things (IOT), autonomous vehicles, and high-performance servers are becoming increasingly integrated, with the number of semiconductor elements and / or the size of each semiconductor element increasing. However, due to limitations in reticles, the concept is expanding to semiconductor chiplets, where the functional parts of a semiconductor element are separated.

[0005] This makes intercommunication between semiconductor devices and / or semiconductor chiplets important, which has led to a trend toward placing an interposer between a semiconductor package substrate and a semiconductor device.

[0006] The interposer functions as a redistribution layer that gradually increases the width of a circuit pattern from the semiconductor device toward the semiconductor package in order to facilitate intercommunication between semiconductor devices and / or semiconductor chiplets or to interconnect the semiconductor device and a semiconductor package substrate, thereby facilitating transmission of electrical signals between the semiconductor device and a semiconductor package substrate having a circuit pattern that is relatively larger than the circuit pattern of the semiconductor device.

[0007] Meanwhile, as the pitch of terminals of semiconductor devices becomes finer, electrodes provided on the package substrate and / or interposer are disposed on the uppermost side and have pad portions protruding above the upper surface of the insulating layer, which may be electrodes electrically connected to the terminals of the semiconductor devices.

[0008] The manufacturing process for the package substrate and / or interposer may include etching the top surface of the insulating layer so that pad portions that are entirely embedded within the insulating layer protrude above the insulating layer.

[0009] In this case, the insulating layer may include a reinforcing member such as a filler, and the reinforcing member provided in the insulating layer may cause the upper surface of the insulating layer to have an uneven height after etching. Exemplarily, etching of the upper surface of the insulating layer may be performed using a dry method using plasma or a wet method using chemicals. The resin of the insulating layer may be removed using a dry method using plasma or a wet method using chemicals, but the reinforcing member including SiO2 or TiO2 may not be removed. Therefore, when etching the upper surface of the insulating layer, at least a portion of the reinforcing member provided in the insulating layer may be exposed at the upper surface of the insulating layer or may fall off from the insulating layer.

[0010] Therefore, the upper surface of the insulating layer after etching includes a first region consisting of the resin of the insulating layer removed by the etching, a second region consisting of the exposed reinforcing member, and a third region consisting of the space where the reinforcing member has fallen off. In this case, the insulating layer may have different heights in the first to third regions, and this height deviation may cause a problem of increased dispersion in the adhesion between the insulating layer and the pad portion, which may reduce the reliability of the adhesion between the insulating layer and the pad portion.

[0011] Furthermore, if the height of the upper surface of the insulating layer is uneven, deviations in the height of the metal layer placed on the pad portion may occur, which may result in a problem of the semiconductor element not being placed stably on the pad portion.

[0012] Furthermore, if the reinforcing member is exposed on the upper surface of the insulating layer after etching, the metal layer may come into contact with the reinforcing member of the insulating layer, which may degrade the electrical properties of the metal layer. For example, the dielectric constant of the reinforcing member may be higher than the dielectric constant of the resin of the insulating layer, which may increase the transmission loss of signals transmitted through the metal layer due to the high dielectric constant of the reinforcing member. Furthermore, the adhesion between the reinforcing member and the metal layer may be weaker than the adhesion between the reinforcing member and the resin of the insulating layer, which may reduce the reliability of the adhesion between the metal layer and the insulating layer.

[0013] Therefore, there is a need for a new method that can prevent the reinforcing member from being exposed on the top surface of the insulating layer after etching, improve the flatness of the insulating layer, improve the electrical properties of the electrode portion, and further improve the adhesion between the electrode portion and the insulating layer. Summary of the Invention [Problem to be solved by the invention]

[0014] The embodiments provide a circuit board with improved flatness and a semiconductor package including the same.

[0015] Furthermore, the embodiments provide a circuit board capable of improving the adhesive strength between an insulating layer and an electrode portion, and a semiconductor package including the same.

[0016] Furthermore, the embodiments provide a circuit board capable of improving the electrical characteristics of the electrode portion and a semiconductor package including the same.

[0017] In addition, the present invention provides a circuit board capable of minimizing deviation in height of electrodes and a semiconductor package including the same.

[0018] Furthermore, the present invention provides a circuit board and a semiconductor package including the same that can solve the problem of large warpage in a specific direction.

[0019] In the proposed embodiments, the technical problems to be solved are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by a person having ordinary skill in the art to which the proposed embodiments pertain from the following description. [Means for solving the problem]

[0020] A circuit board according to an embodiment includes an insulating layer including a first layer including a first filler and a second layer arranged on the first layer, a pad portion arranged on the insulating layer, and a metal layer arranged on the pad portion, and the pad portion includes a first portion that overlaps the first filler of the first layer along the horizontal direction and a second portion that does not overlap the first filler of the first layer along the horizontal direction.

[0021] Furthermore, the resin of the first layer and the resin of the second layer of the insulating layer contain the same insulating material.

[0022] The first resin layer and the second resin layer of the insulating layer contain different insulating materials.

[0023] Additionally, the second layer of the insulating layer includes a second filler.

[0024] The diameter of the first filler is the same as the diameter of the second filler.

[0025] Furthermore, the content of the first filler in the first layer of the insulating layer is greater than the content of the second filler in the second layer.

[0026] The diameter of the second filler is smaller than the diameter of the first filler.

[0027] The resin of each of the first and second layers includes any one of Ajinomoto Build-up Film (ABF), FR-4, Bismaleimide Triazine (BT), and Photo Imageable Dielectric resin (PID).

[0028] The pad portion is disposed in a recess provided in the upper surface of the insulating layer.

[0029] The recess has a through hole penetrating the second layer of the insulating layer, and the pad portion is disposed in the through hole.

[0030] The recess further includes a groove portion connected to the through hole and provided on the upper surface of the first layer of the insulating layer, and the pad portion is disposed within the through hole and the groove portion.

[0031] The second portion of the pad overlaps the second layer of the insulating layer in the horizontal direction.

[0032] The second layer of the insulating layer has an uneven portion, and the metal layer has a protrusion corresponding to the uneven portion.

[0033] Furthermore, the curvature of the concave and convex portions is different from the curvature of the first filler.

[0034] The circuit board further includes a protective layer disposed on the metal layer, and the second portion of the pad portion includes a first region that overlaps horizontally with the second layer of the insulating layer, and a second region that is provided on the first region and overlaps horizontally with the protective layer.

[0035] The protective layer also overlaps the metal layer in a vertical direction and has openings penetrating the top and bottom surfaces of the protective layer.

[0036] The horizontal width of the opening is smaller than the horizontal width of at least one of the pad portion and the metal layer.

[0037] The second portion of the pad portion has a slope that increases in width toward the first portion.

[0038] It also includes a separation portion provided between the slope of the second portion and the inner wall of the through hole of the second layer, and the metal layer is disposed within the separation portion and contacts the slope of the second portion and the inner wall of the through hole of the second layer.

[0039] The insulating layer comprises a plurality of insulating layers stacked along a vertical direction, and the uppermost insulating layer of the plurality of insulating layers includes the first layer and the second layer, and the remaining insulating layers of the plurality of insulating layers, excluding the uppermost insulating layer, do not include the second layer.

[0040] The circuit board further includes a connecting member embedded in the insulating layer.

[0041] On the other hand, a semiconductor package according to an embodiment includes the above-mentioned circuit board, a connection portion arranged on a metal layer of the circuit board, and a semiconductor element arranged on the connection portion, and the semiconductor element has a first terminal portion that vertically overlaps the connecting member and a second terminal portion that does not vertically overlap the connecting member. [Effects of the Invention]

[0042] The embodiment can improve the flatness of the circuit board and the semiconductor package including the same, and can stably attach the semiconductor element.

[0043] Specifically, the circuit board and semiconductor package including the circuit board according to the embodiment include an insulating layer including a filler, a pad portion disposed on the insulating layer, and a metal layer disposed on the pad portion. The pad portion includes a first portion that overlaps the filler of the insulating layer in the horizontal direction and a second portion that does not overlap the filler of the insulating layer in the horizontal direction. The insulating layer includes a first layer that includes a reinforcing member and a second layer that does not include a reinforcing member. The first portion of the pad portion overlaps the first layer of the insulating layer in the horizontal direction, and the second portion overlaps the second layer of the insulating layer in the horizontal direction. This allows the second layer to be free of a reinforcing member, making the height of the top surface of the second layer uniform throughout.

[0044] Furthermore, the embodiment can improve the adhesive strength between the metal layer and the insulating layer disposed on the pad portion.

[0045] That is, the upper surface of the insulating layer is located lower than the upper surface of the pad portion. Also, the upper surface of the insulating layer is located higher than the lower surface of the pad portion. That is, at least a portion of the pad portion is embedded in the insulating layer, and at least a remaining portion protrudes above the insulating layer. For this reason, in this embodiment, a process of etching a portion of the insulating layer to reduce its thickness is performed while the upper surface of the insulating layer is located at a height equal to or higher than the upper surface of the pad portion.

[0046] In this case, if a reinforcing member is provided over the entire insulating layer, the flatness of the upper surface of the insulating layer may be reduced during the process of etching the insulating layer to reduce its thickness. That is, if the process of etching the insulating layer to reduce its thickness is performed while the reinforcing member is provided over the entire insulating layer, the reinforcing member provided in the insulating layer may be exposed to the upper side of the insulating layer. Furthermore, if the reinforcing member provided in the insulating layer is exposed to the upper side, the adhesion between the insulating layer and a metal layer (described later) may be reduced. For example, the adhesion between the reinforcing member and the metal layer may be weaker than the adhesion between the resin of the insulating layer and the metal layer. This may reduce the adhesion between the insulating layer and the metal layer, resulting in a problem of the metal layer peeling off from the insulating layer. Furthermore, if the metal layer comes into contact with the reinforcing member, the reinforcing member, which has a relatively high dielectric constant, may cause a loss of electrical signals and / or power transmitted through the metal layer.

[0047] Furthermore, when a process of etching an insulating layer to reduce its thickness is performed while the entire insulating layer is provided with a reinforcing member, at least a portion of the reinforcing member provided in the insulating layer may be removed, resulting in a recess, which is a space created by the removed reinforcing member, being formed on the upper surface of the insulating layer. In this case, the recess may have a depth greater than that of other portions of the upper surface of the insulating layer. As a result, when a recess is formed on the upper surface of the insulating layer, a problem may occur in which the metal layer is not completely filled in the recess, resulting in a void between the insulating layer and the metal layer. Furthermore, when a recess with a relatively large depth is formed on the upper surface of the insulating layer, stress acting on the insulating layer may be concentrated in the recess, which may reduce the physical and / or electrical reliability of the semiconductor package.

[0048] In contrast, the insulating layer of the embodiment includes a first layer and a second layer. The first layer of the insulating layer includes a resin and a reinforcing member, and the second layer includes only a resin without a reinforcing member. Therefore, in the embodiment, the reinforcing member is not exposed on the upper surface of the insulating layer after etching, and the height of the upper surface of the insulating layer can be made uniform.

[0049] Therefore, the embodiment can improve the flatness of the circuit board and the semiconductor package including the same. Furthermore, the embodiment can improve the adhesion between the metal layer and the insulating layer and the electrical characteristics of the metal layer by preventing the metal layer from contacting the reinforcing member disposed on the pad portion.

[0050] Furthermore, in the embodiment, by making the top surface of the insulating layer have a uniform height, it is possible to prevent stress from concentrating at a specific location on the top surface of the insulating layer, and to distribute the stress evenly over the entire area, thereby improving the physical reliability and electrical reliability of the semiconductor package.

[0051] Furthermore, the embodiment can prevent the connection portion disposed on the metal layer from penetrating into the gap between the metal layer and the insulating layer by improving the adhesion between the metal layer and the insulating layer.

[0052] Therefore, the embodiment can suppress the formation of intermetallic compounds (IMCs), which are brittle, between the connection portion and the pad portion, thereby improving the physical reliability and electrical reliability of the semiconductor package.

[0053] In addition, in the embodiment, the insulating layer includes a first layer having a reinforcing member and a second layer having no reinforcing member, thereby preventing the semiconductor package from warping significantly in a specific direction, thereby enabling the semiconductor device to be stably mounted and further enabling the semiconductor device to operate stably.

[0054] Specifically, the circuit board and the semiconductor package including the same may warp significantly in a specific direction. This may be due to factors such as differences in the thermal expansion coefficients between the insulating layer and the protective layer, differences in the thickness of each insulating layer, differences in the density of the electrodes provided on the surface of each insulating layer, differences in the density of the electrodes provided on the surface of each insulating layer, and differences in the thickness of the electrodes provided on the surface of each insulating layer. In this embodiment, a second insulating layer without a reinforcing member is provided on the uppermost side of the substrate. The second insulating layer can match the thermal expansion coefficients of the different insulating layers, thereby preventing the substrate from warping significantly in a specific direction. For example, if the second insulating layer is not provided, both ends of the substrate may warp downward. In this case, the second insulating layer can induce both ends of the substrate to warp upward, thereby ultimately maintaining the substrate in a flat state without warping.

[0055] In addition, an uneven portion is formed on the upper surface of the second insulating layer. The uneven portion may be formed on the upper surface of the second insulating layer by etching the second insulating layer to reduce its thickness. In this embodiment, the uneven portion is formed by etching the second insulating layer, which does not include a reinforcing member. As a result, the reinforcing member does not need to be exposed through the uneven portion, and the uneven portion may have a uniform depth on the upper surface of the second layer. The uneven portion contacts at least a portion of the metal layer disposed on the pad portion. This may further improve adhesion between the insulating layer and the metal layer.

[0056] The uneven portion has a specific curvature. The curvature of the uneven portion is different from the curvature of the reinforcing member provided on the first layer of the insulating layer. Here, the different curvature may mean that the reinforcing member is not exposed to the upper side through the uneven portion. Alternatively, the different curvature may mean that the reinforcing member is not removed from the insulating layer during a process of etching the insulating layer to reduce its thickness, and thus the uneven portion does not include a portion formed by the removal of the reinforcing member. As a result, the embodiment may improve the physical reliability and / or electrical reliability of the semiconductor package. [Brief explanation of the drawings]

[0057] [Figure 1] 1 is a cross-sectional view showing a semiconductor package according to a first embodiment. [Figure 2] 2 is a diagram showing a semiconductor package including a semiconductor element mounted on the circuit board of FIG. 1. [Figure 3a] FIG. 2 is an enlarged view of an area R1 of FIG. 1 according to the first embodiment. [Figure 3b] FIG. 10 is an enlarged view of a region R1 of FIG. 1 according to a second embodiment. [Figure 3c] FIG. 10 is an enlarged view of a region R1 of FIG. 1 according to a third embodiment. [Figure 4] FIG. 10 is a cross-sectional view showing a semiconductor package according to a second embodiment. [Figure 5] FIG. 10 is a cross-sectional view showing a semiconductor package according to a third embodiment. [Figure 6] FIG. 10 is a cross-sectional view showing a semiconductor package according to a fourth embodiment. [Figure 7] FIG. 10 is a cross-sectional view showing a partial region of a semiconductor package according to a fifth embodiment. [Figure 8] FIG. 13 is a cross-sectional view showing a partial region of a semiconductor package according to a sixth embodiment. [Figure 9] FIG. 13 is a cross-sectional view showing a semiconductor package according to a seventh embodiment. [Figure 10] 2A to 2C are diagrams showing a method for manufacturing the semiconductor package shown in FIG. 1 in the order of steps. [Figure 11] 2A to 2C are diagrams showing a method for manufacturing the semiconductor package shown in FIG. 1 in the order of steps. [Figure 12] 2A to 2C are diagrams showing a method for manufacturing the semiconductor package shown in FIG. 1 in the order of steps. [Figure 13] 2A to 2C are diagrams showing a method for manufacturing the semiconductor package shown in FIG. 1 in the order of steps. [Figure 14] 2A to 2C are diagrams showing a method for manufacturing the semiconductor package shown in FIG. 1 in the order of steps. [Figure 15] 2A to 2C are diagrams showing a method for manufacturing the semiconductor package shown in FIG. 1 in the order of steps. [Figure 16] 2A to 2C are diagrams showing a method for manufacturing the semiconductor package shown in FIG. 1 in the order of steps. [Figure 17] 2A to 2C are diagrams showing a method for manufacturing the semiconductor package shown in FIG. 1 in the order of steps. [Figure 18] 2A to 2C are diagrams showing a method for manufacturing the semiconductor package shown in FIG. 1 in the order of steps. [Figure 19] 2A to 2C are diagrams showing a method for manufacturing the semiconductor package shown in FIG. 1 in the order of steps. [Figure 20] 2A to 2C are diagrams showing a method for manufacturing the semiconductor package shown in FIG. 1 in the order of steps. [Figure 21] 2A to 2C are diagrams showing a method for manufacturing the semiconductor package shown in FIG. 1 in the order of steps. [Figure 22] 2A to 2C are diagrams showing a method for manufacturing the semiconductor package shown in FIG. 1 in the order of steps. [Figure 23] 2A to 2C are diagrams showing a method for manufacturing the semiconductor package shown in FIG. 1 in the order of steps. [Figure 24] 2A to 2C are diagrams showing a method for manufacturing the semiconductor package shown in FIG. 1 in the order of steps. DETAILED DESCRIPTION OF THE INVENTION

[0058] Hereinafter, the embodiments disclosed herein will be described in detail with reference to the accompanying drawings. Regardless of the drawing numbers, identical or similar components will be assigned the same reference numerals, and redundant descriptions thereof will be omitted. The suffixes "module" and "unit" used in the following description are used or mixed together solely for the convenience of drafting the specification, and do not have any distinct meanings or roles. Furthermore, in describing the embodiments disclosed herein, if a detailed description of related publicly known technology is deemed to obscure the gist of the embodiments disclosed herein, such a detailed description will be omitted. Furthermore, the accompanying drawings are merely provided to facilitate understanding of the embodiments disclosed herein, and the technical concept disclosed herein should not be limited by the accompanying drawings. It should be understood that the accompanying drawings include all modifications, equivalents, and alternatives within the concept and technical scope of the present invention.

[0059] Terms including ordinal numbers such as first, second, etc. may be used to describe various components, but the components are not limited by the terms. The terms are used only to distinguish one component from another.

[0060] When a component is referred to as being "coupled" or "connected" to another component, it should be understood that it may be directly coupled or connected to the other component, but that there may be other components in between. Conversely, when a component is referred to as being "directly coupled" or "directly connected" to another component, it should be understood that there are no other components in between.

[0061] The singular expression includes the plural expression unless the context clearly indicates otherwise.

[0062] In this application, the use of terms such as "comprises" or "having" is intended to specify the presence of features, numbers, steps, operations, components, parts, or combinations thereof described herein, and should be understood as not precluding the possible presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0063] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0064] -Electronic Devices-

[0065] Before describing the embodiments, an electronic device to which the semiconductor package of the embodiments can be applied will be briefly described. The electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be connected to the semiconductor package of the embodiments. Various semiconductor elements may be mounted in the semiconductor package.

[0066] The semiconductor device may include active and / or passive devices. The active device may be a semiconductor chip in the form of an integrated circuit (IC) in which hundreds to millions of devices are integrated into a single chip. The semiconductor device may be a logic chip, a memory chip, or the like. The logic chip may be a central processor (CPU), a graphics processor (GPU), or the like. For example, the logic chip may be an application processor (AP) chip including at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, a cryptographic processor, a microprocessor, or a microcontroller, or may be an analog-to-digital converter, an application-specific IC (ASIC), or the like, or a chipset including a specific combination of the above.

[0067] The memory chips may be stacked memories such as HBM, and may include volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, and the like.

[0068] The semiconductor element may be an integrated passive device (IPD), a multi-layer ceramic capacitor (MLCC), or a Si-based capacitor.

[0069] Meanwhile, the product group to which the semiconductor package of the embodiment is applied may be any one of CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package On Package), and SIP (System In Package), but is not limited thereto.

[0070] Furthermore, the electronic device may be a smartphone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automobile, etc. However, it is not limited to these, and it may also be any other electronic device that processes data.

[0071] -Semiconductor Package-

[0072] Fig. 1 is a cross-sectional view showing a semiconductor package according to a first embodiment, Fig. 2 is a diagram showing a semiconductor package including a semiconductor element mounted on the circuit board of Fig. 1, Fig. 3a is an enlarged view of a region R1 of Fig. 1 according to the first embodiment, Fig. 3b is an enlarged view of a region R1 of Fig. 1 according to a second embodiment, and Fig. 3c is an enlarged view of a region R1 of Fig. 1 according to a third embodiment.

[0073] Referring to FIGS. 1 to 3c, a semiconductor package includes a substrate.

[0074] The substrate in one embodiment refers to a package substrate. Exemplarily, the substrate is disposed between a main board of an electronic device and the semiconductor elements 320, 330, and can electrically connect them. The substrate can electrically connect the semiconductor elements 320, 330 horizontally and also electrically connect the semiconductor elements 320, 330 and the main board of the electronic device vertically.

[0075] In another embodiment, the substrate refers to an intermediate substrate disposed between the package substrate and the semiconductor elements 320 and 330. Exemplarily, the intermediate substrate may refer to an interposer. That is, the substrate may electrically connect the semiconductor elements 320 and 330 horizontally and electrically connect the semiconductor elements 320 and 330 vertically to the package substrate.

[0076] The semiconductor package includes semiconductor devices 320 and 330 electrically connected on a substrate.

[0077] The semiconductor elements 320, 330 may include, but are not limited to, a first semiconductor element 320 and a second semiconductor element 330. As an example, three or more semiconductor elements may be disposed on the substrate, or only one semiconductor element may be disposed on the substrate.

[0078] The semiconductor package includes a connection portion 310 disposed between the semiconductor elements 320 and 330 and the substrate. The connection portion 310 electrically connects the terminals 325 and 335 of the semiconductor elements 320 and 330 to the electrode portion of the substrate (obviously, the metal layer 140).

[0079] The connection part 310 is formed by using at least one bonding method among wire bonding, solder bonding, and direct metal-to-metal bonding, and electrically connects the electrode part of the substrate and the terminals 325 and 335 of the semiconductor elements 320 and 330 .

[0080] The wire bonding method means that an electrode portion of a substrate and the terminals 325 and 335 of the semiconductor elements 320 and 330 are electrically connected using a conductive wire such as gold (Au).

[0081] The solder bonding method electrically connects the electrodes of the substrate and the terminals 325 and 335 of the semiconductor elements 320 and 330 using a material containing at least one of Sn, Ag, and Cu.

[0082] The metal-to-metal direct bonding method refers to applying heat and pressure between the electrode portion of the substrate and the terminals 325, 335 of the semiconductor elements 320, 330 to recrystallize them without using materials such as solder, wire, or conductive adhesive, thereby directly bonding the electrode portion of the substrate and the terminals 325, 335 of the semiconductor elements 320, 330. In this case, the connection portion 310 may refer to a metal layer provided between the electrode portion of the substrate and the terminals 325, 335 of the semiconductor elements 320, 330 by recrystallization.

[0083] For example, the connection unit 310 may electrically connect the electrode unit of the substrate and the terminals 325, 335 of the semiconductor devices 320, 330 using a thermal compression bonding method. The thermal compression bonding method may reduce the volume of the connection unit 310 and prevent short circuits between multiple connection units. Therefore, the thermal compression bonding method may be advantageous when the terminals 325, 335 of the semiconductor devices 320, 330 and / or the electrode unit of the substrate have a fine pitch.

[0084] According to one embodiment, the semiconductor package includes a connecting member 200 embedded within a substrate.

[0085] The connecting member 200 partially overlaps in the vertical direction with the semiconductor elements 320, 330 disposed on the substrate.

[0086] The connecting member 200 electrically connects a part of the terminal 325 of the first semiconductor element 320 and a part of the terminal 335 of the second semiconductor element 330 .

[0087] A plurality of semiconductor devices having different functions, such as a chiplet unit in which semiconductor devices are functionally separated, or a CPU and a GPU, a GPU and an HBM, may be mounted on a substrate, and the connecting member 200 may serve to electrically connect these devices horizontally.

[0088] In one embodiment, the connecting member 200 is an inorganic bridge. Exemplarily, the inorganic bridge may be a silicon bridge. Exemplarily, the connecting member 200 may include a silicon substrate and a redistribution layer.

[0089] In another embodiment, the connecting member 200 is an organic bridge. Exemplarily, the connecting member 200 may include an organic material. For example, the connecting member 200 may include an organic substrate in which the silicon substrate of the inorganic bridge is replaced with an organic material.

[0090] The connecting member 200 includes a connection pad 210. The connection pad 210 of the connecting member 200 is electrically connected to an electrode portion of the substrate. In addition, the electrode portion of the substrate is electrically connected to the terminals 325 and 335 of the semiconductor elements 320 and 330. Therefore, the connecting member 200 electrically connects the terminals 325 and 335 of the semiconductor elements 320 and 330.

[0091] In addition, a connection member 220 is disposed between the connecting member 200 and the electrode unit 120 of the substrate. The connection member 220 is provided between the connection pads 210 of the connecting member 200 and the electrode unit 120. The connection member 220 can fix the connection pads 210 of the connecting member 200 on the electrode unit 120 and electrically connect them together.

[0092] The substrate electrically connected to the connecting member 200 and the semiconductor elements 320 and 330 will be described in detail below.

[0093] The substrate includes an insulating layer 110. The insulating layer 110 may include an organic material that does not include a reinforcing member, which allows for excellent processability, slimming of the substrate, and miniaturization of the electrode unit 120 provided on the substrate. For example, the insulating layer 110 of the substrate may be made of Ajinomoto Build-up Film (ABF), a product sold by Ajinomoto Co., Inc., or may be made of FR-4, BT (Bismaleimide Triazine), PID (Photo Imageable Dielectric resin), BT, etc.

[0094] The insulating layer 110 may be provided in a form in which a plurality of layers are stacked. For example, as shown in Fig. 1, the insulating layer 110 may include, but is not limited to, first to fourth insulating layers 111, 112, 113, and 114. For example, the insulating layer 110 may be provided with three or less insulating layers, or may be provided with five or more insulating layers.

[0095] In one embodiment, the multiple layers of the insulating layer 110 may be made of the same insulating material, but are not limited to this, and at least one of the multiple layers of the insulating layer 110 may be made of an insulating material that is different from at least the other layers.

[0096] When the insulating layer 110 is formed of multiple layers, it may be difficult to distinguish the interfaces between the multiple layers. In this case, the distinction between the interfaces may be achieved by an electrode unit 120 disposed within the insulating layer 110. The electrode unit 120 includes a first electrode unit 121 and a second electrode unit 122. The first electrode unit 121 is disposed at the interface between the multiple layers of the insulating layer 110. The first electrode unit 121 may include a pad and / or a trace and may be referred to as a wiring electrode unit. The second electrode unit 122 may be referred to as a via electrode unit or a through electrode unit. The second electrode unit 122 electrically connects the first electrodes 121 disposed on different layers in the vertical direction. In this case, the horizontal width of the first electrode unit 121 is different from the horizontal width of the second electrode unit 122. Therefore, the distinction between the multiple interfaces between the multiple layers of the insulating layer 110 may be achieved using the difference between the horizontal widths of the first electrode unit 121 and the second electrode unit 122. Furthermore, the inclination of the side surface of the first electrode portion 121 is different from the inclination of the side surface of the second electrode portion 122. Therefore, the difference between the inclination of the side surface of the first electrode portion 121 and the inclination of the side surface of the second electrode portion 122 can be used to distinguish the multiple interlayer interfaces of the insulating layer 110.

[0097] However, even if the layers of the insulating layer 110 contain the same insulating material, the interfaces between them may be distinct.

[0098] Through the stacked structure of the insulating layer 110, the substrate of the embodiment can electrically connect the semiconductor devices 320 and 330 to the package substrate and / or the main board.

[0099] The insulating layer 110 includes a resin and a reinforcing member provided in the resin. Exemplarily, each of the first to fourth insulating layers 111, 112, 113, and 114 includes a resin and a reinforcing member. Here, the reinforcing member may refer to a filler, which may be distinguished from glass fiber. The reinforcing member may refer to a filler having a predetermined diameter. The reinforcing members may be distributed and arranged in any size in each of the first to fourth insulating layers 111, 112, 113, and 114.

[0100] In this case, the reinforcing members provided in at least one of the first to fourth insulating layers 111, 112, 113, and 114 may have an arrangement structure that is different from the arrangement structures of the reinforcing members provided in at least the other layers. Here, the arrangement structure may refer to the arrangement positions of the reinforcing members provided in the insulating layers. Therefore, a different arrangement structure may mean that the arrangement positions of the reinforcing members provided in at least one insulating layer are different from the arrangement positions of the reinforcing members provided in at least one other insulating layer.

[0101] For example, the reinforcing members provided in at least one of the first to fourth insulating layers 111, 112, 113, and 114 may be arranged in a partial area excluding a specific area from the entire area of ​​the insulating layer in the thickness direction, and the reinforcing members provided in at least another layer may be arranged dispersedly throughout the entire area of ​​the insulating layer in the thickness direction.

[0102] Specifically, the arrangement structure of the reinforcing members provided on the first insulating layer 111, which is arranged on the uppermost side of the semiconductor package among the first to fourth insulating layers 111, 112, 113, and 114, may be different from the arrangement structure of the reinforcing members provided on the second to fourth insulating layers 112, 113, and 114.

[0103] That is, the reinforcing member provided in the first insulating layer 111 may be provided in a partial region of the entire region in the thickness direction of the first insulating layer 111. Exemplarily, the first insulating layer 111 may be divided into a first layer 111-1 and a second layer 111-2 on the first layer 111-1. The first layer 111-1 of the first insulating layer 111 may be a lower region of the first insulating layer 111, and the second layer 111-2 of the first insulating layer 111 may be an upper region of the first insulating layer 111 excluding the first layer 111-1. Here, the first layer 111-1 and the second layer 111-2 of the first insulating layer 111 may be a single insulating layer divided along the thickness direction into a region where the reinforcing member is provided and a region where the reinforcing member is not provided, or may refer to a plurality of layers including layers with reinforcing members and layers without reinforcing members.

[0104] The first layer 111-1 of the first insulating layer 111 includes a resin and reinforcing members 111F provided in the resin. Exemplarily, the reinforcing members 111F are distributed over the entire area of ​​the resin of the first layer 111-1 of the first insulating layer 111.

[0105] Furthermore, the second layer 111-2 of the first insulating layer 111 does not include a reinforcing member. Exemplarily, the second layer 111-2 of the first insulating layer 111 may include only resin, and thus may be referred to as a non-filler resin layer. Here, the non-filler resin layer may refer to a layer that does not include a reinforcing member such as a filler, but is not limited thereto. Exemplarily, the non-filler resin layer may refer to a layer that includes a reinforcing member having a size smaller than that of the reinforcing member of the first layer 111-1 of the first insulating layer 111, or a layer that includes a reinforcing member with a content smaller than that of the reinforcing member of the first layer 111-1 of the first insulating layer 111. The second layer 111-2 of the first insulating layer 111 may be freely used within a range that does not cause problems such as peeling by controlling the difference in thermal expansion rate between the second layer 111-2 and the first layer 111-1 of the first insulating layer 111, in accordance with the technical concept of the present invention.

[0106] Referring to FIGS. 3a to 3c, the second layer 111-2 of the first insulating layer 111 may or may not include a reinforcing member.

[0107] 3a, the first layer 111-1 of the first insulating layer 111 may include a reinforcing member 111F, and the second layer 111-2 of the first insulating layer 111 may not include a reinforcing member. In this case, the non-filler resin layer included in the second layer 111-2 of the first insulating layer 111 may refer to a layer that does not include a reinforcing member. Therefore, according to one embodiment, by using the second layer 111-2 of the first insulating layer 111 that does not include a reinforcing member, a reinforcing member such as a filler is not exposed on the upper side of the first insulating layer 111, thereby improving adhesion between the multiple insulating layers and minimizing electrical loss of the electrode portion.

[0108] 3b, the first layer 111-1 of the first insulating layer 111 may include a first reinforcing member 111F such as a first filler. The second layer 111-2 of the first insulating layer 111 may include a second reinforcing member 111-2F such as a second filler. In this case, the diameter of the first reinforcing member 111F may be the same as the diameter of the second reinforcing member 111-2F. In this case, the content of the second reinforcing member 111-2F in the second layer 111-2 of the first insulating layer 111 may be smaller than the content of the first reinforcing member 111F in the first layer 111-1. Therefore, according to another embodiment, by using the second layer 111-2 of the first insulating layer 111 having a relatively small content of the second reinforcing member 111-2F, a reinforcing member such as a filler may not be exposed on the upper side of the first insulating layer 111, thereby improving adhesion between multiple insulating layers and minimizing electrical loss of the electrode portion.

[0109] 3c, the first layer 111-1 of the first insulating layer 111 may include a first reinforcing member 111F, such as a first filler. The second layer 111-2 of the first insulating layer 111 may include a second reinforcing member 111-2F, such as a second filler. In this case, the diameter of the first reinforcing member 111F may be different from the diameter of the second reinforcing member 111-2F. Preferably, in this case, the diameter of the first reinforcing member 111F may be larger than the diameter of the second reinforcing member 111-2F. In addition, the content of the second reinforcing member 111-2F in the second layer 111-2 of the first insulating layer 111 may be smaller than the content of the first reinforcing member 111F in the first layer 111-1. Therefore, according to another embodiment, the second layer 111-2 of the first insulating layer 111 having the second reinforcing member 111-2F with a relatively small diameter may be used to prevent the reinforcing member, such as a filler, from being exposed on the upper side of the first insulating layer 111, thereby improving the adhesion between the plurality of insulating layers and minimizing electrical loss of the electrode portion. For convenience of explanation, the following description will be given assuming that the second layer 111-2 of the first insulating layer 111 does not have a reinforcing member.

[0110] Therefore, the first insulating layer 111 includes a first layer 111-1 having a reinforcing member 111F and a second layer 111-2 having no reinforcing member, thereby improving the flatness of the semiconductor package and stably attaching the semiconductor device.

[0111] For example, in the embodiment, the second layer 111-2 of the first insulating layer 111 does not include a reinforcing member, thereby making the height of the top surface of the second layer 111-2 uniform overall. Furthermore, the embodiment may improve adhesion with the metal layer 140 disposed on the first insulating layer 111. Furthermore, the embodiment may prevent the semiconductor package from warping significantly in a specific direction. Furthermore, the embodiment may improve the physical reliability and / or electrical reliability of the semiconductor package. Furthermore, as described above, the absence of a reinforcing member in the second layer 111-2 of the first insulating layer 111 may mean that a relatively small content of reinforcing members and / or a reinforcing member with a relatively small diameter may be provided.

[0112] The upper surface of the first insulating layer 111 is located lower than the upper surface of the pad portion 130, which will be described later. In addition, the upper surface of the first insulating layer 111 is located higher than the lower surface of the pad portion 130. That is, at least a portion of the pad portion 130 is embedded in the first insulating layer 111, and at least a remaining portion protrudes above the first insulating layer 111. To this end, in this embodiment, a process of etching a portion of the first insulating layer 111 to reduce its thickness is performed while the upper surface of the first insulating layer 111 is located at a height equal to or higher than the upper surface of the pad portion 130.

[0113] In this case, if the reinforcing member 111F is provided over the entire region of the first insulating layer 111, the flatness of the upper surface of the first insulating layer 111 may be reduced during the process of etching the first insulating layer 111 to reduce its thickness. That is, if the process of etching the first insulating layer 111 to reduce its thickness is performed while the reinforcing member 111F is provided over the entire region of the first insulating layer 111, the reinforcing member provided on the first insulating layer 111 may be exposed to the upper side of the first insulating layer 111. In addition, if the reinforcing member 111F provided on the first insulating layer 111 is exposed to the upper side, the adhesion between the insulating layer 110 and the metal layer 140 (described later) may be reduced. For example, the adhesion between the reinforcing member 111F and the metal layer 140 may be weaker than the adhesion between the resin of the insulating layer 110 and the metal layer 140. This may reduce the adhesion between the insulating layer 110 and the metal layer 140, which may result in a problem of the metal layer 140 peeling off from the insulating layer 110. Furthermore, when the metal layer 140 comes into contact with the reinforcing member 111F, loss of electrical signals and / or power transmitted through the metal layer 140 may occur due to the reinforcing member 111F having a relatively large dielectric constant.

[0114] Furthermore, if the first insulating layer 111 is etched to reduce its thickness while the reinforcing members 111F are provided over the entire area of ​​the first insulating layer 111, at least some of the reinforcing members provided on the first insulating layer 111 may fall off, and as a result, a recess, which is a space where the reinforcing members have fallen off, may be formed in the upper part of the first insulating layer 111. In this case, the recess may have a greater depth than other parts of the upper surface of the first insulating layer 111. As a result, if a recess is provided on the upper surface of the first insulating layer 111, the metal layer 140 may not be completely filled in the recess, and as a result, a void may be formed between the first insulating layer 111 and the metal layer 140. Furthermore, if a recess is provided on the upper surface of the first insulating layer 111, stress acting on the insulating layer 110 may concentrate in the recess, which may reduce the physical and / or electrical reliability of the semiconductor package.

[0115] In contrast, the first insulating layer 111 of the example includes a first layer 111-1 and a second layer 111-2. The first layer 111-1 of the first insulating layer 111 includes a resin and a reinforcing member 111F, and the second layer 111-2 does not include a reinforcing member.

[0116] Therefore, in this embodiment, the reinforcing member 111F can be prevented from being exposed on the upper surface of the first insulating layer 111 after etching, and this makes it possible to make the height of the upper surface of the first insulating layer 111 uniform.

[0117] Therefore, the embodiment can improve the flatness of the semiconductor package. Furthermore, the embodiment can improve the electrical properties of the metal layer 140 by preventing the metal layer 140 disposed on the pad portion 130 from contacting the reinforcing member 111F, thereby improving the adhesion between the metal layer 140 and the insulating layer 110.

[0118] Furthermore, in the embodiment, by making the top surface of the first insulating layer 111 have a uniform height, it is possible to prevent stress from concentrating at a specific position on the top surface of the first insulating layer 111, and to distribute the stress evenly over the entire area, thereby improving the physical reliability and electrical reliability of the semiconductor package.

[0119] In addition, by improving the adhesion between the metal layer 140 and the insulating layer 110, the embodiment can prevent the connection portion 310 arranged on the metal layer 140 from penetrating or diffusing into the gap between the metal layer 140 and the insulating layer 110.

[0120] Therefore, the embodiment can suppress the formation of intermetallic compounds (IMCs), which are not brittle, between the connection portion 310 and the pad portion 130, thereby improving the physical and electrical reliability of the semiconductor package.

[0121] In addition, in the embodiment, the first insulating layer 111 has a first layer 111-1 having a reinforcing member 111F and a second layer 111-2 having no reinforcing member, which is advantageous for warpage control of the semiconductor package and prevents the semiconductor package from warping significantly in a specific direction, thereby allowing the semiconductor element to be stably mounted and further allowing the semiconductor element to operate stably.

[0122] Specifically, when the first insulating layer 111 includes the first layer 111-1 excluding the second layer 111-2, the semiconductor package may warp significantly in a specific direction. This may be due to differences in the thermal expansion coefficients of the insulating layer 110 and the protective layer 170, differences in the thickness of each layer of the insulating layer 110, differences in the density of the electrode portions 120 provided on the surface of each layer of the insulating layer 110, and differences in the thickness of the electrode portions 120 provided on the surface of each layer of the insulating layer 110. In this embodiment, the second layer 111-2 of the first insulating layer 111, which does not include a reinforcing member, is provided on the uppermost side of the substrate. In this case, the thermal expansion coefficient of the second layer 111-2 of the first insulating layer 111 is different from the thermal expansion coefficients of the first layer 111-1, second insulating layer 112, third insulating layer 113, fourth insulating layer 114, and protective layer 170 of the first insulating layer 111. Exemplarily, the second layer 111-2 of the first insulating layer 111 may function as a buffer layer that alleviates the difference in thermal expansion coefficient between the layers of the insulating layer 110 and the protective layer 170. Therefore, the second layer 111-2 of the first insulating layer 111 may perform a thermal expansion coefficient matching function that alleviates the difference in thermal expansion coefficient between the insulating layer 110 and the protective layer 170, thereby preventing the substrate from warping significantly in a specific direction. Exemplarily, the substrate may warp downward at both ends when the second layer 111-2 is not provided on the first insulating layer 111. In this case, the second layer 111-2 provided on the first insulating layer 111 may induce both ends of the substrate to warp upward, thereby ultimately maintaining the substrate in a flat state without warping. Furthermore, the embodiment may easily control the warpage of the substrate by adjusting the thickness of the second layer 111-2 of the first insulating layer 111, thereby improving the physical and / or electrical reliability of the semiconductor package.

[0123] 3a to 3c, an uneven portion 111T is provided on an upper surface of the second layer 111-2 of the first insulating layer 111. The uneven portion 111T may be provided on the upper surface of the second layer 111-2 of the first insulating layer 111 by etching the second layer 111-2 of the first insulating layer 111 to reduce its thickness. In this embodiment, the uneven portion 111T is formed by etching the second layer 111-2 of the first insulating layer 111, which does not include a reinforcing member. As a result, the reinforcing member may not be exposed through the uneven portion 111T, and thus the uneven portion 111T may be provided with a uniform depth on the upper surface of the second layer 111-2. The uneven portion 111T contacts at least a portion of the metal layer 140 disposed on the pad portion 130. As a result, the embodiment may further improve adhesion between the first insulating layer 111 and the metal layer 140.

[0124] The uneven portion 111T has a specific curvature. In this case, the curvature of the uneven portion 111T is different from the curvature of the reinforcing member 111F provided on the first layer 111-1 of the first insulating layer 111. Here, the different curvature may mean that the reinforcing member 111F is not exposed to the upper side through the uneven portion 111T. Alternatively, the different curvature may mean that the reinforcing member 111F is not removed from the first insulating layer 111 during a process of etching the first insulating layer 111 to reduce its thickness, and therefore the uneven portion 111T does not include a recess formed by the removal of the reinforcing member 111F. As a result, the embodiment may improve the physical reliability and / or electrical reliability of the semiconductor package.

[0125] The second layer 111-2 of the first insulating layer 111 has a predetermined thickness T1. The thickness T1 of the second layer 111-2 of the first insulating layer 111 may refer to, but is not limited to, the vertical distance from the upper surface of the second layer 111-2 to the lower surface of the second layer 111-2. Exemplarily, the thickness T1 of the second layer 111-2 may refer to the vertical distance from the bottom surface of the uneven portion 111T to the lower surface of the second layer 111-2.

[0126] In this case, the thickness T1 of the second layer 111-2 is in the range of 1 μm to 5.5 μm. For example, the thickness T1 of the second layer 111-2 is in the range of 1.5 μm to 5.0 μm. For example, the thickness T1 of the second layer 111-2 is in the range of 1.5 μm to 4.5 μm. If the thickness T1 of the second layer 111-2 is less than 1 μm, the effect achieved by the first insulating layer 111 not having a reinforcing member may be insufficient. For example, if the thickness T1 of the second layer 111-2 is less than 1 μm, the effect of improving the flatness of the semiconductor package, the effect of improving the adhesion between the insulating layer and the metal layer, the effect of preventing warpage of the semiconductor package, or the effect of suppressing the formation of intermetallic compounds may be insufficient. Furthermore, if the thickness T1 of the second layer 111-2 is less than 1 μm, at least a portion of the reinforcing member 111F provided in the first region 111-2 of the first insulating layer 111 may be exposed to the upper side due to process deviations in the etching process of the first insulating layer 111. Furthermore, if the thickness T1 of the second layer 111-2 exceeds 5.5 μm, the content of the reinforcing member provided in the first insulating layer 111 may be reduced, which may reduce the rigidity of the circuit board. Furthermore, if the thickness of the first layer 111-1 of the first insulating layer 111 is increased to prevent the rigidity of the circuit board from being reduced, the thickness of the semiconductor package may increase, which may make it difficult to miniaturize the semiconductor package.

[0127] In this case, in one embodiment, the first insulating layer 111 is formed as a single layer. Exemplarily, the first layer 111-1 and the second layer 111-2 of the first insulating layer 111 are formed as a single layer, and in an embodiment, the reinforcing member 111F may be formed only in the first layer 111-1, excluding the second layer 111-2, of the single-layer first insulating layer 111. Exemplarily, in an embodiment, with the reinforcing member 111F disposed in both the first layer 111-1 and the second layer 111-2 of the first insulating layer 111, a metal member having a protrusion may be pressed onto the second layer 111-2 of the first insulating layer 111, thereby allowing the reinforcing member 111F disposed on the second layer 111-2 of the first insulating layer 111 to be transferred to the first layer 111-1 of the first insulating layer 111. Accordingly, the first layer 111-1 of the first insulating layer 111 may be provided with a reinforcing member 111F, and the second layer 111-2 may not be provided with a reinforcing member. In this case, the resin of the first layer 111-1 and the resin of the second layer 111-2 of the first insulating layer 111 may be made of the same material, and therefore the interface between the first layer 111-1 and the second layer 111-2 may not be distinct.

[0128] In another embodiment, the first insulating layer 111 may be formed of multiple layers. Exemplarily, the first insulating layer 111 may have a structure in which a first layer 111-1 and a second layer 111-2 are bonded together. For example, the first insulating layer 111 may include a first layer 111-1 having a reinforcing member and a second layer 111-2 having no reinforcing member stacked on the first layer 111-1. In this case, the resin of the first layer 111-1 and the resin of the second layer 111-2 may contain the same insulating material. In this case, the interface between the first layer 111-1 and the second layer 111-2 may not be distinct. Alternatively, even if the resin of the first layer 111-1 and the resin of the second layer 111-2 contain the same insulating material, the interface between the first layer 111-1 and the second layer 111-2 may be distinct due to a difference in molecular weight at the bonding interface during bonding. Furthermore, the resin of the first layer 111-1 and the resin of the second layer 111-2 may contain different insulating materials, and in this case, the interface between the first layer 111-1 and the second layer 111-2 may be distinct.

[0129] In this case, the resin of the first layer 111-1 and the resin of the second layer 111-2 of the first insulating layer 111 may include any one of a thermosetting resin, a thermoplastic resin, or a photocurable resin, and may be, for example, any one of polyimide (PI), polyethylene terephthalate (PET), propylene glycol, polycarbonate (PC), cyclic olefin copolymer (COC), cyclic olefin polymer (COP), optically isotropic polycarbonate (PC), optically isotropic polymethyl methacrylate (PMMA), Ajinomoto build-up film (ABF), FR-4, bismaleimide triazine (BT), and photoimageable dielectric resin (PID).

[0130] In addition, each of the second insulating layer 112, the third insulating layer 113, and the fourth insulating layer 114, excluding the first insulating layer 111, may be provided with a reinforcing member in the entire area in the thickness direction, thereby improving the rigidity of the substrate.

[0131] 3a to 3c, the interface between the first insulating layer 111 and the second insulating layer 112 has a convex portion 112T that convex toward the upper surface of the first insulating layer 111. Exemplarily, the lower surface of the first insulating layer 111 may have a concave surface that is concave toward the upper surface of the first insulating layer 111, and the upper surface of the second insulating layer 112 may have a convex surface that corresponds to the concave surface of the first insulating layer 111. This is because a groove having a certain depth is formed in the lower surface of the first insulating layer 111, and the second insulating layer 112 can fill the groove formed in the lower surface of the first insulating layer 111, thereby allowing the upper surface of the second insulating layer 112 to have a convex portion 112T.

[0132] The protrusion 112T does not overlap the connecting member 200 in the vertical direction at the interface between the first insulating layer 111 and the second insulating layer 112. For example, the interface between the first insulating layer 111 and the second insulating layer 112 includes an overlapping region that vertically overlaps the connecting member 200. The protrusion 112T may be provided at a position spaced a predetermined distance horizontally from the overlapping region. The protrusion 112T may have a closed loop shape surrounding the periphery of the overlapping region, but is not limited thereto. Exemplarily, the protrusion 112T may be provided in the form of a plurality of convex patterns spaced apart from one another around the overlapping region. The protrusion 112T may function as an align pit for guiding the attachment position of the connecting member 200 during a semiconductor package manufacturing process and for aligning the electrode unit 120 with the connection pad 210 of the connecting member 200. For example, the connecting member 200 may be attached to the electrode unit 120 with the connection pads 210 facing downward, which may make it difficult to accurately align the connection pads 210 of the connecting member 200 with the electrode unit 120. Therefore, in this embodiment, a protrusion 112T corresponding to the alignment pit may be provided at a position where the connecting member 200 is attached, thereby improving the degree of alignment between the connection pads 210 of the connecting member 200 and the electrode unit 120.

[0133] The substrate also includes an electrode portion 120 disposed on the insulating layer 110. The electrode portion 120 includes a first electrode portion 121 and a second electrode portion 122 that are differentiated according to their positions and functions.

[0134] The first electrode portion 121 may be arranged horizontally between each of the multiple layers of the insulating layer 110, and the second electrode portion 122 may be arranged vertically through each of the multiple layers of the insulating layer 110.

[0135] The electrode unit 120 is divided into a plurality of groups. The electrode unit 120 includes a first group of electrode units that vertically overlap the semiconductor elements 320 and 330 and the connecting member 200. The electrode unit 120 also includes a second group of electrode units that horizontally overlap the electrode units of the first group but do not vertically overlap the connecting member 200. The electrode units of the first group vertically overlap the semiconductor elements 320 and 330. That is, the electrode units of the second group are electrode units that vertically overlap the connecting member 200 and the semiconductor elements 320 and 330, respectively, and the electrode units of the first group are electrode units that vertically overlap the semiconductor elements 320 and 330 but do not vertically overlap the connecting member 200.

[0136] At least one of the width of the first electrode portions, the width of the second electrode portions, and the spacing between the horizontally spaced first electrode portions of the first group of electrode portions may be different from the width of the first electrode portions, the width of the second electrode portions, and the spacing between the horizontally spaced first electrode portions of the second group of electrode portions. Exemplarily, at least one of the width of the first electrode portions, the width of the second electrode portions, and the spacing between the horizontally spaced first electrode portions of the first group of electrode portions may be smaller than the width of the first electrode portions, the width of the second electrode portions, and the spacing between the horizontally spaced first electrode portions of the second group of electrode portions.

[0137] Through this, the embodiment can arrange both the first electrode portion and the second electrode portion of the first group of electrode portions within a limited space, and can stably electrically connect the semiconductor elements 320, 330 and the connecting member 200.

[0138] The electrode unit 120 includes a pad unit 130 disposed on the uppermost side of the substrate. The pad unit 130 is provided on the first insulating layer 111. The pad unit 130 is connected to a terminal of the semiconductor device and may accordingly be referred to as a bump. The electrode unit 120 further includes a lower pad unit 150 disposed on the lowermost side of the substrate. The lower pad unit 150 may function as a terminal connected to an external substrate (e.g., a package substrate or a main board).

[0139] The pad portion 130 is disposed in a recess 111R provided in the upper surface of the first insulating layer 111. The recess 111R penetrates the second layer 111-2 of the first insulating layer 111. As a result, the recess 111R includes a through-hole 111R1 (see FIG. 4) that penetrates the second layer 111-2 of the first insulating layer 111. The recess 111R is also provided in a concave shape in the upper surface of the first layer 111-1 of the first insulating layer 111. As a result, the recess 111R includes a groove portion 111R2 (see FIG. 4) that is concavely provided in the upper surface of the first layer 111-1 of the first insulating layer 111, and the through-hole 111R1 that penetrates the second layer 111-2 of the first insulating layer 111. As a result, the pad portion 130 is provided so as to penetrate the second layer 111-2 of the first insulating layer 111.

[0140] The pad unit 130 may be divided into a plurality of sections in the vertical direction. Exemplarily, the pad unit 130 includes a first section that overlaps the reinforcing member of the insulating layer 110 in the horizontal direction and a second section that is located on the first section and does not overlap the reinforcing member of the insulating layer 110 in the horizontal direction. Specifically, the pad unit 130 includes a plurality of first pads 131 that overlap the connecting member 200 in the vertical direction and a plurality of second pads 132 that overlap the first pads 131 in the horizontal direction but do not overlap the connecting member 200 in the vertical direction. Each of the plurality of first pads 131 and the plurality of second pads 132 of the pad unit 130 is disposed in a recess 111R provided on the upper surface of the first insulating layer 111.

[0141] The plurality of first pads 131 include a first portion 131-1 that overlaps the reinforcing member of insulating layer 110 in the horizontal direction and a second portion 131-2 that does not overlap the reinforcing member of insulating layer 110 in the horizontal direction. The plurality of second pads 132 include a first portion 132-1 that overlaps the reinforcing member of insulating layer 110 in the horizontal direction and a second portion 132-2 that does not overlap the reinforcing member of insulating layer 110 in the horizontal direction. In this case, the second portions 131-2 and 132-2 of the plurality of first pads 131 and the plurality of second pads 132 overlap the insulating layer 110 in the horizontal direction but do not overlap the reinforcing member of insulating layer 110 in the horizontal direction. That is, the second portions 131-2 and 132-2 of the plurality of first pads 131 and the plurality of second pads 132 overlap the second layer 111-2 of the first insulating layer 111 in the horizontal direction and do not overlap the reinforcing member 111F provided on the first insulating layer 111 in the horizontal direction. This embodiment can improve the flatness of the semiconductor package and stably attach the semiconductor device. That is, by preventing the second portions 131-2 and 132-2 of the plurality of first pads 131 and the plurality of second pads 132 from overlapping the reinforcing member of the insulating layer 110 in the horizontal direction, the flatness of the metal layer 140 disposed on the first pads 131 and the second pads 132 can be improved, and further, the adhesion between the metal layer 140 and the insulating layer 110 and the adhesion between the metal layer 140 and the pad portion 130 can be improved. Furthermore, the embodiment can minimize stress due to thermal stress transmitted to the second portions 131-2, 132-2 of each of the plurality of first pads 131 and the plurality of second pads 132, thereby improving the physical reliability and / or electrical reliability of the plurality of first pads 131 and the plurality of second pads 132.

[0142] Furthermore, each of the first pads 131 overlaps the connecting member 200 in the vertical direction, and each of the second pads 132 does not overlap the connecting member 200 in the vertical direction, so that they have different horizontal widths. Exemplarily, the horizontal width of each of the first pads 131 may be smaller than the horizontal width of each of the second pads 132. This may improve the circuit integration of the pad unit 130, thereby reducing the length of electrode wires connected to a semiconductor device. Therefore, the embodiment may minimize signal transmission loss, improve signal transmission characteristics, and further reduce the volume of a semiconductor package.

[0143] In addition, the upper surfaces of the first pads 131 and the second pads 132 of the embodiment are located on the same plane, so that the embodiment can stably bond semiconductor elements onto the first pads 131 and the second pads 132.

[0144] The substrate also includes a metal layer 140 disposed on the pad portion 130. The metal layer 140 may be provided on the upper and side surfaces of the pad portion 130. The lower surface of the metal layer 140 contacts the upper surface of the second layer 111-2 of the first insulating layer 111. In this case, the upper surface of the second layer 111-2 is provided with an uneven portion 111T, so that the metal layer 140 may have a protrusion corresponding to the uneven portion 111T.

[0145] Specifically, the metal layer 140 includes a plurality of first metal layers 141 disposed on the plurality of first pads 131 and a plurality of second metal layers 142 disposed on the plurality of second pads 132. Further, a lower surface of each of the plurality of first metal layers 141 includes a convex portion 141B corresponding to the uneven portion 111T provided on the upper surface of the second layer 111-2 of the first insulating layer 111. Further, a lower surface of each of the plurality of second metal layers 142 includes a convex portion 142B corresponding to the uneven portion 111T provided on the upper surface of the second layer 111-2 of the first insulating layer 111. As a result, the embodiment can increase the contact area between the metal layer 140 and the insulating layer 110, thereby improving the adhesion between the metal layer 140 and the insulating layer 110. Furthermore, in the embodiment, the metal layer 140 contacts the second layer 111-2 of the first insulating layer 111, thereby minimizing deviations in height of the top surfaces of the plurality of first metal layers 141 and the plurality of second metal layers 142, thereby stably mounting the semiconductor device. Also, the embodiment improves the adhesion between the plurality of first metal layers 141 and the plurality of second metal layers 142 and the insulating layer 110, thereby preventing intermetallic compounds from penetrating between the connection portion 310 and the pad portion 130, thereby further improving the physical reliability and / or electrical reliability of the semiconductor package.

[0146] The plurality of first metal layers 141 and the plurality of second metal layers 142 may be bonding portions where connection portions 310 such as solder for bonding with a semiconductor element are disposed.

[0147] In this case, the plurality of first metal layers 141 and the plurality of second metal layers 142 may include a metal material different from that of the first pad 131 and the second pad 132. Exemplarily, the plurality of first metal layers 141 and the plurality of second metal layers 142 may include a metal material that prevents an intermetallic compound from permeating in a direction toward the first pad 131 and the second pad 132.

[0148] For example, the first metal layers 141 and the second metal layers 142 may contain nickel. When the first metal layers 141 and the second metal layers 142 contain nickel, the adhesion between the pad unit 130 and the connection unit 310 can be improved and the diffusion of intermetallic compounds can be prevented. For example, intermetallic compounds can have poor mechanical and electrical reliability issues. In particular, when the pad unit 130 contains copper, mechanical and / or electrical reliability issues, such as cracks and / or reduced electrical characteristics, caused by intermetallic compounds can be exacerbated. In this case, when the first metal layers 141 and the second metal layers 142 contain nickel and are provided surrounding the exposed surfaces of the first pads 131 and the second pads 132, the diffusion of the connection unit 310, such as solder, can be prevented, preventing the formation of intermetallic compounds, thereby improving the electrical and mechanical reliability of the semiconductor package. Furthermore, the first metal layers 141 and the second metal layers 142 contact the second layer 111-2 of the first insulating layer 111, which has improved flatness compared to the prior art, thereby further improving adhesion therebetween and further preventing the penetration of intermetallic compounds. The first metal layers 141 and the second metal layers 142 may include metals other than nickel. For example, the first metal layers 141 and the second metal layers 142 may include gold and / or palladium.

[0149] FIG. 4 is a cross-sectional view showing a semiconductor package according to the second embodiment.

[0150] 4, the semiconductor package may differ from the semiconductor package of FIG 1 in the shapes of the pad portion 130 and the metal layer 140. Therefore, hereinafter, the same components as those in the semiconductor package of FIG 1 will be denoted by the same reference numerals, and detailed description thereof will be omitted.

[0151] Referring to FIG. 4, pad portion 130A includes tapered, sloping sides.

[0152] For example, the side surface of the pad portion 130A includes a portion where the slope changes. Here, the portion where the slope changes means that not only the direction of the slope but also the magnitude of the slope changes.

[0153] That is, pad portion 130A includes a first portion 130A-1 that overlaps with first layer 111-1 of first insulating layer 111 along the horizontal direction and thereby overlaps with reinforcing member 111F along the horizontal direction. Pad portion 130A also includes a second portion 130A-2 that overlaps with second layer 111-2 of first insulating layer 111 along the horizontal direction and thereby does not overlap with reinforcing member 111F along the horizontal direction. Second portion 130A-2 of pad portion 130A includes tapered, inclined side surfaces whose width changes along the vertical direction.

[0154] The side of the second portion 130A-2 of the pad portion 130A may include a first slope 130A-2S1 adjacent to the upper surface 130A-2T of the pad portion 130A, the width of which gradually increases toward the lower surface of the pad portion 130A. The side of the second portion 130A-2 of the pad portion 130A also includes a second slope 130A-2S2 different from the first slope 130A-2S1. The second slope 130A-2S2 may be perpendicular to the upper surface 130A-2T or the lower surface of the pad portion 130A, but is not limited to this. The side of the first portion 130A-1 of the pad portion 130A also has the same slope 130A-1S as the second slope 130A-2S2 of the second portion 130A-2. That is, the pad portion 130A includes the first slope 130A-2S1 and the second slope 130A-2S2. 4 illustrates that the second portion 130A-2 of the pad portion 130A includes the first slope 130A-2S1 and the second slope 130A-2S2, and the first insulating layer 111 includes the slope 130A-1 corresponding to the second slope 130A-2S2, but this is not limited thereto. For example, the side surface of the second portion 130A-2 of the pad portion 130A may include only the first slope 130A-2S1 as a whole, and the first portion 130A-1 of the pad portion 130A may include both the first slope and the second slope. Alternatively, the side surface of the second portion 130A-2 of the pad portion 130A may include only the first slope as a whole, and the first portion 130A-1 may include only the second slope as a whole.

[0155] The interior angle between the upper surface 130A-2T of the pad portion 130A and the first slope 130A-2S1 is an obtuse angle. The interior angle between the upper surface 130A-2T of the pad portion 130A and the first slope 130A-2S1 may be in the range of 95 degrees to 160 degrees. The interior angle between the upper surface 130A-2T of the pad portion 130A and the first slope 130A-2S1 may be in the range of 100 degrees to 150 degrees. The interior angle between the upper surface 130A-2T of the pad portion 130A and the first slope 130A-2S1 may be in the range of 105 degrees to 140 degrees. If the interior angle between the upper surface 130A-2T and the first slope 130A-2S1 of the pad portion 130A is less than 95 degrees, the effect of increasing the contact area between the pad portion 130A and the metal layer 140A may be insufficient, which may result in a problem of the metal layer 140A peeling off from the pad portion 130A. For example, the substrate may expand and / or contract due to thermal stress, which may result in a problem of mechanical reliability, such as peeling off of the pad portion 130A and the metal layer 140A. Furthermore, if the interior angle between the upper surface 130A-2T and the first slope 130A-2S1 of the pad portion 130A exceeds 160 degrees, the difference in width between the upper and lower surfaces of the pad portion 130A may increase. Furthermore, as the difference in width between the upper and lower surfaces of the pad portion 130A increases, the transmission loss of signals transmitted through the pad portion 130A may increase, which may result in degradation of signal transmission characteristics. Furthermore, as the width of the upper surface and the width of the lower surface of the pad portion 130A increase, the area of ​​the upper surface of the pad portion 130A may decrease, which may cause a semiconductor element to be stably disposed on the pad portion 130A.

[0156] Additionally, the first slope 130A-2S1 and the second slope 130A-2S2 of the pad portion 130A may be provided by a process of planarizing the pad portion 130A or a pre-processing process prior to forming the metal layer 140A. Through this, the embodiment can minimize changes in the characteristics of signals transmitted through the pad portion 130A. For example, impedance matching can be performed by adjusting the thickness and / or width of the pad portion 130A. If multiple pads of the pad portion 130A have different thicknesses and / or heights due to plating deviations or the like, this can change the impedance characteristics and cause problems with electrical reliability. Therefore, the embodiment includes the pad portion 130A having the first slope 130A-2S1 and the second slope 130A-2S2, thereby improving adhesion between the pad portion 130A and the metal layer 140A and preventing changes in the electrical characteristics of the pad portion 130A. In the embodiment, the pad portion 130A includes a first slope 130A-2S1 and a second slope 130A-2S2 through a planarization process or pretreatment process, thereby improving the flatness of the upper surface of the pad portion 130A and preventing foreign matter from remaining on the upper surface of the pad portion 130A, thereby improving electrical characteristics.

[0157] At this time, at least a portion of the first slope 130A-2S1 of the pad portion 130A does not contact the insulating layer 110. Preferably, at least a portion of the first slope 130A-2S1 of the pad portion 130A may overlap the second layer 111-2 of the first insulating layer 111 in the horizontal direction while not contacting the second layer 111-2.

[0158] That is, the pad portion 130A is provided in a recess 111R provided in the first insulating layer 111. The recess 111R includes a through hole 111R1 penetrating the second layer 111-2 of the first insulating layer 111 and a groove portion 111R2 provided in the first layer 111-1. In this case, an inner wall of the through hole 111R1 in the second layer 111-2 and the first slope 130A-2S1 of the pad portion 130A may be spaced a predetermined distance apart in the horizontal direction. For example, a separation portion may be provided between the inner wall of the through hole 111R1 in the second layer 111-2 and the first slope 130A-2S1 of the pad portion 130A.

[0159] This allows the metal layer 140A to contact the first slope 130A-2S1 of the pad portion 130A and the inner wall of the through-hole 111R1 of the second layer 111-2. That is, the metal layer 140A may be provided to fill the gap. That is, the metal layer 140A may be provided to cover the first slope 130A-2S1 of the pad portion 130A. The side surface of the metal layer 140A has a slope 140AS corresponding to the first slope 130A-2S1 of the pad portion 130A.

[0160] As a result, the embodiment can further improve the adhesion between the insulating layer 110, the pad portion 130A, and the metal layer 140A, thereby improving the electrical reliability and / or mechanical reliability of the semiconductor package.

[0161] FIG. 5 is a cross-sectional view showing a semiconductor package according to the third embodiment.

[0162] 5, the semiconductor package may differ from the semiconductor package of FIG 4 in that it further includes a protective layer 180 disposed on the metal layer 140A. Therefore, hereinafter, the same components as those in the semiconductor package of FIG 4 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0163] The semiconductor package further includes a protective layer 180 disposed on the insulating layer 110 .

[0164] The protective layer 180 is disposed on the second layer 111-2 of the first insulating layer 111. The protective layer 180 is also disposed on the metal layer 140A.

[0165] The protective layer 180 has an opening 180R. The opening 180R vertically overlaps the metal layer 140A. Therefore, at least a portion of the upper surface of the metal layer 140A is not covered by the protective layer 180. Furthermore, the portion of the upper surface of the metal layer 140A that is not covered by the protective layer 180 can function as a bump that is electrically coupled to a semiconductor element.

[0166] When the protective layer 180 is provided, the process of disposing the connection portion 310 on the metal layer 140A in this embodiment can solve the problem of electrical shorts caused by adjacent connection portions being connected to each other, thereby further improving the electrical reliability of the semiconductor package. In addition, by further disposing the protective layer 180 on the second layer 111-2 of the first insulating layer 111, it can be more advantageous to control warpage of the semiconductor package, thereby improving the physical reliability and / or electrical reliability of the semiconductor package.

[0167] The protective layer 180 includes a protrusion 180B. That is, the protective layer 180 includes the protrusion 180B filling the uneven portion 111T provided on the upper surface of the second layer 111-2 of the first insulating layer 111. This configuration further improves the adhesion between the protective layer 180 and the insulating layer 110, thereby solving the problem of the protective layer 180 peeling off from the insulating layer 110, and at least a portion of the metal layer 140A can be stably protected by the protective layer 180. Furthermore, since the protective layer 180 is disposed to cover at least a portion of the metal layer 140A, it can further prevent an intermetallic compound from penetrating into the interface between the insulating layer 110 and the metal layer 140A, thereby further improving the physical reliability and / or mechanical reliability of the semiconductor package.

[0168] FIG. 6 is a cross-sectional view showing a semiconductor package according to a fourth embodiment.

[0169] 6, the semiconductor package may differ from the semiconductor package of FIG 5 in that the width of the opening formed in the protective layer is larger than the width of the metal layer 140A. Therefore, hereinafter, the same components as those in the semiconductor package of FIG 5 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0170] The semiconductor package further includes a protective layer 180A disposed on the insulating layer 110.

[0171] The protective layer 180A is disposed on the second layer 111-2 of the first insulating layer 111. The protective layer 180A is also disposed on the metal layer 140A.

[0172] The protective layer 180A includes an opening 180AR that vertically overlaps the metal layer 140A. The horizontal width of the opening 180AR may be greater than the horizontal width of the metal layer 140A. For example, the metal layer 140A may not contact the protective layer 180A.

[0173] As a result, the embodiment can increase the volume of the connection portion 310 disposed on the metal layer 140A, thereby improving the bonding strength with the semiconductor device.

[0174] FIG. 7 is a cross-sectional view showing a partial region of a semiconductor package according to a fifth embodiment.

[0175] 7, the semiconductor package may differ from the semiconductor package of FIG 6 in that the metal layer penetrates the protective layer and protrudes above the protective layer. Therefore, hereinafter, the same components as those in the semiconductor package of FIG 6 will be denoted by the same reference numerals, and detailed description thereof will be omitted.

[0176] The semiconductor package includes a metal layer 140B disposed on the pad portion 130A.

[0177] In this case, the metal layer 140B may differ from the previous embodiment in that it is formed after the protective layer 180B is formed, and therefore the metal layer 140B may penetrate the protective layer 180B and protrude above the protective layer 180B.

[0178] The width of the opening in the protective layer 180B is greater than the width of the pad portion 130A. This allows a step to be formed between the inner wall of the opening in the protective layer 180B and the inner wall of the through-hole 111R1 provided in the second layer 111-2 of the first insulating layer 111.

[0179] The metal layer 140B is disposed on the pad portion 130A. The metal layer 140B is also disposed on the protective layer 180B. The metal layer 140B may protrude above the protective layer 180B while filling the openings in the protective layer 180B. Therefore, the metal layer 140B may be divided into a plurality of regions along the vertical direction.

[0180] The metal layer 140B may include a first portion 140B1 protruding above the protective layer 180B. The horizontal width of the first portion 140B1 of the metal layer 140B is greater than the width of the opening in the protective layer 180B. Therefore, at least a portion of the first portion 140B1 of the metal layer 140B contacts the upper surface of the protective layer 180B. The side surface of the first portion 140B1 of the metal layer 140B may have a slope such that the width increases downward.

[0181] Additionally, the metal layer 140B includes a second portion 140B2 that passes through the opening in the protective layer 180B. The second portion 140B2 of the metal layer 140B contacts the inner wall of the opening in the protective layer 180B.

[0182] The metal layer 140B also includes a third portion 140B3 that fills the space between the inner wall of the through-hole 111R1 of the second layer 111-2 of the first insulating layer 111 and the first slope 130A-2S1 of the pad portion 130A.

[0183] As a result, the side surfaces of the metal layer 140B may have steps in the horizontal direction. For example, the side surfaces of the first to third portions of the metal layer 140B may have steps. This may further increase the contact area between the metal layer 140B and the protective layer 180B or the pad unit 130A, thereby further improving the adhesion therebetween.

[0184] In addition, the metal layer 140B protrudes above the protective layer 180B, thereby improving the alignment between the metal layer 140B and the terminals of the semiconductor device. For example, in the embodiment, when thermal compression bonding is performed to reduce the volume of a connecting member such as solder, the metal layer 140B is disposed to protrude above the protective layer 180B, thereby improving the alignment between the terminals of the semiconductor device and the metal layer 140B during the thermal compression bonding process.

[0185] Furthermore, in the embodiment, since the first insulating layer 111 comprises a first layer 111-1 and a second layer 111-2, the flatness of the upper surface of the protective layer 180B disposed on the second layer 111-2 can be improved, and thereby the flatness of the metal layer 140B disposed on the protective layer 180B can be improved.

[0186] FIG. 8 is a cross-sectional view showing a partial region of a semiconductor package according to a sixth embodiment.

[0187] 8, the semiconductor package differs from the semiconductor package of FIG 7 in that the width of the opening in the protective layer is smaller than the width of the pad portion. Therefore, hereinafter, the same components as those in the semiconductor package of FIG 7 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0188] The protective layer 180C is disposed on the second layer 111-2 of the first insulating layer 111 and the pad portion 130A. At this time, the width of the opening of the protective layer 180C is smaller than the width of the upper surface of the second portion 130A-2 of the pad portion 130A. As a result, the protective layer 180C can be provided by filling the space between the inner wall of the through-hole 111R1 of the second layer 111-2 of the first insulating layer 111 and the first inclined surface 130A-2S1 of the side surface of the pad portion 130A.

[0189] The metal layer 140C is disposed on the pad portion 130A. The metal layer 140C is also disposed on the protective layer 180C. The metal layer 140C includes a first portion 140C1 disposed on the protective layer 180C and a second portion 140C2 penetrating the protective layer 180C. The widths of the first portion 140C1 and the second portion 140C2 of the metal layer 140C are smaller than the width of the pad portion 130A. This allows the embodiment to further reduce the width of the metal layer 140C, thereby reducing the pitch between adjacent metal layers. Furthermore, while maintaining the pitch between adjacent metal layers the same as in the previous embodiment, the embodiment allows the spacing between adjacent metal layers to be increased, thereby resolving the problem of electrical shorts occurring when multiple metal layers are connected to each other.

[0190] FIG. 9 is a cross-sectional view showing a semiconductor package according to the seventh embodiment.

[0191] 9, the semiconductor package of the seventh embodiment may have a difference in thickness of the second layer 111-2 of the first insulating layer 111 compared to the semiconductor package of the second embodiment of FIG.

[0192] That is, the semiconductor package of the seventh embodiment includes an insulating layer 110. The insulating layer 110 includes a first insulating layer 111 arranged on the uppermost side.

[0193] The first insulating layer 111 includes a first layer 111-1 that includes a reinforcing member and a second layer 111-2 that does not include a reinforcing member.

[0194] In this case, the upper surface of the first layer 111-1 is positioned lower than the lower surface of the pad portion 130A. Furthermore, the lower surface of the second layer 111-2 is positioned lower than the lower surface of the pad portion 130A. As a result, the pad portion 130A does not need to overlap the reinforcing member of the pad portion 130A in the horizontal direction as a whole. For example, the pad portion 130A does not need to overlap the first layer 111-1 of the first insulating layer 111 in the horizontal direction, and may overlap the second layer 111-2 in the horizontal direction. Furthermore, at least a portion of the side surface of the second electrode portion 122 penetrating the first layer 111-1 may be surrounded by the second layer 111-2 of the first insulating layer 111.

[0195] Through this, the embodiment can control the warpage characteristics of the semiconductor package by increasing the thickness of the second layer 111-2 of the first insulating layer 111, thereby solving the problem of the semiconductor package warping significantly in a specific direction.

[0196] The embodiment can improve the flatness of the semiconductor package and allow the semiconductor element to be stably attached.

[0197] Specifically, the semiconductor package of the embodiment includes an insulating layer including a filler, a pad portion disposed on the insulating layer, and a metal layer disposed on the pad portion. The pad portion includes a first portion that overlaps the filler of the insulating layer in the horizontal direction and a second portion that does not overlap the filler of the insulating layer in the horizontal direction. The insulating layer includes a first layer that includes a reinforcing member and a second layer that does not include a reinforcing member. The first portion of the pad portion overlaps the first layer of the insulating layer in the horizontal direction, and the second portion overlaps the second layer of the insulating layer in the horizontal direction. This allows the second layer to be free of a reinforcing member, making the height of the top surface of the second layer uniform throughout.

[0198] Furthermore, the embodiment can improve the adhesive strength between the metal layer and the insulating layer disposed on the pad portion.

[0199] That is, the upper surface of the insulating layer is located lower than the upper surface of the pad portion. Also, the upper surface of the insulating layer is located higher than the lower surface of the pad portion. That is, at least a portion of the pad portion is embedded in the insulating layer, and at least a remaining portion protrudes above the insulating layer. For this reason, in this embodiment, a process of etching a portion of the insulating layer to reduce its thickness is performed while the upper surface of the insulating layer is located at a height equal to or higher than the upper surface of the pad portion.

[0200] In this case, if a reinforcing member is provided over the entire insulating layer, the flatness of the upper surface of the insulating layer may be reduced during the process of etching the insulating layer to reduce its thickness. That is, if the process of etching the insulating layer to reduce its thickness is performed while the reinforcing member is provided over the entire insulating layer, the reinforcing member provided in the insulating layer may be exposed to the upper side of the insulating layer. Furthermore, if the reinforcing member provided in the insulating layer is exposed to the upper side, the adhesion between the insulating layer and a metal layer (described later) may be reduced. For example, the adhesion between the reinforcing member and the metal layer may be weaker than the adhesion between the resin of the insulating layer and the metal layer. This may reduce the adhesion between the insulating layer and the metal layer, resulting in a problem of the metal layer peeling off from the insulating layer. Furthermore, if the metal layer comes into contact with the reinforcing member, the reinforcing member, which has a relatively high dielectric constant, may cause a loss of electrical signals and / or power transmitted through the metal layer.

[0201] Furthermore, when a process of etching an insulating layer to reduce its thickness is performed while the entire insulating layer is provided with a reinforcing member, at least a portion of the reinforcing member provided in the insulating layer may be removed, resulting in a recess, which is a space created by the removed reinforcing member, being formed on the upper surface of the insulating layer. In this case, the recess may have a depth greater than that of other portions of the upper surface of the insulating layer. As a result, when a recess is formed on the upper surface of the insulating layer, a problem may occur in which the metal layer is not completely filled in the recess, resulting in a void between the insulating layer and the metal layer. Furthermore, when a recess with a relatively large depth is formed on the upper surface of the insulating layer, stress acting on the insulating layer may be concentrated in the recess, which may reduce the physical and / or electrical reliability of the semiconductor package.

[0202] In contrast, the insulating layer of the embodiment includes a first layer and a second layer. The first layer of the insulating layer includes a resin and a reinforcing member, and the second layer includes only a resin without a reinforcing member. Therefore, in the embodiment, the reinforcing member is not exposed on the upper surface of the insulating layer after etching, and the height of the upper surface of the insulating layer can be made uniform.

[0203] Therefore, the embodiment can improve the flatness of the semiconductor package. Furthermore, the embodiment can improve the electrical properties of the metal layer by preventing the metal layer disposed on the pad portion from contacting the reinforcing member, thereby improving the adhesion between the metal layer and the insulating layer.

[0204] Furthermore, in the embodiment, by making the top surface of the insulating layer have a uniform height, it is possible to prevent stress from concentrating at a specific location on the top surface of the insulating layer, and to distribute the stress evenly over the entire area, thereby improving the physical reliability and electrical reliability of the semiconductor package.

[0205] Furthermore, the embodiment can prevent the connection portion disposed on the metal layer from penetrating into the gap between the metal layer and the insulating layer by improving the adhesion between the metal layer and the insulating layer.

[0206] Therefore, the embodiment can suppress the formation of intermetallic compounds (IMCs), which are brittle, between the connection portion and the pad portion, thereby improving the physical reliability and electrical reliability of the semiconductor package.

[0207] In addition, in the embodiment, the insulating layer includes a first layer having a reinforcing member and a second layer having no reinforcing member, thereby preventing the semiconductor package from warping significantly in a specific direction, thereby enabling the semiconductor device to be stably mounted and further enabling the semiconductor device to operate stably.

[0208] Specifically, the semiconductor package may warp significantly in a specific direction. This may be due to factors such as differences in the thermal expansion coefficients of the insulating layer and the protective layer, differences in the thickness of each insulating layer, differences in the density of the electrodes provided on the surface of each insulating layer, differences in the density of the electrodes provided on the surface of each insulating layer, and differences in the thickness of the electrodes provided on the surface of each insulating layer. In this embodiment, a second insulating layer without a reinforcing member is provided on the uppermost side of the substrate. The second insulating layer can match the thermal expansion coefficients of the different insulating layers, thereby preventing the substrate from warping significantly in a specific direction. For example, if the second insulating layer is not provided, both side edges of the substrate may warp downward. In this case, the second insulating layer can induce both side edges of the substrate to warp upward, thereby ultimately maintaining the substrate in a flat state without warping.

[0209] In addition, an uneven portion is formed on the upper surface of the second insulating layer. The uneven portion may be formed on the upper surface of the second insulating layer by etching the second insulating layer to reduce its thickness. In this embodiment, the uneven portion is formed by etching the second insulating layer, which does not include a reinforcing member. As a result, the reinforcing member does not need to be exposed through the uneven portion, and the uneven portion may have a uniform depth on the upper surface of the second layer. The uneven portion contacts at least a portion of the metal layer disposed on the pad portion. This may further improve adhesion between the insulating layer and the metal layer.

[0210] The uneven portion has a specific curvature. The curvature of the uneven portion is different from the curvature of the reinforcing member provided on the first layer of the insulating layer. Here, the different curvature may mean that the reinforcing member is not exposed to the upper side through the uneven portion. Alternatively, the different curvature may mean that the reinforcing member is not removed from the insulating layer during a process of etching the insulating layer to reduce its thickness, and thus the uneven portion does not include a portion formed by the removal of the reinforcing member. As a result, the embodiment may improve the physical reliability and / or electrical reliability of the semiconductor package.

[0211] 10 to 24 are diagrams showing the manufacturing method of the semiconductor package shown in FIG. 1 in the order of steps.

[0212] Referring to FIG. 10 , an embodiment provides an insulating member serving as a base for manufacturing a circuit board. The insulating member may be a carrier board CB. For example, the carrier board CB may include a carrier insulating layer CB1 and carrier metal layers CB2 and CB3. The carrier metal layers CB2 and CB3 may have a two-layer structure. For example, the carrier metal layers CB2 and CB3 may be metal layers including different metal materials. A first carrier metal layer CB2 may be disposed below the carrier insulating layer CB1. The first carrier metal layer CB2 may include a first metal material. The first metal material may include copper. The carrier insulating layer CB1 and the first carrier metal layer CB2 may be a copper clad laminate (CCL). A second carrier metal layer CB3 may be disposed below the first carrier metal layer CB2. The second carrier metal layer CB3 may include a second metal material different from the first metal material. The second metal material may include nickel. For example, the second carrier metal layer CB2 may be formed of a metal material that is not etched by the etchant used to etch the first metal material. This prevents the pad portion 130 from being etched during a seed layer etching process included in a circuit board manufacturing process. This minimizes height deviations between the first and second pads of the pad portion 130. While FIG. 10 illustrates the first and second carrier metal layers CB2 and CB3 disposed on one side of the carrier insulating layer CB1, this is not limiting. For example, the first and second carrier metal layers CB2 and CB3 may be disposed on both sides of the carrier insulating layer CB1, respectively. In this case, a process for simultaneously manufacturing multiple circuit boards may be performed on both sides of the carrier insulating layer CB1.

[0213] 11, in this embodiment, a process of forming a pad unit 130 on the second carrier metal layer CB3 may be performed. The pad unit 130 may be formed by performing electrolytic plating using the second carrier metal layer CB3 as a seed layer.

[0214] 12, in this embodiment, a process of stacking a second layer 111-2 of the first insulating layer 111 on the second carrier metal layer CB3 to cover a portion of the pad portion 130 may be performed. The second layer 111-2 does not include a reinforcing member. In this case, the second layer 111-2 may be disposed to cover the entire pad portion 130, and then etched to reduce its thickness, so that a portion of the side of the pad portion 130 may be covered.

[0215] 13, in this embodiment, a process of stacking the first layer 111-1 of the first insulating layer 111 on the second layer 111-2 may be performed. At this time, the first layer 111-1 and the second layer 111-2 may be stacked separately, but this is not limited to this. For example, if the first layer 111-1 and the second layer 111-2 are provided as one single layer, the processes of FIGS. 12 and 13 may be performed at the same time.

[0216] 14, in the embodiment, a process of forming the electrode unit 120 on the first insulating layer 111 may be performed. At this time, in the embodiment, when forming the electrode unit 120, a recess 111T may be formed on a surface of the first layer 111-1 of the first insulating layer 111. At this time, the recess 111T may be provided surrounding the periphery of the electrode unit that vertically overlaps with the connecting member 200 among the electrode units.

[0217] Next, referring to FIG. 15, in this embodiment, a process of arranging the connection member 220 on the electrode portion and a process of attaching the linking member 200 can be performed using the recess 111T as an alignment pit.

[0218] Next, referring to FIG. 16, in this embodiment, the insulating layer laminating step and the electrode portion forming step are repeatedly performed to manufacture a multilayer substrate.

[0219] 17, an embodiment may perform a process of removing the carrier board CB. To this end, an embodiment may perform a process of removing the carrier insulating layer CB1. Then, an embodiment may perform a process of removing the first carrier metal layer CB2. In this case, the second carrier metal layer CB3 may include a different metal material from the first carrier metal layer CB2, and therefore may not be removed in the process of removing the first carrier metal layer CB2.

[0220] 18, in this embodiment, a process of removing the second carrier metal layer CB3 by etching may be performed. At this time, the second carrier metal layer CB3 includes a metal material different from that of the pad portion 130, so that the pad portion 130 may not be removed in the process of removing the second carrier metal layer CB3.

[0221] 19, a process of thinning the thickness of the second layer 111-2 may be performed by etching a portion of the second layer 111-2 of the first insulating layer 111. As a result, the top surface of the second layer 111-2 of the first insulating layer 111 may be positioned lower than the top surface of the pad unit 130. Furthermore, the second layer 111-2 does not include a reinforcing member, and as a result, the pad unit 130 includes a region that overlaps the second layer 111-2 in the horizontal direction but does not overlap the reinforcing member in the horizontal direction.

[0222] In this manner, the embodiment can form a first insulating layer 111 that is positioned lower than the top surface of the pad portion 130 and includes a first layer 111-1 having a reinforcing member and a second layer 111-2 not having a reinforcing member.

[0223] At this time, in FIGS. 10 to 19, the substrate manufacturing process is carried out in a state where the second layer 111-2 of the first insulating layer 111 is preferentially stacked, but the present invention is not limited to this.

[0224] 12. In this case, as shown in FIG. 20, after removing the carrier substrate, the first layer 111-1 of the first insulating layer 111 may be provided while entirely covering the side surface of the pad portion 130.

[0225] 21, in this embodiment, a process of thinning the first layer 111-1 of the first insulating layer 111 by etching may be performed, so that the first layer 111-1 of the first insulating layer 111 is positioned lower than the top surface of the pad portion 130.

[0226] 22, in this embodiment, a process of stacking a second layer 111-2 on the first layer 111-1 of the first insulating layer 111 is performed. At this time, the second layer 111-2 may be provided to entirely cover the top surface of the pad portion 130.

[0227] 23, in this embodiment, a process of thinning the second layer 111-2 by etching may be performed, so that the top surface of the second layer 111-2 may be positioned lower than the top surface of the pad portion 130.

[0228] 24, in this embodiment, a process of forming a metal layer 140 on the pad portion 130 may be performed. In addition, in this embodiment, a process of forming a protection layer 170 under the fourth insulating layer 114 and a process of forming a lower metal layer 160 under the lower pad portion 150 may be performed.

[0229] Meanwhile, when a circuit board having the above-described inventive features is used in IT devices or home appliances such as smartphones, server computers, and TVs, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the features of the present invention functions as a semiconductor package, it can safely protect the semiconductor chip from external moisture and contaminants, and can solve problems such as leakage current, electrical shorts between terminals, and electrical open circuits in terminals supplying power to the semiconductor chip. Furthermore, when it performs the signal transmission function, it can solve noise problems. As a result, the circuit board having the above-described inventive features can maintain stable functionality of IT devices and home appliances, and the entire product and the circuit board to which the present invention is applied can achieve functional integration or technical interrelationship with each other.

[0230] When a circuit board having the above-described features of the present invention is used in a transportation device such as a vehicle, it can solve the problem of distortion of signals transmitted to the transportation device, safely protect the semiconductor chip that controls the transportation device from the outside, and solve the problems of leakage current, electrical short circuits between terminals, and electrical open circuits of terminals supplying power to the semiconductor chip, thereby further improving the stability of the transportation device. Therefore, the transportation device and the circuit board to which the present invention is applied can be functionally integrated or technically linked with each other.

[0231] The features, structures, effects, etc. described in the above embodiments are included in at least one embodiment and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by a person skilled in the art to which the embodiment belongs. Therefore, content related to such combinations and modifications should be interpreted as being included in the scope of the embodiments.

[0232] The above description focuses on the embodiments, but these are merely illustrative and do not limit the embodiments. Those skilled in the art will understand that various modifications and applications not exemplified above are possible within the scope of the essential characteristics of the embodiments. For example, each component specifically illustrated in the embodiments can be modified and implemented. Differences related to such modifications and applications should be construed as being included within the scope of the embodiments defined in the appended claims.

Claims

1. an insulating layer including a first layer including a first filler and a second layer disposed on the first layer; a pad portion disposed on the insulating layer; a metal layer disposed on the pad portion; The pad portion includes a first portion that overlaps horizontally with a first filler of the first layer of the insulating layer, and a second portion that does not overlap horizontally with the first filler of the first layer.

2. The circuit board of claim 1 , wherein the resin of the first layer and the resin of the second layer of the insulating layer comprise the same insulating material.

3. The circuit board according to claim 1 , wherein the first resin layer and the second resin layer of the insulating layer contain different insulating materials.

4. The circuit board of claim 1 , wherein the second layer of the insulating layer comprises a second filler.

5. The circuit board according to claim 4 , wherein the diameter of the first filler is the same as the diameter of the second filler.

6. The circuit board according to claim 4 , wherein the content of the first filler in the first layer of the insulating layer is greater than the content of the second filler in the second layer.

7. The circuit board according to claim 4 , wherein the diameter of the second filler is smaller than the diameter of the first filler.

8. 3. The circuit board of claim 2, wherein each of the first and second layers of resin includes any one of ABF (Ajinomoto Build-up Film), FR-4, BT (Bismaleimide Triazine), and PID (Photo Imageable Dielectric resin).

9. 9. The circuit board according to claim 1, wherein the pad portion is disposed in a recess provided in the upper surface of the insulating layer.

10. the recess comprises a through hole penetrating the second layer of the insulating layer; The circuit board according to claim 9 , wherein the pad portion is disposed within the through hole.

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