Circuit board and semiconductor package including same

Abstract

A circuit board according to an embodiment includes a first insulating layer, a metal layer disposed on the first insulating layer, and a second insulating layer disposed on the metal layer and having a cavity, the metal layer including a plurality of metal patterns spaced apart from each other along a circumferential direction of the lower end of the side wall of the cavity.

Description

[Technical Field]

[0001] The embodiments relate to a circuit board and a semiconductor package including the same. [Background technology]

[0002] 2. Description of the Related Art As the performance of electric / electronic products continues to improve, technologies for attaching more packages to a substrate with a limited size are being proposed and researched.

[0003] A typical semiconductor package has a structure in which multiple chips are arranged. Recently, the size of semiconductor packages has increased due to the high specifications of products to which semiconductor packages are applied and the adoption of multiple chips such as HBM (High Bandwidth Memory). As a result, semiconductor packages include interposers to connect multiple chips.

[0004] In addition, semiconductor packages used in products that provide the Internet of Things (IOT), autonomous vehicles, and high-performance servers are required to have high performance and reliability in line with the trend toward higher integration.

[0005] Furthermore, the semiconductor package has a vertical connection structure between multiple substrates, interposers, and semiconductor devices, so that the semiconductor package may have a large vertical thickness depending on the thickness and number of the substrates, interposers, and semiconductor devices.

[0006] Therefore, semiconductor packages use substrates with cavities to reduce their vertical thickness.

[0007] In this case, a desmear process must be performed in the process of manufacturing a substrate including a cavity, because if the desmear process is not performed, the adhesion between the molding member disposed in the cavity and the substrate decreases, which can lead to separation of the molding member from the substrate.

[0008] Furthermore, when the desmear process is performed, the bottom surface of the cavity may be etched along with the sidewall of the cavity, which may cause damage to the bottom surface of the cavity and may affect the physical reliability of the substrate.

[0009] Furthermore, the bottom surface of the cavity may be the top surface of the thermosetting resin containing glass fibers. Therefore, when the desmear process is performed, the thermosetting resin is etched, which may cause a problem in that the glass fibers contained in the thermosetting resin are exposed through the cavity. Furthermore, the exposed glass fibers may act as a factor causing defects such as copper migration.

[0010] (Patent Document 1) KR10-2012-0045639A Summary of the Invention [Problem to be solved by the invention]

[0011] The embodiments provide a circuit board with a new structure and a semiconductor package including the same.

[0012] Further, the embodiment provides a circuit board including the cavity and a semiconductor package including the same.

[0013] Furthermore, the embodiments provide a circuit board with improved circuit integration and a semiconductor package including the same.

[0014] Furthermore, the embodiments provide a circuit board and a semiconductor package including the same with improved electrical reliability and / or mechanical reliability.

[0015] Furthermore, the embodiments provide a circuit board with improved warpage characteristics and a semiconductor package including the same.

[0016] In the proposed embodiments, the technical problems to be solved are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by a person having ordinary skill in the technical field to which the proposed embodiments pertain from the following description. [Means for solving the problem]

[0017] A circuit board according to an embodiment includes a first insulating layer, a metal layer disposed on the first insulating layer, and a second insulating layer disposed on the metal layer and having a cavity, the metal layer including a plurality of metal patterns spaced apart from each other along a circumferential direction of the lower end of the side wall of the cavity.

[0018] The device further includes a first circuit pattern layer disposed on the first insulating layer, the first circuit pattern layer including a first pad that vertically overlaps the cavity and a second pad that does not vertically overlap the cavity.

[0019] The first circuit pattern layer further includes a connection pattern that connects the first pad and the second pad, and the connection pattern includes a first portion that vertically overlaps the cavity and is not covered by the second insulating layer, and a second portion that does not vertically overlap the cavity and is covered by the second insulating layer.

[0020] The connecting pattern is provided on the first insulating layer across the plurality of metal patterns.

[0021] In addition, the connection pattern is not connected to each of the plurality of metal patterns.

[0022] The connecting pattern may be a plurality of patterns, and at least one of the connecting patterns may be connected to at least one of the metal patterns.

[0023] The plurality of metal patterns may have different horizontal widths along the circumferential direction.

[0024] The plurality of metal patterns are spaced apart at intervals in the range of 2 μm to 12 μm along the circumferential direction.

[0025] Further, each of the first pad and the second pad includes a first layer disposed on the first insulating layer and a second layer disposed on the first layer, and the thickness of each of the plurality of metal patterns corresponds to the thickness of the second layer of the first and second pads.

[0026] The second insulating layer also includes a first recess portion that is recessed in a horizontal direction from a lower end of the sidewall of the cavity toward an outer surface of the second insulating layer.

[0027] The first recess portion includes a plurality of first recesses provided between the plurality of metal patterns and a sidewall of the cavity, and a portion of each side surface of the plurality of metal patterns is exposed through the first recesses and the cavity.

[0028] Furthermore, the vertical distance of each of the plurality of first recesses corresponds to the thickness of each of the plurality of metal patterns.

[0029] The first insulating layer also includes a second recess portion connected to a lower end of the sidewall of the cavity and recessed in a vertical direction from the upper surface of the first insulating layer to the lower surface of the first insulating layer.

[0030] The second recess portion includes a plurality of second recesses spaced apart from one another along the circumferential direction, and the plurality of first recesses and the plurality of second recesses are alternately arranged along the circumferential direction.

[0031] Meanwhile, a semiconductor package according to an embodiment includes a first insulating layer, a second insulating layer disposed on the first insulating layer and including a cavity, a first circuit pattern layer disposed between the first insulating layer and the second insulating layer and including a first pad vertically overlapping the cavity, a second pad not vertically overlapping the cavity, and a connecting pattern connecting the first pad and the second pad, a connecting member disposed on the first pad, a connecting member disposed on the connecting member, and a metal layer provided on the first insulating layer along a circumferential direction of a lower end of a side wall of the cavity, and the metal layer includes a plurality of metal patterns spaced apart from each other along the circumferential direction.

[0032] The semiconductor package also includes a molding member disposed within the cavity by molding the connecting member, the molding member contacting the plurality of metal patterns.

[0033] The second insulating layer may include a first recess portion that is horizontally concave from a lower end of the sidewall of the cavity toward an outer surface of the second insulating layer, the first recess portion including a plurality of first recesses that are formed between the plurality of metal patterns and the sidewall of the cavity, and the molding member that fills the plurality of first recesses.

[0034] The first insulating layer may include a plurality of second recesses that are concave in a vertical direction from an upper surface of the first insulating layer to a lower surface of the first insulating layer and are alternately arranged with the plurality of first recesses along the circumferential direction, and the molding member may further fill the plurality of second recesses.

[0035] The connecting member includes at least one of an interposer, a semiconductor element, an organic bridge, and an inorganic bridge. [Effects of the Invention]

[0036] An embodiment may include a first insulating layer and a second insulating layer disposed on the first insulating layer and including a cavity. A metal layer is disposed between the first insulating layer and the second insulating layer along a circumferential direction of a lower end of a sidewall of the cavity. The metal layer includes a plurality of metal patterns spaced apart from each other along the circumferential direction.

[0037] The metal patterns may function as a reinforcing member that improves the rigidity of the circuit board. For example, the metal patterns may distribute or mitigate stress acting on the circuit board, thereby improving the warpage characteristics of the circuit board. Furthermore, the metal patterns may mitigate horizontal expansion of the circuit board due to thermal stress generated in the manufacturing or use environment of the circuit board, thereby improving the mechanical and / or physical reliability of the circuit board and a semiconductor package including the circuit board.

[0038] The embodiment further includes a connection pattern disposed on the first insulating layer and directly connecting the first pad and the second pad. The connection pattern may be provided across the plurality of metal patterns. A plurality of connection patterns may be provided. The plurality of metal patterns may be spaced apart from each other along the circumferential direction, so that the connection patterns may not be electrically connected to each other on the first insulating layer. Therefore, the embodiment may directly connect the first pad and the second pad using the connection pattern, thereby eliminating the need for a first through-electrode that vertically overlaps the first pad. Furthermore, by directly connecting the first pad and the second pad using the connection pattern, the embodiment may reduce the length of the signal line between them. For example, a signal line including the connection pattern may be shorter than a signal line including the first through-electrode. Therefore, the embodiment may minimize signal transmission loss by reducing the signal transmission line between the first pad and the second pad, thereby improving electrical characteristics. Furthermore, the embodiment may improve circuit integration by disposing a connection pattern that directly connects the first pad and the second pad.

[0039] Meanwhile, in the embodiment, the second insulating layer may include a first recess portion provided between the plurality of metal patterns and a lower end of the sidewall of the cavity. The first recess portion may distribute or mitigate stress acting on the first insulating layer and the second insulating layer, thereby improving the warpage characteristics of the circuit board. For example, the first recess portion may reduce the area of ​​the interface between the first insulating layer and the second insulating layer, thereby dispersing stress acting on the second insulating layer. Therefore, the first recess portion may mitigate warpage of the circuit board in a specific direction (e.g., warpage of both ends of the circuit board upward or downward).

[0040] In addition, the first insulating layer of the embodiment may include a second recess portion formed along the circumferential direction. The second recess portion may be formed vertically concave from the top surface to the bottom surface of the first insulating layer. In this case, the first recess portion is a recess formed horizontally in the second insulating layer, and the second recess portion is a recess formed vertically in the first insulating layer. Therefore, the embodiment may use the first and second recess portions to distribute or relieve stress acting on the circuit board, thereby improving the warpage characteristics of the circuit board.

[0041] For example, the first and second recesses can mitigate horizontal expansion of the circuit board due to thermal stress generated in the manufacturing or use environment of the circuit board, thereby improving the mechanical and / or physical reliability of the circuit board and the semiconductor package including the circuit board. In this case, the second insulating layer can include an insulating material different from that of the first insulating layer. As a result, the first and second insulating layers can have different thermal expansion coefficients, which can cause vertical warping of the circuit board. Therefore, the first and second recesses can prevent the circuit board from warping in a specific direction (e.g., both ends of the circuit board warping upward or both ends of the circuit board warping downward).

[0042] Therefore, the embodiments may minimize the degree of warping along the vertical direction and the degree of expansion or contraction along the horizontal direction of the circuit board and the semiconductor package, thereby improving the mechanical and / or physical reliability of the circuit board and the semiconductor package. Furthermore, the embodiments may enable stable operation of semiconductor devices arranged on the circuit board, thereby improving the operational characteristics of electronic products and / or servers to which the semiconductor package is applied.

[0043] Meanwhile, in the embodiment, the plurality of metal patterns may have different horizontal widths along the circumferential direction. For example, the horizontal width of the metal pattern in the region with a relatively low metal density may be greater than the horizontal width of the metal pattern in the region with a relatively high metal density. Therefore, the embodiment may minimize warpage of the circuit board caused by the difference in metal density, thereby further improving the physical and / or electrical reliability of the circuit board and the semiconductor package.

[0044] In addition, in the embodiment, the desmear process of the second insulating layer is performed after the cavity is formed with the barrier layer provided, thereby preventing the glass fibers of the first insulating layer from being exposed and resolving the resulting problems with physical reliability and / or electrical reliability. Furthermore, in the embodiment, the desmear process conditions can be determined without taking into consideration the exposure of the glass fibers. For example, in the embodiment, the desmear conditions can be determined to optimally improve the adhesion between the second insulating layer and the second circuit pattern layer, thereby improving the adhesion between the second insulating layer and the second circuit pattern layer without causing the problem of the reinforcing member being exposed.

[0045] Meanwhile, the desmear process of the embodiment may be performed in a state where a through hole and a cavity penetrating the second insulating layer are formed. Therefore, the surface of the inner wall of the through hole and the inner wall of the cavity may also be treated during the desmear process. This may improve the adhesion between the second through electrode disposed in the through hole and the second insulating layer. Furthermore, the embodiment may improve the adhesion between the molding member disposed in the cavity and the second insulating layer.

[0046] Furthermore, the molding member may be provided by filling at least one of the first recessed portion and the second recessed portion, thereby further improving the bonding strength between the molding member and the circuit board. [Brief explanation of the drawings]

[0047] [Figure 1] 1 is a cross-sectional view showing a semiconductor package according to a first embodiment. [Figure 2] 2 is a plan view illustrating a process of providing a metal pattern on the circuit board of FIG. 1. FIG. [Figure 3] 2 is a plan view illustrating a process of providing a metal pattern on the circuit board of FIG. 1. FIG. [Figure 4] FIG. 2 is a plan view showing a metal pattern provided on the circuit board of FIG. [Figure 5] 5 is a cross-sectional view of the circuit board taken along the AA' direction in FIG. 4. [Figure 6] FIG. 10 is a cross-sectional view showing a circuit board according to a second embodiment. [Figure 7] FIG. 10 is a cross-sectional view showing a circuit board according to a third embodiment. [Figure 8] FIG. 10 is a cross-sectional view showing a circuit board according to a fourth embodiment. [Figure 9] FIG. 9 is a diagram showing a plan view of the circuit board of FIG. 8. [Figure 10] FIG. 10 is a cross-sectional view showing a circuit board according to a fifth embodiment. [Figure 11] FIG. 11 is a plan view of the circuit board of FIG. [Figure 12] 11 is an enlarged view of a partial area of ​​the circuit board of FIG. 10. FIG. [Figure 13] 4A and 4B are diagrams illustrating the top surfaces of the first regions of the first insulating layer according to an example and a comparative example. [Figure 14] 1 is a cross-sectional view showing a semiconductor package according to an embodiment. [Figure 15] 9A to 9C are diagrams showing a method for manufacturing the circuit board of FIG. 8 according to an embodiment in the order of steps. [Figure 16] 9A to 9C are diagrams showing a method for manufacturing the circuit board of FIG. 8 according to an embodiment in the order of steps. [Figure 17] 9A to 9C are diagrams showing a method for manufacturing the circuit board of FIG. 8 according to an embodiment in the order of steps. [Figure 18] 9A to 9C are diagrams showing a method for manufacturing the circuit board of FIG. 8 according to an embodiment in the order of steps. [Figure 19] 9A to 9C are diagrams showing a method for manufacturing the circuit board of FIG. 8 according to an embodiment in the order of steps. [Figure 20] 9A to 9C are diagrams showing a method for manufacturing the circuit board of FIG. 8 according to an embodiment in the order of steps. [Figure 21] 9A to 9C are diagrams showing a method for manufacturing the circuit board of FIG. 8 according to an embodiment in the order of steps. [Figure 22] 9A to 9C are diagrams showing a method for manufacturing the circuit board of FIG. 8 according to an embodiment in the order of steps. [Figure 23] 9A to 9C are diagrams showing a method for manufacturing the circuit board of FIG. 8 according to an embodiment in the order of steps. [Figure 24] 9A to 9C are diagrams showing a method for manufacturing the circuit board of FIG. 8 according to an embodiment in the order of steps. [Figure 25] 9A to 9C are diagrams showing a method for manufacturing the circuit board of FIG. 8 according to an embodiment in the order of steps. [Figure 26] 9A to 9C are diagrams showing a method for manufacturing the circuit board of FIG. 8 according to an embodiment in the order of steps. [Figure 27] 9A to 9C are diagrams showing a method for manufacturing the circuit board of FIG. 8 according to an embodiment in the order of steps. [Figure 28] 9A to 9C are diagrams showing a method for manufacturing the circuit board of FIG. 8 according to an embodiment in the order of steps. DETAILED DESCRIPTION OF THE INVENTION

[0048] Hereinafter, preferred embodiments of the present specification will be described in detail with reference to the accompanying drawings.

[0049] However, the technical concept of the present invention is not limited to the described embodiments, but may be realized in various different forms, and one or more of the components of the embodiments may be selectively combined or substituted for each other within the scope of the technical concept of the present invention.

[0050] Furthermore, unless otherwise clearly defined and described, terms (including technical and scientific terms) used in the examples of the present invention are interpreted as meanings that can be commonly understood by a person having ordinary skill in the art to which the present invention belongs, and commonly used terms such as terms defined in a dictionary can be interpreted in consideration of the contextual meaning of the relevant art. Furthermore, the terms used in the examples of the present invention are intended to explain the examples and are not intended to limit the present invention.

[0051] In this specification, unless otherwise specified, the singular can also include the plural, and when it is stated that "A and (and) at least one (or more) of B and C" it can include one or more of all possible combinations of A, B, and C. Furthermore, when describing components of embodiments of the present invention, terms such as first, second, A, B, (a), (b), etc. can be used.

[0052] Such terms are used merely to distinguish a component from other components, and do not determine the essence, order, or procedure of the components. When a component is described as being "coupled," "bonded," or "connected" to another component, it includes not only the case where the component is directly coupled, coupled, or connected to the other component, but also the case where the component is "coupled," "coupled," or "connected" by another component between the component and the other component.

[0053] Furthermore, when it is described as being formed or disposed "above or below" a component, "above" or "below" includes not only the case where two components are in direct contact with each other, but also the case where one or more other components are formed or disposed between the two components. Furthermore, when it is expressed as "above or below," it can mean not only the upper direction based on one component, but also the lower direction.

[0054] -Electronic Devices-

[0055] Before describing the embodiments, an electronic device to which the semiconductor package of the embodiments can be applied will be briefly described. The electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be connected to the semiconductor package of the embodiments. Various semiconductor elements may be mounted in the semiconductor package.

[0056] The semiconductor device may include active and / or passive devices. The active device may be a semiconductor chip in the form of an integrated circuit (IC) in which hundreds to millions of devices are integrated into a single chip. The semiconductor device may be a logic chip, a memory chip, or the like. The logic chip may be a central processor (CPU), a graphics processor (GPU), or the like. For example, the logic chip may be an application processor (AP) chip including at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, a cryptographic processor, a microprocessor, or a microcontroller, or may be an analog-to-digital converter, an application-specific IC (ASIC), or the like, or a chipset including a specific combination of the above.

[0057] The memory chips may be stacked memories such as HBM, and may include volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, and the like.

[0058] Meanwhile, the product group to which the semiconductor package of the embodiment is applied may be any one of CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package On Package), and SIP (System In Package), but is not limited thereto.

[0059] The electronic device may be a smartphone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automobile, etc. However, it is not limited to these, and it may also be any other electronic device that processes data.

[0060] The following describes circuit boards and semiconductor packages including the same according to embodiments. The semiconductor packages may have various vertical and horizontal stacking structures including the circuit boards described below. For example, the semiconductor packages may include at least one semiconductor element coupled to the circuit board and / or a connecting member including at least one of a high-density wiring bridge substrate and an interposer.

[0061] FIG. 1 is a cross-sectional view showing a circuit board according to a first embodiment, FIGS. 2 and 3 are plan views for explaining the process of providing a metal pattern on the circuit board of FIG. 1, FIG. 4 is a plan view showing the metal pattern provided on the circuit board of FIG. 1, and FIG. 5 is a cross-sectional view of the circuit board cut along the A-A' direction of FIG. 4.

[0062] First, with reference to FIG. 1, the general structure of the circuit board according to the first embodiment will be described.

[0063] 1, the circuit board of the embodiment may include multiple insulating layers, each of which may have a single layer structure or may be composed of multiple layers.

[0064] Specifically, the circuit board may include a first insulating layer 111 and a second insulating layer 112. In this case, the first insulating layer 111 may have a single-layer structure as shown in Figure 1, or may have a different multi-layer structure.

[0065] The second insulating layer 112 may be disposed on the first insulating layer 111. The second insulating layer 112 may have a single-layer structure, or alternatively, may have a multi-layer structure.

[0066] The second insulating layer 112 may include a cavity 150. If the second insulating layer 112 has a multi-layer structure, the cavity 150 may penetrate any one of the multiple second insulating layers, or alternatively, may penetrate at least two layers simultaneously.

[0067] In one embodiment, the first insulating layer 111 and the second insulating layer 112 may include the same insulating material. In this case, the first insulating layer 111 may refer to an insulating layer that does not include a cavity 150, and the second insulating layer 112 may refer to an insulating layer that includes a cavity 150.

[0068] In another embodiment, the first insulating layer 111 and the second insulating layer 112 may include different insulating materials.

[0069] However, for the sake of convenience, the following description will be given assuming that the first insulating layer 111 and the second insulating layer 112 each have a single-layer structure and contain different insulating materials.

[0070] The first insulating layer 111 and the second insulating layer 112 may include different insulating materials. For example, the first insulating layer 111 may include a thermosetting resin. The second insulating layer 112 may include a photocurable resin. However, the embodiment is not limited thereto. The first insulating layer 111 and the second insulating layer 112 may each be formed of a thermosetting resin, or each of the first insulating layer 111 and the second insulating layer 112 may each be formed of a photocurable resin. Alternatively, the first insulating layer 111 may be formed of a photocurable resin and the second insulating layer 112 may be formed of a photocurable resin.

[0071] The second insulating layer 112 may include a cavity 150. The cavity 150 may penetrate the upper and lower surfaces of the second insulating layer 112. The cavity 150 may include a bottom surface and sidewalls 150S.

[0072] The bottom surface of the cavity 150 may refer to the top surface of the first insulating layer 111 that overlaps the cavity 150 vertically. Also, the sidewall 150S of the cavity 150 may refer to the sidewall of the second insulating layer 112 that overlaps the cavity 150 vertically.

[0073] The sidewall 150S of the cavity 150 may have a slope. For example, the sidewall 150S of the cavity 150 may have a slope such that the width of the cavity 150 decreases from the upper surface of the second insulating layer 112 to the lower surface thereof. However, the embodiment is not limited thereto. For example, the sidewall 150S may have a slope such that the width of the cavity 150 decreases from the lower surface of the second insulating layer 112 to the upper surface thereof. Furthermore, although the drawings illustrate the sidewall 150S having one slope, the embodiment is not limited thereto. For example, the sidewall 150S may include at least one inflection portion, and the inflection portions may be inclined with different slopes.

[0074] The top surface of the first insulating layer 111 may be divided into a plurality of regions. For example, the first insulating layer 111 may include a first region R1 that vertically overlaps the cavity 150. In this case, if the cavities 150 have different widths in the thickness direction of the second insulating layer 112, the first region R1 may refer to a region that vertically overlaps a lower region of the cavity 150 corresponding to a lower end of the sidewall 150S.

[0075] In addition, the first insulating layer 111 may include a second region R2 that does not vertically overlap the cavity 150. The second region R2 may refer to a region of the top surface of the first insulating layer 111 that is covered with the second insulating layer 112.

[0076] In this case, the circuit board of the embodiment may include a reinforcing portion. The reinforcing portion can disperse stress acting due to expansion and / or contraction of the circuit board caused by thermal stress, and can prevent warping of the circuit board in the vertical and / or horizontal directions. The reinforcing portion of the first embodiment may include a first recess portion 112R and a metal layer 121BP, which will be described later. For example, in the first embodiment, the reinforcing portion may include a plurality of reinforcing patterns, and the plurality of reinforcing patterns may include a plurality of first recesses in the first recess portion 112R and a plurality of metal patterns in the metal layer 121BP, respectively.

[0077] For example, the second insulating layer 112 may include a first recess 112R that is a part of the reinforcing portion.

[0078] The first recessed portion 112R may be connected to a lower end of the sidewall 150S of the second insulating layer 112. Exemplarily, the lower end of the sidewall 150S of the second insulating layer 112 may include a portion connected to the first recessed portion 112R. In this case, the lower end of the sidewall 150S of the second insulating layer 112 may be partially connected to the first recessed portion 112R. For example, the lower end of the sidewall of the second insulating layer 112 may include a connected portion connected to the first recessed portion 112R and a non-connected portion not connected to the first recessed portion 112R.

[0079] Therefore, the lower end of the sidewall 150S of the second insulating layer 112 may have a step along the circumferential direction. For example, the lower end of the sidewall 150S of the second insulating layer 112 may include a connecting portion and a non-connecting portion with the first recess portion 112R, and the connecting portion and the non-connecting portion may have different heights. The connecting portion of the lower end of the sidewall 150S of the second insulating layer 112 may be located higher than the non-connecting portion. For example, the connecting portion of the lower end of the sidewall 150S of the second insulating layer 112 may not contact the upper surface of the first insulating layer 111, and the non-connecting portion may contact the upper surface of the first insulating layer 111.

[0080] In this case, the first recessed portion 112R may be formed along the horizontal direction in the second insulating layer 112. For example, the first recessed portion 112R may be formed in a concave shape from the lower end of the sidewall 150S of the cavity 150 toward the outer surface of the second insulating layer 112.

[0081] That is, the first recessed portion 112R may be formed at a lower end of the sidewall 150S of the cavity 150 of the second insulating layer 112 and may be concave in the horizontal direction away from the cavity 150. The first recessed portion 112R may vertically overlap the second region R2 of the first insulating layer 111 located adjacent to the first region R1 of the first insulating layer 111. The first recessed portion 112R may be a region where a portion of the barrier layer 121BR protecting the upper surface of the first region R1 of the first insulating layer 111 is removed.

[0082] The first region R1 of the first insulating layer 111 may vertically overlap the cavity 150 and not contact the second insulating layer 112. Also, a portion of the second region R2 of the first insulating layer 111 may vertically overlap the first recess portion 112R and not contact the second insulating layer 112.

[0083] In the embodiment, a first recess portion 112R having a horizontally concave shape may be provided in the second insulating layer 112 adjacent to the cavity 150. This may distribute or relieve stress acting on the first insulating layer 111 and the second insulating layer 112, thereby improving the warpage characteristics of the circuit board.

[0084] For example, the first recessed portion 112R may reduce the area of ​​the interface between the first insulating layer 111 and the second insulating layer 112, thereby dispersing stress acting on the second insulating layer 112. Therefore, the first recessed portion 112R may mitigate a phenomenon in which the circuit board warps in a specific direction (e.g., a phenomenon in which both ends of the circuit board warp upward or a phenomenon in which both ends of the circuit board warp downward).

[0085] In this case, the first recess portion 112R is provided along the circumferential direction of the lower end of the side wall 150S of the cavity 150. Preferably, the first recess portion 112R may include a plurality of first recesses provided along the circumferential direction of the lower end of the side wall 150S of the cavity 150.

[0086] The first recesses of the first recess portion 112R are spaced apart from one another along the circumferential direction of the lower end of the side wall 150S of the cavity 150. This allows the embodiment to efficiently distribute stress acting on the second insulating layer 112 while maintaining adhesion between the first insulating layer 111 and the second insulating layer 112.

[0087] For example, in contrast to the structure described herein, the first recessed portion 112R may have a closed-loop shape connected to each other along the circumferential direction of the lower end of the sidewall 150S of the cavity 150. In this case, the adhesion between the first insulating layer 111 and the second insulating layer 112 may be reduced, which may result in the second insulating layer 112 peeling off from the first insulating layer 111. Furthermore, when the first recessed portion 112R has a closed-loop shape, stress caused by contraction and / or expansion of the second insulating layer 112 can be dispersed in the horizontal direction, but warpage in the vertical direction may increase. Therefore, in this embodiment, the first recessed portion 112R includes a plurality of first recesses spaced apart from each other along the circumferential direction, which may achieve stress dispersion, improved adhesion between the first insulating layer 111 and the second insulating layer 112, and reduced warpage in the vertical direction.

[0088] Furthermore, each of the plurality of first recesses of the first recess portion 112R may have the same horizontal width along the circumferential direction of the lower end of the sidewall 150S of the cavity 150, but is not limited to this. Exemplarily, each of the plurality of first recesses may have different horizontal widths along the circumferential direction of the lower end of the sidewall 150S of the cavity 150. Furthermore, each of the horizontal widths of the plurality of first recesses may be determined depending on the warping direction of the circuit board, but is not limited to this.

[0089] Therefore, the embodiments may minimize the degree of expansion or contraction of the circuit board and the semiconductor package along the horizontal direction, thereby improving the mechanical and / or physical reliability of the circuit board and the semiconductor package. Furthermore, the embodiments may enable stable operation of semiconductor devices arranged on the circuit board, thereby improving the operational characteristics of electronic products and / or servers to which the semiconductor package is applied.

[0090] The first recessed portion 112R may be filled with a molding material in the semiconductor package. The first recessed portion 112R may function as an anchor to improve the bonding strength between the molding material and the circuit board. Therefore, the embodiment may solve the mechanical reliability problem of the molding material peeling off from the circuit board.

[0091] Meanwhile, a circuit pattern layer is disposed on the first insulating layer 111 and the second insulating layer 112. A portion of the circuit pattern layer may not function as a circuit (e.g., transmit an electrical signal), and may be defined as a "metal layer." Therefore, the term "circuit pattern layer" refers to a layer that performs a circuit function, and the term "metal layer" refers to a layer that does not perform a circuit function, but is not limited thereto. For example, at least one of the metal patterns of the metal layer may be connected to the circuit pattern layer, and the metal pattern connected to the circuit pattern layer may function to transmit an electrical signal together with the circuit pattern layer. In this case, the "metal layer" may be part of the barrier layer and may form a reinforcing portion together with the first recess portion 112R. This will be described in detail below.

[0092] The first circuit pattern layer 121 may be provided between the upper surface of the first insulating layer 111 and the lower surface of the second insulating layer 112 .

[0093] A second circuit pattern layer 122 may be provided on the top surface of the second insulating layer 112 .

[0094] The third circuit pattern layer 123 may be provided on the lower surface of the first insulating layer 111 .

[0095] That is, the first circuit pattern layer 121 may be disposed on the first insulating layer 111. For example, the first circuit pattern layer 121 may protrude above the upper surface of the first insulating layer 111.

[0096] The second circuit pattern layer 122 may protrude above the upper surface of the second insulating layer 112. The second circuit pattern layer 122 may refer to the uppermost circuit pattern layer disposed on the uppermost side of the circuit board.

[0097] The third circuit pattern layer 123 may protrude below the lower surface of the first insulating layer 111. The third circuit pattern layer 123 may refer to the lowermost circuit pattern layer disposed on the lowermost side of the circuit board.

[0098] Each of the first circuit pattern layer 121, the second circuit pattern layer 122, and the third circuit pattern layer 123 may include pads and traces (or connection patterns) depending on the function. The pads may be mounting pads on which elements or chips are mounted, or terminal pads connected to an external substrate. The traces may be long signal wiring lines connecting multiple pads. The traces are fine patterns having a width smaller than that of the pads. For example, in an embodiment, the spacing between multiple traces may be in the range of 2 μm to 15 μm, and the line width of each trace may be in the range of 2 μm to 15 μm.

[0099] The circuit pattern layers may be formed of at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). The circuit pattern layers may also be formed of a paste or solder paste containing at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn), which has excellent bonding strength. Preferably, the first circuit pattern layer 121, the second circuit pattern layer 122, and the third circuit pattern layer 123 may be formed of copper (Cu), which has high electrical conductivity and is relatively inexpensive.

[0100] The first circuit pattern layer 121, the second circuit pattern layer 122, and the third circuit pattern layer 123 may each have a thickness in the range of 10 μm to 25 μm. For example, the first circuit pattern layer 121, the second circuit pattern layer 122, and the third circuit pattern layer 123 may each have a thickness in the range of 10 μm to 23 μm. The first circuit pattern layer 121, the second circuit pattern layer 122, and the third circuit pattern layer 123 may each have a thickness in the range of 10 μm to 20 μm.

[0101] If the thickness of each of the first circuit pattern layer 121, the second circuit pattern layer 122, and the third circuit pattern layer 123 is less than 10 μm, the resistance of the circuit pattern increases, which can reduce signal transmission efficiency. For example, if the thickness of each of the first circuit pattern layer 121, the second circuit pattern layer 122, and the third circuit pattern layer 123 is less than 10 μm, signal transmission loss can increase. For example, if the thickness of each of the first circuit pattern layer 121, the second circuit pattern layer 122, and the third circuit pattern layer 123 is more than 25 μm, the line width of the circuit pattern increases, which can increase the overall volume of the circuit board.

[0102] The first circuit pattern layer 121 may include a plurality of pads.

[0103] The first circuit pattern layer 121 may include a first pad 121-1 disposed on the first region R1 of the first insulating layer 111. The first pad 121-1 may vertically overlap the cavity 150. Therefore, the first pad 121-1 may not be in contact with the second insulating layer 112.

[0104] The first circuit pattern layer 121 may include a second pad 121-2 disposed on the second region R2 of the first insulating layer 111. The second pad 121-2 may not vertically overlap the cavity 150. Therefore, the second pad 121-2 may be covered by the second insulating layer 112.

[0105] In this case, at least a portion of the upper surface of the first region R1 of the first insulating layer 111 may vertically overlap the first pad 121-1, and the remaining portion may not vertically overlap the first circuit pattern layer 121 and the second insulating layer 112.

[0106] Therefore, when a desmear process is performed after the formation of the cavity 150, the region of the first region R1 of the first insulating layer 111 where the first pad 121-1 is not disposed may also be etched. Furthermore, when the first region R1 of the first insulating layer 111 is etched in the desmear process, glass fibers included in the first insulating layer 111 may be exposed through the cavity 150. The exposed glass fibers may cause reliability problems such as copper migration.

[0107] Therefore, in the circuit board of the embodiment, a cavity 150 may be formed with a barrier layer 121BR disposed on the first region R1 of the first insulating layer 111. The barrier layer 121BR forms a reinforcing portion including the first recess portion 112R and the metal layer 121BP, thereby improving the mechanical reliability and / or electrical reliability of the circuit board and protecting the upper surface of the first region R1 of the first insulating layer 111 during the desmear process.

[0108] In addition, in the manufacturing process of the circuit board in the first embodiment, the barrier layer 121BR may be partially removed, and therefore the reinforcing portion of the circuit board in the first embodiment may include a metal layer 121BP corresponding to a portion of the barrier layer 121BR and connected to the first recess portion 112R.

[0109] The metal layer 121BP may be provided along the circumferential direction of the lower end of the sidewall 150S of the cavity 150. Preferably, the metal layer 121BP may include a plurality of metal patterns, each corresponding to a respective one of the first recesses of the first recess portion 112R. That is, a portion of the barrier layer 121BR may be removed to form the first recess portion 112R of the reinforcing portion, and the remaining portion of the barrier layer 121BR may not be removed to form the metal layer 121BP of the reinforcing portion. In this case, the metal layer 121BP may be disposed in the same layer as the first circuit pattern layer 221 and may not be electrically connected to the first circuit pattern layer 221. Therefore, the metal layer 121BP may be referred to as a dummy pattern or a barrier pattern that is not electrically connected to the first circuit pattern layer 221.

[0110] The embodiment may include a first recess portion 112R having a plurality of first recesses spaced apart from one another along the circumferential direction of the lower end of the side wall 150S of the cavity 150, and a metal layer having a plurality of metal patterns corresponding to the plurality of first recesses of the first recess portion 112R, respectively.

[0111] In summary, the second insulating layer 112 may be provided with a first recessed portion 112R along the circumferential direction of the lower end of the sidewall 150S of the cavity 150, and the metal layer 121BP may be provided along the circumferential direction of the first recessed portion 112R. The first recessed portion 112R and the metal layer 121BP may be connected to each other in the horizontal direction to form a reinforcing portion.

[0112] Exemplarily, each of the metal layers 121BP includes a plurality of metal patterns spaced apart from one another along the circumferential direction, through which the connection patterns 221-3 that directly connect the plurality of pads to one another as shown in Fig. 8 can be arranged. That is, the metal layer 121BP of the embodiment can prevent the glass fiber provided in the first insulating layer 111 from being exposed while allowing the connection patterns 221-3 to be arranged, thereby improving the circuit integration density while resolving problems with electrical reliability and / or mechanical reliability caused by the exposed glass fiber. This will be described in more detail below.

[0113] In addition, the first embodiment uses a barrier layer 121BR to provide a first recess portion 112R and a metal layer 121BP of the reinforcing portion, thereby minimizing horizontal and vertical deformation of the circuit board and semiconductor package.

[0114] Furthermore, the embodiment may be advantageous in selecting conditions for the desmear process because it is not necessary to consider damage to the first insulating layer 111 due to the barrier layer during the desmear process. Accordingly, the embodiment may improve adhesion between the second insulating layer 112 and the second circuit pattern layer 122 disposed on the second insulating layer 112. Specifically, the cavity 150 may be formed together with the through hole in a process of forming the through hole corresponding to the second through electrode 132 of the second insulating layer 112. Accordingly, in the embodiment, the second circuit pattern layer 122 may be disposed on the second insulating layer 112 after the desmear process. Therefore, the embodiment is advantageous in selecting conditions for the desmear process, and the desmear process may be performed under conditions that can improve adhesion between the second insulating layer 112 and the second circuit pattern layer 122. Accordingly, the embodiment may improve adhesion between the second insulating layer 112 and the second circuit pattern layer 122.

[0115] The circuit board according to the embodiment may include a through electrode. The through electrode may function to electrically connect circuit pattern layers disposed on different layers. The through electrode may also be referred to as a "via."

[0116] The through electrodes penetrate the first insulating layer 111 and the second insulating layer 112 included in the circuit board, thereby electrically connecting circuit patterns arranged on different layers. In this case, the through electrodes may be formed to penetrate only one insulating layer, or alternatively, may be formed to commonly penetrate at least two or more insulating layers.

[0117] For example, the circuit board includes a first through electrode 131. The first through electrode 131 may be formed to penetrate the first insulating layer 111. The first through electrode 131 may electrically connect the first circuit pattern layer 121 and the third circuit pattern layer 123. For example, an upper surface of the first through electrode 131 may be directly connected to a lower surface of the first circuit pattern layer 121. For example, a lower surface of the first through electrode 131 may be directly connected to the third circuit pattern layer 123.

[0118] Therefore, the first circuit pattern layer 121 and the third circuit pattern layer 123 are electrically connected to each other through the first through electrodes 131, thereby transmitting signals.

[0119] In this case, the first through electrode 131 may include a first through portion 131a connected to the first pad 121-1 and a second through portion connected to the second pad 121-2.

[0120] The circuit board may also include a second through-hole electrode 132. The second through-hole electrode 132 may be formed to penetrate the second insulating layer 112. The second through-hole electrode 132 may electrically connect the first circuit pattern layer 121 and the second circuit pattern layer 122. For example, a lower surface of the second through-hole electrode 132 may be directly connected to the first circuit pattern layer 121. For example, an upper surface of the second through-hole electrode 132 may be directly connected to the second circuit pattern layer 122. Thus, the first circuit pattern layer 121 and the second circuit pattern layer 122 may be directly electrically connected to each other through the second through-hole electrode 132 to transmit signals.

[0121] The first through electrode 131 and the second through electrode 132 can be formed by forming through holes that penetrate the first insulating layer 111 and the second insulating layer 112, and filling the inside of the formed through holes with a conductive material.

[0122] Meanwhile, the circuit board of the embodiment may include a first protective layer 141 and a second protective layer 142. The first protective layer 141 and the second protective layer 142 may be disposed on the outermost side of the circuit board.

[0123] For example, the first protective layer 141 may be disposed on the first outermost or bottom side of the circuit board, for example, on the lower surface of the first insulating layer 111.

[0124] For example, the second protective layer 142 may be disposed on the second outermost or uppermost side of the circuit board. For example, the second protective layer 142 may be disposed on the top surface of the second insulating layer 112.

[0125] The first protective layer 141 may include at least one opening (not shown). For example, the first protective layer 141 may include an opening that vertically overlaps at least one of the third circuit pattern layers 123. For example, the first protective layer 141 may include an opening that vertically overlaps a terminal pad (not shown) of the third circuit pattern layer 123 on which a conductive coupling portion for connection to an external board is disposed.

[0126] The second protective layer 142 may include at least one opening (not shown). For example, the second protective layer 142 may include an opening that vertically overlaps at least one of the second circuit pattern layers 122. For example, the second protective layer 142 may include an opening that vertically overlaps a terminal pad (not shown) of the second circuit pattern layer 122 on which a conductive coupling portion for connecting to a memory substrate or an interposer substrate is disposed. The second protective layer 142 may also include a through-hole (not shown) that vertically overlaps the cavity 121 of the second insulating layer 112.

[0127] Meanwhile, a process of providing the reinforcing portion including the first recess portion 112R and the metal layer 121BP according to the first embodiment will be described below.

[0128] As shown in FIG. 2, the first insulating layer 111, the second insulating layer 112, and the cavity 150 formed in the second insulating layer 112 are roughly described. A first circuit pattern layer 121 including a first pad 121-1 and a second pad 121-2 spaced apart from each other along the horizontal direction may be formed on the first insulating layer 111.

[0129] The first pads 121-1 may be provided in plurality and spaced apart from each other in the horizontal direction on the first region R1 of the first insulating layer 111. The second pads 121-2 may be physically separated from the first pads 121-1 and may be provided in plurality and spaced apart from each other in the horizontal direction on the second region R2 of the first insulating layer 111.

[0130] A second insulating layer 112 may be disposed on the first insulating layer 111. The second insulating layer 112 may have a cavity 150 penetrating an upper surface and a lower surface of the second insulating layer 112. The planar shape of the cavity 150 may be, but is not limited to, a quadrangle. For example, the planar shape of the cavity 150 may be a triangle, a circle, an ellipse, a polygon, or the like.

[0131] A sidewall 150S of the cavity 150 of the second insulating layer 112 may be divided into a plurality of parts. For example, if the planar shape of the cavity 150 is a rectangle, the sidewall 150S may be divided into first to fourth parts 150S1, 150S2, 150S3, and 150S4 corresponding to the rectangle.

[0132] At this time, a barrier layer 121BR is provided on the first insulating layer 111 before the cavity 150 is formed. The outer width of the barrier layer 121BR may be larger than the width of the cavity 150. Therefore, the barrier layer 121BR may include a first portion 121BR1 that vertically overlaps the cavity 150 and a second portion 121BR2 that does not vertically overlap the cavity 150.

[0133] In this case, the barrier layer 121BR has recesses 121BC. The recesses 121BC are recessed from the outer surface of the barrier layer 121BR toward the inside. A plurality of recesses 121BC are provided spaced apart from each other along the circumferential direction of the outer surface of the barrier layer 121BR. At least a portion of the recesses 121BC may be provided in a first portion 121BR1 of the barrier layer 121BR, and the remaining portion may be provided in a second portion 121BR2 of the barrier layer 121BR.

[0134] The barrier layer 121BR may be a stopper used to form the cavity 150 in the second insulating layer 112. Alternatively, the barrier layer 121BR may be a protective part for protecting the upper surface of the first insulating layer 111 during a desmear process of the second insulating layer 112 after the cavity 150 is formed.

[0135] Therefore, the first region R1 of the first insulating layer 111 may be divided into a plurality of parts. For example, the first region R1 may include a first part R1-1 that vertically overlaps the first portion 121BR1 of the barrier layer 121BR and a second part R1-2 that does not vertically overlap the first portion 121BR1 of the barrier layer 121BR but vertically overlaps the recess 121BC. In this case, in one embodiment, the width of the recess 121BC or desmear conditions may be adjusted so that the second part R1-2 of the first insulating layer 111 is not desmeared in the desmear process. However, the embodiment is not limited thereto. For example, the second part R1-2 of the first insulating layer 111 may be desmeared in the desmear process, and thus a second recess (described below) having a vertically concave shape may be formed in the second part R1-2 of the first insulating layer 111.

[0136] 3 and 4, once the formation of the cavity 150 and the desmear process are completed with the barrier layer 121BR in place, a process of removing a portion of the barrier layer 121BR by etching is performed.

[0137] At this time, the first portion 121BR1 of the barrier layer 121BR vertically overlaps the cavity 150, and can therefore be entirely removed in an etching process.

[0138] In addition, the second portion 121BR2 of the barrier layer 121BR may be partially removed as over-etching is performed in the process of removing the first portion 121BR1. At this time, a recess 121BC is formed in the barrier layer 121BR. Accordingly, a first recess portion 112R may be formed in the second insulating layer 112 by over-etching the second portion 121BR2 of the barrier layer 121BR. At this time, the second portion 121BR2 of the barrier layer 121BR may be formed in a plurality of parts spaced apart along the circumferential direction of the barrier layer 121BR by the recess 121BC. As a result, the first recess portion 112R may include a plurality of first recesses spaced apart from each other along the circumferential direction of the cavity 150.

[0139] In addition, a portion of the second portion 121BR2 of the barrier layer 121BR may not be removed by the etching process. Therefore, a metal layer 121BP including a plurality of metal patterns corresponding to the plurality of first recesses of the first recess portion 112R along the circumferential direction of the first recess portion 112R may be provided.

[0140] In this case, the first recessed portion 112R may be formed by etching the barrier layer 121BR and may have a shape corresponding to the shape of the barrier layer 121BR. For example, the vertical cross-sectional shape of the first recessed portion 112R may be a quadrangle.

[0141] In summary, the barrier layer 121BR includes a first portion 121BR1 and a second portion 121BR2, and the second portion 121BR2 is divided into a plurality of parts spaced apart from each other along the circumferential direction of the outer surface of the barrier layer 121BR by recesses 121BC. Therefore, when etching the second portion 121BR2 of the barrier layer 121BR, a first recess portion 112R including a plurality of first recesses and the metal layer 121BP including a plurality of metal patterns may be provided corresponding to the plurality of parts of the second portion 121BR2 of the barrier layer 121BR.

[0142] 4 and 5, the first pad 121-1 and the second pad 121-2 of the first circuit pattern layer 121 of the embodiment may have the same layer structure. Although not shown in the figures, the second circuit pattern layer 122, the third circuit pattern layer 123, the first through electrode 131, and the second through electrode 132 may also have layer structures corresponding to the first pad 121-1 and the second pad 121-2 described below.

[0143] The first circuit pattern layer 121 includes a plurality of layers.

[0144] The first circuit pattern layer 121 includes a first layer 121a disposed on the first insulating layer 111. The first layer 121a may serve as a seed layer for electroplating a second layer 121b of the first circuit pattern layer 121.

[0145] For example, the first layer 121a may be a chemical copper plating layer, or may be a copper foil layer (Cu foil).

[0146] In an embodiment, the first layer 121a may include only one of the chemical copper plating layer and the copper foil layer.

[0147] In another embodiment, the first layer 121a may include both the chemical copper plating layer and the copper foil layer.

[0148] The thickness T1 of the first layer 121a may be in the range of 0.5 μm to 3.0 μm. Preferably, the thickness T1 of the first layer 121a may be in the range of 0.7 μm to 2.8 μm. More preferably, the thickness T1 of the first layer 121a may be in the range of 0.8 μm to 2.5 μm.

[0149] If the thickness T1 of the first layer 121a is less than 0.5 μm, the first layer 121a may not function as a seed layer. If the thickness T1 of the first layer 121a is less than 0.5 μm, it may be difficult to form the first layer 121a with a uniform thickness on the upper surface of the first insulating layer 111.

[0150] If the thickness T1 of the first layer 121a exceeds 3.0 μm, the time required to etch the first layer 121a may increase. If the thickness T1 of the first layer 121a exceeds 3.0 μm, deformation of the second layer 121b may occur when etching the first layer 121a. The deformation of the second layer 121b may mean that the difference between the width of the upper surface and the width of the lower surface of the second layer 121b increases because the side portions of the first layer 121a are also etched.

[0151] A second layer 121b may be disposed on the first layer 121a. The second layer 121b may be an electroplated layer formed by electroplating using the first layer 121a as a seed layer.

[0152] The thickness of the second layer 121b may correspond to a value obtained by subtracting the thickness T1 of the first layer 121a from the total thickness of the first circuit pattern layer 121. The total thickness of the first circuit pattern layer 121 has already been described, so a detailed description thereof will be omitted.

[0153] Meanwhile, the first pad 121-1 and the second pad 121-2 of the first circuit pattern layer 121 may include the first layer 121a and the second layer 121b, respectively. In this case, the first pad 121-1 and the second pad 121-2 may include the same first layer 121a and second layer 121b and may be distinguished according to their arrangement positions and functions.

[0154] The horizontal width W1 of the first pad 121-1 can be in the range of 40 μm to 70 μm. Preferably, the horizontal width W1 of the first pad 121-1 can be in the range of 42 μm to 68 μm. More preferably, the horizontal width W1 of the first pad 121-1 can be in the range of 45 μm to 65 μm.

[0155] If the width W1 of the first pad 121-1 is smaller than 40 μm, a connecting member (e.g., a semiconductor device) may not be stably mounted on the first pad 121-1. For example, if the width W1 of the first pad 121-1 is smaller than 40 μm, the amount of conductive adhesive (e.g., solder) disposed on the first pad 121-1 may be reduced, which may reduce the bonding strength between the first pad 121-1 and the connecting member.

[0156] If the width W1 of the first pad 121-1 is greater than 70 μm, the area of ​​the cavity 150 may increase corresponding to the width of the first pad 121-1, which may result in a decrease in circuit integration or an increase in the area of ​​the circuit board and semiconductor package.

[0157] The first recessed portion 112R may be recessed in a direction from a lower end of the sidewall 150S of the cavity 150 in the second insulating layer 112 toward the outer surface of the second insulating layer 112 (or in a direction away from the cavity). For example, the first recessed portion 112R may be recessed in the second insulating layer 112 in a horizontal direction.

[0158] A vertical distance of the first recessed portion 112R may correspond to a thickness T1 of the first layer 121a of the first pad 121-1. For example, the barrier layer 121BR may be a part of the first layer 121a that is entirely formed on the first insulating layer 111 during the manufacturing process of the first circuit pattern layer. Therefore, the barrier layer 121BR may have a thickness corresponding to the first layer 121a. Thus, a vertical distance of the first recessed portion 112R may correspond to a thickness T1 of the first layer 121a of the first pad 121-1.

[0159] The vertical distance of the first recessed portion 112R may be in the range of 0.5 μm to 3.0 μm. Preferably, the vertical distance of the first recessed portion 112R may be in the range of 0.7 μm to 2.8 μm. More preferably, the vertical distance of the first recessed portion 112R may be in the range of 0.8 μm to 2.5 μm.

[0160] The horizontal width W2 of the first recessed portion 112R may correspond to the vertical distance of the first recessed portion 112R. That is, the first recessed portion 112R may be formed by etching a portion of the second portion 121BR2 of the barrier layer 121BR, which is covered by the second insulating layer 112, after the cavity 150 is formed. Therefore, the horizontal width W2 of the first recessed portion 112R may correspond to the vertical distance of the first recessed portion 112R. For example, the horizontal width W2 of the first recessed portion 112R may be in the range of 0.5 μm to 3.0 μm. Preferably, the horizontal width W2 of the first recessed portion 112R may be in the range of 0.7 μm to 2.8 μm. More preferably, the horizontal width W2 of the first recessed portion 112R may be in the range of 0.8 μm to 2.5 μm.

[0161] However, taking into consideration process deviations in the process of etching the entire first portion 121BR1 and part of the second portion 121BR2 of the barrier layer 121BR, the horizontal width W2 of the first recessed portion 112R may be smaller than the vertical distance of the first recessed portion 112R. For example, the horizontal width W2 of the first recessed portion 112R may be 50% to 95% of the vertical distance of the first recessed portion 112R or the thickness T1 of the first layer 121a. For example, the horizontal width W2 of the first recessed portion 112R may be 55% to 92% of the vertical distance of the first recessed portion 112R or the thickness T1 of the first layer 121a. For example, the horizontal width W2 of the first recessed portion 112R may be 60% to 90% of the vertical distance of the first recessed portion 112R or the thickness T1 of the first layer 121a.

[0162] For example, if the horizontal width W2 of the first recessed portion 112R is smaller than 50% of the vertical distance of the first recessed portion 112R or the thickness T1 of the first layer 121a, the effect of preventing warpage of the circuit board and the semiconductor package caused by the first recessed portion 112R may be insufficient. Furthermore, under the condition of over-etching the barrier layer 121BR, it may be difficult to form the horizontal width W2 of the first recessed portion 112R to be larger than 95% of the vertical distance of the first recessed portion 112R or the thickness T1 of the first layer 121a.

[0163] Meanwhile, the width W1 of the first pad 121-1 may be greater than the thickness T1 of the first layer 121a. Also, the width W1 of the first pad 121-1 may be greater than the vertical distance of the first recessed portion 112R. Also, the width W1 of the first pad 121-1 may be greater than the horizontal width W2 of the first recessed portion 112R.

[0164] For example, the width W1 of the first pad 121-1 may be 35 times or more, 40 times or more, or 45 times or more the thickness T1 of the first layer 121a. The width W1 of the first pad 121-1 may also be 35 times or more, 40 times or more, or 45 times or more the vertical distance of the first recessed portion 112R. The width W1 of the first pad 121-1 may also be 35 times or more, 40 times or more, or 45 times or more the horizontal width W2 of the first recessed portion 112R. That is, the thickness T1 of the first layer 121a, the vertical distance of the first recessed portion 112R, and the horizontal width W2 of the first recessed portion 112R may have corresponding values, thereby satisfying the above-described relationship with the width W1 of the first pad 121-1. This allows the embodiment to maximize the effects of the first recessed portion 112R while improving circuit integration and physical and electrical reliability.

[0165] Furthermore, a metal layer 121BP may be provided along the first recess portion 112R. The horizontal width W3 of the metal layer 121BP may be in the range of 1.0 μm to 7.0 μm. Preferably, the horizontal width W3 of the metal layer 121BP may be in the range of 1.5 μm to 6.5 μm. More preferably, the horizontal width W3 of the metal layer 121BP may be in the range of 2.0 μm to 6.0 μm.

[0166] The metal layer 121BP may be provided adjacent to the first recess portion 112R, thereby functioning as a reinforcing member to prevent vertical warping of the circuit board and semiconductor package while preventing thermal expansion or contraction in the horizontal direction.

[0167] The horizontal width W3 of the metal layer 121BP may be greater than the horizontal width W2 of the first recessed portion 112R. In this case, if the first recessed portion 112R is provided, thermal expansion and / or thermal contraction can be alleviated, but this may cause warpage in the vertical direction. Therefore, the horizontal width W3 of the metal layer 121BP is set greater than the horizontal width W2 of the first recessed portion 112R, thereby alleviating thermal expansion and / or thermal contraction and minimizing warpage in the vertical direction.

[0168] The metal layer 121BP is disposed along the periphery of the first recessed portion 112R, so that at least a portion of the side surface of the metal layer 121BP may be exposed through the first recessed portion 112R. For example, the first recessed portion 112R may include a plurality of first recesses formed along the circumferential direction of the inner surface of the plurality of metal patterns of the metal layer 121BP. For example, the side surface of the metal layer 121BP may overlap the first recessed portion 112R in the horizontal direction and may not be covered by the second insulating layer 112.

[0169] The metal layer 121BP also includes a plurality of metal patterns spaced apart from one another along the circumferential direction of the lower end of the sidewall of the cavity 150. In this case, each of the plurality of metal patterns of the metal layer 121BP may have the same horizontal width W3 as shown in FIG. 4, but is not limited to this.

[0170] For example, the metal patterns of the metal layer 121BP may have different horizontal widths along the circumferential direction of the first recessed portion 112R, thereby more efficiently preventing the circuit board from warping significantly in a specific direction.

[0171] Exemplarily, the second pads 121-2 may be provided at different densities along the circumferential direction of the lower end of the sidewall 150S of the cavity 150. For example, the density of the second pads adjacent to a first part of the sidewall of the cavity 150 may be greater than the density of the second pads adjacent to a second part opposite the first part. In this case, in an embodiment, a metal pattern having a horizontal width of 3-1 width may be provided along the circumferential direction of the first part of the sidewall of the cavity 150, and a metal pattern having a horizontal width of 3-2 width, which is greater than the 3-1 width, may be provided along the circumferential direction of the second part of the sidewall of the cavity 150.

[0172] Thus, in this embodiment, the metal density of each region can be made uniform using the metal layer 121BP, thereby further preventing warpage of the circuit board.

[0173] In addition, the metal patterns of the metal layer 121BP may be spaced apart from each other by a predetermined distance W4.

[0174] The spacing W4 between the plurality of metal patterns of the metal layer 121BP can be in the range of 2 μm to 12 μm. Preferably, the spacing W4 between the plurality of metal patterns of the metal layer 121BP can be in the range of 2.5 μm to 11.5 μm. More preferably, the spacing W4 between the plurality of metal patterns of the metal layer 121BP can be in the range of 3 μm to 11 μm.

[0175] If the spacing W4 between the metal patterns of the metal layer 121BP is less than 2 μm, warpage of the circuit board in the vertical direction may increase, thereby reducing the physical reliability of the circuit board. If the spacing W4 between the metal patterns of the metal layer 121BP is less than 2 μm, it may be difficult to arrange a connection pattern (221-3 in FIG. 8) that directly connects the first pad and the second pad on the first insulating layer 111. Exemplarily, if the spacing W4 between the metal patterns of the metal layer 121BP is less than 2 μm, at least two of the metal patterns may be electrically connected to each other due to process errors in the process of forming the metal patterns, and an electrical short problem may occur in which the metal patterns electrically connect the connection patterns 221-3 to each other.

[0176] Furthermore, if the spacing W4 between the multiple metal patterns of the metal layer 121BP is greater than 12 μm, the adhesion between the first insulating layer 111 and the second insulating layer 112 may decrease, which may result in a mechanical reliability problem in which the second insulating layer 112 peels off from the first insulating layer 111. Furthermore, if the spacing W4 between the multiple metal patterns of the metal layer 121BP is greater than 12 μm, the effect of improving the mechanical and / or electrical reliability provided by the metal layer 121BP may be insufficient.

[0177] FIG. 6 is a cross-sectional view showing a circuit board according to the second embodiment.

[0178] Referring to FIG. 6, the circuit board 100A of the second embodiment includes a first insulating layer 111, a second insulating layer 112, a first circuit pattern layer 121, a second circuit pattern layer 122, a third circuit pattern layer 123, a first through electrode 131, a second through electrode 132, a first protective layer 141, and a second protective layer 142.

[0179] Furthermore, the circuit board 100A of the second embodiment includes a reinforcing portion.

[0180] In this case, the reinforcing portion in the circuit board of the first embodiment includes the first recess portion 112R and the metal layer 121BP provided along the circumferential direction of the lower end of the side wall 150S of the cavity 150.

[0181] In contrast, the reinforcing portion of the circuit board 100A of the second embodiment may include only the first recessed portion 112R.

[0182] For example, in the first embodiment, a part of the second portion 121BR2 of the barrier layer 121BR is removed to provide the reinforcing portion including the first recessed portion 112R and the metal layer 121BP.

[0183] In contrast, in the second embodiment, the second portion 121BR2 of the barrier layer 121BR is entirely removed, so that the circuit board of the second embodiment can include only the first recess portion 112R formed by entirely removing the second portion 121BR2 of the barrier layer 121BR.

[0184] FIG. 7 is a cross-sectional view showing a circuit board according to the third embodiment.

[0185] Referring to FIG. 7, the circuit board 100A of the third embodiment includes a first insulating layer 111, a second insulating layer 112, a first circuit pattern layer 121, a second circuit pattern layer 122, a third circuit pattern layer 123, a first through electrode 131, a second through electrode 132, a first protective layer 141, and a second protective layer 142.

[0186] Furthermore, the circuit board 100B of the third embodiment includes a reinforcing portion.

[0187] In this case, the reinforcing portion in the circuit board of the first embodiment included a first recess 112R and a metal layer 121BP provided along the circumferential direction of the lower end of the side wall 150S of the cavity 150. In addition, the reinforcing portion in the circuit board of the second embodiment included a first recess 112R provided along the circumferential direction of the lower end of the side wall 150S of the cavity 150.

[0188] In contrast, the reinforcing portion of the circuit board 100B of the third embodiment can include only the metal layer 121BP.

[0189] For example, in the first embodiment, a part of the second portion 121BR2 of the barrier layer 121BR is removed to provide a reinforcing portion including the first recessed portion 112R and the metal layer 121BP, and in the second embodiment, the entire second portion 121BR2 of the barrier layer 121BR is removed to provide a reinforcing portion including only the first recessed portion 112R.

[0190] In contrast to this, in the third embodiment, only the first portion 121BR1 of the barrier layer 121BR is selectively removed without removing the second portion 121BR2 of the barrier layer 121BR. As a result, the circuit board of the second embodiment can provide a reinforcing portion including only the metal layer 121BP, since the second portion 121BR2 of the barrier layer 121BR is not removed.

[0191] Therefore, the metal layer 121BP in the first embodiment is provided at a certain distance from the lower end of the side surface of the cavity 150 toward the outside of the second insulating layer 112.

[0192] In contrast, the metal layer 121BP of the third embodiment does not need to be spaced apart from the lower end of the side surface of the cavity 150, and the side surface of the metal layer 121BP may be directly connected to the lower end of the side surface of the cavity 150.

[0193] FIG. 8 is a cross-sectional view showing a circuit board according to a fourth embodiment, and FIG. 9 is a plan view of the circuit board of FIG.

[0194] Referring to Figures 8 and 9, the circuit board 200 of the fourth embodiment includes a first insulating layer 211, a second insulating layer 212, a first circuit pattern layer 221, a second circuit pattern layer 222, a third circuit pattern layer 223, a first through electrode 231, a second through electrode 232, a first protective layer 241, and a second protective layer 242.

[0195] The second insulating layer 212 may also include a cavity 250 .

[0196] Additionally, the first circuit pattern layer 221 may include a first pad 221-1 and a second pad 222-2.

[0197] Here, the circuit board of the fourth embodiment may differ from the circuit board of the first embodiment in that the first circuit pattern layer 221 further includes a connecting pattern 221-3.

[0198] The connecting pattern 221-3 can directly connect the first pad 221-1 and the second pad 221-2 of the first circuit pattern layer 221.

[0199] One end of the connection pattern 221-3 may be connected to the first pad 221-1, and the other end of the connection pattern 221-3 may be connected to the second pad 221-2. A plurality of first pads 221-1 may be provided, and therefore, a plurality of connection patterns 221-3 may be provided corresponding to the number of first pads 221-1.

[0200] The connecting pattern 221-3 may include a first pattern region 221-31 that vertically overlaps the cavity 250. An end of the first pattern region 221-31 of the connecting pattern 221-3 may be connected to the first pad 221-1.

[0201] The connecting pattern 221-3 may include a second pattern region 221-32 that does not vertically overlap the cavity 250. An end of the second pattern region 221-32 of the connecting pattern 221-3 may be connected to the second pad 221-2.

[0202] The connecting pattern 221-3 may not be connected to a reinforcing portion provided along the circumferential direction of the lower end of the sidewall 250S of the cavity 250. For example, the connecting pattern 221-3 may not be connected to the metal layer 221BP of the reinforcing portion. That is, the metal layer 221BP may include a plurality of metal patterns, which may be provided at the lower end of the sidewall 250S of the cavity 250, avoiding the area where the connecting pattern 221-3 is disposed. For example, the connecting pattern 221-3 may be disposed across a spaced area between the plurality of metal patterns of the metal layer 221BP on the first insulating layer 211.

[0203] In this case, the metal layer 221BP of the embodiment has a plurality of metal patterns provided along the circumferential direction of the lower end of the side wall 250S of the cavity 250. As a result, in the embodiment, it is possible to arrange a connection pattern 221-3 on the first insulating layer 211 that directly connects the first pad 221-1 and the second pad 221-2.

[0204] For example, in the prior art, when a stopper is used, the metal layer is provided in a closed loop shape along the circumferential direction, which makes it impossible to arrange the connection pattern. For example, when arranging the connection pattern in the prior art, adjacent connection patterns are electrically connected by the stopper having the closed loop shape, which causes an electrical short problem.

[0205] In contrast, in the embodiment, the metal layer 221BP includes a plurality of metal patterns spaced apart from each other in the circumferential direction by changing the shape of the barrier layer 121BR, thereby resolving the reliability problem of electrical connection between the plurality of connection patterns due to the separated metal patterns even when the plurality of connection patterns are disposed on the first insulating layer 211.

[0206] Furthermore, although the figures illustrate that the connection pattern 221-3 is not connected to the first recess portion 212R and the metal layer 221BP of the reinforcing portion, this is not limiting. For example, at least a portion of the connection pattern 221-3 may be connected to the first recess portion 112R and the metal layer 221BP. However, if multiple connection patterns are provided, each of the multiple connection patterns may be connected to a different first recess and metal pattern, thereby electrically isolating the multiple connection patterns from each other.

[0207] For example, the metal layer 221BP may include a first metal pattern and a second metal pattern spaced apart from each other, and the connecting pattern 221-3 may include a first connecting pattern and a second connecting pattern spaced apart from each other. In this case, the first connecting pattern may be connected to the first metal pattern, and the second connecting pattern may be connected to the second metal pattern. However, the first metal pattern and the second metal pattern may be electrically isolated from each other, and therefore the first connecting pattern and the second connecting pattern may also be electrically isolated from each other.

[0208] 9, any one of the plurality of connection patterns 221-3 may vertically overlap any one of the plurality of metal patterns of the metal layer 221BP. For example, a first layer, which is a seed layer, of at least one of the plurality of connection patterns 221-3 may include a portion whose width varies depending on the extension direction of the connection pattern 221-3. The portion whose width varies may correspond to a portion where the metal pattern of the metal layer 221BP is disposed.

[0209] 1 can be omitted from the first through-electrode 231 that penetrates the first insulating layer 211. For example, if the connection pattern 221-3 is not provided, a first through-electrode that overlaps the first pad 221-1 in the vertical direction must be provided to electrically connect the first pad 221-1 and the second pad 221-2.

[0210] In contrast, in the embodiment, the first pad 221-1 and the second pad 221-2 can be directly connected using the connection pattern 221-3, thereby eliminating the need for a first through-electrode that vertically overlaps the first pad 221-1. Furthermore, in the embodiment, the first pad 221-1 and the second pad 221-2 can be directly connected using the connection pattern 221-2, thereby reducing the length of the signal line between them. For example, the signal line including the connection pattern 221-3 may be shorter than the signal line including the first through-electrode. Therefore, in the embodiment, the signal transmission line between the first pad 221-1 and the second pad 221-2 can be reduced, thereby minimizing signal transmission loss and improving electrical characteristics.

[0211] Therefore, in the embodiment, a reinforcing portion including the first recess portion 212R and the metal layer 221BP may be disposed, and a connecting pattern 221-3 that directly connects the first pad 221-1 and the second pad 221-2 may be disposed on the first insulating layer 211. Therefore, the embodiment may directly connect the first pad and the second pad using the connecting pattern, thereby improving circuit integration. Therefore, the embodiment may minimize signal transmission loss by reducing the number of signal transmission lines between the first pad 221-1 and the second pad 221-2, thereby improving electrical characteristics.

[0212] 10 is a cross-sectional view showing a circuit board according to a fifth embodiment, FIG. 11 is a plan view of the circuit board of FIG. 10, and FIG. 12 is an enlarged view of a partial area of ​​the circuit board of FIG.

[0213] 10 to 12, the circuit board 300 of the fifth embodiment includes the first insulating layer 311, the second insulating layer 312, the first circuit pattern layer 321, the second circuit pattern layer 322, the third circuit pattern layer 323, the first through electrode 331, the second through electrode 332, the first protective layer 341, and the second protective layer 342.

[0214] The second insulating layer 312 may also include a cavity 350 .

[0215] The first circuit pattern layer 321 may also include a first pad 321-1, a second pad 322-2, and a connecting pattern 321-3.

[0216] The circuit board of the fifth embodiment may differ from the circuit board of the fourth embodiment in that a second recess portion 311R is further provided on the upper surface of the first insulating layer 311.

[0217] The second recess portion 311R may be provided on the upper surface of the first insulating layer 311.

[0218] That is, the circuit board of the fifth embodiment may include a first recessed portion 312R provided in the second insulating layer 312 and a second recessed portion 311R provided in the first insulating layer 311.

[0219] Each of the first recessed portion 312R and the second recessed portion 311R may be connected to a lower end of the side wall 350S of the cavity 350.

[0220] For example, a portion of the lower end of the side wall 350S of the cavity 350 may be connected to the first recessed portion 312R, and the remaining portion of the lower end of the side wall 350S of the cavity 350 may be connected to the second recessed portion 311R.

[0221] At this time, the first recessed portion 312R includes a plurality of first recesses formed in the second insulating layer 312 in a horizontally concave shape, as described in the previous embodiment.

[0222] The second recess portion 311R includes a second recess formed in the upper surface of the first insulating layer 311 in a concave shape extending in a vertical direction.

[0223] The second recessed portion 311R may be provided in a periphery region of the first region R1 of the first insulating layer 311. For example, the second recessed portion 311R may be provided in a periphery region of the bottom surface of the cavity 350. That is, the second recessed portion 311R may be provided in an upper surface of the first insulating layer 311 connected to a lower end of the sidewall 350S of the cavity 350. The second recessed portion 311R may be concave from the upper surface toward the lower surface of the first insulating layer 311.

[0224] The second recessed portion 311R may be formed on the upper surface of the first insulating layer 311 by a desmear process that is performed after forming the cavity 350 in the second insulating layer 312.

[0225] For example, the barrier layer 121BR has a recess 121BC, and at least a portion of the recess 121BC vertically overlaps the cavity 350. Therefore, when a desmear process is performed with the barrier layer 121BR in place, a portion of the upper surface of the first insulating layer 311 may be exposed to the outside through the recess 121BC. In this case, in the embodiment, by adjusting the width of the recess 121BC, the second recess 311R may be prevented from being formed during the desmear process, or the second recess 311R may be formed on the upper surface of the first insulating layer 311. The second recess 311R may be formed corresponding to the recess 121BC.

[0226] Therefore, according to the embodiment, the second insulating layer 312 may be provided with the first recessed portion 312R in the horizontal direction, and the first insulating layer 311 may be provided with the second recessed portion 311R in the vertical direction.

[0227] As a result, the embodiment can more efficiently distribute the stress acting on the first insulating layer 31 and the second insulating layer 32, thereby improving the warpage characteristics of the circuit board.

[0228] For example, the second recessed portion 311R may increase the surface area of ​​the upper surface of the first insulating layer 311. As a result, the second recessed portion 311R may mitigate horizontal expansion of the circuit board due to thermal stress generated in the manufacturing or use environment of the circuit board, thereby improving the mechanical and / or physical reliability of the circuit board and a semiconductor package including the circuit board.

[0229] In addition, the first recessed portion 312R can reduce the area of ​​the interface between the first insulating layer 311 and the second insulating layer 312, thereby dispersing stress acting on the second insulating layer 312. Therefore, the first recessed portion 312R can mitigate a phenomenon in which the circuit board warps in a specific direction (for example, a phenomenon in which both ends of the circuit board warp upward or downward).

[0230] In this case, the first recessed portions 312R and the second recessed portions 311R may be alternately provided along the circumferential direction of the lower end of the side wall 350S of the cavity 350.

[0231] For example, the first recess portion 312R includes a plurality of first recesses, and the second recess portion 311R includes a plurality of second recesses. In this case, the plurality of first recesses and the plurality of second recesses may be alternately arranged along the circumferential direction of the lower end of the side wall 350S of the cavity 350. This is because the second recess portion 311R is a region corresponding to the recess 121BC of the barrier layer 121BR, and the first recess portion 312R corresponds to a region of the second portion 121BR2 of the barrier layer 121BR excluding the recess 121BC.

[0232] The vertical distance T2 of the second recessed portion 311R may be in the range of 0.1 μm to 6.0 μm. Preferably, the vertical distance T2 of the second recessed portion 311R may be in the range of 0.5 μm to 5.5 μm. More preferably, the vertical distance T2 of the second recessed portion 311R may be in the range of 1.0 μm to 5 μm.

[0233] The vertical distance T2 of the second recess 311R may refer to the vertical distance from the top end of the upper surface of the first insulating layer 311 to the bottom end of the bottom surface of the second recess 311R. If the vertical distance T2 of the second recess 311R is less than 0.1 μm, the second recess 311R may not be able to sufficiently mitigate thermal expansion and / or thermal contraction of the circuit board. Furthermore, if the vertical distance T2 of the second recess 311R is less than 0.1 μm, the adhesion between the second insulating layer 312 and the second circuit pattern layer 322 may be reduced. For example, the second recess 311R may be formed by a desmear process to impart a certain level of surface roughness to the top surface of the second insulating layer 312 and thereby increase the adhesion between the second insulating layer 312 and the second circuit pattern layer 322. In this case, if the vertical distance T2 of the second recess portion 311R is less than 0.1 μm, it may mean that the second insulating layer 312 is not given a surface roughness of a certain level or more, which may reduce the adhesion between the second insulating layer 312 and the second circuit pattern layer 322.

[0234] If the vertical distance T2 of the second recessed portion 311R exceeds 6.0 μm, the surface roughness of the second insulating layer 312 may increase correspondingly, and the surface roughness of the second circuit pattern layer 322 may increase correspondingly to the surface roughness of the second insulating layer 312. Furthermore, if the surface roughness of the second circuit pattern layer 322 increases, a skin effect may occur, increasing transmission loss of signals transmitted through the second circuit pattern layer 322. Furthermore, if the vertical distance T2 of the second recessed portion 311R exceeds 6.0 μm, the glass fibers 311GF provided in the first insulating layer 311 may be exposed through the second recessed portion 311R, and the exposed glass fibers 311GF may reduce the mechanical and / or electrical reliability of the circuit board and the semiconductor package.

[0235] For example, the vertical distance T2 of the second recessed portion 311R may be determined based on the position of the glass fiber 311GF provided in the first insulating layer 311.

[0236] For example, the vertical distance T3 from the upper surface of the first insulating layer 311 to the uppermost end of the glass fiber 311GF may be greater than the vertical distance T2 of the second recessed portion 311R. For example, the vertical distance T3 from the upper surface of the first insulating layer 311 to the uppermost end of the glass fiber 311GF may be in the range of 3 μm to 10 μm. Preferably, the vertical distance T3 may be in the range of 3.5 μm to 9.5 μm. More preferably, the vertical distance T3 may be in the range of 4.0 μm to 9.0 μm.

[0237] If the vertical distance T3 is less than 3.0 μm, the glass fiber 311GF provided in the first insulating layer 311 may be exposed to the outside due to various tolerances that occur in the manufacturing process of the circuit board, which may cause reliability problems. Also, if the vertical distance T3 is more than 10 μm, the amount of glass fiber 311GF provided in the first insulating layer 311 may decrease or the thickness of the first insulating layer 311 may increase, which may result in a decrease in warpage characteristics or an increase in volume of the circuit board and the semiconductor package.

[0238] For example, the vertical distance T2 of the second recessed portion 311R may be in the range of 4% to 70% of the vertical distance T3 of the glass fiber 311GF. Preferably, the vertical distance T2 of the second recessed portion 311R may be in the range of 8% to 65% of the vertical distance T3 of the glass fiber 311GF. More preferably, the vertical distance T2 of the second recessed portion 311R may be in the range of 10% to 60% of the vertical distance T3 of the glass fiber 311GF.

[0239] The horizontal width W5 of the second recess portion 311R may correspond to, but is not limited to, the spacing between the plurality of first recesses of the first recess portion 312R and / or the spacing W4 between the plurality of metal patterns of the metal layer 321BP.

[0240] At least one of the second recesses of the second recess portion 311R may be connected to the connection pattern 321-3.

[0241] For example, the second recesses of the second recess portion 311R may include a 2-1 recess 311R1 that is not connected to the connection pattern 321-3 and is provided between the first recesses, and the second recess portion 311R may include a 2-2 recess 311R2 that is connected to the connection pattern 321-3.

[0242] For example, the connecting pattern 321-3 may include a first pattern region 321-31 that vertically overlaps the cavity 350 and a second pattern region 321-32 that does not vertically overlap the cavity 350. In addition, the 2-2 recess 311R2 may be connected to at least a portion of a side surface of the second pattern region 221-32 of the connecting pattern 321-3.

[0243] As a result, the embodiment can more efficiently solve the problem of electrical reliability caused by electrical connection between multiple connection patterns due to process errors by connecting the 2-2 recess 311R2 of the second recess portion 311R to the connection pattern 321-3.

[0244] FIG. 13 is a diagram showing the top surface of the first region of the first insulating layer according to the example and the comparative example.

[0245] Referring to FIG. 13(a), in the comparative example, the desmear process is performed without providing a barrier layer, and as a result, the glass fibers 311GF may be exposed through the upper surface of the first region R1 of the first insulating layer 311.

[0246] 13(b), in the embodiment, the desmear process is performed with the barrier layer provided, so that the glass fibers 311GF may not be exposed through the upper surface of the first region R1 of the first insulating layer 311. For example, only the filler provided in the first insulating layer 311 may be exposed on the upper surface of the first region R1 of the first insulating layer 311.

[0247] FIG. 14 is a cross-sectional view showing a semiconductor package according to an embodiment.

[0248] 14, a semiconductor package according to an embodiment may include the circuit board of FIG. 8. However, the embodiment is not limited thereto, and the semiconductor package may include any one of the circuit boards of FIGS. 1 to 7 and 10 to 12.

[0249] The semiconductor package may include a connecting member 410 disposed on the first pad 221-1 and a connecting member 420 disposed on the connecting member 410.

[0250] The connecting member 420 may be any one of a semiconductor device, an interposer, a package substrate, an inorganic bridge, and an organic bridge.

[0251] Meanwhile, a molding member 430 may be disposed in the cavity 250. The molding member 430 may be disposed in the cavity 250 by molding the connection member 420 therein.

[0252] Furthermore, the molding member 430 may be provided by filling the first recessed portion 212R. In this case, when the circuit board of Fig. 10 is included, the molding member may be provided by further filling the second recessed portion 311R.

[0253] The first recessed portion 212R may increase the contact area between the molding member 430 and the first and second insulating layers 211 and 212. Exemplarily, the first recessed portion 212R may function as an anchor that improves the bonding strength between the molding member 430 and the first and second insulating layers 211 and 212. At least a portion of the molding member 430 may be connected to the metal pattern of the metal layer 221BP provided along the first recessed portion 212R. Thus, in this embodiment, the heat dissipation effect may be maximized through the metal layer 221BP and the molding member 430.

[0254] Furthermore, the molding member 430 may have a low dielectric constant to enhance heat dissipation characteristics. For example, the dielectric constant Dk of the molding member 430 may be 0.2 to 10. For example, the dielectric constant Dk of the molding member 430 may be 0.5 to 8. For example, the dielectric constant Dk of the molding member 430 may be 0.8 to 5. Thus, in an embodiment, the molding member 430 has a low dielectric constant, which can enhance the heat dissipation characteristics of the connecting member.

[0255] An embodiment may include a first insulating layer and a second insulating layer disposed on the first insulating layer and including a cavity. A metal layer is disposed between the first insulating layer and the second insulating layer along a circumferential direction of a lower end of a sidewall of the cavity. The metal layer includes a plurality of metal patterns spaced apart from each other along the circumferential direction.

[0256] The metal patterns may function as a reinforcing member that improves the rigidity of the circuit board. For example, the metal patterns may distribute or mitigate stress acting on the circuit board, thereby improving the warpage characteristics of the circuit board. Furthermore, the metal patterns may mitigate horizontal expansion of the circuit board due to thermal stress generated in the manufacturing or use environment of the circuit board, thereby improving the mechanical and / or physical reliability of the circuit board and a semiconductor package including the circuit board.

[0257] The embodiment further includes a connection pattern disposed on the first insulating layer and directly connecting the first pad and the second pad. The connection pattern may be provided across the plurality of metal patterns. A plurality of connection patterns may be provided. The plurality of metal patterns may be spaced apart from each other along the circumferential direction, so that the connection patterns may not be electrically connected to each other on the first insulating layer. Therefore, the embodiment may directly connect the first pad and the second pad using the connection pattern, thereby eliminating the need for a first through-electrode that vertically overlaps the first pad. Furthermore, by directly connecting the first pad and the second pad using the connection pattern, the embodiment may reduce the length of the signal line between them. For example, a signal line including the connection pattern may be shorter than a signal line including the first through-electrode. Therefore, the embodiment may minimize signal transmission loss by reducing the signal transmission line between the first pad and the second pad, thereby improving electrical characteristics. Furthermore, the embodiment may improve circuit integration by disposing a connection pattern that directly connects the first pad and the second pad.

[0258] Meanwhile, in the embodiment, the second insulating layer may include a first recess portion provided between the plurality of metal patterns and a lower end of the sidewall of the cavity. The first recess portion may distribute or mitigate stress acting on the first insulating layer and the second insulating layer, thereby improving the warpage characteristics of the circuit board. For example, the first recess portion may reduce the area of ​​the interface between the first insulating layer and the second insulating layer, thereby dispersing stress acting on the second insulating layer. Therefore, the first recess portion may mitigate warpage of the circuit board in a specific direction (e.g., warpage of both ends of the circuit board upward or downward).

[0259] In addition, the first insulating layer of the embodiment may include a second recess portion formed along the circumferential direction. The second recess portion may be formed vertically concave from the top surface to the bottom surface of the first insulating layer. In this case, the first recess portion is a recess formed horizontally in the second insulating layer, and the second recess portion is a recess formed vertically in the first insulating layer. Therefore, the embodiment may use the first and second recess portions to distribute or relieve stress acting on the circuit board, thereby improving the warpage characteristics of the circuit board.

[0260] For example, the first and second recesses can mitigate horizontal expansion of the circuit board due to thermal stress generated in the manufacturing or use environment of the circuit board, thereby improving the mechanical and / or physical reliability of the circuit board and the semiconductor package including the circuit board. In this case, the second insulating layer can include an insulating material different from that of the first insulating layer. As a result, the first and second insulating layers can have different thermal expansion coefficients, which can cause vertical warping of the circuit board. Therefore, the first and second recesses can prevent the circuit board from warping in a specific direction (e.g., both ends of the circuit board warping upward or both ends of the circuit board warping downward).

[0261] Therefore, the embodiments may minimize the degree of warping along the vertical direction and the degree of expansion or contraction along the horizontal direction of the circuit board and the semiconductor package, thereby improving the mechanical and / or physical reliability of the circuit board and the semiconductor package. Furthermore, the embodiments may enable stable operation of semiconductor devices arranged on the circuit board, thereby improving the operational characteristics of electronic products and / or servers to which the semiconductor package is applied.

[0262] Meanwhile, in the embodiment, the plurality of metal patterns may have different horizontal widths along the circumferential direction. For example, the horizontal width of the metal pattern in the region with a relatively low metal density may be greater than the horizontal width of the metal pattern in the region with a relatively high metal density. Therefore, the embodiment may minimize warpage of the circuit board caused by the difference in metal density, thereby further improving the physical and / or electrical reliability of the circuit board and the semiconductor package.

[0263] In addition, in the embodiment, the desmear process of the second insulating layer is performed after the cavity is formed with the barrier layer provided, thereby preventing the glass fibers of the first insulating layer from being exposed and resolving the resulting problems with physical reliability and / or electrical reliability. Furthermore, in the embodiment, the desmear process conditions can be determined without taking into consideration the exposure of the glass fibers. For example, in the embodiment, the desmear conditions can be determined to optimally improve the adhesion between the second insulating layer and the second circuit pattern layer, thereby improving the adhesion between the second insulating layer and the second circuit pattern layer without causing the problem of the reinforcing member being exposed.

[0264] Meanwhile, the desmear process of the embodiment may be performed in a state where a through hole and a cavity penetrating the second insulating layer are formed. Therefore, the surface of the inner wall of the through hole and the inner wall of the cavity may also be treated during the desmear process. This may improve the adhesion between the second through electrode disposed in the through hole and the second insulating layer. Furthermore, the embodiment may improve the adhesion between the molding member disposed in the cavity and the second insulating layer.

[0265] Furthermore, the molding member may be provided by filling at least one of the first recessed portion and the second recessed portion, thereby further improving the bonding strength between the molding member and the circuit board.

[0266] A method for manufacturing a circuit board according to the embodiment will be described below.

[0267] 15 to 28 are diagrams showing the manufacturing method of the circuit board of FIG. 8 according to the embodiment in the order of steps.

[0268] 15, an embodiment may prepare an insulating member based on the manufacture of a circuit board. For example, an embodiment may prepare an insulating member including a first insulating layer 211 and a metal member (not shown) on the first insulating layer 211.

[0269] Referring to FIG. 16, in this embodiment, a process of forming a first through hole TH1 penetrating the first insulating layer 211 may be performed.

[0270] 17, in this embodiment, a process may be performed to form the circuit pattern layer and the first layers 221a and 223a of the through electrodes along the upper and lower surfaces of the first insulating layer 211 and the inner walls of the first through holes TH1. The first layers 221a and 223a may function as seed layers and may be formed through a chemical copper plating process.

[0271] 18, a process of forming an electroplated layer by performing electroplating using the first layers 221a and 223a as seed layers may be performed. The electroplated layer may include the second layer 221b of the first circuit pattern layer 221, the second metal layer 223b of the third circuit pattern layer 223, and the first through electrode 231. The first circuit pattern layer 221 may also include a first pad 221-1, a second pad 221-2, and a connecting pattern 221-3.

[0272] 19, in an embodiment, a process of removing a portion of the first layers 221a and 223a may be performed. For example, in an embodiment, the entire region of the first layers 221a and 223a may be removed by etching, excluding a portion that vertically overlaps the cavity 250 and functions as a barrier layer.

[0273] That is, in a general circuit board manufacturing process, the area that does not vertically overlap the second layer 221b of the entire first layer 221a of the first circuit pattern layer 221 may be entirely removed. However, in an embodiment, a portion of the first layer 221a that does not vertically overlap the second layer 221b (for example, an area where a cavity is formed) may not be removed.

[0274] 20, a part of the first layer 221a of the first circuit pattern layer 221 may function as a barrier layer 221BR. The outer surface of the barrier layer 221BR may be provided with a plurality of recesses 221BC spaced apart from one another.

[0275] Referring to FIG. 21, in this embodiment, a process of stacking a second insulating layer 212 on a first insulating layer 211 may be performed.

[0276] 22 and 23 , an embodiment may include a process of forming the cavity 250 and the second through hole TH2 by processing the second insulating layer 212. The second insulating layer 212 may include a photocurable resin, whereby the cavity 250 and the second through hole TH2 may be formed through a photolithography process including an exposure and development process. The barrier layer 221BR may include an overlapping portion 221BR1 that vertically overlaps the cavity 250 and a non-overlapping portion 221BR2 that does not vertically overlap the cavity 250 and is covered by the second insulating layer 212.

[0277] 24, in an embodiment, a desmear process may be performed after the cavity 250 and the second through hole TH2 are formed, whereby the inner wall of the cavity 250, the inner wall of the second through hole TH2, and the top surface of the second insulating layer 212 may be desmeared, thereby providing a certain level of surface roughness.

[0278] 10, at least a portion of the top surface of the first insulating layer 211 that vertically overlaps the cavity 350 (a region that vertically overlaps the recess) is not covered with the barrier layer 221BR, and thus the corresponding portion can also be desmeared. As a result, a second recess portion 311R can be further provided.

[0279] 25 and 26, in an embodiment, a portion of the barrier layer 221BR that does not vertically overlap the first pad 121-1 and the connecting pattern 121-3 may be removed.

[0280] At this time, the overlapping portion 221BR1 of the barrier layer 221BR may be completely removed. However, the non-overlapping portion 221BR2 of the barrier layer 221BR may be partially removed. For example, a portion of the non-overlapping portion 221BR2 of the barrier layer 221BR adjacent to the overlapping portion 221BR1 may be removed by over-etching. As a result, a first recess portion 212R may be formed in the second insulating layer 212, which is a region where the non-overlapping portion 221BR1 has been removed by over-etching.

[0281] In addition, a portion of the non-overlapping portion 221BR2 of the barrier layer 221BR may not be removed. Therefore, a metal layer 221BP corresponding to the non-overlapping portion that has not been removed may be formed along the first recess portion 212R between the first insulating layer 211 and the second insulating layer 212.

[0282] Next, referring to FIG. 27, in this embodiment, a process of forming the second through electrodes 232 and the second circuit pattern layer 222 may be performed.

[0283] Also, referring to FIG. 28, in this embodiment, a process of forming a first protective layer 241 on the second insulating layer 212 and a process of forming a second protective layer 242 under the first insulating layer 211 may be performed.

[0284] Meanwhile, when a circuit board having the above-described inventive features is used in IT devices or home appliances such as smartphones, server computers, and TVs, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the features of the present invention functions as a semiconductor package, it can safely protect the semiconductor chip from external moisture and contaminants, and can solve problems such as leakage current, electrical shorts between terminals, and electrical open circuits in terminals supplying power to the semiconductor chip. Furthermore, when it performs the signal transmission function, it can solve noise problems. As a result, the circuit board having the above-described inventive features can maintain stable functionality of IT devices and home appliances, and the entire product and the circuit board to which the present invention is applied can achieve functional integration or technical interrelationship with each other.

[0285] When a circuit board having the above-described features of the present invention is used in a transportation device such as a vehicle, it can solve the problem of distortion of signals transmitted to the transportation device, safely protect the semiconductor chip that controls the transportation device from the outside, and solve the problems of leakage current, electrical short circuits between terminals, and electrical open circuits of terminals supplying power to the semiconductor chip, thereby further improving the stability of the transportation device. Therefore, the transportation device and the circuit board to which the present invention is applied can be functionally integrated or technically linked with each other.

[0286] The features, structures, effects, etc. described in the above embodiments are included in at least one embodiment and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by a person skilled in the art to which the embodiment belongs. Therefore, content related to such combinations and modifications should be interpreted as being included in the scope of the embodiments.

[0287] The above description focuses on the embodiments, but these are merely illustrative and do not limit the embodiments. Those skilled in the art will understand that various modifications and applications not exemplified above are possible within the scope of the essential characteristics of the embodiments. For example, each component specifically illustrated in the embodiments can be modified and implemented. Differences related to such modifications and applications should be construed as being included within the scope of the embodiments defined in the appended claims.

Claims

1. a first insulating layer; a second insulating layer disposed on the second insulating layer and including a cavity; a circuit pattern layer disposed between the first insulating layer and the second insulating layer; The circuit pattern layer is a first pad overlapping the cavity along a vertical direction; a second pad that overlaps the first pad along the horizontal direction and does not overlap the cavity along the vertical direction; The circuit board includes a connection pattern that connects the first pad and the second pad.

2. further comprising a metal layer disposed between the first insulating layer and the second insulating layer; The circuit board according to claim 1 , wherein the metal layer includes a plurality of metal patterns spaced apart from one another and provided along a circumferential direction of a lower end of the side wall of the cavity.

3. The connection pattern is a first portion that vertically overlaps the cavity and is not covered by the second insulating layer; a second portion that does not vertically overlap the cavity and is covered with the second insulating layer.

4. The circuit board according to claim 2 , wherein the connecting pattern is provided on the first insulating layer across the plurality of metal patterns.

5. The circuit board according to claim 4 , wherein the connecting pattern is not connected to each of the plurality of metal patterns.

6. The connection pattern is provided in plurality, The circuit board according to claim 4 , wherein at least one of the plurality of connection patterns is connected to at least one of the plurality of metal patterns.

7. The circuit board according to claim 2 , wherein the plurality of metal patterns are provided along the circumferential direction with different horizontal widths.

8. The circuit board according to claim 2 , wherein the plurality of metal patterns are spaced apart at intervals in the range of 2 μm to 12 μm along the circumferential direction.

9. Each of the first pad and the second pad includes: a first layer disposed on the first insulating layer and a second layer disposed on the first layer; The circuit board according to claim 2 , wherein the thickness of each of the plurality of metal patterns corresponds to the thickness of the second layer of the first and second pads.

10. The circuit board according to any one of claims 1 to 9, wherein the second insulating layer includes a first recess portion that is horizontally concave from a lower end of the side wall of the cavity toward an outer surface of the second insulating layer.

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