Dynamic management of memory read requests

Abstract

The present application relates to dynamic management of memory read requests in a memory system of an electronic device. The electronic device identifies a queue of memory access requests for accessing the memory system. The queue of memory access requests includes at least one host read request and a current system read request. The electronic device monitors a workload state of the memory system based on the queue of memory access requests, and generates at least a first system read request and a second system read request from the current system read request based on the workload state of the memory system. The queue of memory access requests is updated by inserting the at least one host read request after the first system read request and before the second system read request.

Description

[Technical Field]

[0001] Related Applications This application is a continuation of and claims priority to U.S. patent application Ser. No. 18 / 092,007, filed Dec. 30, 2022, entitled "Dynamic Management of Memory Read Requests," the entire contents of which are incorporated herein by reference.

[0002] The present application generally relates to memory management, including, but not limited to, methods, systems, and non-transitory computer-readable media for managing the granularity level of background system read requests for memory access and improving quality of service associated with memory workloads. [Background technology]

[0003] In a computer system, memory is used to store instructions and data, and data is processed by one or more processors according to the instructions stored in the memory. Multiple memory units are used in different parts of a computer system to perform different functions. One or more processors use primary memory (e.g., registers and cache) to support real-time calculations and operations on data. The one or more processors are coupled to main memory, often including random access memory (RAM), via a memory bus. The main memory provides instructions and data to the one or more processors when the instructions and data are not found in the primary memory. Both the primary memory and main memory are volatile memories that must be periodically refreshed, and data stored in the memories will be lost if the processor is disconnected from a power source. Additionally, the one or more processors are further coupled to secondary memory (e.g., a hard disk drive (HDD) or a solid-state drive (SSD)), which is a non-volatile memory that retains the data stored in the memory when the processor is disconnected from a power source.

[0004]

[0003] A secondary storage device receives not only host read and write requests from one or more processors of a computer system, but also system read and write requests from a memory controller for managing the secondary storage device itself. Because a system read request typically involves a relatively large block of memory, any host write and write requests that follow the system read request will have a long latency. To efficiently access the memory of the computer device in response to the host access requests, it is beneficial to manage the memory read and write requests in a memory access queue to balance the system memory access requests with the host memory access requests. Summary of the Invention

[0005] Various embodiments of the present application relate to methods, systems, devices, and non-transitory computer-readable media for managing workloads of memory devices (e.g., SSDs, HDDs). Host read requests and system read requests are queued in a memory workload and prioritized based on the workload state of the memory workload. Specifically, system read requests (also referred to as background read requests or non-host read requests) are dispatched by a memory controller to perform internal memory management functions, including, but not limited to, garbage collection, read disturb, memory snapshot capture, memory mirroring, caching, and memory sparing. In some embodiments, a host read request following a system read request is completely moved ahead of the system read request. Alternatively, in some embodiments, system read requests are managed at different levels of granularity. A system read operation corresponding to a system read request is split into multiple system read operations for smaller memory chunks, and a host read request following the system read request is moved ahead of, and performed before, a subset of the multiple system read operations. By these measures, the latency of host read requests is reduced and, given the priority given to host read requests, the quality of service (QoS) of memory workloads is improved.

[0006] In one aspect, a method for controlling access to a memory system of an electronic device is implemented in an electronic device. The method includes identifying a queue of memory access requests for accessing the memory system. The queue of memory access requests includes at least one host read request and a current system read request. The method further includes monitoring a workload state of the memory system based on the queue of memory access requests, and generating at least a first system read request and a second system read request from the current system read request based on the workload state of the memory system. The method further includes updating the queue of memory access requests by inserting the at least one host read request after the first system read request and before the second system read request.

[0007] In some embodiments, the method further includes determining a system read chunk size based on the workload state of the memory system. The first and second system read requests are generated from the current system read request based on the system read chunk size. Furthermore, in some embodiments, determining the system read chunk size based on the workload state of the memory system further includes selecting a first system read chunk size in accordance with a determination that more than a threshold portion (e.g., >50%) of the queue of memory access requests are read requests, and selecting a second system read chunk size in accordance with a determination that the threshold portion or less (e.g., <50%) of the queue of memory access requests are read requests. The first system read chunk size is smaller than the second system read chunk size.

[0008] In some embodiments, the method further includes determining a host read transfer limit based on the workload state of the memory system. Moreover, in some embodiments, determining the host read transfer limit based on the workload state of the memory system further includes selecting a first host read transfer limit in accordance with a determination that more than a threshold portion (e.g., >50% or more) of the queue of memory access requests are read requests, and selecting a second host read transfer limit in accordance with a determination that the threshold portion or less (e.g., <50%) of the queue of memory access requests are read requests. The first host read transfer limit is greater than (i.e., more aggressive than) the second host read transfer limit.

[0009] In another aspect, some implementations include an electronic device including one or more processors and a memory having stored thereon instructions that, when executed by the one or more processors, cause the processors to perform any of the methods described above to control access to a memory system of the electronic device.

[0010] In yet another aspect, some implementations include a non-transitory computer-readable storage medium storing one or more programs that, when executed by one or more processors, cause the processors to perform any of the methods described above to control access to a memory system of an electronic device.

[0011] These exemplary embodiments and implementations are mentioned not to limit or define the present disclosure, but to provide examples to aid in its understanding. Additional embodiments are discussed in the detailed description of the invention, and further description is provided therein.

[0012] For a better understanding of the various implementations described, reference should be made to the following detailed description of the invention in connection with the following drawings, in which like reference numerals refer to corresponding parts throughout the drawings: [Brief explanation of the drawings]

[0013] [Figure 1] FIG. 1 is a block diagram of exemplary system modules in a typical electronic device according to some embodiments. [Figure 2] 1 is a block diagram of a memory system of an exemplary electronic device having one or more memory access queues, according to some embodiments. [Figure 3] 1 is a flowchart of a process for managing system read requests in a memory workload, according to some embodiments. [Figure 4A] FIG. 1 is a diagram of an exemplary memory access queue including a current system read request followed by at least one host read request, according to some embodiments. [Figure 4B] FIG. 1 is a diagram of an exemplary memory access queue including a system read request for a memory chunk followed by a host read request, according to some embodiments. [Figure 4C] 1A-1C are diagrams of three exemplary memory access queues in which host read requests progress around at least a subset of memory chunks, according to some embodiments. [Figure 4D] 1A-1C are diagrams of three exemplary memory access queues in which host read requests progress around at least a subset of memory chunks, according to some embodiments. [Figure 4E] 1A-1C are diagrams of three exemplary memory access queues in which host read requests progress around at least a subset of memory chunks, according to some embodiments. [Figure 5A] FIG. 1 is a diagram of an exemplary memory access queue including a current system read request followed by an additional system access request and at least one host read request, according to some embodiments. [Figure 5B] FIG. 1 is a diagram of an exemplary memory access queue including a system read request for a memory chunk followed by an additional system access request and a host read request, according to some embodiments. [Figure 5C] 1A-1C are diagrams of three exemplary memory access queues in which host read requests progress around at least a subset of memory chunks and additional system access requests, according to some embodiments. [Figure 5D] 1A-1C are diagrams of three exemplary memory access queues in which host read requests progress around at least a subset of memory chunks and additional system access requests, according to some embodiments. [Figure 5E] 1A-1C are diagrams of three exemplary memory access queues in which host read requests progress around at least a subset of memory chunks and additional system access requests, according to some embodiments. [Figure 6A] FIG. 10 is a diagram of another exemplary memory access queue including a system read request followed by a system access request and a host read request, in accordance with some embodiments. [Figure 6B] 1A-1C are diagrams of two exemplary memory access queues in which host read requests progress around system access requests, according to some embodiments. [Figure 6C] 1A-1C are diagrams of two exemplary memory access queues in which host read requests progress around system access requests, according to some embodiments. [Figure 7A] 1 is a flowchart of a method for controlling access to a memory system, according to some embodiments. [Figure 7B] 1 is a flowchart of a method for controlling access to a memory system, according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0014] Like reference numerals refer to corresponding parts throughout the several views of the drawings.

[0015] Reference will now be made in detail to specific embodiments, examples of which are illustrated in the accompanying drawings. In the following detailed description, numerous non-limiting specific details are set forth to aid in understanding the subject matter presented herein. However, it will be apparent to those skilled in the art that various alternatives may be employed without departing from the scope of the claims and that the subject matter may be practiced without these specific details. For example, it will be apparent to those skilled in the art that the subject matter presented herein can be implemented on many types of electronic devices having digital video capabilities.

[0016] 1 is a block diagram of an exemplary system module 100 in a typical electronic device according to some embodiments. The system module 100 in this electronic device includes at least a processor module 102, a memory module 104 for storing programs, instructions, and data, an input / output (I / O) controller 106, one or more communication interfaces, such as a network interface 108, and one or more communication buses 140 for interconnecting these components. In some embodiments, the I / O controller 106 enables the processor module 102 to communicate with I / O devices (e.g., a keyboard, mouse, or trackpad) via a Universal Serial Bus interface. In some embodiments, the network interface 108 includes one or more interfaces for Wi-Fi, Ethernet, and Bluetooth networks, each enabling data exchange between the electronic device and an external source (e.g., a server or another electronic device). In some embodiments, the communication bus 150 includes circuitry (sometimes referred to as a chipset) that interconnects and controls communication between various system components included in the system module 100.

[0017] In some embodiments, memory module 104 includes high-speed random access memory, such as DRAM, SRAM, DDR RAM, or other random access solid-state memory devices. In some embodiments, memory module 104 includes non-volatile memory, such as one or more magnetic disk storage devices, optical disk storage devices, flash memory devices, or other non-volatile solid-state storage devices. In some embodiments, memory module 104, or alternatively, the non-volatile memory device(s) within memory module 104, includes a non-transitory computer-readable storage medium. In some embodiments, a memory slot is reserved on system module 100 to receive memory module 104. When memory module 104 is inserted into the memory slot, it is incorporated into system module 100.

[0018] In some embodiments, the system module 100 further includes one or more components selected from a memory controller 110, a solid-state drive (SSD) 112, a hard disk drive (HDD) 114, a power management integrated circuit (PMIC) 118, a graphics module 120, and a sound module 122. The memory controller 110 is configured to control communication between the processor module 102 and memory components, including the memory module 104, in the electronic device. The SSD 112 is configured to employ integrated circuit assemblies to store data in the electronic device and, in many embodiments, is based on a NAND or NOR memory configuration. The HDD 114 is a conventional data storage device for storing and retrieving digital information based on an electromechanical magnetic disk. The power connector 116 is electrically coupled to receive an external power source. The PMIC 118 is configured to modulate the received external power source to other desired DC voltage levels, such as 5V, 3.3V, or 1.8V, depending on the needs of various components or circuits (e.g., the processor module 102) within the electronic device. The graphics module 120 is configured to generate an output image feed to one or more display devices according to the desired image / video format of the display device(s). The sound module 122 is configured to facilitate the input and output of audio signals to and from the electronic device under the control of a computer program.

[0019] Note that communication bus 150 also interconnects and controls communication between various system components, including components 110-122.

[0020] Furthermore, those skilled in the art will appreciate that as new data storage technologies are developed, other non-transitory computer-readable storage media may be used to store information on the non-transitory computer-readable storage media in memory module 104 and SSD 112. These new non-transitory computer-readable storage media include, but are not limited to, those made from biological materials, nanowires, carbon nanotubes, and individual molecules, although the corresponding data storage technologies are currently under development and have not yet been commercialized.

[0021] Some implementations of the present application relate to managing the workload of a memory system (e.g., SSD 112 of system module 100 in FIG. 1 ) by controlling the granularity level of background system read requests in a host read workload or mixed host workload of the memory system. System read requests (also referred to as background read requests or non-host read requests) are dispatched by a memory controller to perform internal memory management functions, including, but not limited to, garbage collection, read disturb, memory snapshot capture, memory mirroring, caching, and memory sparing. System read requests are queued in the memory workload together with host read requests. In some embodiments, the host read request is completely moved ahead of the system read request. Alternatively, in some embodiments, the system read operation corresponding to the system read request is split into multiple system read operations for smaller memory chunks, and the host read request is moved ahead of, and is performed ahead of, a subset (e.g., less than all) of the multiple system read operations. The latency of the host read request is reduced by at least the operation time of the subset (e.g., less than all) of the multiple system read operations. These measures improve the QoS of the corresponding host read workload or mixed host workload by taking into account the priority given to host read requests in such memory workloads.

[0022] In some embodiments, the system read request corresponds to a memory block of a substantially large size (e.g., equal to 64 KB), for example, to perform garbage collection and obtain better performance for random write workloads. Based on the corresponding workload state, the memory block associated with the system read request is divided into multiple memory chunks of smaller size (e.g., 4 KB, 16 KB), and multiple system read requests are generated to read the multiple memory chunks from the memory system. Each memory chunk has a corresponding reduced read and I / O overhead compared to the memory block associated with the original system read request. Subsequent host read requests are forwarded around one or more of the multiple memory chunks that have not yet been processed in response to the system read request, rather than waiting for an extended system read operation to be completed on the entire memory block in response to the system read request.

[0023] In some cases, the completion time of a host read request is a combination of the host read time to access the memory cell, the data transfer time, the firmware processing time, and the latency for one or more system reads that precede the host read request waiting to complete. The latency of a host read request is reduced by forwarding the host read request around a system read of one or more small memory chunks associated with a system read request for a larger memory block. These measures reduce the total completion time of a host read request in a memory workload that includes host and system read requests (e.g., a host read workload, a mixed host workload).

[0024] In some embodiments, host read requests are prioritized based on a workload state of the memory system. The state of the memory workload is monitored, for example, to detect a ratio between the number of read requests and the number of total memory access requests, and is applied to determine a system read chunk size and a host read transfer limit. A system read request to access a memory block is received. The memory block corresponding to the system read request is divided into multiple memory chunks based on the system read chunk size. The host read request is moved to the front of a queue associated with the memory workload and is processed before access to one or more (i.e., less than all) memory chunks corresponding to the system read request. In other words, based on the workload state, the host read request is prioritized by suspending access to one or more memory chunks associated with the system read request, thereby reducing the latency of the host read request.

[0025] FIG. 2 is a block diagram of an exemplary electronic device memory system 200 having one or more memory access queues, according to some embodiments. The memory system 200 is coupled to a host device 220 (e.g., processor module 102 in FIG. 1 ) and configured to store instructions and data for extended periods of time, for example, when the electronic device is in a sleep, hibernate, or shutdown state. The host device 220 is configured to access the instructions and data stored in the memory system 200 and process these instructions and data to execute an operating system and run user applications. The memory system 200 further includes a controller 202 and multiple memory channels 204. Each memory channel 204 includes multiple memory cells. The controller 202 is configured to execute firmware-level software to bridge the multiple memory channels 204 to the host device 220. Specifically, the controller 202 is configured to communicate with the host device 220, manage a file system directory 212 to track data locations within the memory channels 204, organize the multiple memory channels 204, and facilitate internal and external requests to access the memory channels 204.

[0026] Each memory channel 204 includes one or more memory packages 206 (e.g., two memory chips, two memory dies). In one example, each memory package 206 corresponds to a memory die. Each memory package 206 includes multiple memory planes 208, each of which further includes multiple memory pages 210. Each memory page 210 includes an ordered set of memory cells, each identified by a respective physical address. In some embodiments, memory system 200 includes a single-level cell (SLC) SSD, where each memory cell stores a single data bit. In some embodiments, memory system 200 includes a multi-level cell (MLC) SSD, where each memory cell stores multiple data bits. In one example, each memory cell in a triple-level cell (TLC) SSD stores three data bits. In another example, each memory cell in a quad-level cell (QLC) SSD stores four data bits. In yet another example, each memory cell in a penta-level cell (PLC) SSD stores five data bits. In some embodiments, each memory cell can store any suitable number of data bits. Compared to MLC SSDs, SLC SSDs operate at higher speeds, higher reliability, and longer lifespans, but have lower device densities and are more expensive.

[0027] Each memory channel 204 is coupled to a respective channel controller 214 configured to control internal and external requests to access memory cells within the respective memory channel 204. In some embodiments, each memory package 206 (e.g., each memory die) corresponds to a respective queue 216 of memory access requests. In some embodiments, each memory channel 204 corresponds to a respective queue 216 of memory access requests. Further, in some embodiments, each memory channel 204 corresponds to a separate, different queue 216 of memory access requests. In some embodiments, a subset (fewer than all) of the multiple memory channels 204 correspond to separate queues 216 of memory access requests. In some embodiments, the multiple memory channels 204 of memory system 200 all correspond to a single queue 216 of memory access requests. Each memory access request is optionally received internally from memory system 200 for managing the respective memory channel 204 or externally from host device 220 for reading and writing data stored in the respective channel 204. Specifically, each memory access request includes one of a system write request received from memory system 200 to write to the respective memory channel 204, a system read request received from memory system 200 to read from the respective memory channel 204, a host write request originating from host device 220 to write to the respective memory channel 204, and a host read request received from host device 220 to read from the respective memory channel 204.

[0028] Additionally, in some embodiments, the queue of memory access requests 216 includes a memory read queue that includes only system read requests, host read requests, or a combination thereof. Alternatively, in some embodiments, the queue of memory access requests 216 includes a mixed memory access queue that includes at least write requests and read requests, where the write requests are optionally system write requests or host write requests, and the read requests are optionally system read requests or read / write requests.

[0029] The memory workload of memory system 200 includes one or more queues 216 of memory access requests. In some embodiments, the memory workload includes a host read workload that begins with a host read request and does not include any host write requests. The memory workload further incorporates system read requests, system write requests, or both, where the one or more queues 216 include host read requests and one or more of system read requests, system write requests, or a combination thereof. Alternatively, in some embodiments, the memory workload includes a host write workload that includes one or more queues 216 that begin with a host write request and includes only system write requests without any host read requests. The memory workload further incorporates system read requests, system write requests, or both, where the one or more queues 216 include host write requests and one or more of system read requests, system write requests, or a combination thereof. Additionally and alternatively, in some embodiments, the memory workload includes a mixed host workload that further has both host read requests and host write requests, and further incorporates system read requests, system write requests, or both. One or more queues 216 include at least write requests and read requests, where the write requests are optionally system write requests or host write requests, and the read requests are optionally system read requests or read / write requests.

[0030] It should be noted that system read requests (also called background read requests or non-host read requests) and system write requests are dispatched by the memory controller to perform internal memory management functions, including but not limited to garbage collection, read disturb, memory snapshot capture, memory mirroring, caching, and memory sparing.

[0031] In some embodiments, the controller 202 further includes a local memory processor 218, a host interface controller 222, an SRAM buffer 224, and a DRAM controller 224 in addition to the FSD 212 and the channel controller 214. The local memory processor 218 accesses the multiple memory channels 204 based on one or more queues 216 of memory access requests. In some embodiments, the local memory processor 218 writes to and reads from the multiple memory channels 204 based on memory blocks. Data in one or more memory blocks is jointly written to or read from multiple channels. Data in the same memory block is not written via more than one operation. Each memory block optionally corresponds to one or more memory pages. In one example, each memory block jointly written to or read from in the multiple memory channels 204 has a size of 16 KB (e.g., one memory page). In another example, each memory block jointly written to or read from across multiple memory channels 204 has a size of 64 KB (e.g., four memory pages). In some embodiments, each page has 16 KB of user data and 2 KB of metadata. Additionally, the number of jointly accessed memory blocks and the size of each memory block are configurable for each of system read, host read, system write, and host write operations.

[0032] In some embodiments, local memory processor 218 stores data written to or read from each memory block in multiple memory channels 204 in an SRAM buffer 224 of controller 202. Alternatively, in some embodiments, local memory processor 218 stores data written to or read from each memory block in multiple memory channels 204 in a DRAM buffer 226, which is the main memory used by processor module 102 (FIG. 1).

[0033] 3 is a flowchart of a process 300 for managing system read requests in a memory workload, according to some embodiments. The memory workload includes one or more queues 216 of memory access requests. Each memory request is one of a system write request received from the memory system 200 for writing to a respective memory channel 204, a system read request received from the memory system 200 for reading from a respective memory channel 204, a host write request received from the host device 220 for writing to a respective memory channel 204, and a host read request received from the host device 220 for reading from a respective memory channel 204. Based on the type of memory access requests in the one or more queues 216, the memory workload has a workload type selected from a host read workload in which one or more queues 216 include at least host read requests, and optionally system read requests, system write requests, or a combination thereof; a host write workload in which one or more queues 216 include at least host write requests, and optionally system write requests, system read requests, or a combination thereof; and a mixed host workload in which one or more queues 216 include at least write requests and read requests.

[0034] In some embodiments, the process 300 is applied to a mixed host workload including at least write requests and read requests. The controller 202 of the memory system 200 (FIG. 2) identifies a workload type of a memory workload including one or more queues 216 of memory access requests (step 302). In accordance with determining that the memory workload is a mixed host workload, the controller 202 determines that the one or more queues 216 include a total number of memory access requests and a first number of read requests. The first number of read requests is the sum of the number of system read requests and the number of host read requests. The controller 202 further monitors the workload status of the memory system 200 based on the memory workload including the one or more queues 216 of memory access requests, and determines whether a percentage of read requests in the one or more queues 216 exceeds a predetermined threshold portion (e.g., 40%, 50%, or 75%) (step 304). Following a determination that the percentage of read requests exceeds the predetermined threshold portion (step 306), the controller 202 selects a first system read chunk size (e.g., 16 KB) and a first host read transfer limit (e.g., a first multiple of the first system read chunk size) (step 308). In some embodiments, while the memory load is monitored, the controller 202 compares the percentage of read requests to the predetermined threshold portion according to a skip check frequency check (e.g., every 100 milliseconds).

[0035] Conversely, in response to a determination that the percentage of read requests is less than or equal to the predetermined threshold portion (step 310) (i.e., equal to or less than the predetermined threshold portion), the controller 202 selects a second system read chunk size (e.g., 64 KB) and a second host read transfer limit (e.g., a second multiple of the first system read chunk size) (step 312). In some embodiments, the second system read chunk size and the second host read transfer limit are default settings applied by the controller 202 to manage system read requests. The first system read chunk size is smaller than the second system read chunk size, and the first host read transfer limit is greater than the second host read transfer limit (i.e., the first multiple is greater than the second multiple). In other words, when processing a mixed host workload with excessive read requests (e.g., exceeding the threshold portion), the controller 202 increases the granularity level and total memory read size that can be retained from system read operations to allow the host read requests to proceed. By these means, host read requests are prioritized to avoid extended latency for the host read requests, and associated system read operations are dynamically adjusted (314) in one or more queues 216 based on the priority of the host read requests.

[0036] In some embodiments, controller 202 selects a first system read chunk size and a first host read transfer limit (step 308) in accordance with a determination that the percentage of read requests is greater than or equal to the predetermined threshold portion (step 306). Controller 202 selects a second system read chunk size and a second host read transfer limit (step 312) in accordance with a determination that the percentage of read requests is less than the predetermined threshold portion (step 310).

[0037] Note that in some embodiments, process 300 includes workload detection (step 302) to ensure the solution is only enabled for one or more predefined workload types (e.g., mixed host workload, host read workload). Based on the percentage of read requests in one or more queues 216 (i.e., the load state of memory system 200), controller 202 determines the granularity level and total memory read size that can be maintained from system read operations to allow host read requests to proceed. Specifically, a memory block corresponding to a system read request is divided into smaller read chunks based on the granularity level. Each memory read chunk has a smaller block size (i.e., corresponds to a memory chunk) and a shorter data transfer time compared to an undivided memory block. io The firmware prioritizes host read requests over system read requests corresponding to smaller read chunks, allowing the host read requests to advance around the memory read chunks of the memory blocks corresponding to the system read requests and obtain lower latency. Additionally, the first or second host read transfer limit is applied to control the priority given to host read requests and to avoid starvation (i.e., excessive delay) of system read requests. Thus, both the system read chunk size and the host read transfer limit are dynamically selected based on the workload conditions (e.g., percentage of read requests) of the memory workload.

[0038] A system read request for a memory block is split into system read requests for multiple smaller memory chunks. One or more of the system read requests for the smaller memory chunks are postponed to allow a subsequent host read request or a subsequent write request to be fulfilled first. This may reduce the efficiency of garbage collection or other system read-based functions related to the system read request, adversely affecting the performance of subsequent random write operations in this mixed host workload. Therefore, process 300 is dynamically implemented to control the priority given to host read requests based on the workload state (e.g., percentage of read requests) of the memory workload.

[0039] In some embodiments, process 300 is applied to a host read workload including at least host read requests. The corresponding queue 216 optionally includes system read requests, system write requests, or a combination thereof. The controller 202 of memory system 200 (FIG. 2) identifies a workload type of the memory workload as a host read workload (step 302). In accordance with determining that the memory workload is a host read workload, the controller 202 determines that one or more queues 216 include a total number of memory access requests and a first number of system and host read requests. The controller 202 further determines whether a proportion of system and host read requests in one or more queues 216 exceeds a predetermined threshold portion (e.g., 40%, 50%, or 75%) (step 304). In response to a determination that the percentage of read requests exceeds the predetermined threshold portion (step 306), the controller 202 selects a first system read chunk size (e.g., 16 KB) and a first host read transfer limit (e.g., a first multiple of the first system read chunk size) (step 308). Conversely, in response to a determination that the percentage of read requests is equal to or less than the predetermined threshold portion (step 310) (i.e., equal to or less than the predetermined threshold portion), the controller 202 selects a second system read chunk size (e.g., 64 KB) and a second host read transfer limit (e.g., a second multiple of the first system read chunk size) (step 308). In other words, when the controller 202 is processing a host read workload having excessive system read requests (e.g., exceeding the threshold portion), it prioritizes the host read requests by increasing the granularity level and total memory read size that can be retained from the system read operations, allowing the host read requests to proceed.

[0040] FIG. 4A is a diagram of an exemplary memory access queue 216-1 including a current system read request 402 followed by at least one host read request 404, according to some embodiments. FIG. 4B is a diagram of an exemplary memory access queue 216-2 including multiple system read requests for multiple memory chunks 406 followed by host read requests 404, according to some embodiments. FIGS. 4C-4E are three diagrams of three exemplary memory access queues 216-3, 216-4, and 216-5 in which host read requests 404 advance around at least a second subset of memory chunks 406B, according to some embodiments. The controller 202 identifies a queue 216-1 of memory access requests for accessing the memory system 200, the queue 216-1 of memory access requests including at least one host read request 404 and a current system read request 402. In some embodiments, the current system read request 402 has begun to be processed and is currently being processed. For example, the current system read request 402 corresponds to four memory chunks, and each memory chunk in the first memory chunk subset 406A (e.g., a single first memory chunk, two first memory chunks) has been processed or is in the process of being processed.

[0041] The controller 202 monitors the workload state of the memory system 200 based on the queue 216-1 of memory access requests. In some embodiments, the controller 202 determines a system read chunk size based on the workload state of the memory system 200. Referring to FIG. 4B , a memory block corresponding to a current system read request 402 is divided into multiple memory chunks 406 based on the system read chunk size. Each system read chunk 406 has a chunk size equal to the system read chunk size. For example, based on the workload state of the memory system 200, the system read chunk size is determined to be 16 KB. The memory block corresponds to four memory chunks 406, each with a chunk size of 16 KB, with a total memory read size of 64 KB.

[0042] The controller 202 generates at least a first system read request 402A corresponding to the first memory chunk subset 406A and a second system read request 402B corresponding to the second memory chunk subset 406B from the current system read requests 402 based on the workload state of the memory system. The queue 216-1 of memory access requests is updated by inserting at least one host read request 404 after the first system read request 402A and before the second system read request 402B. In some embodiments, the controller 202 determines that each memory chunk of the first memory chunk subset 406A has been processed or is being processed in response to the current system read request 402, and therefore associates the first memory chunk subset 406A with the first system read request 402A that is already too late to be held for later. In one example, the first memory chunk subset 406A corresponding to the first system read request 402A includes a single memory chunk 406A. In another example, not shown, the memory chunk subset 406A corresponding to the first system read request 402A includes two or more memory chunks.

[0043] 4C , in some embodiments, the second memory chunk subset 406B includes three remaining memory chunks of the plurality of memory chunks corresponding to the current system read request 402. The first memory chunk subset 406A and the second memory chunk subset 406B form the entirety of the memory block 406 corresponding to the current system read request 402. The host read request 404 moves forward around the second system read request 402B until it encounters an in-flight first system read request 402A, which cannot be held or postponed to prioritize the host read request 404.

[0044] Referring to FIG. 4D , in some embodiments, the second memory chunk subset 406B includes two of the three remaining memory chunks corresponding to the current system read request 402. The first memory chunk subset 406A and the second memory chunk subset 406B do not form the entirety of the memory block 406 corresponding to the current system read request 402. The host read request 404 progresses around the second system read request 402B corresponding to the second memory chunk subset 406B, but does not progress further beyond the third memory chunk subset 406C (e.g., including a single memory chunk) that has not yet been processed in response to the current system request. Referring to FIG. 4E , in some embodiments, the second memory chunk subset 406B includes the last memory chunk corresponding to the current system read request 402. The first memory chunk subset 406A and the second memory chunk subset 406B do not form the entirety of the memory block 406 corresponding to the current system read request 402. The host read request 404 progresses around the second system read request 402B, which corresponds to the second memory chunk subset 406B, but does not progress further beyond the third memory chunk subset 406C (e.g., including two intermediate memory chunks) that has not yet been processed in response to the current system read request 402.

[0045] In some embodiments, a third system read request 402C is generated for the third memory chunk subset 406C. A host read request 404 is inserted after the third system read request 402C and before the second system read request 402B. Alternatively, in some embodiments, the first system read request 402 is generated to include the third memory chunk subset 406C in addition to the first memory chunk subset 406A. The host read request 404 is inserted between the first system read request 402A and the second system read request 402B.

[0046] 4D and 4E , in some embodiments, after making progress around the second memory chunk subset 406B, the host read request 404 reaches a host read transfer limit and therefore cannot make further progress around the third memory chunk subset 406C (e.g., including two intermediate memory chunks) that have not yet been processed in response to the current system read request 402. The host read transfer limit is determined based on a workload state of the memory system 200. In some embodiments, the workload state of the memory system 200 is monitored based on the queue 216-1 of memory access requests. In response to a determination that more than a threshold portion (e.g., >50%) of the queue 216-1 of memory access requests are read requests (e.g., system read requests or host read requests), the controller selects a first host read transfer limit (e.g., 48 KB, 3 access requests). The first read transfer limit is optionally measured by one of the size of the memory data being accessed, the number of memory access requests, and the time of the memory access operation. Conversely, in accordance with a determination that a threshold portion or less than a threshold portion (e.g., ≦50%) of queue 216-1 of memory access requests are read requests, controller 202 selects a second host read transfer limit. The first host read transfer limit is greater than the second host read transfer limit. In other words, because there are a relatively large number of read requests in queue 216-1, controller 202 is configured to grant higher priority to host read request 404 by allowing host read request 404 to make progress around a larger memory read size.

[0047] 5A is a diagram of an exemplary memory access queue 216-1 including a current system read request 402 followed by one or more additional system access requests 502 and at least one host read request 404, according to some embodiments. FIG. 5B is a diagram of an exemplary memory access queue 216-2 including multiple system read requests for multiple memory chunks 406 followed by one or more additional system access requests 502 and host read requests 404, according to some embodiments. FIGs. 5C-5E are three diagrams of three exemplary memory access queues 216-3, 216-4, and 216-5 in which a host read request 404 advances around at least a second memory chunk subset 406B and one or more additional system access requests 502, according to some embodiments. As mentioned above, in some embodiments (FIGS. 4A-4E), a system read request 402 is immediately followed by a host read request 404. 5A-5E, in some embodiments, a system read request 402 is not immediately followed by a host read request 404. Alternatively, a system read request 402 is immediately followed by one or more additional system access requests 502, which are in turn immediately followed by a host read request 404. In some embodiments, the host read request 404 does not advance around the host write request to avoid read errors.

[0048] The host read request 404 advances around both the one or more additional system access requests 502 and the second system read request 402B in queue 216-2, each of which has not yet been processed by the controller 202, and the second system read request 402B corresponds to a second memory chunk subset 406B that has not been processed by the controller 202 in response to the current system read request 402. Thus, queue 216-1 of memory access requests is updated to queue 216-3, 216-4, or 216-5, and the host read request 404 advances around the one or more additional system access requests 502 and the second system read request 402B in queue 216-2.

[0049] The controller 202 monitors the workload state of the memory system 200 based on the queue 216-1 of memory access requests. In some embodiments, the controller 202 determines a system read chunk size and a host read transfer limit based on the workload state of the memory system 200. In some embodiments, in response to a determination that more than a threshold portion (e.g., >50%) of the queue 216-1 of memory access requests are read requests, the controller 202 selects a first system read chunk size (e.g., 16 KB) and a first host read transfer limit (e.g., 16 KB × 32). Conversely, in response to a determination that a threshold portion or less than a threshold portion (e.g., ≦50%) of the queue 216-1 of memory access requests are read requests, the controller 202 selects a second system read chunk size (e.g., 64 KB) and a second host read transfer limit (e.g., 64 KB × 2). The first system read chunk size is smaller than the second system read chunk size and corresponds to a higher level of granularity than the second system read chunk size. The first host read transfer limit is greater than the second host read transfer limit, which results in a more aggressive operation in advancing host read requests 404 .

[0050] In some embodiments, the current system read request 402 is implemented based on a memory block having a size equal to the second system read chunk size. The memory block corresponding to the current system read request 402 has a similar level of granularity as the second system read chunk size. In other words, if a threshold portion or less than a threshold portion (e.g., ≦50%) of the queue of memory access requests 216-1 are read requests, the current system read request 402 is not split into two or more system read requests, and the memory block corresponding to the current system read request 402 is not divided into multiple memory chunk subsets smaller than the memory block. The memory block corresponding to the current system read request 402 is optionally bypassed in its entirety by the host read request 404 or processed before the host read request 404.

[0051] 5C , in some embodiments, the first memory chunk subset 406A is in progress and the host read request 404 cannot proceed. The second memory chunk subset 406B includes three remaining memory chunks of the plurality of memory chunks corresponding to the current system read request 402. The first memory chunk subset 406A and the second memory chunk subset 406B form the entire memory block 406 corresponding to the current system read request 402. The host read request 404 proceeds around both the one or more system access requests 502 and the second system read request 402B until it encounters the in-progress first system read request 402A, which cannot be held or postponed to prioritize the host read request 404. The total memory size of the one or more system access requests 502 and the second system read request 402B is optionally equal to or less than a host read transfer limit (e.g., a first host read transfer limit).

[0052] 5D, in some embodiments, the second memory chunk subset 406B includes two of the three remaining memory chunks corresponding to the current system read request 402. The host read request 404 proceeds around both the one or more system access requests 502 and the second system read request 402B corresponding to the second memory chunk subset 406B. The host read request 404 does not proceed further around the third memory chunk subset 406C (e.g., including a single memory chunk) that has not yet been processed in response to the current system request. With reference to FIG. 5E, in some embodiments, the second memory chunk subset 406B includes the last memory chunk corresponding to the current system read request 402. The host read request 404 proceeds around both the one or more system access requests 502 and the second system read request 402B corresponding to the second memory chunk subset 406B. The host read request 404 does not progress further around the third memory chunk subset 406C (e.g., including two intermediate memory chunks) that have not yet been processed in response to the current system read request 402. Referring to Figures 5D and 5E, after progressing around one or more system access requests 502 and the second memory chunk subset 406B, the host read request 404 has reached the host read transfer limit and therefore cannot progress further beyond the third memory chunk subset 406C (e.g., including two intermediate memory chunks) that have not yet been processed in response to the current system read request 402.

[0053] Figure 6A is a diagram of another exemplary memory access queue 216-1 including a system read request 402 followed by one or more system access requests 502 and a host read request 404, according to some embodiments. Figures 6B and 6C are two diagrams of two exemplary memory access queues 216-2 and 216-3, according to some embodiments, in which the host read request 404 advances around the one or more system access requests 502. The system read request 402 is immediately followed by one or more additional system access requests 502, which are further immediately followed by the host read request 404.

[0054] As previously described, in some cases, the workload state of memory system 200 indicates that a threshold portion or less than a threshold portion (e.g., ≦50%) of queue 216-1 of memory access requests are read requests. Controller 202 selects a second system read chunk size (e.g., 64 KB) and a second host read transfer limit (e.g., 64 KB×2) that are different from those selected if more than the threshold portion of queue 216-1 are read requests. In some embodiments, the second system read chunk size and the second host read transfer limit correspond to default settings for memory system 200. In some embodiments, current system read requests 402 are configured to be implemented on a memory block basis, where the memory block has a size equal to the selected system read chunk size (e.g., 64 KB). The memory block corresponding to current system read request 402 has a similar level of granularity as the second system read chunk size. The current system read request 402 is not split into two or more system read requests (e.g., 402A-402C in FIGS. 4C-4E), and the memory block corresponding to the current system read request 402 is not split into multiple memory chunk subsets smaller than the memory block (e.g., 406A-406C in FIGS. 4C-4E). The memory block corresponding to the current system read request 402 is optionally bypassed in its entirety by the host read request 404 or processed before the host read request 404.

[0055] Referring to FIG. 6B , in some embodiments, a system read request 402 is being processed to access a corresponding memory block, and a host read request 404 cannot proceed around the system read request 402. The memory block has a size equal to a selected system read chunk size and cannot be divided into smaller memory chunks. The host read request 404 proceeds around one or more system access requests 502 until it encounters an in-process system read request 402 that cannot be held or postponed to prioritize the host read request 404. The total memory size of the one or more system access requests 502 is optionally equal to or less than a selected host read transfer limit (e.g., a second host read transfer limit). The queue of memory access requests 206-1 is updated to insert the host read request 404 after the system read request and before the one or more system access requests 502, thereby forming the queue of memory access requests 206-2 in FIG. 6B .

[0056] 6C , in some embodiments, the host read request 404 progresses through the first subset of system access requests 502A. The host read request 404 does not progress further through the second subset of system access requests 502B, which have not yet been processed. After progressing through the first subset of system access requests 502A, the host read request 404 has reached the selected host read transfer limit and therefore cannot progress further beyond the second subset of system access requests 502B, which have not yet begun to be processed.

[0057] In some cases, the host read request 404 has a relatively large memory read size (e.g., 256 KB) compared to the size of the memory block corresponding to the system read request 402 (e.g., 64 KB) or the selected system read chunk size (e.g., 16 KB) of the system read request, and therefore does not move around as a whole. The controller 202 determines that the host read request 404 has a memory read size and compares the memory read size to a predetermined host read size (e.g., 64 KB). The host read request 404 is inserted after the first system read request 402A (FIGS. 4C-4E) and before the second system read request 402B (FIGS. 4C-4E) in accordance with a determination that the memory read size of the host read request 404 is smaller than the predetermined host read size.

[0058] Conversely, in some embodiments, in accordance with a determination that the memory read size of host read request 404 is greater than or equal to the predetermined host read size, host read request 404 is divided into a series of consecutive host read requests, each consecutive host read request corresponding to a memory read size less than or equal to the predetermined host read size. A first consecutive host read request is inserted after first system read request 402A (FIGS. 4C-4E) and before second system read request 402B (FIGS. 4C-4E). Each of the one or more remaining host read requests optionally proceeds based on host read transfer limits and whether each system read request 402A, 402B, or 402C is in progress.

[0059] In some embodiments, the predetermined host read size is substantially smaller than or comparable to the size of the memory block corresponding to the system read request 404 (e.g., 64 KB) or the selected system read chunk size (e.g., 16 KB) of the system read request 404. That is, the memory system 200 includes multiple memory chunks corresponding to the current system read request 402. The controller 202 determines whether each of the multiple memory chunks 406 has been processed, is currently being processed, or will be processed, and identifies a second memory chunk subset 406B to be advanced by the host read request 404. Each memory chunk 406 has a selected system read chunk size, and the predetermined host read size is smaller than or substantially equal to the selected system read chunk size. As a result, the latency of the system read request 402 caused by advancing the host read request 404 is controlled to a reasonable level.

[0060] 7A and 7B are flowcharts of a method 700 for controlling access to memory system 200, according to some embodiments. Method 700 is implemented in an electronic device including memory system 200 (FIG. 2). Memory system 200 identifies a queue 216 of memory access requests for accessing memory system 200 (step 702), where the queue 216 of memory access requests (FIG. 2) includes at least one host read request 404 and a current system read request 402. Memory system 200 monitors a workload state of memory system 200 based on the queue 216 of memory access requests (step 704), and generates at least a first system read request 402A (FIGS. 4A-4E and 5A-5E) and a second system read request 402B (FIGS. 4A-4E and 5A-5E) from the current system read request 402 based on the workload state of memory system 200 (step 706). The queue 216 of memory access requests is updated by inserting at least one host read request 404 after the first system read request 402A and before the second system read request 402B (step 708).

[0061] In some embodiments, the memory system 200 determines a system read chunk size based on a workload state of the memory system 200 (step 710), and generates the first system read request 402A and the second system read request 402B from the current system read request 402 based on the system read chunk size. Furthermore, in some embodiments, the memory system 200 determines the system read chunk size according to a predefined skip check frequency, for example, every 100 milliseconds. In some embodiments, in response to a determination that more than a threshold portion (e.g., 50%) of the queue of memory access requests 216 are read requests, the memory system 200 selects a first system read chunk size (e.g., 16 KB) (step 712). In response to a determination that at or below a threshold portion of the queue of memory access requests 216 are read requests, the memory system 200 selects a second system read chunk size (e.g., 64 KB) (step 714). The first system read chunk size is smaller than the second system read chunk size. In some embodiments, the second system read chunk size is a default system read chunk size that matches the memory read size of the current system read request 402. The current system read request 402 is bypassed or processed without being split or divided to accommodate the host read request 404 that follows the current system read request 402. By these means, the host read request 404 does not have to wait until the current system read request 402 is completely processed, but instead moves forward around a portion of the current system read request 402, thereby reducing the latency of the host read request 404.

[0062] Additionally, in some embodiments, memory system 200 determines (step 716) that the current system read request 402 corresponds to a plurality of memory chunks 406 (FIG. 4B) based on the system read chunk size. The plurality of memory chunks 406 includes a first memory chunk subset 406A. Memory system 200 determines that each memory chunk in first memory chunk subset 406A has been processed or is currently being processed. In accordance with the determination that each memory chunk in first memory chunk subset 406A has been processed or is currently being processed, memory system 200 generates (step 718) a first system read request 402A corresponding to first memory chunk subset 406A.

[0063] In some embodiments, memory system 200 determines that current system read request 402 corresponds to multiple memory chunks 406 based on the system read chunk size. The multiple memory chunks 406 include a first memory chunk subset 406A corresponding to first system read request 402A and a second memory chunk subset 406B corresponding to second system read request 402B. Each memory chunk in second memory chunk subset 406B is different from first memory chunk subset 406A. Additionally, in some embodiments, multiple memory chunks 406 include only first memory chunk subset 406A and second memory chunk subset 406B, forming the entire memory block corresponding to current system read request 402. In other words, first system read request 402A has a first memory read size, and second system read request 402B has a second memory read size. The first memory read size is a first multiple of the memory read chunk size, and the second memory read size is a second multiple of the memory read chunk size. The current system read request 402 has a total memory read size, which is equal to the sum of the first memory read size and the second memory read size.

[0064] In some embodiments, memory system 200 determines a host read transfer limit based on a workload state of memory system 200 (step 720). Further, in some embodiments, memory system 200 determines a host read transfer limit according to a predefined skip check frequency, for example, every 100 milliseconds. Additionally, in some embodiments, memory system 200 selects a first host read transfer limit in accordance with a determination that more than a threshold portion of queue 216 of memory access requests are read requests (step 722). In accordance with a determination that at or below a threshold portion of queue 216 of memory access requests are read requests, memory system 200 selects a second host read transfer limit (step 724). The first host read transfer limit is greater than the second host read transfer limit.

[0065] Additionally, in some embodiments, memory system 200 determines that the current system read request 402 corresponds to multiple memory chunks 406. The multiple memory chunks 406 include a second memory chunk subset 406B that has not yet been processed in response to the current system read request 402. In accordance with a determination that the at least one host read request 404 reaches the host read transfer limit by progressing around the second memory chunk subset 406B, memory system 200 generates a second system read request 402B corresponding to the second memory chunk subset 406B (step 726).

[0066] In some embodiments, memory system 200 generates a third system read request (step 728). This third system read request corresponds to a third memory chunk subset 406C that has not yet been processed in response to the current system read request 402. At least one host read request 404 is inserted after the third system read request and before the second system read request 402B. In other words, the at least one host read request 404 has reached the host read transfer limit by advancing around the second memory chunk subset 406B and cannot move further beyond the third memory chunk subset 406C. Alternatively, in some embodiments, memory system 200 identifies first memory chunk subset 406A, each memory chunk of which has been processed or is currently being processed in response to the current system read request. The first memory chunk subset cannot be bypassed by the host read request 404. The memory system 200 further identifies a third memory chunk subset 406C that has not yet been processed in response to a current system read request. The first system read request is generated to access both the first memory chunk subset 406A and the third memory chunk subset 406C.

[0067] In some embodiments, the queue of memory access requests 216 further includes one or more additional system access requests 502 following the current system read request 402, followed by at least one host read request 404. The queue of memory access requests 216 is updated by moving the at least one host read request 404 past the one or more additional system access requests 502. After processing the host read request 404, the memory system 200 sequentially accesses the second memory chunk subset 406B in response to the second system read request 402B and sequentially accesses one or more additional memory blocks in response to the one or more system access requests.

[0068] In some embodiments, memory system 200 includes a solid-state drive (SSD) with multiple memory channels, and memory access request queue 216 corresponds to one or more of the multiple memory channels.

[0069] In some embodiments, memory system 200 determines that at least one host read request 404 has a memory read size and compares the memory read size to a predetermined host read size. The at least one host read request 404 is inserted after the first system read request 402A and before the second system read request 402B in accordance with a determination that the memory read size is smaller than the predetermined host read size. Furthermore, in some embodiments, memory system 200 includes multiple memory chunks 406 corresponding to the current system read requests 402. Memory system 200 determines whether each of the multiple memory chunks 406 has been processed, is currently being processed, or will be processed. Each memory chunk has a system read chunk size, and the predetermined host read size is smaller than or substantially equal to the system read chunk size.

[0070] In some embodiments, the current system read request 402 has a total memory read size of 64 KB and corresponds to four memory chunks 406. Each memory chunk 406 includes 16 KB, and the first system read request 402A and the second system read request 402B each have a memory read size equal to a corresponding multiple of 16 KB. In some embodiments, the memory system 200 includes four memory chunks 406. The first system read request 402A corresponds to only the first memory chunk 406A, and the second system read request 402B corresponds to three remaining memory chunks 406B of the four memory chunks (FIG. 4C). In some embodiments, the memory system 200 includes four memory chunks, the first system read request 402A includes only the first memory chunk, and the second system read request 402B corresponds to one or two last memory chunks 406B of the four memory chunks (FIGS. 4D and 4E).

[0071] It should be understood that the particular order in which the operations in Figure 7 are described is merely exemplary, and that the described order is not intended to indicate the only order in which the operations may be performed. Those skilled in the art will recognize various methods for improving the efficiency of processing host read requests in memory system 200 (e.g., an SSD). Additionally, it should be noted that other process details described above with respect to Figures 1-6C can be applied in a similar manner to method 700 described above with respect to Figure 7. For the sake of brevity, these details will not be repeated here.

[0072] The memory is also used to store instructions and data related to method 700 and includes high-speed random access memory such as DRAM, SRAM, DDR RAM, or other random access solid-state memory devices, and optionally includes non-volatile memory, such as one or more magnetic disk storage devices, one or more optical disk storage devices, one or more flash memory devices, or one or more other non-volatile solid-state storage devices. The memory optionally includes one or more storage devices located remotely from the one or more processing units. The memory, or alternatively, the non-volatile memory within the memory, comprises a non-transitory computer-readable storage medium. In some embodiments, the memory or the non-transitory computer-readable storage medium of the memory stores programs, modules, and data structures, or a subset or superset, for implementing method 700.

[0073] Each of the above-identified elements may be stored in one or more of the memory devices mentioned above and may correspond to an instruction set for performing the functions described above. The above-identified modules or programs (i.e., instruction sets) need not be implemented as separate software programs, procedures, modules, or data structures; thus, various subsets of these modules may be combined or otherwise rearranged in various embodiments. In some embodiments, memory optionally stores a subset of the above-identified modules and data structures. Memory also optionally stores additional modules and data structures not described above.

[0074] The terms used in describing the various implementations described herein are for the purpose of describing particular implementations only and are not intended to be limiting. When used in describing the various implementations described and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. As used herein, the term "and / or" is also understood to refer to and encompass any and all possible combinations of one or more of the associated listed items. As used herein, the terms "includes," "including," "comprises," and / or "comprising" specify the presence of stated features, integers, steps, operations, elements, and / or components, but are further understood not to exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. Additionally, while terms such as "first," "second," etc. may be used herein to describe various elements, it is understood that these elements should not be limited by these terms. These terms are only used to distinguish one element from another.

[0075] As used herein, the term "if" may be interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting" or "in accordance with a determination that," depending on the context. Similarly, the phrase "if it is determined" or "if [a stated condition or event is detected]" may be interpreted to mean "upon determining" or "in response to determining" or "upon detecting [the stated condition or event]" or "in response to detecting [the stated condition or event]" or "in accordance with a determination that [a stated condition or event] is detected," depending on the context.

[0076] The foregoing description has been described with reference to specific embodiments for purposes of explanation. However, the above exemplary discussion is not intended to be exhaustive or to limit the scope of the claims to the precise form disclosed. Many modifications and variations are possible in light of the above teachings. The embodiments have been chosen and described in order to best explain the principles of operation and practical applications, thereby enabling those skilled in the art to understand.

[0077] While the various figures depict multiple logical stages in a particular order, stages that are not order-dependent may be rearranged, and other stages may be combined or separated. While some rearrangements or other groupings have been specifically mentioned, other rearrangements or groupings will be apparent to those skilled in the art. As such, the order and groupings presented herein are not an exhaustive list of alternatives. It should also be recognized that the stages described above may be implemented in hardware, firmware, software, or any combination thereof.

Claims

1. 1. A method for controlling access to a memory system, implemented in an electronic device, comprising: identifying a queue of memory access requests for accessing the memory system, the queue of memory access requests including at least one host read request and a current system read request; monitoring a workload state of the memory system based on the queue of memory access requests; generating at least a first system read request and a second system read request from the current system read request based on the workload state of the memory system; updating the queue of memory access requests by inserting the at least one host read request after the first system read request and before the second system read request; A method comprising:

2. 2. The method of claim 1, further comprising determining a system read chunk size based on the workload state of the memory system, wherein the first and second system read requests are generated from the current system read request based on the system read chunk size.

3. Generating at least the first system read request and the second system read request includes: determining, based on the system read chunk size, that the current system read request corresponds to a plurality of memory chunks, the plurality of memory chunks including a first memory chunk subset; determining that each memory chunk of the first memory chunk subset has been processed or is currently being processed; generating the first system read request corresponding to the first memory chunk subset according to a determination that each memory chunk in the first memory chunk subset has been processed or is currently being processed; The method of claim 2 further comprising:

4. 4. The method of claim 2 or 3, further comprising: determining, based on the system read chunk size, that the current system read request corresponds to a plurality of memory chunks, the plurality of memory chunks including a first memory chunk subset corresponding to the first system read request and a second memory chunk subset corresponding to the second system read request, each of the second memory chunk subsets being different from the first memory chunk subset.

5. The method of claim 4 , wherein the plurality of memory chunks includes only the first memory chunk subset and the second memory chunk subset, forming an entire memory block corresponding to the current system read request.

6. Determining the system read chunk size based on the workload state of the memory system includes: selecting a first system read chunk size in accordance with a determination that more than a threshold portion of the queue of memory access requests are read requests; selecting a second system read chunk size in accordance with determining that the threshold portion or less of the queue of memory access requests are read requests, wherein the first system read chunk size is smaller than the second system read chunk size; The method of any one of claims 2 to 4, further comprising:

7. The method of any one of claims 1 to 6, further comprising determining a host read transfer limit based on the workload state of the memory system.

8. Generating at least the first system read request and the second system read request includes: determining that the current system read request corresponds to a plurality of memory chunks, the plurality of memory chunks including a second subset of memory chunks that have not yet been processed in response to the current system read request; generating the second system read request corresponding to the second memory chunk subset in accordance with a determination that the at least one host read request reaches the host read transfer limit by proceeding around the second memory chunk subset; The method of claim 7 further comprising:

9. 9. The method of claim 8, further comprising generating a third system read request corresponding to a third subset of memory chunks not yet processed in response to the current system read request, wherein the at least one host read request is inserted after the third system read request and before the second system read request.

10. identifying a first subset of memory chunks, each memory chunk having been processed or currently being processed in response to the current system read request; identifying a third subset of memory chunks that have not yet been processed in response to the current system read request; The method of claim 8 or 9, wherein the first system read request is generated to access both the first memory chunk subset and the third memory chunk subset.

11. Determining the host read transfer limit based on the workload state of the memory system includes: selecting a first host read transfer limit in accordance with a determination that more than a threshold portion of the queue of memory access requests are read requests; selecting a second host read transfer limit in accordance with a determination that the threshold portion or less of the queue of memory access requests are read requests, the first host read transfer limit being greater than the second host read transfer limit; The method of claim 7 further comprising:

12. 12. The method of claim 1, wherein the queue of memory access requests further includes one or more additional system access requests following the current system read request, followed by the at least one host read request, and wherein updating the queue of memory access requests further includes moving the at least one host read request past the one or more additional system access requests.

13. 13. The method of claim 1, wherein the memory system includes a solid-state drive (SSD) having multiple memory channels, and the queue of memory access requests corresponds to one or more of the multiple memory channels.

14. determining that the at least one host read request has a memory read size; comparing the memory read size to a predetermined host read size; pursuant to determining that the memory read size is less than the predetermined host read size, the at least one host read request is inserted after the first system read request and before the second system read request. The method according to any one of claims 1 to 13.

15. The memory system includes a plurality of memory chunks corresponding to the current system read request, and the method includes:

14. The method of claim 13, further comprising determining whether each of the plurality of memory chunks has been processed, is currently being processed, or will be processed, each memory chunk having a system read chunk size, and wherein the predetermined host read size is less than or substantially equal to the system read chunk size.

16. 16. The method of claim 1, wherein the current system read request has a total memory read size of 64 KB and corresponds to four memory chunks containing 16 KB each, and each of the first and second system read requests has a memory read size equal to a corresponding multiple of 16 KB.

17. 17. The method of claim 1, wherein the memory system includes four memory chunks, the first system read request corresponds to only a first memory chunk, and the second system read request corresponds to three remaining memory chunks of the four memory chunks.

18. 18. The method of claim 1, wherein the memory system includes four memory chunks, the first system read request includes only a first memory chunk, and the second system read request corresponds to one or two last memory chunks of the four memory chunks.

19. one or more processors; a memory having stored thereon instructions that, when executed by said one or more processors, cause said processors to perform the method of any one of claims 1 to 18; An electronic device comprising:

20. A non-transitory computer readable storage medium having stored thereon instructions that, when executed by one or more processors, cause the processors to perform the method of any one of claims 1 to 18.

Images