Light-emitting device and display device including the light-emitting device

Abstract

The display device includes a light-emitting element disposed on a substrate and having a first end and a second end. The first electrode is electrically connected to the first end of the light-emitting element. The second electrode is electrically connected to the second end of the light-emitting element. The first semiconductor layer, light-emitting layer, second semiconductor layer, and electrode layer of the light-emitting element are sequentially disposed along the longitudinal direction from the second end to the first end. The insulating coating of the light-emitting element extends parallel to the longitudinal direction and covers the side surfaces of the first semiconductor layer, light-emitting layer, second semiconductor layer, and electrode layer. The shielding layer is disposed inside the insulating coating.

Description

[Technical Field]

[0001] SUMMARY OF THE INVENTION Embodiments of the present invention relate to light-emitting devices and display devices including the light-emitting devices. [Background technology]

[0002] 2. Description of the Related Art In recent years, interest in information displays has increased, leading to continuous research and development of display devices. Summary of the Invention [Problem to be solved by the invention]

[0003] SUMMARY OF THE INVENTION The present invention provides a light emitting device having improved optical properties and a display device including the same.

[0004] However, embodiments of the present invention are not limited to those described herein, and these and other embodiments will become apparent to those skilled in the art upon review of the detailed description of the invention provided. [Means for solving the problem]

[0005] A light-emitting element according to an embodiment of the present invention may include a first semiconductor layer, a light-emitting layer disposed on the first semiconductor layer, a second semiconductor layer disposed on the light-emitting layer, an electrode layer disposed on the second semiconductor layer, an insulating coating covering side surfaces of the first semiconductor layer, the light-emitting layer, the second semiconductor layer, and the electrode layer, and a shielding layer disposed inside the insulating coating.

[0006] The shielding layer may be spaced apart from the first semiconductor layer, the light emitting layer, the second semiconductor layer, and the electrode layer.

[0007] The shielding layer may cover the side surfaces of the light-emitting layer.

[0008] The light transmittance of the shielding layer is about 70% or more, and the light emitted from the light emitting layer can pass through the shielding layer.

[0009] The shielding layer may comprise a metal and have a thickness of about 5 nm or less.

[0010] The shielding layer completely covers the sides of the light emitting layer and the second semiconductor layer and partially covers the first semiconductor layer, and the light reflectivity of the shielding layer is about 90% or more, so that light emitted from the light emitting layer can be reflected by the shielding layer and travel to the outside of the light emitting device through the first semiconductor layer and the electrode layer.

[0011] The shielding layer may include a first shielding layer covering the side surfaces of the second semiconductor layer and the light emitting layer, and a second shielding layer partially covering the side surfaces of the first semiconductor layer and spaced apart from the first shielding layer.

[0012] The second shielding layer may extend to one end of the insulating film adjacent to the lower surface of the first semiconductor layer and be exposed to the outside, and the first shielding layer may extend to the other end of the insulating film adjacent to the upper surface of the electrode layer and be exposed to the outside of the light emitting device.

[0013] A display device according to an embodiment of the present invention includes a light-emitting element disposed on a substrate and including a first end and a second end aligned in a direction parallel to an upper surface of the substrate, a first electrode electrically connected to the first end of the light-emitting element, and a second electrode electrically connected to the second end of the light-emitting element. The light-emitting element includes a first semiconductor layer, a light-emitting layer, a second semiconductor layer, and an electrode layer sequentially arranged along a longitudinal direction from the second end to the first end, an insulating coating extending parallel to the longitudinal direction and covering side surfaces of the first semiconductor layer, the light-emitting layer, the second semiconductor layer, and the electrode layer, and a shielding layer disposed inside the insulating coating.

[0014] The shielding layer may be spaced apart from the first semiconductor layer, the light emitting layer, the second semiconductor layer, the electrode layer, the first electrode, and the second electrode.

[0015] The shielding layer may cover a side surface of the light-emitting layer, and the shielding layer may overlap the first electrode in a plan view.

[0016] The light transmittance of the shielding layer is about 70% or more, so that the light emitted from the light emitting layer can pass through the shielding layer.

[0017] The shielding layer may comprise a metal and have a thickness of about 5 nm or less.

[0018] The shielding layer covers most of the sides of the light emitting layer and the second semiconductor layer and partially covers the first semiconductor layer, and the light reflectivity of the shielding layer is about 90% or more, so that light emitted from the light emitting layer can be reflected by the shielding layer and travel to the outside of the light emitting device through the first end and the second end.

[0019] The shielding layer may include a first shielding layer covering the side surfaces of the second semiconductor layer and the light emitting layer, and a second shielding layer partially covering the side surfaces of the first semiconductor layer and spaced apart from the first shielding layer.

[0020] The first shielding layer may extend to the first end and be electrically connected to the first electrode, and the second shielding layer may extend to the second end and be electrically connected to the second electrode.

[0021] A display device according to an embodiment of the present invention includes a light-emitting element disposed on a first insulating layer and having a first end and a second end, a second insulating layer disposed on the light-emitting element and exposing the first end and the second end of the light-emitting element, a first electrode disposed on the first end of the light-emitting element, a second electrode disposed on the second end of the light-emitting element, and a shielding layer disposed between the second insulating layer and the light-emitting element and electrically isolated from the first electrode and the second electrode.

[0022] The shielding layer may be in a floating state.

[0023] The light transmittance of the shielding layer is about 70% or more, so that the light emitted from the light emitting device can pass through the shielding layer.

[0024] The display device may further include a third insulating layer disposed between the shielding layer and the second insulating layer and covering the shielding layer.

[0025] Further details of the embodiments are included in the detailed description and drawings. [Effects of the Invention]

[0026] The light emitting device according to the embodiment of the present invention includes a shielding layer covering side surfaces of the light emitting layer and the second semiconductor layer, and the shielding layer can shield or suppress an electric field formed between the light emitting device and an external component, for example, formed on a side surface of the light emitting device, thereby preventing a deterioration (or degradation) of the characteristics of the light emitting device due to the electric field.

[0027] A display device according to an embodiment of the present invention includes a shielding layer disposed on the side (or circumferential surface) of the light-emitting element or between the pixel electrode and the side of the light-emitting element, and the shielding layer can shield or suppress the electric field formed between the pixel electrode and the side of the light-emitting element.

[0028] The effects of the embodiments are not limited to those exemplified above, and various other effects are included within the present specification. [Brief explanation of the drawings]

[0029] [Figure 1] 1 is a schematic perspective view showing a light emitting device according to an embodiment; [Figure 2] 2 is a schematic cross-sectional view showing an embodiment of the light-emitting device of FIG. 1. FIG. [Figure 3] 2 is a schematic cross-sectional view showing an embodiment of the light-emitting device of FIG. 1. FIG. [Figure 4] 4 is a schematic cross-sectional view showing an embodiment of the light-emitting device of FIG. 3. FIG. [Figure 5] 2 is a schematic cross-sectional view showing an embodiment of the light-emitting device of FIG. 1. FIG. [Figure 6]2 is a schematic cross-sectional view showing an embodiment of the light-emitting device of FIG. 1. FIG. [Figure 7] 1 is a schematic plan view showing a display device according to an embodiment; [Figure 8] 8 is a schematic equivalent circuit diagram showing an embodiment of a pixel included in the display device of FIG. 7. [Figure 9] 9 is a schematic plan view showing an embodiment of the pixel of FIG. 8. FIG. [Figure 10] FIG. 8 is a schematic cross-sectional view showing an embodiment of the display device of FIG. 7. [Figure 11] 11 is a schematic cross-sectional view showing an embodiment in which a region of FIG. 10 is enlarged. [Figure 12] 11 is a schematic cross-sectional view showing an embodiment in which a region of FIG. 10 is enlarged. [Figure 13] 11 is a schematic cross-sectional view showing an embodiment in which a region of FIG. 10 is enlarged. [Figure 14] 11 is a schematic cross-sectional view showing an embodiment in which a region of FIG. 10 is enlarged. [Figure 15] 8 is a schematic equivalent circuit diagram showing an embodiment of a pixel included in the display device of FIG. 7. [Figure 16] FIG. 16 is a schematic cross-sectional view showing an embodiment of the pixel of FIG. [Figure 17] FIG. 16 is a schematic cross-sectional view showing an embodiment of the pixel of FIG. [Figure 18] FIG. 16 is a schematic cross-sectional view showing an embodiment of the pixel of FIG. DETAILED DESCRIPTION OF THE INVENTION

[0030] In the following description, for purposes of explanation, numerous specific details are presented to provide a thorough understanding of various embodiments or implementations of the present invention. As used herein, "embodiment" and "implementation" are interchangeable terms for non-limiting examples of devices or methods disclosed herein. However, it will be apparent that various embodiments may be practiced without these specific details or in one or more equivalent arrangements. Here, various embodiments are not necessarily exclusive and do not necessarily limit the disclosure. For example, specific shapes, configurations, and characteristics of an embodiment may be used or embodied in other embodiments.

[0031] Unless otherwise specified, it should be understood that the illustrated embodiments provide features of the present invention. Accordingly, unless otherwise specified, the features, components, modules, layers, films, panels, regions, and / or aspects, etc. (hereinafter individually or collectively referred to as "components") of the various embodiments may be combined, separated, interchanged, and / or rearranged with one another without departing from the scope of the present invention.

[0032] Cross-hatching and / or shading in the accompanying drawings are typically used to clarify boundaries between adjacent elements. Therefore, unless otherwise specified, the presence or absence of cross-hatching or shading does not convey or indicate preferences or requirements for specific materials, material characteristics, dimensions, proportions, commonalities between elements in the drawings, and / or other characteristics, attributes, properties, etc. Also, the sizes and relative sizes of elements in the accompanying drawings may be exaggerated for clarity and / or illustrative purposes. When different embodiments can be implemented, the order of certain processes may be performed differently from the order described. For example, two steps described as consecutive may be performed substantially simultaneously or in the reverse order from the order described. Also, the same reference numerals refer to the same elements.

[0033] When an element such as a layer is referred to as being "on," "connected," or "coupled" to another element or layer, it may be directly connected or coupled to the other element or layer. An element or layer, or an intermediate element or layer, may be present. However, when an element or layer is referred to as being "directly connected to" or "directly coupled to" another element or layer, there is no intermediate element or layer present. Therefore, the term "connected" may refer to a physical, electrical, and / or fluid connection with or without intermediate elements. Furthermore, the DR1, DR2, and DR3 axes are not limited to the three axes of a Cartesian coordinate system, such as the X, Y, and Z axes, but may be interpreted in a broader sense. For example, the DR1, DR2, and DR3 axes may be mutually orthogonal, or may indicate different directions that are not orthogonal to each other. Furthermore, the X, Y, and Z axes are not limited to the three axes of a Cartesian coordinate system, such as the x, y, and z axes, but may be interpreted in a broader sense. For example, the X, Y, and Z axes may be mutually orthogonal, or may indicate different directions that are not orthogonal to each other. For purposes of this disclosure, "at least one of A and B" may be interpreted to mean A alone, B alone, or any combination of A and B. Also, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as X alone, Y alone, Z alone, or any combination of two or more of X, Y, and Z. As used herein, the term "and / or" includes all combinations of one or more of the associated listed items.

[0034] In this specification, terms such as "first" and "second" may be used to describe various types of components, but the components should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, the first element discussed below can be referred to as the second element without departing from the spirit of the present invention.

[0035] Spatially relative terms such as "beneath," "below," "under," "lower," "above," "upper," "over," "higher," "side (e.g., "sidewall")," and the like may be used herein for descriptive purposes and to describe the relationship of one element to other elements as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device during use, operation, and / or manufacture in addition to the orientation depicted in the figures. For example, if the device in the figures were inverted, elements described as "beneath" or "below" other elements or features would now be oriented "above" the other elements or features.

[0036] Hereinafter, a display device according to an embodiment will be described with reference to the drawings relating to the embodiment.

[0037] Fig. 1 is a schematic perspective view showing a light-emitting device according to one embodiment. Fig. 2 is a schematic cross-sectional view showing one embodiment of the light-emitting device of Fig. 1. For example, Fig. 2 shows one embodiment of a cross section of the light-emitting device LD taken along line II' in Fig. 1.

[0038] 1 and 2, the light-emitting element LD may include a first semiconductor layer SCL1, an emission layer EML, a second semiconductor layer SCL2, and an electrode layer ETL, which are sequentially arranged and / or stacked along one direction (e.g., the longitudinal direction or the thickness direction). In one embodiment, the light-emitting element LD may further include at least one other semiconductor layer (e.g., at least one other semiconductor layer arranged above and / or below the emission layer EML) and / or at least one electrode layer (e.g., an electrode layer arranged around the first semiconductor layer SCL1).

[0039] In one embodiment, the light emitting device LD may be formed in a rod shape. In describing the embodiment, the rod shape may include various rod-like shapes or bar-like shapes, including a cylindrical shape or a polygonal prism shape, and the cross-sectional shape is not limited. In one embodiment, the length L of the light emitting device LD may be greater than its diameter D (or width of the cross section).

[0040] In one embodiment, the light-emitting element LD may have a small size in the nanometer to micrometer range. For example, the light-emitting element LD may have a diameter D (or cross-sectional width) and / or length L in the nanometer to micrometer range. As an example, the light-emitting element LD may have a diameter D and / or length L in the range of about tens of nanometers to tens of micrometers. For example, the length L of the light-emitting element LD may be about 1 μm to about 10 μm, or about 3.5 μm to about 4 μm, and the diameter D of the light-emitting element LD may be about 0.1 μm to about 1 μm, or about 500 nm to about 600 nm. However, the size of the light-emitting element LD may be changed.

[0041] The light emitting element LD may include a first end EP1 and a second end EP2 facing each other. For example, the light emitting element LD may include the first end EP1 and the second end EP2 at both ends in the longitudinal direction (or thickness direction). The first end EP1 of the light emitting element LD may include a first bottom surface (e.g., an upper surface) of the light emitting element LD and / or a surrounding area thereof. The second end EP2 of the light emitting element LD may include a second bottom surface (e.g., a lower surface) of the light emitting element LD and / or a surrounding area thereof.

[0042] In one embodiment, the first semiconductor layer SCL1, the light emitting layer EML, the second semiconductor layer SCL2, and the electrode layer ETL may be arranged in this order from the second end EP2 to the first end EP1 of the light emitting element LD. For example, the electrode layer ETL may be arranged at the first end EP1 of the light emitting element LD, and the first semiconductor layer SCL1 (or another electrode layer adjacent to the first semiconductor layer SCL1 and electrically connected to the first semiconductor layer SCL1) may be arranged at the second end EP2 of the light emitting element LD.

[0043] The light emitting element LD may further include an insulating film INF covering the side surfaces of the first semiconductor layer SCL1, the light emitting layer EML, and the second semiconductor layer SCL2. The insulating film INF may at least partially cover the side surfaces of the electrode layer ETL.

[0044] The first semiconductor layer SCL1 may include a semiconductor layer of the first conductivity type containing a dopant of the first conductivity type. For example, the first semiconductor layer SCL1 may be an n-type semiconductor layer containing an n-type dopant.

[0045] In one embodiment, the first semiconductor layer SCL1 may include a nitride-based semiconductor material or a phosphide-based semiconductor material. For example, the first semiconductor layer SCL1 may include a nitride-based semiconductor material including at least one of GaN, AlGaN, InGaN, InAlGaN, AlN, and InN, or a phosphide-based semiconductor material including at least one of GaP, InGaP, AlGaP, InAlGaP, AlP, and InP. In one embodiment, the first semiconductor layer SCL1 may include an n-type dopant such as Si, Ge, or Sn. The material constituting the first semiconductor layer SCL1 is not limited thereto, and various other materials may be used to form the first semiconductor layer SCL1.

[0046] The light-emitting layer EML (also referred to as the "active layer") may be disposed on the first semiconductor layer SCL1. The light-emitting layer EML may include a single or multiple quantum well (QW) structure. When a voltage equal to or greater than a threshold voltage is applied across the light-emitting element LD, electron-hole pairs recombine in the light-emitting layer EML, causing light to be emitted.

[0047] In one embodiment, the emitting layer EML can emit light in the visible wavelength range, e.g., light in the wavelength range of about 400 nm to 900 nm. For example, the emitting layer EML can emit blue light having a wavelength in the range of about 450 nm to 480 nm, green light having a wavelength in the range of about 480 nm to 560 nm, or red light having a wavelength in the range of about 620 nm to 750 nm. For example, the color and / or wavelength range of the light generated by the emitting layer EML can be changed.

[0048] In one embodiment, the light emitting layer EML may include a nitride-based semiconductor material or a phosphide-based semiconductor material. For example, the light emitting layer EML may include a nitride-based semiconductor material including at least one of GaN, AlGaN, InGaN, InGaAlN, AlN, InN, and AlInN, or a phosphide-based semiconductor material including at least one of GaP, InGaP, AlGaP, InAlGaP, AlP, and InP. The materials constituting the light emitting layer EML are not limited thereto, and various other materials may be used to form the light emitting layer EML.

[0049] In one embodiment, the light emitting layer EML may contain elements that affect the color (or wavelength band) of light, and the color of light generated by the light emitting layer EML can be controlled by adjusting the content and / or composition ratio of these elements. For example, the light emitting layer EML may be formed as a multilayer structure in which GaN layers and InGaN layers are alternately or repeatedly stacked, and light of a specific color can be emitted depending on the content and / or composition ratio of indium (In) contained in the InGaN layer. Therefore, a light emitting device LD with a desired color can be manufactured by adjusting the content and / or composition ratio of indium (In) contained in the light emitting layer EML.

[0050] The second semiconductor layer SCL2 may be disposed on the light emitting layer EML. The second semiconductor layer SCL2 may include a second conductivity type semiconductor layer containing a second conductivity type dopant. For example, the second semiconductor layer SCL2 may be a p-type semiconductor layer containing a p-type dopant.

[0051] In one embodiment, the second semiconductor layer SCL2 may include a nitride-based semiconductor material or a phosphide-based semiconductor material. For example, the second semiconductor layer SCL2 may include a nitride-based semiconductor material including at least one of GaN, AlGaN, InGaN, InAlGaN, AlN, and InN, or a phosphide-based semiconductor material including at least one of GaP, InGaP, AlGaP, InAlGaP, AlP, and InP. In one embodiment, the second semiconductor layer SCL2 may include a p-type dopant such as Mg. The material constituting the second semiconductor layer SCL2 is not limited thereto, and various other materials may be used to form the second semiconductor layer SCL2.

[0052] In one embodiment, the first semiconductor layer SCL1 and the second semiconductor layer SCL2 may include the same semiconductor material but dopants of different conductivity types, or in another embodiment, the first semiconductor layer SCL1 and the second semiconductor layer SCL2 may include different semiconductor materials and dopants of different conductivity types.

[0053] In one embodiment, the first semiconductor layer SCL1 and the second semiconductor layer SCL2 may have different lengths (or thicknesses) in the longitudinal direction of the light emitting element LD. For example, the first semiconductor layer SCL1 may have a longer length (or a thicker thickness) than the second semiconductor layer SCL2 along the longitudinal direction of the light emitting element LD. This allows the light emitting layer EML to be located closer to the first end EP1 (e.g., p-type end) than the second end EP2 (e.g., n-type end).

[0054] The electrode layer ETL may be disposed on the second semiconductor layer SCL2. For example, the electrode layer ETL may be formed on (for example, directly on) the second semiconductor layer SCL2 so as to be in contact with the second semiconductor layer SCL2.

[0055] The electrode layer ETL can protect the second semiconductor layer SCL2 and configure an electrode for smoothly connecting the second semiconductor layer SCL2 to a predetermined electrode or wiring, etc. For example, the electrode layer ETL can be an ohmic contact electrode or a Schottky contact electrode.

[0056] In one embodiment, the electrode layer ETL may include a metal or a metal oxide. For example, the electrode layer ETL may be formed of a metal such as chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), or copper (Cu), an oxide or alloy thereof, or a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), zinc oxide (ZnO), tin dioxide (SnO2), or indium oxide (In2O3), either alone or in combination. The materials constituting the electrode layer ETL are not limited thereto, and various other conductive materials may be used to form the electrode layer ETL.

[0057] In one embodiment, the electrode layer ETL may be substantially transparent, so that light generated by the light emitting element LD may pass through the electrode layer ETL and be emitted from the first end EP1 of the light emitting element LD.

[0058] In one embodiment, the electrode layer ETL may have a thickness in the range of about 100 nm to 200 nm, and the thickness of the electrode layer ETL may be variously changed depending on the embodiment. When the electrode layer ETL has a relatively small thickness (for example, a thickness in the range of 100 nm to 200 nm), a decrease in the light output efficiency of the light emitting device LD due to the electrode layer ETL can be prevented or minimized.

[0059] The insulating coating film INF may be provided on the surface of the light-emitting element LD so as to cover the side surfaces (or circumferential surfaces) of the first semiconductor layer SCL1, the light-emitting layer EML, the second semiconductor layer SCL2, and the electrode layer ETL.

[0060] When the insulating film INF is provided on the surface of the light emitting device LD, it is possible to prevent a short circuit through the light emitting device LD, thereby ensuring the electrical stability of the light emitting device LD. For example, when the insulating film INF is provided on the surface of the light emitting device LD, it is possible to minimize surface defects of the light emitting device LD and improve the lifespan and efficiency.

[0061] The insulating film INF may include a transparent insulating material, so that light generated in the light emitting layer EML may pass through the insulating film INF and be emitted to the outside of the light emitting device LD. For example, the insulating film INF may include a silicon oxide (SiO X ) (e.g., SiO2), silicon nitride (SiN X ) (e.g., Si3N4), aluminum oxide (AlxOy) (e.g., Al2O3), titanium oxide (Ti x O y The insulating material may include at least one of titanium dioxide (TiO2) and hafnium oxide (HfOx), or other insulating materials.

[0062] The insulating coating INF may be composed of a single layer or multiple layers, for example, the insulating coating INF may include a double layer.

[0063] The insulating coating INF may expose the first semiconductor layer SCL1 and the second semiconductor layer SCL2 at the first end EP1 and the second end EP2 of the light emitting element LD, respectively. For example, the insulating coating INF may not be provided on the upper surface of the second semiconductor layer SCL2, thereby exposing the upper surface of the second semiconductor layer SCL2 at the first end EP1 of the light emitting element LD. For example, the insulating coating INF may not be provided on the lower surface of the first semiconductor layer SCL1 (e.g., the bottom surface of the light emitting element LD), thereby exposing the lower surface of the first semiconductor layer SCL1 at the second end EP2 of the light emitting element LD. This may allow the first semiconductor layer SCL1 and the second semiconductor layer SCL2 to be connected to at least one electrode, wiring, and / or conductive pattern layer, etc., to apply driving power and / or signals to the first end EP1 and the second end EP2 of the light emitting element LD.

[0064] The insulating film INF may cover (e.g., completely cover) at least the side surfaces of the light emitting layer EML and the second semiconductor layer SCL2. This may ensure electrical stability of the light emitting device LD and prevent short defects through the light emitting device LD. In the process of removing the insulating film INF from the upper surface of the electrode layer ETL, the insulating film INF may also be partially removed or minimized from the upper layer portions of the side surfaces of the electrode layer ETL.

[0065] The thickness and / or surface profile of the insulating coating INF may vary depending on the embodiment. For example, the thickness and / or surface profile of the insulating coating INF may vary depending on the process method, process conditions, and / or materials used to form the insulating coating INF. In one embodiment, when the insulating coating INF is formed using an atomic layer deposition (ALD) process technique that can form a coating with high step coverage, the insulating coating INF may have a surface profile that corresponds to (e.g., follows) the side shapes of the first semiconductor layer SCL1, the light emitting layer EML, the second semiconductor layer SCL2, and the electrode layer ETL, and may be formed to a uniform thickness overall.

[0066] The structure, shape, size, and / or type of the light emitting device LD may be varied depending on the embodiment, for example, the structure, shape, size, and / or type of the light emitting device LD may vary depending on the design conditions of a light emitting device using the light emitting device LD, the desired light emitting characteristics, etc.

[0067] The light-emitting device including the light-emitting element LD may be used in various types of devices that require a light source. For example, the light-emitting element LD may be disposed in the pixel of a display device, and the light-emitting element LD may be used as a light source for the pixel. The light-emitting element LD may also be used in other types of devices that require a light source, such as a lighting device.

[0068] Fig. 3 is a schematic cross-sectional view showing an embodiment of the light-emitting element of Fig. 1. Fig. 4 is a schematic cross-sectional view showing an embodiment of the light-emitting element of Fig. 3.

[0069] 1 to 4, except for the shielding layer SHL, the light emitting device LD_1 in Figures 3 and 4 may be substantially the same as or similar to the light emitting device LD in Figures 1 and 2. Therefore, a redundant description will be omitted.

[0070] The light emitting element LD_1 may further include a shielding layer SHL (or a shielding film), and the shielding layer SHL may be disposed inside the insulating coating INF.

[0071] The shielding layer SHL may cover the side surfaces of the emitting layer EML. For example, the shielding layer SHL may completely cover the side surfaces of the emitting layer EML. The shielding layer SHL may be extended or expanded in the longitudinal direction of the light emitting element LD_1 to further cover the side surfaces of the second semiconductor layer SCL2. The shielding layer SHL may also partially cover the side surfaces of the electrode layer ETL. For example, the shielding layer SHL may cover the side surfaces of the first semiconductor layer SCL1. For example, the shielding layer SHL may cover the side surfaces of a portion of the first semiconductor layer SCL1 adjacent to the emitting layer EML, but may not cover the side surfaces of the remaining portion of the first semiconductor layer SCL1.

[0072] As will be described later with reference to Figures 11 and 12, the shielding layer SHL can shield or suppress an electric field (or electric field) formed between the light-emitting element LD_1 and an external configuration, for example, formed on the side surface of the light-emitting element LD_1. When the light-emitting element LD_1 is driven for a long period of time, the electric field causes electrons or holes to concentrate on the side surface of the light-emitting element LD_1, which can result in a decrease (or deterioration) in the characteristics of the light-emitting element LD_1. By shielding the electric field on the side surface of the light-emitting element LD_1, the shielding layer SHL can prevent a decrease (or deterioration) in the characteristics of the light-emitting element LD_1 due to long-term driving.

[0073] The shielding layer SHL may be spaced apart from the first semiconductor layer SCL1, the light emitting layer EML, the second semiconductor layer SCL2, and the electrode layer ETL. For example, the shielding layer SHL may be spaced apart from the first end EP1 (or a first end or upper surface corresponding to the first end EP1) and the second end EP2 (or a second end or lower surface corresponding to the second end EP2). Referring to FIG. 4 , for example, the insulating coating INF may be a double layer including a first insulating coating INF1 and a second insulating coating INF2, and the shielding layer SHL may be disposed between the first insulating coating INF1 and the second insulating coating INF2. The first insulating coating INF1 may cover the side surfaces of the first semiconductor layer SCL1, the light emitting layer EML, the second semiconductor layer SCL2, and the electrode layer ETL, and the second insulating coating INF2 may cover or encase the surface of the first insulating coating INF1 and the shielding layer SHL. For example, the shielding layer SHL may be separated from components outside the light emitting element LD_1, and the shielding layer SHL may be in a floating state.

[0074] The shielding layer SHL may include at least one conductive material. For example, the shielding layer SHL may include at least one metal or alloy containing at least one of various metal materials including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), molybdenum (Mo), copper (Cu), or the like, or may include at least one metal or alloy containing at least one metal selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), zinc oxide (ZnO), aluminum doped zinc oxide (AZO), gallium doped zinc oxide (GZO), zinc tin oxide (ZTO), gallium tin oxide (GTO), and fluorine doped tin oxide (FTO). The conductive material may include at least one conductive oxide such as a conductive oxide (e.g., ethylenedioxythiophene) (PEDOT), or a conductive polymer such as poly(3,4-ethylenedioxythiophene) (PEDOT).

[0075] In one embodiment, the light transmittance of the shielding layer SHL may be approximately 70% or more. For example, light may be emitted from the emitting layer EML to the outside of the light-emitting element LD_1 through the shielding layer SHL. For example, the shielding layer SHL may include a transparent material (or a transparent conductive material), but the embodiment is not limited thereto. For example, even if the shielding layer SHL includes a metal (e.g., silver (Ag)) and has a thin thickness of a few nanometers (e.g., 5 nm or less) in the width direction of the light-emitting element LD_1, the shielding layer SHL can transmit light.

[0076] However, the light transmittance of the shielding layer SHL is not limited to this. For example, if the specifications of the display device including the light-emitting element LD_1 do not require light emission through the side surface of the light-emitting element LD_1, the light transmittance of the shielding layer SHL may be approximately 70% or less.

[0077] As described above, the light emitting element LD_1 includes a shielding layer SHL covering the side surfaces of the light emitting layer EML and the second semiconductor layer SCL2, and the shielding layer SHL can shield or suppress an electric field formed between the light emitting element LD_1 and an external structure, for example, formed on the side surface of the light emitting element LD_1, thereby preventing or minimizing deterioration (or degradation) of the characteristics of the light emitting element LD_1 due to the electric field.

[0078] FIG. 5 is a schematic cross-sectional view showing an embodiment of the light-emitting element of FIG.

[0079] 1 to 5, except for the shielding layer SHL_1, the light emitting device LD_2 in Fig. 5 is substantially the same as or similar to the light emitting device LD_1 in Fig. 3 and Fig. 4 (or the light emitting device LD in Fig. 1 and Fig. 2), and therefore, a duplicated description will be omitted.

[0080] The shielding layer SHL_1 may extend to the first end EP1 and the second end EP2 in the longitudinal direction of the light emitting element LD_2. The shielding layer SHL_1 may be covered by the insulating coating INF (or the second insulating coating INF2 in FIG. 4). For example, the shielding layer SHL_1 may not be exposed to the outside.

[0081] The shielding layer SHL_1 may cover most of the side surfaces of the first semiconductor layer SCL1, the light emitting layer EML, and the second semiconductor layer SCL2. For example, the shielding layer SHL_1 may cover (e.g., completely cover) the side surfaces of the light emitting layer EML and the second semiconductor layer SCL2, and may cover most of the first semiconductor layer SCL1. For example, the shielding layer SHL_1 may cover approximately 90% or more of the side surface of the first semiconductor layer SCL1. According to an embodiment, the shielding layer SHL_1 may also cover the side surfaces of the electrode layer ETL. For example, the shielding layer SHL_1 may reinforce the core-shell structure of the light emitting element LD_2.

[0082] In one embodiment, the light reflectivity of the shielding layer SHL_1 may be approximately 90% or more. For example, light emitted from the light emitting layer EML is reflected (or totally reflected) by the shielding layer SHL_1 and can proceed (or be transmitted) to the outside of the light emitting device LD_2 via the first end EP1 and the second end EP2 (or via the first semiconductor layer SCL1 and the electrode layer ETL). For example, the light output efficiency of the light emitting device LD_2 via the first end EP1 and the second end EP2 can be improved. For example, the shielding layer SHL may include a reflective material (or a reflective conductive material).

[0083] As described above, the light-emitting element LD_2 includes a shielding layer SHL_1 that covers most of the side surface and has high reflectivity, and the shielding layer SHL_1 can improve the light output efficiency of the light-emitting element LD_2 through the first and second ends EP1, EP2.

[0084] FIG. 6 is a schematic cross-sectional view showing an embodiment of the light-emitting element of FIG.

[0085] 1 to 6, except for the shielding layer SHL_2, the light emitting device LD_3 in Fig. 6 is substantially the same as or similar to the light emitting device LD_2 in Fig. 5. Therefore, a duplicated description will be omitted.

[0086] The shielding layer SHL_2 may include a first shielding layer SHL1 (or a first sub-shielding layer) and a second shielding layer SHL2 (or a second sub-shielding layer) that are spaced apart from each other. For example, the first shielding layer SHL1 and the second shielding layer SHL2 may be disposed in the same layer between the first insulating coating INF1 and the second insulating coating INF2 in FIG. 4 but may be spaced apart from each other. The first shielding layer SHL1 and the second shielding layer SHL2 may be electrically independent from each other and electrically separated or insulated from each other.

[0087] The first shielding layer SHL1 may extend to a first end of the light-emitting element LD_3 (e.g., the top surface of the light-emitting element LD_3 corresponding to the first end EP1) and cover the side surfaces of the light-emitting layer EML, the second semiconductor layer SCL2, and the electrode layer ETL. The first shielding layer SHL1 may be exposed to the outside at the first end EP1. For example, the first shielding layer SHL1 may be in contact with or connected to components outside the light-emitting element LD_3.

[0088] For example, the second shielding layer SHL2 may extend to the second end of the light-emitting element LD_3 (e.g., the bottom surface of the light-emitting element LD_3 corresponding to the second end EP2) and cover the side surface of the first semiconductor layer SCL1. The second shielding layer SHL2 may be exposed to the outside at the second end EP2. For example, the second shielding layer SHL2 may contact or be connected to a component outside the light-emitting element LD_3.

[0089] For example, when the first shielding layer SHL1 and / or the second shielding layer SHL2 are at least selectively connected to an external component (e.g., ground), the first shielding layer SHL1 and / or the second shielding layer SHL2 can shield (e.g., completely shield) the electric field. For example, the shielding layer SHL_2 can have enhanced shielding properties.

[0090] In one embodiment, the light reflectivity of the shielding layer SHL_2 may be about 90% or more, thereby improving the light output efficiency of the light emitting element LD_3 through the first end EP1 and the second end EP2.

[0091] As described above, the light emitting element LD_3 may include a first shielding layer SHL1 and a second shielding layer SHL2 that are spaced apart from each other and cover most of the side surfaces of the light emitting element LD_3. When at least one of the first shielding layer SHL1 and the second shielding layer SHL2 is connected to an external component (e.g., ground), the electric field formed on the side surfaces of the light emitting element LD_3 can be more reliably shielded.

[0092] 7 is a schematic plan view showing a display device according to an embodiment. Fig. 7 shows a simplified structure of a display device DD, focusing on a display panel DP including a display area DA. The display device DD may further include driving circuits (e.g., a scan driver, a data driver, a timing controller, etc.) for driving the pixels PXL.

[0093] 7, the display device DD may include a base layer BSL (or substrate) and pixels PXL disposed on the base layer BSL. The base layer BSL and the display device DD including the base layer BSL may be formed in various shapes. For example, the base layer BSL and the display device DD including the base layer BSL may be formed in a substantially rectangular plate shape in a plan view, or may include angular or rounded corners. The shapes of the base layer BSL and the display device DD may be changed. For example, the base layer BSL and the display device DD may be polygonal, such as a hexagon or octagon, in a plan view, or may have a shape including a curved periphery, such as a circle or ellipse.

[0094] 7 shows a display device DD that is a rectangular plate. For example, the lateral direction (e.g., row direction or horizontal direction) of the display device DD is defined as a first direction DR1, the longitudinal direction (e.g., column direction or vertical direction) of the display device DD is defined as a second direction DR2, and the thickness direction (or height direction) of the display device DD is defined as a third direction DR3.

[0095] The base layer BSL may be a base member for constructing the display device DD. For example, the base layer BSL may provide a bottom surface of the display device DD.

[0096] The base layer BSL and the display device DD including the base layer BSL may include a display area DA for displaying an image, and a non-display area NA located around the display area DA.

[0097] The display area DA is an area in which the pixels PXL are arranged, and may be an area in which an image is displayed by the pixels PXL. In one embodiment, the display area DA may be arranged in a central area of ​​the base layer BSL and the display device DD (e.g., a central area of ​​the display panel DP).

[0098] The display area DA may have various shapes, including, for example, a rectangular shape, a circular shape, an elliptical shape, etc. In one embodiment, the display area DA may have a shape corresponding to the shape of the base layer BSL, but the embodiment is not limited thereto.

[0099] The non-display area NA may be the remaining area excluding the display area DA. In one embodiment, the non-display area NA may be arranged in the edge area of ​​the base layer BSL and the display device DD so as to surround the display area DA.

[0100] The pixels PXL may be arranged in the display area DA. For example, the display area DA may include a pixel area in which the respective pixels PXL are provided and / or arranged.

[0101] In one embodiment, at least two types of pixels PXL for emitting light of different colors may be arranged in the display area DA. For example, a first color pixel PXL1, a second color pixel PXL2, and a third color pixel PXL3 may be arranged in the display area DA. At least one first color pixel PXL1, at least one second color pixel PXL2, and at least one third color pixel PXL3 arranged adjacent to each other may constitute one pixel group PXG. By individually controlling the brightness of the first color, second color, and third color pixels PXL1, PXL2, and PXL3 included in each pixel group PXG, the color of light emitted from the pixel group PXG can be varied in various ways.

[0102] In one embodiment, a first color pixel PXL1, a second color pixel PXL2, and a third color pixel PXL3, which are consecutively arranged along a first direction DR1, may constitute one pixel group PXG. For example, the number, type, and / or relative arrangement structure of the pixels PXL constituting each pixel group PXG may vary.

[0103] In one embodiment, the first color pixel PXL1 may be a red pixel for emitting red light, the second color pixel PXL2 may be a green pixel for emitting green light, and the third color pixel PXL3 may be a blue pixel for emitting blue light. For example, the colors of light emitted from the pixels PXL constituting each pixel group PXG may vary.

[0104] In one embodiment, each pixel PXL may include at least one light-emitting element LD. For example, the pixel PXL may include a light-emitting element LD according to at least one of the embodiments of FIGS. 1 to 6. In one embodiment, each light-emitting element LD may have a size in the range of approximately nanometers to micrometers and may have a rod shape, but the embodiment is not limited thereto. For example, the number, type, structure, and / or size of the light-emitting elements LD provided in each pixel PXL may vary depending on the embodiment.

[0105] In one embodiment, the first color pixel PXL1, the second color pixel PXL2, and the third color pixel PXL3 may include first color, second color, and third color light emitting elements LD as light sources, respectively, so that the first color pixel PXL1, the second color pixel PXL2, and the third color pixel PXL3 can emit first color light, second color light, and third color light, respectively.

[0106] In another embodiment, the first color pixel PXL1, the second color pixel PXL2, and the third color pixel PXL3 may each include a light-emitting element LD that emits light of the same color, and a light conversion layer including wavelength conversion particles (e.g., particles that convert the color and / or wavelength of light, such as quantum dots QDs) may be disposed in the light-emitting regions of the first color pixel PXL1, the second color pixel PXL2, and / or the third color pixel PXL3, thereby allowing the first color pixel PXL1, the second color pixel PXL2, and the third color pixel PXL3 to emit light of the first color, the second color, and the third color, respectively.

[0107] For example, the first color pixel PXL1, the second color pixel PXL2, and the third color pixel PXL3 may each include a blue light-emitting element, and a light conversion layer including wavelength conversion particles of a first color (e.g., red quantum dots) may be disposed in the light-emitting region of the first color pixel PXL1, and a light conversion layer including wavelength conversion particles of a second color (e.g., green quantum dots) may be disposed in the light-emitting region of the second color pixel PXL2, thereby allowing the first color pixel PXL1 to emit light of a first color (e.g., red light) and the second color pixel PXL2 to emit light of a second color (e.g., green light).

[0108] The pixel PXL may have a structure according to at least one of the embodiments described below. For example, the pixel PXL may have a structure to which any one of the embodiments described below is applied, or a structure to which at least two of the embodiments are applied in combination.

[0109] In one embodiment, the pixel PXL may be an active pixel, but the embodiment is not limited thereto. For example, in other embodiments, the pixel PXL may be a passive pixel.

[0110] In the non-display area NA, wiring and / or an internal circuit section connected to the pixels PXL in the display area DA may be arranged.

[0111] In one embodiment, the non-display area NA may have a narrow width, for example, a width of about 100 μm or less, so that the display device DD may be embodied as a bezel-less display device.

[0112] Figure 8 is a schematic equivalent circuit diagram showing one embodiment of a pixel included in the display device of Figure 7. The pixel PXL shown in Figure 8 may be any one of the pixels PXL arranged in the display area DA of Figure 7. The pixels PXL may have substantially the same or similar structures to each other.

[0113] 8, the pixel PXL may be connected to a scan line SL (also referred to as a "first scan line"), a data line DL, a first power line PL1, and a second power line PL2. For example, the pixel PXL may be further connected to at least one other power line and / or signal line. For example, the pixel PXL may be further connected to a sensing line SENL (also referred to as an "initialization power line") and / or a sensing control line SSL (also referred to as a "second scan line").

[0114] The pixel PXL may include a light emitting unit EMU for generating light of a brightness corresponding to each data signal. For example, the pixel PXL may further include a pixel circuit PXC for driving the light emitting unit EMU.

[0115] The pixel circuit PXC is connected to the scan line SL and the data line DL, and may be connected between the first power line PL1 and the light emitting unit EMU. For example, the pixel circuit PXC may be electrically connected to the scan line SL to which the first scan signal is supplied, the data line DL to which the data signal is supplied, the first power line PL1 to which the voltage of the first power supply VDD is applied, and the light emitting unit EMU.

[0116] The pixel circuit PXC may be selectively further connected to a sensing control line SSL to which a second scan signal is supplied, and a sensing line SENL connected to a reference power supply (or initialization power supply) or a sensing circuit corresponding to a display period or a sensing period. In one embodiment, the second scan signal may be the same as or different from the first scan signal. If the second scan signal is the same as the first scan signal, the sensing control line SSL may be integrated with the scan line SL.

[0117] The pixel circuit PXC may include at least one transistor M and a capacitor Cst. For example, the pixel circuit PXC may include a first transistor M1, a second transistor M2, a third transistor M3, and a capacitor Cst.

[0118] The first transistor M1 may be connected between the first power line PL1 and a second node N2. The second node N2 may be a node at which the pixel circuit PXC and the light emitting unit EMU are connected. For example, the second node N2 may be a node at which one electrode (e.g., a source electrode) of the first transistor M1 and the light emitting unit EMU are electrically connected to each other. The gate electrode of the first transistor M1 may be connected to the first node N1. The first transistor M1 can control the driving current supplied to the light emitting unit EMU in response to the voltage of the first node N1. For example, the first transistor M1 may be a driving transistor of the pixel PXL.

[0119] In one embodiment, the first transistor M1 may further include a lower metal layer BML (also referred to as a "back gate electrode" or a "second gate electrode"), which may be connected to one electrode (e.g., a source electrode) of the first transistor M1.

[0120] In an embodiment in which the first transistor M1 includes a bottom metal layer BML, a back bias technique can be applied in which a back bias voltage is applied to the bottom metal layer BML of the first transistor M1 to shift the threshold voltage of the first transistor M1 in a negative or positive direction. For example, if the bottom metal layer BML is disposed below a semiconductor pattern (e.g., the semiconductor pattern layer SCP in FIG. 10) that forms the channel of the first transistor M1, light incident on the semiconductor pattern layer can be blocked, thereby stabilizing the operating characteristics of the first transistor M1.

[0121] The second transistor M2 may be connected between the data line DL and the first node N1. For example, the gate electrode of the second transistor M2 may be connected to the scan line SL. The second transistor M2 may be turned on to connect the data line DL and the first node N1 when a first scan signal having a gate-on voltage (e.g., a logic high voltage or a high level voltage) is supplied from the scan line SL.

[0122] During each frame period, a data signal of a corresponding frame may be supplied to the data line DL, and the data signal may be transmitted to the first node N1 through the second transistor M2 during a period in which a first scan signal of a gate-on voltage is supplied. For example, the second transistor M2 may be a switching transistor for transmitting each data signal to the inside of the pixel PXL.

[0123] A first electrode of the capacitor Cst may be connected to a first node N1, and a second electrode of the capacitor Cst may be connected to a second node N2, and the capacitor Cst may be charged with a voltage corresponding to a data signal supplied to the first node N1 during each frame period.

[0124] The third transistor M3 may be connected between the second node N2 and the sensing line SENL. For example, the gate electrode of the third transistor M3 may be connected to the sensing control line SSL (or the scan line SL). When a second scan signal (or a first scan signal) having a gate-on voltage (e.g., a logic high voltage or a high-level voltage) is supplied from the sensing control line SSL, the third transistor M3 is turned on to transmit the reference voltage (or initialization voltage) supplied to the sensing line SENL to the second node N2 or transmit the voltage of the second node N2 to the sensing line SENL. In one embodiment, the voltage of the second node N2 may be transmitted to a sensing circuit via the sensing line SENL and may be provided in a driving circuit (e.g., a timing controller) to compensate for characteristic deviations of the pixel PXL.

[0125] 8, the transistors M included in the pixel circuit PXC may all be n-type transistors, but embodiments are not limited thereto. For example, at least one of the first, second, and third transistors M1, M2, and M3 may be changed to a p-type transistor. The structure and driving method of the pixel PXL may vary depending on the embodiment.

[0126] The light emitting unit EMU may include at least one light emitting element LD. For example, the light emitting unit EMU may include a light emitting element LD according to at least one of the embodiments of FIGS. 1 to 6. In one embodiment, the light emitting unit EMU may include a single light emitting element LD connected in a forward bias direction between a first power supply VDD and a second power supply VSS. In another embodiment, the light emitting unit EMU may include a light emitting element LD connected in a forward bias direction between the first power supply VDD and the second power supply VSS. At least one light emitting element LD connected in a forward bias direction between the first power supply VDD and the second power supply VSS can constitute an effective light source of the pixel PXL.

[0127] In one embodiment, the light emitting unit EMU may include a light emitting element LD connected in parallel between the pixel circuit PXC and a second power supply line PL2. A first end EP1 of the light emitting element LD may be electrically connected to the pixel circuit PXC and electrically connected to the first power supply line PL1 via the pixel circuit PXC. A second end EP2 of the light emitting element LD may be electrically connected to the second power supply line PL2. A voltage of the second power supply VSS may be applied to the second power supply line PL2.

[0128] The number, type, and / or structure of the light emitting elements LD constituting the effective light source of the pixel PXL may vary depending on the embodiment. For example, the arrangement and / or connection structure of the light emitting elements LD may also vary depending on the embodiment.

[0129] In one embodiment, the light emitting unit EMU may include light emitting elements LD connected in series-parallel between the pixel circuit PXC and the second power supply line PL2. For example, the light emitting elements LD may be arranged and / or connected in at least two series stages between the pixel circuit PXC and the second power supply line PL2, and each series stage may include at least one light emitting element LD connected in a forward bias direction between the first power supply VDD and the second power supply VSS.

[0130] The first power supply VDD and the second power supply VSS may have different potentials. For example, the first power supply VDD may be a high-potential pixel power supply and the second power supply VSS may be a low-potential pixel power supply. The potential difference between the first power supply VDD and the second power supply VSS may be equal to or greater than the threshold voltage of the light-emitting element LD.

[0131] The light emitting element LD can emit light at a brightness corresponding to the drive current supplied via the pixel circuit PXC. During each frame period, the pixel circuit PXC can supply a drive current corresponding to a data signal to the light emitting unit EMU. The drive current supplied to the light emitting unit EMU flows through the light emitting element LD, causing the light emitting element LD to emit light. This allows the light emitting unit EMU to emit light at a brightness corresponding to the drive current.

[0132] 8 shows only the light emitting element LD (e.g., effective light source) connected in a forward bias direction between the first power supply VDD and the second power supply VSS, but the embodiment is not limited thereto. For example, the light emitting unit EMU may further include at least one ineffective light source in addition to the light emitting element LD constituting each effective light source. For example, the light emitting unit EMU may further include at least one ineffective light emitting element arranged in a reverse bias direction between the first power supply VDD and the second power supply VSS or having at least one end floating.

[0133] Fig. 9 is a schematic plan view showing one embodiment of the pixel of Fig. 8. Fig. 9 shows the structure of the pixel PXL of Fig. 8, focusing on the light-emitting unit EMU of the pixel PXL.

[0134] 1 to 9, the pixel PXL may include a light-emitting area EA in which at least one light-emitting element LD is arranged. In one embodiment, the light-emitting area EA may include at least two light-emitting elements LD and electrodes electrically connected to the light-emitting elements LD. In one embodiment, the electrodes may include an alignment electrode ALE and a pixel electrode ELT (also referred to as a "contact electrode"). For example, the pixel PXL may further include a bank pattern layer BNP arranged below the alignment electrode ALE.

[0135] The alignment electrodes ALE may have various shapes and may be spaced apart from each other. In one embodiment, the alignment electrodes ALE may be spaced apart from each other along the first direction DR1 and may each have a shape (e.g., a bar shape) extending along the second direction DR2.

[0136] The shape, size, number, position, and / or relative arrangement structure of the alignment electrodes ALE may be variously changed depending on the embodiment. For example, the alignment electrodes ALE may have similar or the same shape and / or size to each other, or may have different shapes and sizes to each other.

[0137] The alignment electrode ALE may include at least two electrodes spaced apart from each other. For example, the alignment electrode ALE may include a first alignment electrode ALE1 and a second alignment electrode ALE2, and may optionally further include a third alignment electrode ALE3.

[0138] In one embodiment, the first alignment electrode ALE1 may be located in the center of the light emitting area EA, and the second alignment electrode ALE2 and the third alignment electrode ALE3 may be located on the sides (e.g., both sides) of the first alignment electrode ALE1. For example, the second alignment electrode ALE2 may be located to the right of the first alignment electrode ALE1, and the third alignment electrode ALE3 may be located to the left of the first alignment electrode ALE1.

[0139] The alignment electrode ALE (or the alignment wiring before being separated into the respective alignment electrodes ALE of the pixel PXL) may receive an alignment signal required for aligning the light emitting elements LD in the alignment step of the light emitting elements LD. As a result, an electric field may be formed between the alignment electrodes ALE, and the light emitting elements LD may be aligned and / or arranged between the alignment electrodes ALE. Here, the alignment and / or arrangement of the light emitting elements LD between the alignment electrodes ALE may mean that at least a portion of each of the light emitting elements LD is disposed between the alignment electrodes ALE.

[0140] For example, the first alignment electrode ALE1, the second alignment electrode ALE2, and the third alignment electrode ALE3 (or the first alignment wiring in a state where the first alignment electrode ALE1 of the pixel PXL is connected, the second alignment wiring in a state where the second alignment electrode ALE2 of the pixel PXL is connected, and the third alignment wiring in a state where the third alignment electrode ALE3 of the pixel PXL is connected) may receive a first alignment signal, a second alignment signal, and a third alignment signal, respectively, in the alignment step of the light emitting element LD. The first alignment signal and the second alignment signal may have different waveforms, potentials, and / or phases. As a result, an electric field may be formed between the first alignment electrode ALE1 and the second alignment electrode ALE2, and the light emitting element LD (e.g., the first light emitting element LD1) may be aligned between the first alignment electrode ALE1 and the second alignment electrode ALE2. The first alignment signal and the third alignment signal may have different waveforms, potentials, and / or phases. As a result, an electric field is formed between the first alignment electrode ALE1 and the third alignment electrode ALE3, and the light emitting element LD (e.g., the second light emitting element LD2) may be aligned between the first alignment electrode ALE1 and the third alignment electrode ALE3. The third alignment signal may be the same as or different from the second alignment signal.

[0141] The alignment electrode ALE may be disposed in the light-emitting area EA of each pixel PXL. In one embodiment, the alignment electrode ALE may extend through a non-light-emitting area NEA around the light-emitting area EA to a separation area SPA. The separation area SPA may be an area where each alignment line (e.g., the first alignment line, the second alignment line, or the third alignment line) is separated into the alignment electrode ALE of the pixel PXL (e.g., the first alignment electrode ALE1, the second alignment electrode ALE2, or the third alignment electrode ALE3 of the pixel PXL) after the alignment of the light-emitting element LD is completed, and may be disposed on at least one side of each light-emitting area EA.

[0142] For example, each pixel PXL may include at least one separation region SPA arranged around the light-emitting region EA (for example, two separation regions SPA arranged above and below each light-emitting region EA). For example, an end of at least one electrode constituting the light-emitting unit EMU (for example, an end of the alignment electrode ALE) may be arranged in each separation region SPA.

[0143] In one embodiment, each alignment electrode ALE may have a separate pattern layer for each pixel PXL, for example, the first, second and third alignment electrodes ALE1, ALE2, ALE3 of each pixel PXL may each have an individually separate pattern layer.

[0144] However, the present invention is not limited to this. For example, in a structure in which the second pixel electrodes ELT2 of the pixels PXL are commonly connected to the second power line PL2, the alignment electrode ALE (e.g., the third alignment electrode ALE3 of the pixel PXL) connected to the second pixel electrode ELT2 may be formed integrally and without being separated between the pixels PXL adjacent to each other along the first direction DR1 and / or the second direction DR2.

[0145] In one embodiment, the first alignment electrode ALE1 may be electrically connected to a pixel circuit PXC (e.g., the pixel circuit PXC of the corresponding pixel PXL) and / or a first power line PL1 located in a circuit layer (e.g., the circuit layer PCL in FIG. 10) via the first contact portion CNT1. For example, a first alignment signal can be supplied to the first alignment electrode ALE1 (or the first alignment line) via at least one line (e.g., the first power line PL1) located in the circuit layer.

[0146] The first contact portion CNT1 may include at least one contact hole and / or via hole. In one embodiment, the first contact portion CNT1 may be located in the non-light-emitting area NEA located around each light-emitting area EA, but the location of the first contact portion CNT1 may be changed. For example, the first contact portion CNT1 may be located in each light-emitting area EA or the separation area SPA.

[0147] In one embodiment, the second alignment electrode ALE2 may be electrically connected to a second power line PL2 located on the circuit layer via the second contact part CNT2. For example, a second alignment signal can be supplied to the second alignment electrode ALE2 (or the second alignment wiring) via the second power line PL2.

[0148] For example, the third alignment electrode ALE3 may be electrically connected to a second power line PL2 located on the circuit layer via a third contact part CNT3. For example, a second alignment signal can also be supplied to the third alignment electrode ALE3 (or the third alignment wiring) via the second power line PL2.

[0149] The second contact portion CNT2 and the third contact portion CNT3 may each include at least one contact hole and / or via hole. In one embodiment, the second contact portion CNT2 and the third contact portion CNT3 may be located in the non-light-emitting area NEA that is located around each light-emitting area EA, but the positions of the second contact portion CNT2 and the third contact portion CNT3 may be changed. For example, the second contact portion CNT2 and the third contact portion CNT3 may be located in each light-emitting area EA or the separation area SPA.

[0150] At least one first light emitting element LD1 may be disposed between the first alignment electrode ALE1 and the second alignment electrode ALE2. For example, the first light emitting element LD1 may be arranged between the first alignment electrode ALE1 and the second alignment electrode ALE2.

[0151] Each first light emitting element LD1 may or may not overlap with the first alignment electrode ALE1 and / or the second alignment electrode ALE2. A first end EP1 of the first light emitting element LD1 may be arranged adjacent to the first alignment electrode ALE1, and a second end EP2 of the first light emitting element LD1 may be arranged adjacent to the second alignment electrode ALE2.

[0152] The first end EP1 of the first light emitting element LD1 may be electrically connected to the first pixel electrode ELT1. In one embodiment, the first end EP1 of the first light emitting element LD1 may be electrically connected to the pixel circuit PXC and / or the first power line PL1 via the first pixel electrode ELT1. For example, the first end EP1 of the first light emitting element LD1 may be electrically connected to the first alignment electrode ALE1 (or a bridge electrode corresponding to the first alignment electrode ALE1) via the first pixel electrode ELT1, or may be electrically connected to the pixel circuit PXC and / or the first power line PL1 via the first alignment electrode ALE1. However, the embodiment is not limited thereto.

[0153] The second end EP2 of the first light-emitting element LD1 may be electrically connected to the third pixel electrode ELT3 and / or the second pixel electrode ELT2. In one embodiment, the second end EP2 of the first light-emitting element LD1 may be electrically connected to the third pixel electrode ELT3. For example, the second end EP2 of the first light-emitting element LD1 may be electrically connected to the second power line PL2 via the third pixel electrode ELT3, at least one second light-emitting element LD2, the second pixel electrode ELT2, and the third alignment electrode ALE3 in this order.

[0154] At least one second light emitting element LD2 may be disposed between the first alignment electrode ALE1 and the third alignment electrode ALE3. For example, the second light emitting element LD2 may be arranged between the first alignment electrode ALE1 and the third alignment electrode ALE3.

[0155] Each second light emitting element LD2 may or may not overlap with the first alignment electrode ALE1 and / or the third alignment electrode ALE3. The first end EP1 of the second light emitting element LD2 may be arranged adjacent to the first alignment electrode ALE1, and the second end EP2 of the second light emitting element LD2 may be arranged adjacent to the third alignment electrode ALE3.

[0156] The first end EP1 of the second light-emitting element LD2 may be electrically connected to the third pixel electrode ELT3. The second end EP2 of the second light-emitting element LD2 may be electrically connected to the second pixel electrode ELT2. In one embodiment, the second end EP2 of the second light-emitting element LD2 may be electrically connected to the second power line PL2 via the second pixel electrode ELT2. For example, the second end EP2 of the second light-emitting element LD2 may be electrically connected to the third alignment electrode ALE3 via the second pixel electrode ELT2, or may be electrically connected to the second power line PL2 via the third alignment electrode ALE3. However, the embodiment is not limited thereto.

[0157] For example, each light-emitting element LD (e.g., the first light-emitting element LD1 or the second light-emitting element LD2) may include a first end EP1 electrically connected to the first pixel electrode ELT1 and a second end EP2 electrically connected to the second pixel electrode ELT2. The light-emitting element LD may be a light-emitting element LD according to at least one of the embodiments of FIGS. 1 to 6. The type, size, shape, structure, and / or number of the light-emitting elements LD constituting the light-emitting unit EMU may be changed.

[0158] The light emitting elements LD may be prepared in the form of a light emitting element mixture (or light emitting element ink) dispersed in a solution, and may be supplied to each light emitting area EA by an inkjet method, a slit coating method, etc. Simultaneously with or after supplying the light emitting elements LD, an alignment signal is applied to the alignment electrodes ALE (or alignment wiring) of the pixels PXL, whereby an electric field is formed between the alignment electrodes ALE, thereby aligning the light emitting elements LD. After the alignment of the light emitting elements LD is completed, the solvent may be removed by a drying process, etc.

[0159] The first pixel electrode ELT1 (also referred to as "first electrode") may be disposed on the first end EP1 of the first light-emitting element LD1 and electrically connected to the first end EP1 of the first light-emitting element LD1. For example, the first pixel electrode ELT1 may be disposed (e.g., directly disposed) on the first end EP1 of the first light-emitting element LD1 so as to be in contact with the first end EP1 of the first light-emitting element LD1.

[0160] In one embodiment, the first pixel electrode ELT1 may overlap the first alignment electrode ALE1 and may be electrically connected to the first alignment electrode ALE1 via the fourth contact portion CNT4. For example, the first pixel electrode ELT1 may be electrically connected to the pixel circuit PXC and / or the first power line PL1 via the first alignment electrode ALE1. In another embodiment, the first pixel electrode ELT1 may be electrically connected to the pixel circuit PXC and / or the first power line PL1 without via the first alignment electrode ALE1.

[0161] The third pixel electrode ELT3 may be disposed on the second end EP2 of the first light emitting element LD1 and the first end EP1 of the second light emitting element LD2 and electrically connected to the second end EP2 of the first light emitting element LD1 and the first end EP1 of the second light emitting element LD2. For example, the third pixel electrode ELT3 may be disposed (e.g., directly disposed) on the second end EP2 of the first light emitting element LD1 and the first end EP1 of the second light emitting element LD2 so as to contact the second end EP2 of the first light emitting element LD1 and the first end EP1 of the second light emitting element LD2. The third pixel electrode ELT3 may be an intermediate electrode for electrically connecting the first light emitting element LD1 and the second light emitting element LD2. In one embodiment, the third pixel electrode ELT3 may overlap a portion of each of the first and second alignment electrodes ALE1 and ALE2, but the embodiment is not limited thereto.

[0162] The second pixel electrode ELT2 (also referred to as "second electrode") may be disposed on the second end EP2 of the second light-emitting element LD2 and electrically connected to the second end EP2 of the second light-emitting element LD2. For example, the second pixel electrode ELT2 may be disposed (e.g., directly disposed) on the second end EP2 of the second light-emitting element LD2 so as to be in contact with the second end EP2 of the second light-emitting element LD2.

[0163] In one embodiment, the second pixel electrode ELT2 may overlap the third alignment electrode ALE3 and may be electrically connected to the third alignment electrode ALE3 via the fifth contact part CNT5. For example, the second pixel electrode ELT2 may be electrically connected to the second power line PL2 via the third alignment electrode ALE3. In another embodiment, the second pixel electrode ELT2 may be electrically connected to the second power line PL2 without via the third alignment electrode ALE3.

[0164] The pixel electrodes ELT (e.g., the first pixel electrode ELT1, the second pixel electrode ELT2, and the third pixel electrode ELT3) may be formed separately in the respective light-emitting areas EA. In one embodiment, at least one pixel electrode ELT may extend from the respective light-emitting areas EA to the non-light-emitting area NEA and / or the isolation area SPA. For example, the first pixel electrode ELT1 and the second pixel electrode ELT2 may extend from the respective light-emitting areas EA to the non-light-emitting area NEA and the isolation area SPA and may be electrically connected to the first alignment electrode ALE1 and the third alignment electrode ALE3, respectively, in the isolation area SPA. The third pixel electrode ELT3 may be formed only in the respective light-emitting areas EA, or may be partially located in the non-light-emitting area NEA. The position, size, shape, and relative arrangement structure of the pixel electrodes ELT, and / or the positions of the fourth and fifth contact portions CNT4 and CNT5 may be variously modified depending on the embodiment.

[0165] The bank pattern layer BNP (also referred to as a "pattern layer" or a "wall pattern layer") may be disposed below the alignment electrode ALE so as to overlap a portion of the alignment electrode ALE. For example, the bank pattern layer BNP may include a first bank pattern layer BNP1, ​​a second bank pattern layer BNP2, and a third bank pattern layer BNP3, which overlap a portion of the first alignment electrode ALE1, the second alignment electrode ALE2, and the third alignment electrode ALE3, respectively. In one embodiment, at least one bank pattern layer BNP may extend into the non-light-emitting area NEA around the light-emitting area EA, but the embodiment is not limited thereto.

[0166] The bank pattern layer BNP allows a portion of the alignment electrode ALE to protrude upward (e.g., in the third direction DR3) of the pixel PXL, thereby easily controlling the region in which the light emitting element LD is aligned, and reflecting light emitted from the light emitting element LD toward the bank pattern layer BNP (e.g., the bank pattern layer BNP arranged around the corresponding light emitting element LD) toward the upward direction of the pixel PXL, thereby increasing the light efficiency of the pixel PXL.

[0167] In one embodiment, at least two adjacent pixels PXL may share at least one bank pattern layer BNP. For example, the second bank pattern layer BNP2 may be formed integrally with the third bank pattern layer BNP3 of the pixel PXL adjacent in the first direction DR1 (e.g., the adjacent pixel on the right). For example, the third bank pattern layer BNP2 may be formed integrally with the second bank pattern layer BNP2 of another pixel adjacent in the first direction DR1 (e.g., the adjacent pixel on the left). The position, structure, number, and / or shape of the bank pattern layer BNP may be variously modified depending on the embodiment.

[0168] A non-light-emitting area NEA may be disposed around each of the light-emitting areas EA and / or each of the separation areas SPA. A first bank BNK1 may be disposed in the non-light-emitting area NEA.

[0169] The first bank BNK1 may include first openings OPA1 corresponding to each light-emitting area EA and may surround the light-emitting area EA. For example, the first bank BNK1 may include second openings OPA2 corresponding to the isolation area SPA and may surround the isolation area SPA. For example, the first bank BNK1 may include openings OPA corresponding to each light-emitting area EA and each isolation area SPA.

[0170] The first bank BNK1 may include at least one light-blocking and / or reflective material, such as at least one black matrix material and / or a color filter material of a specific color, thereby preventing or minimizing light leakage between adjacent pixels PXL.

[0171] The first bank BNK1 can define each light-emitting area EA to which the light-emitting element LD is to be supplied in the step of supplying the light-emitting element LD to each pixel PXL. For example, the first bank BNK1 separates and partitions the light-emitting areas EA of the pixel PXL, allowing a desired type and / or amount of light-emitting element mixture to be supplied to each light-emitting area EA.

[0172] In one embodiment, the first bank BNK1 may include a hydrophobic surface. For example, the first bank BNK1 itself may be formed as a hydrophobic pattern layer using a hydrophobic material, or a hydrophobic coating made of a hydrophobic material may be formed on the first bank BNK1 to form the first bank BNK1 with a hydrophobic surface. For example, the first bank BNK1 may be formed using a hydrophobic organic material with a large contact angle, such as polyacrylate, thereby forming the first bank BNK1 as a hydrophobic pattern layer. This allows the light emitting element mixture to flow stably into the light emitting region EA.

[0173] Fig. 10 is a schematic cross-sectional view showing one embodiment of the display device of Fig. 7. For example, Fig. 10 shows one embodiment of the cross section of the display device DD, with the cross section of the pixel PXL taken along line II-II' in Fig. 9 at the center.

[0174] 1 to 10, the display device DD may include a base layer BSL, a circuit layer PCL, and a display layer DPL. The circuit layer PCL and the display layer DPL may be provided on the base layer BSL so as to overlap each other. For example, the circuit layer PCL and the display layer DPL may be sequentially disposed on one surface of the base layer BSL.

[0175] The display device DD may further include a color filter layer CFL and / or an encapsulation layer ENC (or a protective layer) disposed on the display layer DPL. In one embodiment, the color filter layer CFL and / or the encapsulation layer ENC may be formed (e.g., directly formed) on one surface of the base layer BSL on which the circuit layer PCL and the display layer DPL are formed, but the embodiment is not limited thereto.

[0176] The base layer BSL may be formed of a substrate or film of a rigid or flexible material. In one embodiment, the base layer BSL may include at least one insulating material, transparent or opaque, and may have a single layer or multi-layer structure.

[0177] The circuit layer PCL may be provided on one surface of the base layer BSL. The circuit layer PCL may include circuit elements that constitute the pixel circuit PXC of each pixel PXL. For example, circuit elements (e.g., a transistor M and a capacitor Cst that constitute each pixel circuit PXC) may be formed in each pixel region of the circuit layer PCL.

[0178] FIG. 10 exemplarily illustrates one of the transistors M (for example, the first transistor M1 including the lower metal layer BML) provided in each pixel circuit PXC as an example of a circuit element that can be arranged in the circuit layer PCL.

[0179] For example, the circuit layer PCL may include various signal lines and power lines connected to the pixels PXL. For example, the circuit layer PCL may include scan lines SL, control lines SSL, data lines DL, sensing lines SENL, and / or first and second power lines PL1, PL2 connected to the pixels PXL. FIG. 10 exemplarily illustrates wiring LI located in the same layer (e.g., the first conductive layer) as the lower metal layer BML as an example of wiring that may be arranged in the circuit layer PCL. Each wiring LI may be either a signal line or a power line connected to the pixels PXL. In one embodiment, at least one signal line and / or power line may also be arranged in another layer of the circuit layer PCL.

[0180] For example, the circuit layer PCL may include an insulating layer, such as a buffer layer BFL, a gate insulating layer GI, an interlayer insulating layer ILD, and / or a passivation layer PSV, which are sequentially disposed on one surface of the base layer BSL.

[0181] The circuit layer PCL may be disposed on the base layer BSL and may include a first conductive layer including a lower metal layer BML of the first transistor M1. For example, the first conductive layer may be disposed between the base layer BSL and the buffer layer BFL and may include the lower metal layer BML of the first transistor M1 provided in each pixel circuit PXC. The lower metal layer BML of the first transistor M1 may overlap the gate electrode GE and the semiconductor pattern layer SCP of the first transistor M1.

[0182] For example, the first conductive layer may further include at least one wiring LI. For example, the first conductive layer may include at least some of the wirings LI extending in the second direction DR2 in the display area DA. For example, the first conductive layer may include sensing lines SENL and data lines DL connected to the pixels PXL, and first power supply lines PL1 (or first sub-power supply lines in the second direction constituting the mesh-type first power supply lines PL1) and / or second power supply lines PL2 (or second sub-power supply lines in the second direction constituting the mesh-type second power supply lines PL2).

[0183] A buffer layer BFL may be disposed on one surface of the base layer BSL including the first conductive layer, The buffer layer BFL can prevent impurities from diffusing (or penetrating) into each circuit element.

[0184] A semiconductor layer may be disposed on the buffer layer BFL. The semiconductor layer may include a semiconductor pattern layer SCP of each transistor M. The semiconductor pattern layer SCP may include a channel region overlapping with the gate electrode GE of the corresponding transistor M, and first and second conductive regions (e.g., source and drain regions) disposed on sides (e.g., opposing sides) of the channel region. The semiconductor pattern layer SCP may be a semiconductor pattern layer made of polysilicon, amorphous silicon, an oxide semiconductor, or the like.

[0185] A gate insulating layer GI may be disposed on the semiconductor layer, for example, a second conductive layer may be disposed on the gate insulating layer GI.

[0186] The second conductive layer may include a gate electrode GE of each transistor M. For example, the second conductive layer may further include one electrode of a capacitor Cst provided in the pixel circuit PXC and / or a bridge pattern layer, etc. For example, if at least one power supply line and / or signal line arranged in the display area DA is configured in multiple layers, the second conductive layer may further include at least one conductive pattern layer constituting the at least one power supply line and / or signal line.

[0187] An interlayer dielectric layer ILD may be disposed on the second conductive layer, for example, a third conductive layer may be disposed on the interlayer dielectric layer ILD.

[0188] The third conductive layer may include a source electrode SE and a drain electrode DE of each transistor M. The source electrode SE may be connected to one region (e.g., a source region) of the semiconductor pattern layer SCP included in the corresponding transistor M through at least one contact hole CH, and the drain electrode DE may be connected to another region (e.g., a drain region) of the semiconductor pattern layer SCP included in the corresponding transistor M through at least one other contact hole CH. For example, the third conductive layer may further include another electrode of the capacitor Cst included in the pixel circuit PXC, predetermined wiring, and / or a bridge pattern layer. For example, the third conductive layer may include at least some of the wirings extending in the first direction DR1 in the display area DA. For example, the third conductive layer may include the scan line SL, the control line SSL, the first power line PL1 (or the first sub-power line in the first direction constituting the mesh-type first power line PL1), and / or the second power line PL2 (or the second sub-power line in the first direction constituting the mesh-type second power line PL2) connected to the pixel PXL. For example, when at least one power line and / or signal line arranged in the display area DA is configured in multiple layers, the third conductive layer may further include at least one conductive pattern layer that configures the at least one power line and / or signal line.

[0189] Each of the conductive pattern layers, electrodes, and / or wirings constituting the first to third conductive layers can be conductive by containing at least one conductive material, and the material is not limited thereto. For example, each of the conductive pattern layers, electrodes, and / or wirings constituting the first to third conductive layers may contain one or more metals selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (C), iridium (Ir), chromium (Cr), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu), and may contain, for example, various types of conductive materials.

[0190] A passivation layer PSV may be disposed on the third conductive layer. Each of the buffer layer BFL, gate insulating layer GI, interlayer insulating layer ILD, and passivation layer PSV may be a single layer or multiple layers and may include at least one inorganic and / or organic material. In one embodiment, each of the buffer layer BFL, gate insulating layer GI, and interlayer insulating layer ILD may include various inorganic materials, such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiOxNy). In one embodiment, the passivation layer PSV may include at least one organic layer containing at least one organic material. In one embodiment, the passivation layer PSV may be disposed in at least the display area DA (or over the entire display area DA) and may planarize the surface of the circuit layer PCL.

[0191] A display layer DPL may be disposed on the passivation layer PSV.

[0192] The display layer DPL may include a light-emitting unit EMU of each pixel PXL. For example, the display layer DPL may include an alignment electrode ALE, at least one light-emitting element LD, and a pixel electrode ELT arranged in a light-emitting area EA of each pixel PXL. In one embodiment, each light-emitting unit EMU may include a light-emitting element LD.

[0193] For example, the display layer DPL may further include an insulating pattern layer and / or an insulating layer sequentially arranged on one surface of the base layer BSL on which the circuit layer PCL is formed. For example, the display layer DPL may include a bank pattern layer BNP, a first insulating layer INS1, a first bank BNK1, a second insulating layer INS2, a third insulating layer INS3, a second bank BNK2, and / or a fourth insulating layer INS4. For example, the display layer DPL may selectively further include a light conversion layer CCL.

[0194] The bank pattern layer BNP may be disposed on the passivation layer PSV. The bank pattern layer BNP may be disposed below the alignment electrodes ALE so as to overlap with a portion of each of the alignment electrodes ALE.

[0195] The bank pattern layer BNP allows the alignment electrode ALE to protrude from around the light emitting element LD toward the upper side of the pixel PXL (e.g., in the third direction DR3). The bank pattern layer BNP and the alignment electrode ALE thereon can form a reflective protruding pattern layer around the light emitting element LD, thereby improving the light efficiency of the pixel PXL.

[0196] The bank pattern layer BNP may be a single layer or multiple layer insulating pattern layer containing inorganic and / or organic materials. The alignment electrodes ALE may be disposed on the bank pattern layer BNP.

[0197] The alignment electrodes ALE may include at least one conductive material. For example, each alignment electrode ALE may be made of at least one metal or alloy containing the metal among various metal materials including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), molybdenum (Mo), copper (Cu), etc., ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), ITZO (Indium Tin Zinc Oxide), ZnO (Zinc Oxide), AZO (Aluminum doped Zinc Oxide), GZO (Gallium doped Zinc Oxide), ZTO (Zinc Tin Oxide), GTO (Gallium Tin Oxide), and FTO (Fluorine doped Tin Oxide). The ALE may include at least one conductive material selected from the group consisting of a conductive oxide such as poly(3,4-ethylenedioxythiophene) (PEDOT) and a conductive polymer such as poly(3,4-ethylenedioxythiophene) (PEDOT), but examples are not limited thereto. For example, the ALE may include other conductive materials such as carbon nanotubes and graphene. For example, the ALE may be conductive by including at least one of various conductive materials. For example, the ALE may include the same or different conductive materials.

[0198] Each alignment electrode ALE may be composed of a single layer or multiple layers. For example, each alignment electrode ALE may include a reflective electrode layer containing a reflective conductive material (e.g., metal), and may be composed of a single layer or multiple layers of electrodes.

[0199] A first insulating layer INS1 may be disposed on the alignment electrodes ALE. In one embodiment, the first insulating layer INS1 may include contact holes for connecting at least one of the alignment electrodes ALE to any one of the pixel electrodes ELT. For example, the first insulating layer INS1 may include contact holes for forming the fourth and fifth contact portions CNT4 and CNT5 of FIG. 9.

[0200] The first insulating layer INS1 may be composed of a single layer or multiple layers and may include inorganic and / or organic materials. In one embodiment, the first insulating layer INS1 may include at least one inorganic material including silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiOxNy).

[0201] By covering the alignment electrode ALE with the first insulating layer INS1, damage to the alignment electrode ALE in subsequent processes can be prevented or minimized, for example, short-circuit defects caused by improper connection between the alignment electrode ALE and the light emitting element LD can be prevented or minimized.

[0202] A first bank BNK1 may be disposed in the display area DA where the alignment electrodes ALE and the first insulating layer INS1 are formed. The first bank BNK1 may be formed in the non-light-emitting area NEA so as to surround the light-emitting area EA of each pixel PXL.

[0203] A light-emitting element LD may be provided in each light-emitting area EA surrounded by the first bank BNK1. The light-emitting element LD may be aligned between the alignment electrodes ALE by an alignment signal applied to the alignment electrodes ALE (or the alignment wiring before being separated into the alignment electrodes ALE of each pixel PXL). For example, if the pixel PXL includes a first alignment electrode ALE1 located in the center and second and third alignment electrodes ALE2, ALE3 located on sides (e.g., opposite sides) of the first alignment electrode ALE1, at least one first light-emitting element LD1 may be aligned between the first alignment electrode ALE1 and the second alignment electrode ALE2, and at least one second light-emitting element LD2 may be aligned between the first alignment electrode ALE1 and the third alignment electrode ALE3.

[0204] A second insulating layer INS2 may be disposed on a portion of the light emitting element LD. In one embodiment, the second insulating layer INS2 may be disposed on a portion including a central portion of the light emitting element LD so as to expose the first and second ends EP1 and EP2 of the light emitting element LD aligned with the light emitting area EA of the corresponding pixel PXL. In another embodiment, the second insulating layer INS2 may be formed (e.g., formed over the entire surface) in the display area DA including a plurality of pixel areas, and may include contact holes exposing the first and second ends EP1 and EP2 of each of the light emitting elements LD. Forming the second insulating layer INS2 on the light emitting element LD allows the light emitting element LD to be stably fixed.

[0205] The second insulating layer INS2 may be composed of a single layer or multiple layers and may include at least one inorganic and / or organic material. For example, the second insulating layer INS2 may include various organic and / or inorganic materials, including silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), aluminum oxide (AlxOy), photoresist material, etc.

[0206] Different pixel electrodes ELT may be disposed and / or formed on both ends of the light emitting element LD that are not covered by the second insulating layer INS2, for example, on the first and second ends EP1 and EP2. For example, a first pixel electrode ELT1 may be disposed on the first end EP1 of the first light emitting element LD1, and a portion of a third pixel electrode ELT3 may be disposed on the second end EP2 of the first light emitting element LD1. Another portion of the third pixel electrode ELT3 may be disposed on the first end EP1 of the second light emitting element LD2, and a second pixel electrode ELT2 may be disposed on the second end EP2 of the second light emitting element LD2.

[0207] In one embodiment, the first pixel electrode ELT1 may be electrically connected to the first alignment electrode ALE1 through at least one contact portion (e.g., the fourth contact portion CNT4 in FIG. 9). For example, the second pixel electrode ELT2 may be electrically connected to the third alignment electrode ALE3 through at least one contact portion (e.g., the fifth contact portion CNT5 in FIG. 9). The third pixel electrode ELT3 may electrically connect at least one first light-emitting element LD1 and at least one second light-emitting element LD2 to each other.

[0208] In one embodiment, the first alignment electrode ALE1 of each pixel PXL may be electrically connected to the first transistor M1 of the corresponding pixel PXL through at least one contact portion (e.g., the first contact portion CNT1 in FIG. 9). For example, the second and third alignment electrodes ALE2 and ALE3 may each be electrically connected to the second power line PL2 through at least one contact portion (e.g., the second contact portion CNT2 and the third contact portion CNT3 in FIG. 9).

[0209] The first pixel electrode ELT1 may be disposed on the first alignment electrode ALE1 to overlap a portion of the first alignment electrode ALE1, and the second pixel electrode ELT2 may be disposed on the third alignment electrode ALE3 to overlap a portion of the third alignment electrode ALE3. The third pixel electrode ELT3 may be disposed on the first alignment electrode ALE1 and the second alignment electrode ALE2 to overlap another portion of the first alignment electrode ALE1 and the second alignment electrode ALE2.

[0210] In one embodiment, the first pixel electrode ELT1 may be electrically connected to the first end EP1 of the first light-emitting element LD1, the second pixel electrode ELT2 may be electrically connected to the second end EP2 of the second light-emitting element LD2, and the third pixel electrode ELT3 may be electrically connected to the second end EP2 of the first light-emitting element LD1 and the first end EP1 of the second light-emitting element LD2.

[0211] The first pixel electrode ELT1, the second pixel electrode ELT2, and / or the third pixel electrode ELT3 may be formed in the same or different layers. In one embodiment, the first and second pixel electrodes ELT1 and ELT2 may be formed in the same layer, and the third pixel electrode ELT3 may be formed in a different layer from the first and second pixel electrodes ELT1 and ELT2. For example, the first and second pixel electrodes ELT1 and ELT2 and the third pixel electrode ELT3 may be disposed in different layers with the third insulating layer INS3 sandwiched therebetween. In other embodiments, the first to third pixel electrodes ELT1 to ELT3 may all be formed in the same layer. For example, the pixel PXL may not include the third insulating layer INS3. The relative positions and / or formation order of the pixel electrodes ELT may vary depending on the embodiment.

[0212] When each pixel PXL includes the light-emitting units EMU in a parallel structure other than a series structure or includes a single light-emitting element LD, the pixel PXL does not need to include the third pixel electrode ELT3. For example, the first pixel electrode ELT1 may be disposed on the first end EP1 of the light-emitting element LD, and the second pixel electrode ELT2 may be disposed on the second end EP2 of the light-emitting element LD.

[0213] The pixel electrode ELT may include at least one conductive material. In one embodiment, the pixel electrode ELT may include a transparent conductive material so that light emitted from the light emitting element LD can be transmitted therethrough.

[0214] In one embodiment, the display device DD may include a light conversion layer CCL disposed on the light emitting portion EMU of each pixel PXL. For example, the light conversion layer CCL may be provided in each light emitting area EA so as to be located above the light emitting element LD of each pixel PXL.

[0215] For example, the display device DD may further include a second bank BNK2 arranged in the non-light-emitting area NEA so as to overlap the first bank BNK1. The second bank BNK2 may define (or partition) each light-emitting area EA in which the light conversion layer CCL is formed. In one embodiment, the second bank BNK2 may be integrated with the first bank BNK1.

[0216] The second bank BNK2 may include a light-blocking and / or reflective material, including a black matrix material, etc. The second bank BNK2 may include the same or a different material as the first bank BNK1.

[0217] The light conversion layer CCL may include at least one of wavelength conversion particles (or color conversion particles) for converting the wavelength and / or color of light emitted from the light emitting element LD and light scattering particles SCT for scattering the light emitted from the light emitting element LD to increase the light output efficiency of the pixel PXL. For example, each light conversion layer CCL may be disposed on each light emitting unit EMU. Each light conversion layer CCL may include at least one type of wavelength conversion particles such as quantum dots QDs (e.g., red, green, and / or blue quantum dots) and / or light scattering particles SCT.

[0218] For example, if any one pixel PXL is set as a red (or green) pixel and a blue light-emitting element LD is provided in the light-emitting unit EMU of the pixel PXL, a light conversion layer CCL including red quantum dots (or green quantum dots) QDs for converting blue light into red light (or green light) may be disposed on the light-emitting unit EMU of the pixel PXL. For example, the light conversion layer CCL may further include light-scattering particles SCT.

[0219] A fourth insulating layer INS4 may be formed on one surface of the base layer BSL including the light emitting unit EMU and / or the light conversion layer CCL of the pixel PXL.

[0220] In one embodiment, the fourth insulating layer INS4 may include at least one organic layer. The fourth insulating layer INS4 may be disposed in at least the display area DA (or disposed over the entire area) and may substantially planarize the surface of the display layer DPL. For example, the fourth insulating layer INS4 may protect the light-emitting unit EMU and / or the light conversion layer CCL of the pixel PXL.

[0221] A color filter layer CFL may be disposed on the fourth insulating layer INS4.

[0222] The color filter layer CFL may include color filters CF corresponding to the colors of the pixels PXL. For example, the color filter layer CFL may include a first color filter CF1 disposed in the light-emitting area EA of the first color pixel PXL1, a second color filter CF2 disposed in the light-emitting area EA of the second color pixel PXL2, and a third color filter CF disposed in the light-emitting area EA of the third color pixel PXL3. Each color filter CF may be disposed on the fourth insulating layer INS4 to overlap the light-emitting unit EMU of the corresponding pixel PXL.

[0223] In one embodiment, the first, second, and third color filters CF1, CF2, and CF3 may overlap each other in the non-light-emitting area NEA. In another embodiment, the first, second, and third color filters CF1, CF2, and CF3 may be separated from each other over the light-emitting area EA of each pixel PXL, and a separate light-blocking pattern layer may be disposed between the first, second, and third color filters CF1, CF2, and CF3.

[0224] An encapsulation layer ENC may be disposed on the color filter layer CFL. The encapsulation layer ENC may include a fifth insulating layer INS5. In one embodiment, the fifth insulating layer INS5 may include at least one organic layer containing at least one organic material, and may be formed as a single layer or multiple layers. The fifth insulating layer INS5 may be formed (e.g., formed over the entire surface) at least in the display area DA to cover the circuit layer PCL, the display layer DPL, and / or the color filter layer CFL, and may planarize the surface of the display device DD.

[0225] Figure 11 is a schematic cross-sectional view showing an embodiment in which a region of Figure 10 is enlarged. For example, Figure 11 is a schematic cross-sectional view showing an enlarged region of a pixel PXL (e.g., the AR region of Figure 10) with the light-emitting element LD at the center. Figure 11 shows an embodiment in which the pixel PXL of Figure 10 includes the light-emitting element LD according to the embodiments of Figures 1 and 2. In describing the embodiment of Figure 11, for convenience of explanation, detailed description of configurations similar or identical to those of the above-mentioned embodiments will be omitted.

[0226] 1, 2, 10, and 11, the light emitting element LD may be disposed on a first insulating layer INS1 (or a base layer). The light emitting element LD may include a first end EP1 and a second end EP2 in a direction parallel to the top surface of the first insulating layer INS1.

[0227] The light-emitting element LD may include a first semiconductor layer SCL1, an emission layer EML, a second semiconductor layer SCL2, and an electrode layer ETL, which are sequentially arranged in a direction from the second end EP2 to the first end EP1. For example, each light-emitting element LD may include an insulating coating INF that covers side surfaces of the first semiconductor layer SCL1, the emission layer EML, the second semiconductor layer SCL2, and the electrode layer ETL.

[0228] The second insulating layer INS2 may be disposed on a portion of the light emitting element LD. The second insulating layer INS2 may be disposed on a portion including a central portion of the light emitting element LD, and may expose the first and second ends EP1 and EP2 of the light emitting element LD.

[0229] The first pixel electrode ELT1 covers the first end EP1 of the light-emitting element LD, contacts the first end EP1 of the light-emitting element LD where the second insulating layer INS2 is not provided and the side of the light-emitting element LD, and may be electrically connected to the electrode layer ETL of the light-emitting element LD.

[0230] The third pixel electrode ELT3 (or the second pixel electrode) covers the second end EP2 of the light-emitting element LD, contacts the second end EP2 of the light-emitting element LD where the second insulating layer INS2 is not provided and the side of the light-emitting element LD, and may be electrically connected to the first semiconductor layer SCL1 of the light-emitting element LD.

[0231] The first pixel electrode ELT1 may overlap not only the electrode layer ETL of the light emitting element LD but also the second semiconductor layer SCL2, the emission layer EML, and the first semiconductor layer SCL1 in the third direction DR3. An electric field may be formed between the first pixel electrode ELT1 and the first semiconductor layer SCL1 (and the emission layer EML, etc.) that overlap each other in the third direction DR3. For example, to drive the light emitting element LD, a driving voltage may be periodically applied to the first pixel electrode ELT1 and a power supply voltage may be applied to the third pixel electrode ELT3, forming an electric field on a side surface of the light emitting element LD that contacts the first pixel electrode ELT1. For example, the electric field may cause electrons or holes to concentrate on the side surface of the light emitting element LD, reducing the driving current flowing from the first end EP1 to the second end EP2 of the light emitting element LD and the brightness corresponding to the driving current. For example, the characteristics of the light emitting element LD may be degraded.

[0232] As described with reference to FIGS. 3 to 6, the light emitting devices LD_1, LD_2, and LD_3 according to the embodiments further include shielding layers SHL, SHL_1, and SHL_2, which can shield or suppress the electric field.

[0233] Figure 12 is a schematic cross-sectional view showing an embodiment in which one region of Figure 10 is enlarged. Figure 12 shows an embodiment in which the pixel PXL of Figure 10 includes the light-emitting element LD_1 according to the embodiment of Figure 3. In describing the embodiment of Figure 12, for convenience of explanation, detailed description of configurations similar or the same as those of the above-described embodiments will be omitted.

[0234] 1 to 4 and 10 to 12, the light emitting device LD_1 further includes a shielding layer SHL (or a shielding film), and the shielding layer SHL may be disposed inside the insulating coating INF.

[0235] The shielding layer SHL may overlap the first pixel electrode ELT1 in the third direction DR3. The shielding layer SHL may be disposed between the first pixel electrode ELT1 and the light emitting stack structure of the light emitting element LD_1 (e.g., the first semiconductor layer SCL1, the light emitting layer EML, and the second semiconductor layer SCL2 excluding the insulating coating film INF). The shielding layer SHL may be spaced apart from the first pixel electrode ETL1 and in a floating state.

[0236] The shielding layer SHL includes a conductive material and can shield or suppress an electric field formed between the first pixel electrode ELT1 and the light emitting stack structure of the light emitting device LD_1, thereby preventing electrons or holes from concentrating on the side surfaces of the light emitting device LD_1 and reducing the driving current flowing through the light emitting device LD_1, thereby preventing a deterioration in the characteristics of the light emitting device LD_1.

[0237] In one embodiment, the light transmittance of the shielding layer SHL may be about 70% or more. For example, light L emitted from the emitting layer EML may travel in a third direction DR3 through the shielding layer SHL. The light L emitted from the emitting layer EML may also travel in the horizontal direction (or the first direction DR1 and the direction opposite to the first direction DR1) through the first and second ends EP1 and EP2.

[0238] Figure 13 is a schematic cross-sectional view showing an embodiment in which one region of Figure 10 is enlarged. Figure 13 shows an embodiment in which the pixel PXL of Figure 10 includes the light-emitting element LD_2 according to the embodiment of Figure 5. In describing the embodiment of Figure 13, for convenience of explanation, detailed description of configurations similar or the same as those of the above-described embodiments will be omitted.

[0239] 1 to 5 and 10 to 13, the light emitting device LD_2 may further include a shielding layer SHL_1.

[0240] The shielding layer SHL_1 may overlap the first pixel electrode ELT1 in the third direction DR3. For example, the shielding layer SHL_1 may overlap the third pixel electrode ELT3 in the third direction DR3. The shielding layer SHL may be disposed between the first pixel electrode ELT1 and the light emitting stack of the light emitting element LD_2, and between the third pixel electrode ELT3 and the light emitting stack of the light emitting element LD_2.

[0241] The shielding layer SHL_1 is covered with an insulating film INF, and the shielding layer SHL_1 may be separated from the first pixel electrode ETL1 and the third pixel electrode ELT3 and may be in a floating state.

[0242] The shielding layer SHL_1 can shield or suppress an electric field that may be formed between the first pixel electrode ELT1 and the light emitting stack structure of the light emitting element LD_2. For example, the shielding layer SHL_1 can also shield or suppress an electric field that may be formed between the third pixel electrode ELT3 and the light emitting stack structure of the light emitting element LD_2. Therefore, electrons or holes do not concentrate on the side of the light emitting element LD_2, and the driving current flowing through the light emitting element LD_2 does not decrease. For example, deterioration of the characteristics of the light emitting element LD_2 can be prevented or minimized.

[0243] In one embodiment, the light reflectivity of the shielding layer SHL_1 may be about 90% or more. For example, light L emitted from the emitting layer EML is reflected (or totally reflected) by the shielding layer SHL_1 and can proceed (or be transmitted) to the outside of the light emitting element LD_2 through the first end EP1 and the second end EP2. For example, the light output efficiency of the light emitting element LD_2 through the first end EP1 and the second end EP2 can be improved.

[0244] Figure 14 is a schematic cross-sectional view showing an embodiment in which one region of Figure 10 is enlarged. Figure 14 shows an embodiment in which the pixel PXL of Figure 10 includes the light-emitting element LD_3 according to the embodiment of Figure 6. In describing the embodiment of Figure 14, for convenience of explanation, detailed description of configurations similar or the same as those of the above-described embodiments will be omitted.

[0245] 1 to 6 and 10 to 14, the light emitting element LD_3 may include a first shielding layer SHL1 (or first shielding layer) and a second shielding layer SHL2 (or second shielding layer) spaced apart from each other. For example, light L emitted from the light emitting layer EML may be reflected (or totally reflected) by the first shielding layer SHL1 and the second shielding layer SHL2 and may travel (or be transmitted) to the outside of the light emitting element LD_3 through the first end EP1 and the second end EP2.

[0246] The first shielding layer SHL1 may overlap the first pixel electrode ELT1 in the third direction DR3. The first shielding layer SHL1 may be disposed between the first pixel electrode ELT1 and the light-emitting stack structure of the light-emitting element LD_3. The first shielding layer SHL1 may be electrically connected to the first pixel electrode ELT1.

[0247] The second shielding layer SHL2 may overlap the third pixel electrode ELT3 in the third direction DR3. The second shielding layer SHL2 may be disposed between the third pixel electrode ELT3 and the light-emitting stack of the light-emitting element LD_3. The second shielding layer SHL2 may be electrically connected to the third pixel electrode ELT3.

[0248] The first shielding layer SHL1 can shield or suppress an electric field that may be formed between the first pixel electrode ELT1 and the light emitting stack structure of the light emitting element LD_3. The second shielding layer SHL2 can shield or suppress an electric field that may be formed between the third pixel electrode ELT3 and the light emitting stack structure of the light emitting element LD_3. Therefore, deterioration of the characteristics of the light emitting element LD_3 can be prevented or minimized.

[0249] In one embodiment, at least one of the first shielding layer SHL1 and the second shielding layer SHL2 may be electrically connected to the ground (or a ground electrode). Referring to Figure 8, for example, a ground voltage may be periodically applied to the sensing line SENL to turn on the third transistor M3. As another example, a ground voltage may be periodically applied to the second power line PL2.

[0250] Figure 15 is a schematic equivalent circuit diagram showing one embodiment of a pixel included in the display device of Figure 7. In describing the embodiment of Figure 15, for convenience of explanation, detailed description of configurations similar or the same as those of the embodiment of Figure 8 will be omitted.

[0251] 8, 9, 14, and 15, the pixel PXL may include a light emitting element LD_3 according to the embodiment of FIG. 6. For example, the pixel PXL may further include a fourth transistor M4 and a fifth transistor M5. The fourth transistor M4 and the fifth transistor M5 may be included in the pixel circuit PXC.

[0252] The fourth transistor M4 may be connected between the second node N2 and the third power line PL3. Here, the third power line PL3 may be connected to ground, or a ground voltage GND may be applied to the third power line PL3. The gate electrode of the fourth transistor M4 may be connected to the control line CL. When a gate-on voltage is supplied from the control line CL, the fourth transistor M4 may be turned on to connect the third power line PL3 to the second node N2. For example, the first shielding layer SHL1 (FIG. 14) of the light emitting element LD_3 in the first series stage may be connected to ground via the second node N2.

[0253] The fifth transistor M5 may be connected between the third node N3 and the third power line PL3. Here, the third node N3 is a node where the first and second series stages are connected and may correspond to the third pixel electrode ETL3 in FIG. 9. The gate electrode of the fifth transistor M5 may be connected to the control line CL. The fifth transistor M5 may be turned on when a gate-on voltage is supplied from the control line CL to connect the third power line PL3 to the third node N3. For example, the second shielding layer SHL2 (FIG. 14) of the light emitting element LD_3 in the first series stage and the first shielding layer SHL1 (FIG. 14) of the light emitting element LD_3 in the second series stage may be connected to ground via the third node N3 (or the third pixel electrode ELT3).

[0254] The second shielding layer SHL2 (FIG. 14) of the light emitting element LD_3 in the second series stage may be connected to ground via the second power line PL2. As another example, the second shielding layer SHL2 (FIG. 14) of the light emitting element LD_3 in the second series stage may be connected to ground via a separate transistor connected to the second power line PL2.

[0255] As described above, the pixel PXL may further include fourth and fifth transistors M4 and M5 for connecting the first and second shielding layers SHL1 and SHL2 of the light emitting element LD_3 to ground.

[0256] Figures 16, 17, and 18 are schematic cross-sectional views showing one embodiment of the pixel of Figure 15. Figures 16, 17, and 18 show an embodiment in which the pixel PXL of Figure 10 includes the light-emitting element LD according to the embodiment of Figures 1 and 2. However, the embodiment is not limited thereto, and the pixel PXL may include one of the light-emitting elements LD_1, LD_2, and LD_3 according to the embodiments of Figures 3 to 6. In describing the embodiments of Figures 16, 17, and 18, detailed descriptions of configurations similar or identical to those of the above-mentioned embodiments will be omitted for the sake of convenience.

[0257] 1 to 11, 16, and 17, the third shielding layer SHL3 may be disposed on the side surface (or circumferential surface) of the light-emitting element LD, or between the light-emitting element LD and the second insulating layer INS2.

[0258] The third shielding layer SHL3 may overlap the light emitting layer EML of the light emitting element LD in the third direction DR3. For example, the third shielding layer SHL3 may overlap the first semiconductor layer SCL1 in the third direction DR3. According to an embodiment, the third shielding layer SHL3 may also overlap the second semiconductor layer SCL2 in the third direction DR3.

[0259] The third shielding layer SHL3 may be disposed between the first pixel electrode ELT1 and the light-emitting element LD. For example, as shown in Fig. 17, when the first pixel electrode ELT1 is also disposed on the second insulating layer INS2, the third shielding layer SHL3 may be disposed between the first pixel electrode ELT1 and the light-emitting element LD with respect to the third direction DR3.

[0260] The third shielding layer SHL3 may be spaced apart from the first pixel electrode ETL1. To electrically separate (or insulate) the first pixel electrode ELT1 and the third shielding layer SHL3, the second insulating layer INS2 covering the third shielding layer SHL3 may be disposed biased (or shifted) toward the first end EP1 of the light emitting element LD rather than the second end EP2 of the light emitting element LD. However, the location of the second insulating layer INS2 is not limited thereto. According to an embodiment, the third shielding layer SHL3 may be disposed between the third pixel electrode ELT3 and the light emitting element LD, and the third shielding layer SHL3 may be spaced apart from the third pixel electrode ETL3.

[0261] The third shielding layer SHL3 may be electrically separated or insulated from the first pixel electrode ELT1 and the third pixel electrode ELT3. The third shielding layer SHL3 may be in a floating state, but the embodiment is not limited thereto. For example, a constant voltage or a ground voltage may be applied to the third shielding layer SHL3.

[0262] The third shielding layer SHL3 includes a conductive material and can shield or suppress an electric field formed between the first pixel electrode ELT1 and the light emitting stack structure of the light emitting device LD. For example, the third shielding layer SHL3 can also shield or suppress an electric field that may be formed between the third pixel electrode ELT3 and the light emitting device LD. Therefore, electrons or holes do not concentrate on the side surfaces of the light emitting device LD, and the driving current flowing through the light emitting device LD does not decrease. For example, deterioration of the characteristics of the light emitting device LD can be prevented.

[0263] In one embodiment, the third shielding layer SHL3 may have a light transmittance of about 70% or more. For example, light emitted from the light emitting element LD may travel (or be transmitted) in a third direction DR3 through the third shielding layer SHL3. For example, the third shielding layer SHL3 may include a transparent material (or a transparent conductive material), but the material of the third shielding layer SHL3 is not limited thereto.

[0264] For example, the light transmittance of the third shielding layer SHL3 is not limited to approximately 70% or more. For example, if the specifications of the display device do not require light emission through the side surface of the light-emitting element LD, the light transmittance of the third shielding layer SHL3 may be approximately 70% or less. For example, the third shielding layer SHL3 may include a reflective material or a light-shielding material.

[0265] As described above, instead of the light-emitting element LD including a shielding layer, the pixel PXL (or the display device) includes a third shielding layer SHL3 arranged on the side (or circumferential surface) of the light-emitting element LD (or arranged between the first pixel electrode ELT1 and the light-emitting element LD), which can shield or suppress the electric field formed on the side of the light-emitting element LD.

[0266] Although FIGS. 16 and 17 show the second insulating layer INS2 covering the third shielding layer SHL3, embodiments are not limited thereto.

[0267] 10 and 18, the pixel PXL further includes a sixth insulating layer INS6, which is disposed between the second insulating layer INS2 and the light-emitting element LD and can cover the third shielding layer SHL3. The second insulating layer INS2 may be disposed on the sixth insulating layer INS6.

[0268] The sixth insulating layer INS6 can electrically separate (or insulate) the third shielding layer SHL3 from the first pixel electrode ELT1 (or the third pixel electrode ELT3). The second insulating layer INS2 is disposed between the first pixel electrode ELT1 and the third pixel electrode ELT3 and can electrically separate (or insulate) the first pixel electrode ELT1 and the third pixel electrode ELT3.

[0269] From the above detailed description, those skilled in the art will appreciate that many variations and modifications can be made to the embodiments without departing substantially from the principles, spirit, and scope of the present invention. Accordingly, the disclosed embodiments have been used in a comprehensive and illustrative sense, and not in a limiting sense.

Claims

1. a first semiconductor layer; a light emitting layer disposed on the first semiconductor layer; a second semiconductor layer disposed on the light emitting layer; an electrode layer disposed on the second semiconductor layer; an insulating coating covering side surfaces of the first semiconductor layer, the light emitting layer, the second semiconductor layer, and the electrode layer; a shielding layer disposed inside the insulating coating.

2. The light-emitting device according to claim 1 , wherein the shielding layer is spaced apart from the first semiconductor layer, the light-emitting layer, the second semiconductor layer, and the electrode layer.

3. The light-emitting element according to claim 1 , wherein the shielding layer covers a side surface of the light-emitting layer.

4. The light transmittance of the shielding layer is about 70% or more, The light-emitting device according to claim 3 , wherein light emitted from the light-emitting layer is transmitted through the shielding layer.

5. The light-emitting device of claim 4 , wherein the shielding layer comprises a metal and the thickness of the shielding layer is about 5 nm or less.

6. the shielding layer completely covers side surfaces of the light emitting layer and the second semiconductor layer and partially covers side surfaces of the first semiconductor layer; The light reflectance of the shielding layer is about 90% or more, The light emitting device according to claim 3 , wherein light emitted from the light emitting layer is reflected by the shielding layer and travels to the outside of the light emitting device through the first semiconductor layer and the electrode layer.

7. The shielding layer is a first shielding layer covering side surfaces of the second semiconductor layer and the light emitting layer; The light emitting device according to claim 6 , further comprising: a second shielding layer that partially covers a side surface of the first semiconductor layer and is spaced apart from the first shielding layer.

8. the second shielding layer extends to one end of the insulating film adjacent to a lower surface of the first semiconductor layer and is exposed to the outside of the light emitting device; The light emitting device according to claim 7 , wherein the first shielding layer extends to another end of the insulating coating adjacent to the upper surface of the electrode layer and is exposed to the outside of the light emitting device.

9. a light emitting element disposed on a substrate, the light emitting element including a first end and a second end aligned in a direction parallel to an upper surface of the substrate; a first electrode electrically connected to the first end of the light emitting element; a second electrode electrically connected to the second end of the light-emitting element; The light-emitting element is a first semiconductor layer, a light emitting layer, a second semiconductor layer, and an electrode layer arranged in this order along a longitudinal direction from the second end to the first end; an insulating coating extending parallel to the longitudinal direction and covering side surfaces of the first semiconductor layer, the light emitting layer, the second semiconductor layer, and the electrode layer; a shielding layer disposed inside the insulating coating.

10. The display device according to claim 9 , wherein the shielding layer is spaced apart from the first semiconductor layer, the light emitting layer, the second semiconductor layer, the electrode layer, the first electrode, and the second electrode.

11. the shielding layer covers a side surface of the light-emitting layer, The display device according to claim 9 , wherein the shielding layer overlaps the first electrode in plan view.

12. The light transmittance of the shielding layer is about 70% or more, The display device of claim 11 , wherein light emitted from the light-emitting layer is transmitted through the shielding layer.

13. The display device of claim 12 , wherein the shielding layer comprises a metal and the thickness of the shielding layer is about 5 nm or less.

14. the shielding layer completely covers the side surfaces of the light emitting layer and the second semiconductor layer and partially covers the first semiconductor layer; The light reflectance of the shielding layer is about 90% or more, The display device of claim 11 , wherein light emitted from the light emitting layer is reflected by the shielding layer and travels to the outside of the light emitting element through the first end and the second end.

15. The shielding layer is a first shielding layer covering side surfaces of the second semiconductor layer and the light emitting layer; The display device according to claim 14 , further comprising: a second shielding layer that partially covers a side surface of the first semiconductor layer and is spaced apart from the first shielding layer.

16. the first shielding layer extends to the first end and is electrically connected to the first electrode; The display device of claim 15 , wherein the second shielding layer extends to the second end and is electrically connected to the second electrode.

17. a light emitting element disposed on the first insulating layer, the light emitting element including a first end and a second end; a second insulating layer disposed on the light emitting element and exposing the first end and the second end of the light emitting element; a first electrode disposed on the first end of the light emitting element; a second electrode disposed on the second end of the light emitting element; a shielding layer disposed between the second insulating layer and the light-emitting element, the shielding layer being electrically isolated from the first electrode and the second electrode.

18. The display device of claim 17 , wherein the shielding layer is floating.

19. The light transmittance of the shielding layer is about 70% or more, The display device according to claim 17 , wherein light emitted from the light-emitting element is transmitted through the shielding layer.

20. The display device of claim 17 , further comprising a third insulating layer disposed between the shielding layer and the second insulating layer and covering the shielding layer.

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