MEMORY ACCESS LINE HAVING MULTIPLE CONDUCTIVE REGIONS - Patent application

Abstract

Some embodiments include a device in which one of the devices includes a first conductive structure, a second conductive structure, a third conductive structure, and a memory cell. The memory cell includes a semiconductor portion disposed in a first level of the device and coupled to the first conductive structure, and a charge storage structure disposed in the first level, coupled to the semiconductor portion, and isolated from the second conductive structure. The third conductive structure is disposed in a second level of the device adjacent to the semiconductor portion and includes a first conductive region, a second conductive region, and a third conductive region. The third conductive region is disposed between the first and second conductive regions and has a material different from the material of the first and second conductive regions.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of priority to U.S. Provisional Application No. 63 / 444,464, filed February 9, 2023, which is incorporated herein by reference in its entirety. [Background technology]

[0002] Memory devices are widely used in computers and many other electronic products to store information. Memory devices are generally classified into two types: volatile memory devices and non-volatile memory devices. Memory devices usually have many memory cells for storing information. In volatile memory devices, the information stored in the memory cells is lost when the memory device is powered off. In non-volatile memory devices, the information stored in the memory cells is retained even when the memory device is powered off.

[0003] The present description relates to volatile memory devices. As the demand for device storage density increases, many conventional techniques provide methods for reducing the size of memory cells to increase the device storage density for a specific device area. However, when attempting to reduce the size of memory cells to a certain dimension, physical limitations and manufacturing constraints can cause challenges for such conventional techniques. Furthermore, such conventional techniques can still have limitations in controlling the current associated with the memory cells during memory operation. [Brief explanation of the drawings]

[0004] [Figure 1] 1 illustrates a block diagram of an apparatus in the form of a memory device including volatile memory cells, according to some embodiments described herein. [Figure 2] 1 shows a schematic diagram of a portion of a memory device including a memory array and memory cells according to some embodiments described herein. [Figure 3] 3 illustrates a variation of the memory device of FIG. 2 according to some embodiments described herein. [Figure 4] 3 illustrates the memory device of FIG. 2, including exemplary voltages used during a read operation of the memory device, according to some embodiments described herein. [Figure 5] 3 illustrates the memory device of FIG. 2, including exemplary voltages used during a write operation of the memory device, according to some embodiments described herein. [Figure 6A] 6A-6C illustrate different views of the structure of the memory device of FIGS. 2-5 including multiple layers of memory cells, according to some embodiments described herein. [Figure 6B] 6A-6C illustrate different views of the structure of the memory device of FIGS. 2-5 including multiple layers of memory cells, according to some embodiments described herein. [Figure 7A] 6A-6C illustrate different views of the structure of the memory device of FIGS. 2-5 including multiple layers of memory cells, according to some embodiments described herein. [Figure 7B] 6A-6C illustrate different views of the structure of the memory device of FIGS. 2-5 including multiple layers of memory cells, according to some embodiments described herein. [Figure 7C] 6A-6C illustrate different views of the structure of the memory device of FIGS. 2-5 including multiple layers of memory cells, according to some embodiments described herein. [Figure 7D] 6A-6C illustrate different views of the structure of the memory device of FIGS. 2-5 including multiple layers of memory cells, according to some embodiments described herein. [Figure 7E] 6A-6C illustrate different views of the structure of the memory device of FIGS. 2-5 including multiple layers of memory cells, according to some embodiments described herein. [Figure 7F] 6A-6C illustrate different views of the structure of the memory device of FIGS. 2-5 including multiple layers of memory cells, according to some embodiments described herein. DETAILED DESCRIPTION OF THE INVENTION

[0005] The memory devices described herein include volatile memory devices having layers of memory cells stacked on top of each other on a substrate (e.g., a semiconductor substrate) of the memory device. The described memory devices include data lines (e.g., bit lines) that may include conductive structures extending through the layers (e.g., extending vertically). Memory cells in different layers can share the conductive structures of the data lines (e.g., vertical data lines). The described memory devices include access lines (e.g., word lines) associated with the memory cells in each layer. The access lines can extend in a direction perpendicular to the data lines (e.g., vertical data lines) (e.g., extending horizontally). Each access line can include a conductive structure having different conductive regions (lateral conductive regions) at the same level of the memory device. The conductive regions can have different conductive materials with different work functions. The described memory devices include a common conductive structure in addition to the conductive structures of the data lines and access lines. The common conductive structure can also extend through the layers (e.g., extending vertically). Memory cells associated with different access lines (e.g., word lines) can share a common conductive structure. The common conductive structure may have different voltages applied to it during read and write operations of the memory device, or alternatively, the common conductive structure may be part of a ground connection (e.g., a ground plate) of the memory device.

[0006] Improvements and advantages of the described memory devices include improved device area efficiency, reduced capacitive coupling between adjacent data lines, reduced total capacitance associated with the data lines, and more transistor material options. Additionally, the different conductive regions of the access line structure can improve the current range associated with memory operation of the memory device. Additionally, the layer structure of the described memory device can also improve (e.g., reduce) the cost per bit of the memory device. Other improvements and advantages of the described memory device and its variations are discussed below with reference to FIGS. 1-7F.

[0007] FIG. 1 illustrates a block diagram of an apparatus in the form of a memory device 100 including volatile memory cells, according to some embodiments described herein. The memory device 100 includes a memory array 101, which may include memory cells 102. The memory device 100 may include a volatile memory device, whereby the memory cells 102 may be volatile memory cells. An example of a memory device 100 is a dynamic random access memory (DRAM) device. Information stored in the memory cells 102 of the memory device 100 may be lost (e.g., invalidated) if power (e.g., a supply voltage Vcc) is removed from the memory device 100. Hereinafter, the supply voltage Vcc will be referred to as representing some voltage level, but is not limited to the supply voltage (e.g., Vcc) of the memory device (e.g., memory device 100). For example, if the memory device (e.g., memory device 100) has an internal voltage generator (not shown in FIG. 1) that generates an internal voltage based on the supply voltage Vcc, such internal voltage may be used instead of the supply voltage Vcc.

[0008] The physical structure of memory device 100 may include multiple levels (e.g., multiple layers) of memory cells, with memory cells at one level (e.g., one layer) formed (e.g., stacked) above memory cells at another level (e.g., another layer). The structure of memory array 101, including memory cells 102, may include the memory array and memory cell structures described below with reference to Figures 2-7F.

[0009] 1, memory device 100 may include access lines 104 (e.g., "word lines") and data lines 105 (e.g., bit lines). Memory device 100 can access memory cells 102 and data lines 105 using signals (e.g., word line signals) on access lines 104 to provide information (e.g., data) to be stored (e.g., written) in or read (e.g., sensed) from memory cells 102.

[0010] The memory device 100 may include an address register 106 that receives address information ADDR (e.g., row address signals and column address signals) on lines (e.g., address lines) 107. The memory device 100 may include row access circuitry (e.g., X decoder) 108 and column access circuitry (e.g., Y decoder) 109 that are operable to decode the address information ADDR from the address register 106. Based on the decoded address information, the memory device 100 can determine which memory cells 102 to access during a memory operation. The memory device 100 can perform write operations to store information in the memory cells 102 and read operations to read (e.g., sense) information in the memory cells 102 (e.g., previously stored information). The memory device 100 can also perform operations (e.g., refresh operations) to refresh (e.g., maintain valid) values ​​of information stored in the memory cells 102. Each of the memory cells 102 can be configured to store information capable of representing at most one bit (e.g., a single bit having a binary zero ("0") or a binary one ("1")), or two or more bits (e.g., multiple bits having a combination of at least two binary bits).

[0011] Memory device 100 may receive supply voltages, including supply voltages Vcc and Vss, on lines 130 and 132, respectively. Supply voltage Vss may operate at ground potential (e.g., having a value of approximately zero volts). Supply voltage Vcc may include an external voltage supplied to memory device 100 from an external power source, such as a battery, or an alternating current-to-direct current (AC-DC) converter circuit.

[0012] 1, memory device 100 may include a memory control unit 118 that includes circuitry (e.g., hardware components) for controlling memory operations (e.g., read and write operations) of memory device 100 based on control signals on lines (e.g., control lines) 120. Examples of signals on lines 120 include a row access strobe signal RAS*, a column access strobe signal CAS*, a write enable signal WE*, a chip select signal CS*, a clock signal CK, and a clock enable signal CKE. These signals may be some of the signals provided to the DRAM device.

[0013] 1, memory device 100 may include lines (e.g., global data lines) 112 capable of carrying signals DQ0-DQN. In a read operation, the value of information (e.g., "0" or "1") provided on lines 112 (in the form of signals DQ0-DQN) (to be read from memory cell 102) may be based on the value of signals on data lines 105. In a write operation, the value of information (e.g., "0" or "1") provided on data lines 105 (to be stored in memory cell 102) may be based on the value of signals DQ0-DQN on lines 112.

[0014] Memory device 100 may include sensing circuitry 103, selection circuitry 115, and input / output (I / O) circuitry 116. Column access circuitry 109 may selectively activate signals on lines (e.g., select lines) based on address signals ADDR. Selection circuitry 115 may select signals on data lines 105 in response to signals on lines 114. The signals on data lines 105 may represent values ​​of information to be stored in memory cells 102 (e.g., during a write operation) or read (e.g., sensed) from memory cells 102 (e.g., during a read operation).

[0015] I / O circuitry 116 is operable to provide information read from memory cells 102 to lines 112 (e.g., during a read operation) and to provide information from lines 112 (e.g., provided by an external device) to data lines 105 for storage in memory cells 102 (e.g., during a write operation). Lines 112 may include nodes within memory device 100 or pins (or solder balls) on the surface of a package on which memory device 100 may be mounted. Other devices external to memory device 100 (e.g., a hardware memory controller or hardware processor) may communicate with memory device 100 via lines 107, 112, and 120.

[0016] Memory device 100 may include other components not shown in Figure 1 so as not to obscure the embodiments described herein. At least a portion of memory device 100 (e.g., a portion of memory array 101) may include a structure and operation similar to or identical to any of the memory devices described below with reference to Figures 2-7F.

[0017] 2 illustrates a schematic diagram of a portion of a memory device 200 including a memory array 201, according to some embodiments described herein. The memory device 200 may correspond to the memory device 100 of FIG. 1. For example, the memory array 201 may form a portion of the memory array 101 of FIG. 1. As shown in FIG. 2, the memory device 200 may include memory cells 210-215, which are volatile memory cells (e.g., DRAM cells). For simplicity, similar or identical elements of the memory cells 210-215 are labeled with the same reference numerals.

[0018] Each of the memory cells 210-215 may include a transistor T and a memory element 202. The transistor T may include a field effect transistor (FET). As an example, the transistor T may be an n-channel FET (NFET), in which case a portion of the transistor T may include an n-channel metal oxide semiconductor (NMOS) structure. Thus, in one example, the transistor T may perform operations similar to those of an NMOS transistor. In another example, the transistor T may be another type of transistor.

[0019] The memory element 202 of each memory cell 210-215 can be configured to store information. For example, the memory element 202 can include a charge storage structure. In one example, the charge storage structure can be part of a capacitor (e.g., part of a plate of a capacitor).

[0020] The memory element 202 can be in a state "0" when information having a value "0" is stored in the memory element 202. The memory element 202 can be in a state "1" when information having a value "1" is stored in the memory element 202.

[0021] Memory element 202 can store charge (e.g., store charge in its charge storage structure). The value of information (e.g., “0” or “1”) stored in a particular one of memory cells 210-215 can be based on the amount of charge in memory element 202 of that particular memory cell. For example, the value of information stored in a particular one of memory cells 210-215 can be “0” or “1” (if each memory cell is configured as a single-bit memory cell) or “00,” “01,” “10,” “11” (or other multi-bit values) if each memory cell is configured as a multi-bit memory cell.

[0022] As shown in FIG. 2 , transistor T (e.g., a channel region of transistor T) of a particular one of memory cells 210-215 may be electrically coupled (e.g., directly coupled (contacted)) to memory element 202 of that particular memory cell. Thus, during operation of memory device 200 (e.g., a read operation or a write operation), a circuit path (e.g., a current path) is formed directly between transistor T of a particular memory cell and memory element 202 of that particular memory cell. During operation of memory device 200 (e.g., a read operation or a write operation), a circuit path (e.g., a current path) is formed by transistor T (e.g., a channel region of transistor T) of a particular memory cell between a respective data line (e.g., data line 221 or 222) of the particular memory cell and memory element 202.

[0023] The memory cells 210-215 may be arranged in memory cell groups 2010 and 2011. FIG. 2 shows two memory cell groups (e.g., 2010 and 2011) as an example. However, the memory device 200 may include three or more memory cell groups. The memory cell groups 2010 and 2011 may include the same number of memory cells. For example, the memory cell group 2010 may include memory cells 210, 212, and 214, and the memory cell group 2011 may include memory cells 211, 213, and 215. FIG. 2 shows three memory cells in each of the memory cell groups 2010 and 2011 as an example. The number of memory cells in the memory cell groups 2010 and 2011 may be other than three.

[0024] Memory device 200 can perform write operations to store information in memory cells 210-215 and read operations to read (e.g., sense) information from memory cells 210-215. Memory device 200 can be configured to operate as a DRAM device. During operation (e.g., a read operation or a write operation) of memory device 200, an access line (e.g., a single access line) and a data line (e.g., a single data line) can be used to access a selected memory cell (e.g., a target memory cell).

[0025] 2, memory device 200 may include access lines (e.g., word lines) 241, 242, and 243 capable of carrying respective signals (e.g., word line signals) WL1, WL2, and WLn. Access lines 241, 242, and 243 may be used to access both memory cell groups 2010 and 2011. In the physical structure of memory device 200, each of access lines 241, 242, and 243 may be configured (formed) as a single conductive line (e.g., a conductive structure) or multiple conductive lines (e.g., multiple conductive structures). The multiple conductive lines of each access line may be electrically coupled (e.g., shorted) to each other.

[0026] Access lines 241, 242, and 243 may be selectively activated (e.g., one at a time) during operation of memory device 200 (e.g., a read operation or a write operation) to access a selected one (or a selected number of) memory cells 210-215. The selected memory cell may be referred to as a target memory cell. A read operation may read information from the selected memory cell (or the selected number of memory cells). A write operation may store information in the selected memory cell (or the selected number of memory cells).

[0027] 2, transistor T may have a gate 252, which may be part of a respective access line (e.g., a respective word line). For example, gate 252 of transistor T of memory cell 210 may be part of access line 241. Gate 252 of transistor T of memory cell 211 may be part of access line 241. In the physical structure of memory device 200, two different portions of conductive material (e.g., two different portions of a continuous piece of metal or polysilicon) forming access line 241 may form two gates, including gate 252 of transistor T of memory cell 210 and gate 252 of transistor T of memory cell 211, respectively.

[0028] Similarly, the two different portions of conductive material (e.g., two different portions of a continuous piece of metal or polysilicon) forming access line 242 can form two gates, respectively, including gate 252 of transistor T of memory cell 212 and gate 252 of transistor T of memory cell 213. Similarly, the two different portions of conductive material (e.g., two different portions of a continuous piece of metal or polysilicon) forming access line 243 can form two gates, respectively, including gate 252 of transistor T of memory cell 214 and gate 252 of transistor T of memory cell 215.

[0029] As used herein, a material may include a single material or a combination of materials. A conductive material may include a single conductive material or a combination of conductive materials.

[0030] 2, memory device 200 may include data lines (e.g., bit lines) 221 and 222 that may carry signals (e.g., bit line signals) BL1 and BL2, respectively. During a read operation, memory device 200 may use data line 221 to obtain information read (e.g., sensed) from selected memory cells of memory cell group 2010 and data line 222 to read information from selected memory cells of memory cell group 2011. During a write operation, memory device 200 may use data line 221 to provide information to be stored in selected memory cells of memory cell group 2010 and data line 222 to provide information to be stored in selected memory cells of memory cell group 2011.

[0031] The memory device 200 may include a connection 297 coupled to the memory cells 210-215. The connection 297 may be coupled to a voltage (e.g., a non-ground voltage) during operation (e.g., a read operation or a write operation) of the memory device 200. Alternatively, the connection 297 may be grounded or part of a ground connection of the memory device 200. As shown in FIG. 2, the connection 297 may be shared by the memory cells 210-215. For example, the connection 297 may include or be part of a common conductive region (e.g., a conductive plate) that may be shared by the memory cells 210-215. In one example, the memory element 202 may include a charge storage structure (e.g., charge storage structure 702 of FIG. 7A) capacitively coupled to the connection 297. As shown in FIG. 2, sharing the connection 297 between the memory cells 210-215 may reduce the capacitance (e.g., plate capacitance) of the conductive structure that forms (or is part of) the connection 297. 2 shows, as an example, connection 297 that is common to (eg, coupled to) memory cells 210-215. However, connection 297 can be coupled to memory cells 210-215 in different ways.

[0032] FIG. 3 illustrates an example in which connection 297 may include different conductive portions, each of which may be configured as a conductive line (e.g., a line (or layer) of conductive material) or a conductive plate (e.g., a layer of conductive material). As illustrated in FIG. 3, different portions of connection 297 may be shared by memory cells associated with different access lines (e.g., word lines). For example, a portion of connection 297 may be shared by memory cells 210, 212, and 214 associated with access lines 241, 242, and 243, respectively. In another example, another portion of connection 297 may be shared by memory cells 211, 213, and 215 associated with access lines 241, 242, and 243, respectively. Alternatively, memory cells associated with different access lines may have their own portions of connection 297. For example, memory cells 210 and 211 associated with access line 241 may be coupled to a portion (not shown in FIG. 3 ) of connection 297 that is not shared by memory cells (e.g., memory cells 212, 213, 214, and 215) associated with other access lines (e.g., access lines 242 and 243). In another example, memory cells 212 and 213 associated with access line 242 may be coupled to a portion (not shown in FIG. 3 ) of connection 297 that is not shared by memory cells (e.g., memory cells 210, 211, 214, and 215) associated with other access lines (e.g., access lines 241 and 243). In another example, memory cells 214 and 215 associated with access line 243 may be coupled to a portion (not shown in FIG. 3 ) of connection 297 that is not shared by memory cells (e.g., memory cells 210, 211, 212, and 213) associated with other access lines (e.g., access lines 241 and 242). Thus, the memory cells associated with access lines 241, 242, and 243 may be coupled to separate portions of connection 297 (eg, three separate portions not shown in FIG. 3).

[0033] The memory device 200 may include a read path (e.g., a circuit path). Information read from a selected memory cell during a read operation may be obtained by the read path coupled to the selected memory cell. In the memory cell group 2010, the read path of a particular memory cell (e.g., memory cell 210, 212, or 214) may include a current path (e.g., a read current path) through a channel region of a transistor T of that particular memory cell and a data line 221. In the memory cell group 2011, the read path of a particular memory cell (e.g., memory cell 211, 213, or 215) may include a current path (e.g., a read current path) through a channel region of a transistor T of that particular memory cell and a data line 222.

[0034] Memory device 200 may include a write path (e.g., a circuit path). Information to be stored in a selected memory cell during a write operation may be provided to the selected memory cell by a write path coupled to the selected memory cell. In memory cell group 2010, the write path of a particular memory cell (e.g., memory cell 210, 212, or 214) may include a current path (e.g., a write current path) through a channel region of transistor T of that particular memory cell and data line 221. In memory cell group 2011, the write path of a particular memory cell (e.g., memory cell 211, 213, or 215) may include a current path (e.g., a write current path) through a channel region of transistor T of that particular memory cell and data line 222.

[0035] During a read operation of memory device 200, only one memory cell in a same memory cell group can be selected at a time to read information from the selected memory cell. For example, during a read operation, memory cells 210, 212, and 214 in memory cell group 2010 can be selected one at a time to read information from the selected memory cell (e.g., in this example, any one of memory cells 210, 212, and 214). In another example, during a read operation, memory cells 211, 213, and 215 in memory cell group 2011 can be selected one at a time to read information from the selected memory cell (e.g., in this example, any one of memory cells 211, 213, and 215).

[0036] During a read operation, memory cells of different memory cell groups (e.g., memory cell groups 2010 and 2011) that share the same access line (e.g., access line 241, 242, or 243) can be selected simultaneously (or alternatively, selected sequentially). For example, memory cells 210 and 211 can be selected simultaneously during a read operation to read (e.g., read simultaneously) information from memory cells 210 and 211. Memory cells 212 and 213 can be selected simultaneously during a read operation to read (e.g., read simultaneously) information from memory cells 212 and 213. During a read operation, memory cells 214 and 215 can be selected simultaneously to read (e.g., read simultaneously) information from memory cells 214 and 215.

[0037] During a read operation, the value of information read from a selected memory cell in memory cell group 2010 can be determined based on a current value detected (e.g., sensed) from a read path (described above) including data line 221 and transistor T of the selected memory cell (e.g., memory cell 210, 212, or 214). During a read operation, the value of information read from a selected memory cell in memory cell group 2011 can be determined based on a current value detected (e.g., sensed) from a read path including data line 222 and transistor T of the selected memory cell (e.g., memory cell 211, 213, or 215).

[0038] Memory device 200 may include detection circuitry (not shown) that operates during a read operation to detect (e.g., sense) a current (e.g., current I1, not shown) on a read path including data line 221 and detect a current (e.g., current I2, not shown) on a read path including data line 222. The value of the detected current may be based on the value of information stored in a selected memory cell. For example, depending on the value of information stored in a selected memory cell in memory cell group 2010, the value of the detected current (e.g., the value of current I1) on data line 221 may be zero or a value greater than zero. Similarly, depending on the value of information stored in a selected memory cell in memory cell group 2011, the value of the detected current (e.g., the value of current I2) on data line 222 may be zero or a value greater than zero. Memory device 200 may include circuitry (not shown) that converts the value of the detected current into the value of information (e.g., a “0,” a “1,” or a combination of multi-bit values) stored in the selected memory cell.

[0039] During a write operation of memory device 200, only one memory cell in a memory cell group can be selected at a time, and information can be stored in the selected memory cell. For example, during a write operation, memory cells 210, 212, and 214 in memory cell group 2010 can be selected one at a time, and information can be stored in the selected memory cell (e.g., in this example, any one of memory cells 210, 212, and 214). In another example, during a write operation, memory cells 211, 213, and 215 in memory cell group 2011 can be selected one at a time, and information can be stored in the selected memory cell (e.g., in this example, any one of memory cells 211, 213, and 215).

[0040] During a write operation, memory cells in different memory cell groups (e.g., memory cell groups 2010 and 2011) that share the same access line (e.g., access line 241, 242, or 243) can be selected simultaneously. For example, memory cells 210 and 211 can be selected simultaneously during a write operation to store (e.g., simultaneously) information in memory cells 210 and 211. Memory cells 212 and 213 can be selected simultaneously during a write operation to store (e.g., simultaneously) information in memory cells 212 and 213. During a write operation, memory cells 214 and 215 can be selected simultaneously to store (e.g., simultaneously) information in memory cells 214 and 215.

[0041] During a write operation, information to be stored in a selected memory cell in memory cell group 2010 may be provided by a write path (described above) including data line 221 and transistor T of the selected memory cell (e.g., memory cells 210, 212, or 214). During a write operation, information to be stored in a selected memory cell in memory cell group 2011 may be provided by a write path (described above) including data line 222 and transistor T of the selected memory cell (e.g., memory cells 211, 213, or 215). As described above, the value (e.g., binary value) of the information to be stored in a particular one of memory cells 210-215 may be determined based on the amount of charge in memory element 202 of that particular memory cell.

[0042] In a write operation, the amount of charge in memory element 202 of a selected memory cell can be changed (to reflect the value of information to be stored in the selected memory cell) by applying a voltage to a write path including transistor T of that particular memory cell and a data line (e.g., data line 221 or 222) coupled to that particular memory cell. For example, if the information to be stored in a selected memory cell among memory cells 210, 212, and 214 has one value (e.g., "0"), a voltage having one value (e.g., 0V) can be applied to data line 221 (e.g., by providing 0V to signal BL1). In another example, if the information to be stored in a selected memory cell among memory cells 210, 212, and 214 has another value (e.g., "1"), a voltage having another value (e.g., a positive voltage) can be applied to data line 221 (e.g., by providing a positive voltage to signal BL1). Thus, information can be stored (e.g., directly stored) in the memory element 202 of a particular memory cell by providing the information to be stored (e.g., in the form of a voltage) to the write path (including transistor T) of that particular memory cell.

[0043] FIG. 4 illustrates the memory device 200 of FIG. 2 including example voltages V1, V2, and V3 used during a read operation of the memory device 200 of FIG. 2, according to some embodiments described herein. In the example of FIG. 4, it is assumed that memory cells 210 and 211 are selected memory cells (e.g., target memory cells) during a read operation to read (e.g., sense) information stored (e.g., previously stored) in memory cells 210 and 211. It is assumed that memory cells 212-215 are unselected memory cells. This means that, in the example of FIG. 4, memory cells 212-215 are not accessed and the information stored in memory cells 212-215 is not read while information is read from memory cells 210 and 211. In this example, access line 241 may be referred to as a selected access line (e.g., a selected word line) and is the access line associated with (e.g., coupled to) the selected memory cells (e.g., memory cells 210 and 211 in this example). In this example, access lines 242 and 243 can be referred to as unselected access lines (e.g., unselected word lines) and are access lines associated with (e.g., coupled to) unselected memory cells (e.g., memory cells 212, 213, 214, and 215 in this example).

[0044] 4, voltages V1, V2, and V3 may represent different voltages applied to the respective access lines 241, 242, 243 and data lines 221, 222 during a read operation of memory device 200. Voltage V1 may be applied to a selected access line (e.g., access line 241). Voltage V2 may be applied to unselected access lines (e.g., access lines 242, 243) during a read operation.

[0045] Voltages V1, V2, and V3 can have different values. By way of example, voltages V1, V2, and V3 may have values ​​of 3 V, 0 V, and 0.5 V, respectively. The specific values ​​of the voltages used herein are merely exemplary values. Different values ​​may be used. Connection 297 may be energized or grounded.

[0046] In the read operation shown in FIG. 4 , voltage V1 can have a value (voltage value) that turns on transistor T of memory cells 210 and 211 (selected memory cells in this example). This couples memory elements 202 of memory cells 210 and 211 to data lines 221 and 222, respectively, via transistor T of memory cells 210 and 211. Voltage V2 can have a value that turns off (e.g., maintains) transistor T of memory cells 212-215 (unselected memory cells in this example). Voltage V3 can have a value that forms a current (e.g., a read current) in a read path including data line 221 and transistor T of memory cell 210, and in a read path (another read path) including data line 222 and transistor T of memory cell 212. This allows current detection on the read paths (e.g., respective data lines 221 and 222) coupled to memory cells 210 and 211, respectively. Sense circuitry (not shown) of memory device 200 may operate to convert the detected current value (during reading of information from a selected memory cell) into an information value (e.g., a "0," a "1," or a combination of multi-bit values) read from the selected memory cell. In the example of FIG. 4, the detected current values ​​on data lines 221 and 222 may be converted into information values ​​read from memory cells 210 and 211, respectively.

[0047] 5 illustrates memory device 200 of FIG. 2 including example voltages V4, V5, V6, and V7 used during a write operation of memory device 200 of FIG. 2, according to some embodiments described herein. In the example of FIG. 5, it is assumed that memory cells 210 and 211 are selected memory cells (e.g., target memory cells) during a write operation to store information in memory cells 210 and 211. It is assumed that memory cells 212-215 are unselected memory cells. This means that in the example of FIG. 5, when information is stored in memory cells 210 and 211, memory cells 212-215 are not accessed and no information is stored in memory cells 212-215.

[0048] 5, voltages V4, V5, V6, and V7 may represent different voltages applied to the respective access lines 241, 242, 243 and data lines 221, 222 during a write operation of memory device 200. During a write operation, voltage V4 may be applied to a selected access line (e.g., access line 241), and voltage V5 may be applied to unselected access lines (e.g., access lines 242, 243).

[0049] Voltages V4, V5, V6, and V7 can have different values. By way of example, voltages V4 and V5 may have values ​​of 3 V and 0 V, respectively. These values ​​are example values. Different values ​​may be used. Connection 297 may be energized or grounded.

[0050] 5, voltage V4 may have a value (voltage value) that turns on transistors T of memory cells 210 and 211 (selected memory cells in this example). This causes memory elements 202 of memory cells 210 and 211 to be coupled to data lines 221 and 222, respectively, via transistors T of memory cells 210 and 211. Voltage V5 may have a value that turns off (e.g., maintains an off state) transistors T of memory cells 212-215 (unselected memory cells in this example).

[0051] The values ​​of the voltages V6 and V7 may be the same or different depending on the value of the information (e.g., "0" or "1") stored in the memory cells 210 and 211. For example, when the memory cells 210 and 211 store information having the same value, the values ​​of the voltages V6 and V7 may be the same (e.g., V6=V7). As an example, when the information stored in the memory cells 210 and 211 is both "0", V6=V7=0V. As another example, when the information stored in the memory cells 210 and 211 is both "1", V6=V7=V+ (e.g., V+ is a positive voltage (e.g., 1V to 3V)).

[0052] In another example, when storing information having different values ​​in memory cells 210 and 211, the values ​​of voltages V6 and V7 may be different (e.g., V6≠V7). As an example, when storing "0" in memory cell 210, V6=0V, and when storing "1" in memory cell 211, V7=V+ (e.g., V+ is a positive voltage (e.g., 1V to 3V)). As another example, when storing "1" in memory cell 210, V6=V+ (e.g., V+ is a positive voltage (e.g., 1V to 3V)), and when storing "0" in memory cell 211, V7=0V. Here, a voltage range of 1V to 3V is used as an example. A different voltage range may also be used.

[0053] The structure of the memory device 200 described above with reference to FIGS. 2 to 5 will now be described with reference to FIGS. 6A to 7F.

[0054] For the sake of brevity, the descriptions of Figures 6A-7F do not repeat detailed descriptions of the same elements of memory device 200. Figures 6A-7F do not show some of the memory cells and associated data and access lines of memory device 200 that are shown schematically in Figure 2. Also shown in Figures 6A-7F are some of the memory cells and associated data and access lines of memory device 200 that are not shown schematically in Figure 2. For the sake of brevity and clarity, cross-section lines (e.g., hatched lines) have been omitted from most of the elements shown in Figures 6A-7F and other figures described herein. Some elements of memory device 200 may be omitted from particular views of the drawings so as not to obscure the description of the element(s) described in that particular view. Dimensions (e.g., physical structures) of elements shown in the figures described herein are not drawn to scale.

[0055] 6A illustrates a structure of a memory device 200 including a substrate 699 and layers 601 and 602 disposed on top of each other (e.g., stacked) on the substrate 699, according to some embodiments described herein. FIG. 6A illustrates two layers 601 and 602 of the memory device 200 as an example. However, the memory device 200 may include multiple layers (e.g., up to or greater than 100 layers).

[0056] The X, Y, and Z directions shown in FIG. 6A may represent directions corresponding to a three-dimensional (3D) structure of the memory device 200. For simplicity, FIG. 6A shows only a portion of the memory device 200 relative to the XZ direction. The Z direction (e.g., vertical direction) is a direction perpendicular to the substrate 699 (e.g., a direction extending outward from the substrate 699). The Z direction is also perpendicular to the X and Y directions (e.g., a direction extending perpendicularly from the X and Y directions). The X and Y directions are perpendicular to each other. FIG. 6B is a top view of the memory device 200 in the XY direction (e.g., an XY plan view) along line 6B-6B. The portion marked "FIG. 7A" in FIG. 6A is shown in detail in FIG. 7A.

[0057] In Figure 6A, substrate 699 can be a semiconductor substrate (e.g., a silicon-based substrate) or other type of substrate. As shown in Figure 6A, each layer 601 and 602 can have its own memory cell (denoted as "memory cell"). Thus, layers 601 and 602 can be referred to as memory cell layers 601 and 602.

[0058] Each of layers 601 and 602 may include its own access line associated with memory cells in the same layer. FIG. 6A shows access lines (also referred to as "access lines") associated with signals WL0, WL1, WLi, WLj, and WL. Memory cells in different layers (e.g., layers 601 and 602) may not share access lines. For example, memory cells in layer 601 may not share access lines with memory cells in layer 602. As shown in FIG. 6A, each memory cell may reside between and be adjacent to (e.g., associated with) two portions of an access line (e.g., an upper access line and a lower access line). For example, memory cell 210 may be associated with two respective portions of an access line associated with signal WL1. In another example, memory cell 299 may be associated with two respective portions of an access line associated with signal WLi. Memory cell 299 is not shown schematically in FIG. 2.

[0059] As shown in FIG. 6A , memory device 200 may include data lines (also referred to as “data lines” or data lines BLA, BLB, BLC, BL1, BLD, and BLE) associated with signals BLA, BLB, BLC, BL1, BLD, and BLE. The data line associated with signal BL1 may correspond to data line 221 (associated signal BL1) in FIG. 2 . Each data line may include a conductive structure. For simplicity, only conductive structures 760, 761, 762, and 763 of the data lines associated with signals BLC, BL1, BLD, and BLE are labeled in FIG. 6A . As shown in FIG. 6A , each data line may have a length that extends through a layer (layers 601 and 602) in a Z-direction, which is a direction perpendicular to substrate 699. As shown in FIG. 6A , the Z-direction may also be a direction from one layer to another (e.g., from one horizontal layer to another horizontal layer). Thus, each data line (and respective conductive structure) of memory device 200 can have a length in a direction from one layer to another (eg, from one horizontal layer to another horizontal layer).

[0060] The memory device 200 may include a dielectric portion (including a dielectric material) 795 between adjacent data lines (e.g., adjacent data lines BLC and BL1, and adjacent data lines BLD and BLE). FIG. 6A shows six data lines BLA, BLB, BLC, BL1, BLD, and BLE as an example. The number of data lines in the memory device 200 can be changed.

[0061] As shown in FIG. 6A , memory device 200 may also include conductive lines (e.g., common conductive lines) associated with signals PLT0 and PLT1 (also referred to as “conductive lines”). Each of these conductive lines may include a respective conductive structure, such as conductive structures 796 and 797. Each of conductive structures 796 and 797 may include a conductive material (e.g., conductively doped polysilicon, metal, or other conductive material). Each of conductive structures 796 and 797 may be a common conductive structure between adjacent memory cells in the Y direction ( FIG. 6A ) of different layers (e.g., layers 601 and 602) and between adjacent memory cells in the X direction ( FIG. 6B ) of the same layer (e.g., layer 602). Conductive structures 796 and 797 of each conductive line (e.g., conductive line associated with signal PLT0 or PLT1) may be coupled to (or be part of) connection 297 of memory device 200. In operation of the memory device, signals PLT0 and PLT1 may be supplied with a voltage or coupled to ground potential. As shown in Figure 6A, the conductive structure 797 of each conductive line (associated with signals PLT0 and PLT1), such as data lines BLA, BLB, BLC, BL1, BLD, and BLE, may have a length that extends through the layers in the Z direction (through layers 601 and 602).

[0062] FIG. 6B illustrates a top view (e.g., cross-section) of the structure of memory device 200 along line 6B-6B in FIG. 6A, including a portion of layer 602 in FIG. 6A. For simplicity, FIG. 6B illustrates only a portion of the memory cells in layer 602 and some of the other data lines of memory device 200 (e.g., data lines associated with signals BLF, BLG, BLH, BLI, BLJ, BLK, and BLL). FIG. 6B also illustrates a top view of some of the memory cells of memory device 200 not shown in FIG. 6A. FIG. 6B also illustrates a top view of other conductive lines (e.g., common conductive lines) associated with signals PLT2 and PLT3. FIG. 6A (discussed above) illustrates a side view of memory device 200 along line 6A-6A. FIGS. 7B (top view) and 7C (top views), respectively, detail the portion of FIG. 6B labeled "FIG. 7B / 7C."

[0063] In FIG. 6B , the access lines associated with signals WL0, WL1, WLi, and WLj are shown in a partially cutaway top view to show portions of the memory cells underlying these access lines. As shown in FIG. 6B , each access line associated with signals WL0, WL1, WLi, and WLj may be an individual strip (e.g., a region of conductive material) having a length in a Y direction perpendicular to the direction from one memory cell to the next in the X direction (e.g., the X direction) in the same layer (e.g., layer 602). The access lines associated with signals WL0, WL1, WLi, and WLj may be separated (electrically isolated) from one another in the X direction. As shown in FIG. 6B , memory cells in the same layer (e.g., layer 602) are spaced apart (spaced apart) in the X direction and spaced apart (spaced apart) in the Y direction. Memory cells in the X direction (e.g., adjacent memory cells) may not share access lines (e.g., may not share word lines). For example, as shown in FIG. 6B , memory cell 210 (associated with an access line associated with signal WL1) that is adjacent (e.g., adjacent to) memory cell 299 and located away from memory cell 299 in the X-direction may not share the access line associated with signal WL1 with memory cell 299 in the X-direction.

[0064] As shown in FIG. 6B , each memory cell may be adjacent to and located between two conductive structures (e.g., an upper conductive structure and a lower conductive structure) of an access line. For example, an access line associated with signal WL1 may include a conductive structure (e.g., an upper conductive structure) 741T′ and a conductive structure (e.g., a lower conductive structure) 741B′. Conductive structures 741T′ and 741B′ may be part of access line 241 ( FIG. 2 ) of memory device 200. Conductive structures 741T′ and 741B′ face each other in the Z direction. Conductive structure 741T′ may be located above (e.g., at) the memory cell 210 with respect to the top view (Z direction shown in FIG. 6A ). Conductive structure 741B′ may be located below (e.g., at) the memory cell 210 with respect to the top view (Z direction shown in FIG. 6A ). As shown in FIG. 6B, each of conductive structures 741T' and 741B' may be configured as a strip (e.g., region) of conductive material that is electrically isolated from adjacent conductive structures of other access lines (e.g., access lines associated with signals WL0, WLi, and WLj).

[0065] Other access lines of memory device 200 (e.g., access lines associated with signals WL0, WLi, and WLj) have a structure similar to the access line associated with signal WL1. For example, as shown in FIG. 6B , the access line associated with signal WLi may include a conductive structure (e.g., an upper conductive structure) 749T′ and a conductive structure (e.g., a lower conductive structure) 749B′. Conductive structures 749T′ and 749B′ may be part of an access line associated with memory cell 299. Conductive structures 749T′ and 749B′ face each other in the Z direction. Conductive structure 749T′ may be located above (e.g., at) the memory cell 210 with respect to the top view (Z direction shown in FIG. 6A ). Conductive structure 749B′ may be located below (e.g., at) the memory cell 210 with respect to the top view (Z direction shown in FIG. 6A ). As shown in FIG. 6B, each of conductive structures 749T′ and 749B′ may be configured as a strip (e.g., region) of conductive material that is electrically isolated from adjacent conductive structures of other access lines (e.g., access lines associated with signals WL0, WLi, and WLj).

[0066] 6B, conductive structures 741T' and 741B' may be electrically coupled to each other by connection 740. Connection 740 may include a conductive connection, which may include a conductive material (e.g., a metal). As shown in FIG. 6B, each of the other access lines (e.g., access lines associated with signals WL0, WLi, and WLj) may also include upper and lower conductive structures, which may also be electrically coupled to each other by respective connection 740.

[0067] FIG. 7A shows a side view (e.g., cross section) of the portion of memory device 200 marked "FIG. 7A" in FIG. 6A. FIG. 7B shows a top view of the portion of memory device 200 along line 7B-7B in FIG. 7A and the portion marked "FIG. 7B / 7C" in FIG. 6B. FIG. 7C shows a top view of the portion of memory device 200 along line 7C-7C in FIG. 7A and the portion marked "FIG. 7B / 7C" in FIG. 6B. FIG. 7D shows a 3D view of charge storage structure 702 of memory device 200. FIG. 7E shows a 3D view of a portion of memory device 200 including conductive portion 797' coupled to conductive structure 797 and extending into an interior region of charge storage structure 702. FIG. 7F shows the same view as FIG. 7E. However, to better visualize the elements shown in FIG. 7E, dielectric material 715 is omitted in FIG. 7F, and conductive structure 797 is shown with dashed lines.

[0068] In Figures 7A, 7B, 7C, 7D, 7E, and 7F, identical elements of memory cells 210 and 299 and other elements of memory device 200 are labeled with the same reference numerals. Therefore, for brevity, the description of the elements of memory cells 210 and 299 and other elements in Figure 7A also refers to the same elements shown in Figures 7B, 7C, 7D, 7E, and 7F. Accordingly, some elements in Figures 7B, 7C, 7D, 7D, 7E, and 7F will not be described individually.

[0069] 7A shows a cross-sectional detail of layers 601 and 602 of memory device 200. As shown in FIG. 7A, layers 601 and 602 may each have different levels (physical levels) arranged (stacked) on top of each other in the Z direction on substrate 699. For example, layer 602 may include levels 771-775. For simplicity, the levels within layer 601 are not labeled.

[0070] Each data line (associated with signals BLC, BL1, BLD, and BLE) may be formed from (e.g., may include) a conductive structure. FIG. 7A shows conductive structures 760, 761, 762, and 763 for data lines associated with signals BLC, BL1, BLD, and BLE, respectively. Each conductive structure 760, 761, 762, and 763 may include a conductive material (e.g., conductively doped polysilicon, metal, or other conductive material). As shown in FIG. 7A, each conductive structure 760, 761, 762, and 763 may have a length that extends through a layer (layers 601 and 602) in the Z direction, which is the direction perpendicular to substrate 699.

[0071] Conductive structures 760, 761, 762, and 763 may be electrically coupled to some elements (eg, the channel region of transistor T, described below) of each memory cell (eg, memory cells 210 and 299) of the memory cells of layer 602.

[0072] Each conductive structure 760, 761, 762, and 763 is electrically isolated from the access lines (e.g., access lines associated with signals WL1, WLi, and WL) of memory device 200 by a respective dielectric portion (e.g., dielectric portions 725, 735, 745, and 755).

[0073] 7A will refer to elements in layer 602. Layer 601 may have elements similar to elements in memory cell 210 (having similar or identical reference numerals).

[0074] In Figure 7A, conductive regions 741T, 751, and 752 on level 775 are part of conductive structure 741T' (labeled in Figure 6B). In Figure 7A, conductive regions 741B, 751, and 752 on level 771 are part of conductive structure 741B' (labeled in Figure 6B).

[0075] 7A , conductive region (e.g., upper conductive region) 741T is adjacent to (e.g., directly coupled to) conductive regions 751 and 752 on level 775, is located between conductive regions 751 and 752, and is disposed on the same level (e.g., level 775) as conductive regions 751 and 752 on level 775. Conductive region (e.g., lower conductive region) 741B is adjacent to (e.g., directly coupled to) conductive regions 751 and 752 on level 771, is located between conductive regions 751 and 752, and is disposed on the same level (e.g., level 771) as conductive regions 751 and 752 on level 771.

[0076] Each of conductive regions 741T and 741B may include a material having a work function that is different from the work function of the material of each of conductive regions 751 and 752. For example, each of conductive regions 741T and 741B may include a material having a work function that is higher than the work function of the material of each of conductive regions 751 and 752.

[0077] The work function of the material of conductive region 741T may be the same as the work function of the material of conductive region 741B. The work function of the material of conductive region 751 may be the same as the work function of the material of conductive region 752.

[0078] Conductive region 741T can have a material that is different from the material of conductive region 751 and the material of conductive region 752. The material of conductive region 751 can be the same as the material of conductive region 752. The material of conductive region 741T can be the same as the material of conductive region 741B.

[0079] In one example, conductive regions 741T and 741B may include a metal. In one example, each of conductive regions 741T and 741B may include at least one of titanium nitride, tungsten, molybdenum, ruthenium, and titanium. These materials (e.g., metals) of conductive regions 741T and 741B described herein are exemplary. Other conductive materials (e.g., other metallic materials) may also be used. In one example, each of conductive regions 751 and 752 may include conductively doped polysilicon. In one example, the conductively doped polysilicon may have N-type conductivity (e.g., N+ polysilicon). In another example, each of conductive regions 751 and 752 may include a metal different from the metal of conductive regions 741T and 741B. For example, each of conductive regions 751 and 752 may include a lanthanum-doped metal (or multiple lanthanum-doped metals) having a lower work function than the material (e.g., metal) of conductive regions 741T and 741B, respectively.

[0080] Thus, as described herein, each of conductive regions 751 and 752 can include a material (e.g., a metal) having a work function different from (e.g., greater than) the work function of the respective material of conductive regions 751 and 752 (e.g., conductively doped polysilicon or lanthanum-doped metal). For example, each of conductive regions 741T and 741B can include a metal, and each of conductive regions 751 and 752 can include conductively doped polysilicon (e.g., N+ polysilicon). In another example, each of conductive regions 741T and 741B can include a metal, and each of conductive regions 751 and 752 can also include a metal. However, the metal of each of conductive regions 751 and 752 can have a lower work function than the metal of each of conductive regions 741T and 741B.

[0081] 7A, conductive region 751 adjacent to conductive region 741T is electrically isolated from conductive structure 761 of the data line associated with signal BL1 and conductive structure 797 of the conductive line (e.g., common conductive line) associated with signal PLT1 by respective dielectric portions 725. Conductive region 752 adjacent to conductive region 741B is electrically isolated from conductive structures 761 and 797 by respective dielectric portions 735.

[0082] In Figure 7A, conductive regions 749T, 751, and 752 on level 775 are part of conductive structure 749T' (e.g., the upper conductive structure labeled in Figure 6B). In Figure 7A, conductive regions 749B, 751, and 752 on level 771 are part of conductive structure 749B' (e.g., the lower conductive structure labeled in Figure 6B).

[0083] 7A , conductive region (e.g., upper conductive region) 749T is adjacent to (e.g., directly coupled to) conductive regions 751 and 752 on level 775, is located between conductive regions 751 and 752, and is disposed on the same level (e.g., level 775) as conductive regions 751 and 752 on level 775. Conductive region (e.g., lower conductive region) 749B is adjacent to (e.g., directly coupled to) conductive regions 751 and 752 on level 771, is located between conductive regions 751 and 752, and is disposed on the same level (e.g., level 771) as conductive regions 751 and 752 on level 771. The material of conductive regions 749T and 749B can be the same as the material of conductive regions 741T and 741B.

[0084] In memory device 200, adjacent memory cells in the X-direction may not share an access line (e.g., a word line) or multiple access lines. For example, memory cells 210 and 299 may not share an access line or multiple access lines. Thus, conductive regions 741T and 749T (located on the same level 775) may be electrically isolated from one another. For example, as shown in FIG. 7A, conductive regions 741T and 749T are not formed from (e.g., are not included in) the same conductive material. Similarly, conductive regions 741B and 749B (located on the same level 771) may be electrically isolated from one another. For example, conductive regions 741B and 749B are not formed from (e.g., are not included in) the same conductive material. In another example, as shown in FIG. 7A, conductive regions 751 and 752 associated with memory cell 210 are electrically isolated from conductive regions 751 and 752 associated with memory cell 299.

[0085] 7A, memory device 200 may include different dielectric portions disposed at different levels in the Z direction, which can electrically isolate elements within the same layer (in the Z direction) and electrically isolate one layer from another layer. For example, as shown in FIG. 7A, memory device 200 may include dielectric portions 717 and 719 disposed at levels 774 and 772, respectively. Dielectric portions 717 and 719 can electrically isolate elements within layer 602 (in the Z direction). Memory device 200 may also include dielectric portion 765, which can electrically isolate one layer from another layer (in the Z direction).

[0086] Dielectric portions 717, 719, and 765 can have the same or different dielectric materials, such as silicon oxide, silicon nitride, hafnium oxide (e.g., HfO), aluminum oxide (e.g., AlO), or other dielectric materials (e.g., other high-k dielectric materials).

[0087] As shown in FIG. 7A , charge storage structure 702 and material 720 may be disposed on level 773. Material 720 may also be referred to as portion 720. Material 720 is adjacent to (e.g., in contact with) and electrically coupled to charge storage structure 702. Material 720 may also be electrically coupled to a respective conductive structure (e.g., conductive structure 761 or 762) of a respective data line (e.g., a data line associated with signal BL1 or BLD). As shown in FIG. 7A , each of memory cells 210 and 299 (and two other memory cells disposed below memory cells 210 and 299) of memory device 200 may include transistor T. Material 720 may form a portion of a channel region (e.g., a write channel region) of transistor T of a respective memory cell (e.g., memory cell 210 or 299).

[0088] Material 720 (also referred to as portion 720) of a particular memory cell (e.g., memory cell 210) can form the source (e.g., source terminal), drain (e.g., drain terminal), or channel region (e.g., write channel region) between the source and drain of transistor T of that particular memory cell (e.g., memory cell 210). For example, as shown in FIG. 7A , the source, channel region, and drain of transistor T of memory cell 210 can be formed from the same material (or a single portion of the same material combination), such as material 720. Thus, the source, drain, and channel region of transistor T of memory cell 210 can be formed from the same material (e.g., material 720) of the same conductivity type (e.g., n-type or p-type).

[0089] Material 720 (e.g., the write channel region of transistor T) of a particular memory cell (e.g., memory cell 210) of memory device 200 may be part of the read path (e.g., during a read operation) or the write path (e.g., during a write operation) of that particular memory cell. Material 720 (portion 720) may include a structure (e.g., one (e.g., a layer)) of semiconductor material. In an example where transistor T is an NFET (as described above), material 720 may include an n-type semiconductor material (e.g., n-type silicon). In one example, the semiconductor material of portion 720 may include graded doping regions such that the semiconductor material of portion 720 can have different regions (e.g., different silicon regions) with different doping concentrations. One of such regions (e.g., an intermediate region) of the semiconductor material may be undoped (e.g., undoped silicon or undoped polysilicon).

[0090] As shown in FIG. 7A, charge storage structure 702 is adjacent to (e.g., in contact with) and electrically coupled to material 720. Charge storage structure 702 may correspond to (or be part of) memory element 202 of memory device 200, as shown schematically in FIG. 2. As shown in FIG. 7A, charge storage structure 702 is electrically separated from conductive structure 797 of a respective conductive line (e.g., the conductive line associated with signal PLT1) by dielectric portion (dielectric material) 715. Charge storage structure 702 may include a charge storage material (or combination of materials) that includes a piece (e.g., layer) of semiconductor material (e.g., polysilicon), a piece (e.g., layer) of metal, or a piece (or multiple materials) of material capable of trapping charge. The materials of charge storage structure 702 and conductive regions 741T, 741B, 749T, and 749B may be the same or different.

[0091] 7D , the charge storage structure 702 can have multiple portions, including portions 702A and 702B (e.g., horizontal portions) and portion 702C (e.g., vertical portion). Portions 702A, 702B, and 702C can form a U-shaped structure and have an interior region 702I. Because interior region 702I is surrounded (e.g., partially surrounded) by portions 702A, 702B, and 702C, the material of the charge storage structure 702 (e.g., the conductive material) is absent in interior region 702I (e.g., the material of portions 702A, 702B, and 702C is absent).

[0092] 7D, portions 702A and 702B (e.g., the long portions of the U-shaped structure) may face each other in the Z direction, which is also perpendicular to the direction from memory cell 210 to memory cell 299 or from one layer (e.g., layer 601 in FIG. 7A) to another layer (e.g., layer 602 in FIG. 7A). Portion 702C (e.g., the short portion of the U-shaped structure) is bonded (connected) to portions 702A and 702C.

[0093] 7A and 7E, conductive portion 797′ may be adjacent to (e.g., in contact with) and electrically coupled to conductive structure 797. Conductive portion 797′ may include a conductive material (e.g., conductively doped polysilicon, a metal, or other conductive material). The material of conductive portion 797′ may be the same as or different from the material of conductive structures 796 and 797.

[0094] As shown in FIGS. 7A and 7E, charge storage structure 702 can be separated (electrically isolated) from conductive structure 797 and conductive portion 797′ by dielectric material 715. Conductive portion 797′ can have a length in the X-direction, which is also the direction from conductive structure 797 to charge storage structure 702. As shown in FIGS. 7A, 7D, and 7F, a portion of conductive portion 797′ can extend to interior region 702I (labeled in FIG. 7D) and be disposed (e.g., positioned) between portion 702A and portion 702B (labeled in FIG. 7D). Conductive portion 797′ (FIG. 7E) is separated from portions 702A, 702B, and 702C by dielectric portion 715. Dielectric material 715 may include silicon dioxide, a high-k dielectric, or another dielectric material. A high-k dielectric material is a dielectric material having a dielectric constant higher than that of silicon dioxide.

[0095] The structure of a memory cell (e.g., memory cell 210) of memory device 200, including charge storage structure 702 with a U-shaped structure, can provide sufficient charge storage capacity within the memory cell. Therefore, leakage of a current (e.g., current IOFF) associated with transistor T (e.g., associated with portion 720) can be relatively mitigated. Therefore, the material of portion 720 is not limited to a particular material (e.g., a material with a relatively low leakage current) but can be selected from different materials (including silicon and polysilicon), as described above. This can provide memory device 200 with an advantage (e.g., a wider range of material options for portions 710 and 720) over some memory devices in which the channel regions of transistors within the memory cell are limited to a particular material (e.g., a material other than silicon and polysilicon).

[0096] 7A, the memory cells of memory device 200 (e.g., memory cells 210, 299 and the two memory cells (not labeled) below memory cells 210, 299) have similar or identical structures. Therefore, for the sake of brevity, a detailed description of memory cell 299 and the other memory cells will be omitted.

[0097] Due to the shape (e.g., U-shaped structure) of the charge storage structure 702 and its arrangement with the conductive portion 797′ (see FIG. 7A ), the charge storage structure 702 can have a relatively high storage capacity (e.g., high capacitance). Therefore, the material 720 (e.g., the write channel region of the transistor T) is not limited to a particular material and can be selected from different materials (e.g., a semiconductor material, a semiconductor oxide material, or other materials capable of conducting current).

[0098] As described above, the structure of memory device 200 may provide improved footprint (e.g., smaller lateral footprint) and cell density (e.g., smaller device volume for a given number of memory cells) compared to some conventional memory devices (e.g., conventional DRAM devices).

[0099] Furthermore, forming the conductive structures (e.g., conductive structures 741T′ or 741B′ of FIG. 6B ) of the access lines (e.g., word lines) such that the conductive structures include different conductive regions at the same level (e.g., conductive regions 741T, 751, and 752 of FIG. 7A ) can also improve the operation of memory device 200. For example, in an alternative structure of memory device 200, the conductive structures (e.g., conductive structure 741T′) of the access lines may include a single conductive region in each conductive structure (e.g., conductive region 741T of FIG. 7A , which does not include adjacent conductive regions 751 and 752). However, in such an alternative structure of memory device 200, the current (e.g., I or I) associated with memory cells of memory device 200 during a memory operation (e.g., a read operation or a write operation) of memory device 200 may be limited to a particular range. In memory device 200 as described above, forming conductive structures having different conductive regions (e.g., conductive regions 741T, 751, 752 of FIG. 7A ) with conductive materials having different work functions can improve the current (e.g., I or I) associated with memory cells of memory device 200 during memory operations (e.g., read or write operations) of memory device 200. For example, for the same value of current I, the current I associated with memory cells of memory device 200 can be higher than the current I associated with memory cells of an alternative structure of memory device 200 (e.g., the single conductive region described above). A higher current I can improve the memory operation of memory device 200.

[0100] The above description with reference to FIGS. 6A-7F illustrates that elements (e.g., memory cells and access lines) can be disposed (e.g., formed) in different layers of memory device 200. This allows multiple layers (e.g., layers 601 and 602, and similar layers) of memory device 200 to be formed simultaneously. Therefore, the cost of forming memory device 200 (e.g., cost per bit) can be reduced. Furthermore, the length of the conductive structure of the data lines can be based on the number of layers. The layer structure and memory cell structure (shown in FIG. 7A ) of the memory cells of memory device 200 can have a relatively compact size (e.g., each memory cell has a relatively small (e.g., thin) dimension in the Z direction). This can improve (e.g., increase) the area efficiency of the memory device compared to similar memory devices. The compact size (e.g., relatively small memory cell dimension in the Z direction) can also improve (e.g., shorten) the length of the data lines (e.g., vertical length in the Z direction) of memory device 200. This can reduce the coupling capacitance between the data lines of memory device 200 and the total capacitance of the data lines. These reduced capacitances can lead to improved operation of memory device 200. Additionally, access lines having different conductive regions (e.g., conductive regions 741T, 751, and 752 of conductive structure 741T′) with different work functions can improve the current associated with memory cells of memory device 200 during memory operations (e.g., read or write operations) of memory device 200.

[0101] The illustrations of apparatus (e.g., memory devices 100 and 200) and methods (e.g., the operation of memory devices 100 and 200) are intended to provide a general understanding of the structure of various embodiments, but are not intended to provide a complete description of all elements and features of apparatus that may utilize the structures described herein. Apparatus herein refers, for example, to a device (e.g., either of memory devices 100 and 200) or a system (e.g., an electronic product that may include either of memory devices 100 and 200).

[0102] Any of the components described above with reference to Figures 1-7F may be implemented in a variety of ways, including through software simulation. Accordingly, the apparatus described above (e.g., memory devices 100 and 200) or portions of each of these memory devices may all be characterized herein as "modules" (or "modules"). Such modules may include hardware circuitry, single-processor and / or multi-processor circuitry, memory circuitry, software program modules and objects and / or firmware, and combinations thereof, as needed and / or suitable for the particular implementation of various embodiments. For example, such modules may be included in a system operation simulation package, such as a software electrical signal simulation package, a power usage and range simulation package, a capacitance-inductance simulation package, a power / heat dissipation simulation package, a signal transmission / reception simulation package, and / or a combination of software and hardware used to operate or simulate the operation of various potential embodiments.

[0103] The memory devices described herein (e.g., memory devices 100 and 200) may be included in devices (e.g., electronic circuits) such as high-speed computers, communications and signal processing circuits, single or multiple processor modules, single or multiple embedded processors, multi-core processors, message information switches, and application-specific modules, including multi-layer, multi-chip modules. Such devices may also be included as subcomponents within a variety of other devices (e.g., electronic systems), such as televisions, mobile phones, personal computers (e.g., laptop computers, desktop computers, handheld computers, tablet computers), workstations, radios, video players, audio players (e.g., Motion Picture Experts Group Audio Layer 3 (MP3) players), vehicles, medical devices (e.g., heart rate monitors, blood pressure monitors), set-top boxes, etc.

[0104] 1-7F include devices in which one of the devices includes a first conductive structure, a second conductive structure, a third conductive structure, and a memory cell. The memory cell includes a semiconductor portion disposed in a first level of the device and coupled to the first conductive structure, and a charge storage structure disposed in the first level and coupled to the semiconductor portion and isolated from the second conductive structure. The third conductive structure is disposed in a second level of the device adjacent to the semiconductor portion and includes a first conductive region, a second conductive region, and a third conductive region. The third conductive region is disposed between the first and second conductive regions and has a material different from the material of the first and second conductive regions.

[0105] Other embodiments, including additional apparatus and methods, are described.

[0106] In the detailed description and claims, the term "surface," when used with reference to two or more elements (e.g., materials), one of which is "on" the other, means at least some contact between the elements (e.g., materials). The term "above" means that the elements (e.g., materials) are in close proximity, but can, but need not, be in contact, possibly with one or more additional intervening elements (e.g., materials). Neither "surface" nor "above" imply any orientation as used herein unless so stated.

[0107] As used herein, the term "adjacent" generally refers to the position where one thing is adjacent to (e.g., immediately next to or close with one or more intervening elements between) or adjacent to (e.g., adjacent to or in contact with (e.g., directly attached to)) another thing.

[0108] In the detailed description and claims, the terms "first," "second," "third," etc. are used merely as labels and are not intended to impose numerical requirements on their objects.

[0109] In the detailed description and claims, a list of items joined by the term "at least one" can mean any combination of the listed items. For example, if items A and B are listed, the phrase "at least one of A and B" means A only, B only, or A and B. As another example, if items A, B, and C are listed, the phrase "at least one of A, B, and C" means A only, B only, C only, A and B (excluding C), A and C (excluding B), B and C (excluding A), or all of A, B, and C. Item A can include a single element or multiple elements. Item B can include a single element or multiple elements. Item C can include a single element or multiple elements.

[0110] In the detailed description and claims, a list of items joined by the term "one of" can mean only one of the listed items. For example, if items A and B are listed, the phrase "one of A and B" means only A (excluding B) or only B (excluding A). In another example, if items A, B, and C are listed, the phrase "any of A, B, or C" means only A, only B, or only C. Item A can include a single element or multiple elements. Item B can include a single element or multiple elements. Item C can include a single element or multiple elements.

[0111] The above description and drawings illustrate some embodiments of the inventive subject matter to enable one skilled in the art to practice embodiments of the inventive subject matter. Other embodiments may incorporate structural, logical, electrical, process, and other changes. The illustrations represent only possible variations. Portions and features of some embodiments may be included in, or substituted for, portions and features of other embodiments. Many other embodiments will be apparent to those skilled in the art upon reading and understanding the above description.

Claims

1. 1. An apparatus comprising: a first conductive structure; and a second conductive structure; and A memory cell comprising: a semiconductor portion disposed in a first level of the device and coupled to the first conductive structure; and the memory cell including a charge storage structure disposed on the first level, coupled to the semiconductor portion, and isolated from the second conductive structure; the device comprising: a third conductive structure disposed in a second level of the device adjacent to the semiconductor portion, the third conductive structure including a first conductive region, a second conductive region, and a third conductive region, the third conductive region being disposed between the first conductive region and the second conductive region and having a material different from a material of the first conductive region and a material of the second conductive region.

2. The device of claim 1 , wherein the material of the first conductive region and the material of the second conductive region are the same.

3. The device of claim 1 , wherein the material of the third conductive region comprises a metal.

4. 10. The device of claim 1, wherein the first conductive region and the second conductive region comprise conductively doped polysilicon.

5. the material of the first conductive region includes a first metal; 10. The device of claim 1, wherein the material of the third conductive region comprises a second metal, the second metal having a higher work function than the first metal.

6. the first conductive region is adjacent to the first conductive structure and separated from the first conductive structure by a first dielectric material; 10. The device of claim 1, wherein the second conductive region is adjacent to the second conductive structure and separated from the second conductive structure by a second dielectric material.

7. further comprising a conductive portion coupled to the second conductive structure; the charge storage structure includes a first portion, a second portion opposite the first portion, and a third portion connecting the first portion and the second portion; 2. The device of claim 1, wherein a portion of the conductive portion is disposed between the first and second portions of the charge storage structure and is separated from the first, second, and third portions of the charge storage structure by a first dielectric material.

8. The device of claim 1 , wherein the first conductive structure is part of a data line of the device.

9. The device of claim 1 , wherein the second conductive structure is part of a ground connection of the device.

10. The device of claim 1 , wherein the third conductive structure is part of a word line of the device.

11. 1. An apparatus comprising: a data line including a first conductive structure having a length in a first direction; a second conductive structure having a length in the first direction; a memory cell coupled to the first conductive structure and the second conductive structure, a transistor coupled to the first conductive structure and including a channel region having a first side and a second side opposite the first side in the first direction; and the memory cell including a charge storage structure coupled to the channel region; a first additional conductive structure disposed on the first side of the channel region, separated from the channel region by a first dielectric material, and having a length in a second direction; a second additional conductive structure disposed on the second side of the channel region, separated from the channel region by a second dielectric material, and having a length in the second direction, wherein the first additional conductive structure and the second additional conductive structure each include a first conductive region and a second conductive region having the same material, and a third conductive region located between the first conductive region and the second conductive region, wherein the third conductive region and the first conductive region have different materials.

12. 12. The device of claim 11, wherein the third conductive region comprises at least one of titanium nitride, tungsten, molybdenum, ruthenium, and titanium.

13. 12. The device of claim 11, wherein the first and second conductive regions comprise at least one of polysilicon and lanthanum doped metal conductively doped with N-type conductivity.

14. The device of claim 11 , wherein the first additional conductive structure and the second additional conductive structure are coupled to one another.

15. The device of claim 11 , wherein a portion of the third conductive region forms a gate of the transistor.

16. 1. An apparatus comprising: layers arranged one above the other, each including a memory cell; a first data line including a first conductive structure and a second data line including a second conductive structure and a third conductive structure, the first conductive structure, the second conductive structure, and the third conductive structure extending through the layer; A first memory cell and a second memory cell included in the memory cells of one of the layers, the first memory cell being disposed at a distance from the second memory cell in a direction perpendicular to a direction from one layer to another layer, and each of the first memory cell and the second memory cell: a semiconductor portion disposed in a first level of the device and coupled to one of the first conductive structure and the second conductive structure; and the first memory cell and the second memory cell, each disposed on the first level, including a charge storage structure coupled to the semiconductor portion and separated from the third conductive structure; a fourth conductive structure disposed in a second level of the device adjacent the semiconductor portion of the first memory cell; and a fifth conductive structure disposed in the second level of the device adjacent to the semiconductor portion of the second memory cell, wherein each of the fourth conductive structure and the fifth conductive structure includes a first conductive region, a second conductive region, and a third conductive region, the third conductive region being disposed between the first conductive region and the second conductive region, and a material of the third conductive region having a different work function than a material of each of the first conductive region and the second conductive region.

17. 17. The device of claim 16, wherein the work function of the third conductivity region is higher than the work function of each of the first conductivity region and the second conductivity region.

18. 17. The device of claim 16, wherein the first and second conductive regions comprise polysilicon doped to N-type conductivity.

19. 17. The device of claim 16, wherein the third conductive region comprises a metal.

20. a first conductive portion coupled to the third conductive structure, disposed adjacent to the charge storage structure of the first memory cell, and separated from the charge storage structure of the first memory cell by a first dielectric material; 17. The device of claim 16, further comprising: a second conductive portion coupled to the third conductive structure, positioned adjacent to the charge storage structure of the second memory cell, and separated from the charge storage structure of the second memory cell by a second dielectric material.

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