Heterogeneous integration of radio frequency transistor chiplets with interconnected tuning circuits

Abstract

The electronic assembly includes a host wafer having a first circuit including passive devices for one of a tuning or matching network. Chiplets are disposed in the cavity. At least one chiplet has a second circuit including at least one transistor or switch device and a passive tuning circuit including at least one of a stabilization network, a gain boosting network, a power delivery network, or a low-noise network. Electrical interconnects between the chiplet and the wafer electrically connect the first circuit to the second circuit.

Description

[Technical Field]

[0001] The present disclosure relates to a host wafer having circuitry and radio frequency (RF) transistor chips (or chiplets) within cavities in the wafer, the chips including network circuitry for tuning the electrical interconnections between the chips and the wafer. [Background technology]

[0002] Description of Related Art

[0003] An electronic assembly, or hybrid circuit, comprises microelectronic circuits that are manufactured separately and assembled together to form a single component, which may itself be enclosed in an electronic circuit package. Assembling separately manufactured microelectronic circuits may improve the manufacturing yield of the final component, for example, by allowing all microelectronic circuits to be tested separately before the microelectronic circuits are assembled. This feature is particularly important when some of the separately manufactured microelectronic circuits are difficult and / or expensive to manufacture. Assembling separately manufactured microelectronic circuits may also allow microelectronic circuits that themselves use different materials and manufacturing processes to be combined into a single final component. This feature may lead to improved circuit performance.

[0004] There is a need for electronic assemblies using host wafers with pre-fabricated integrated circuits, such as passive components, connected to microelectronic active chiplets (i.e., transistors) integrated into through-wafer cavities in the host wafer. This need is required, for example, for assemblies for microwave or other radio frequency (RF) integrated circuits, separating the fabrication of the active circuitry (e.g., transistors) from the fabrication of the passive circuit components (e.g., interconnects, resistors, capacitors). Meeting this need would allow for very rapid fabrication of circuits at lower cost and without the burden of cost and cycle time, as well as the scaling-up of active device technology into circuits. [Brief explanation of the drawings]

[0005] [Figure 1A] FIG. 1 is a schematic top view of a host wafer for heterogeneous integration of radio frequency (RF) transistor chiplets with tuning circuits for impedance matching.

[0006] [Figure 1B] FIG. 1 is a schematic top view of a radio frequency (RF) transistor chiplet with interconnect tuning circuits for heterogeneous integration into a wafer cavity of a host wafer.

[0007] [Figure 1C] 1 is a schematic circuit diagram of an electronic assembly having heterogeneous integration of radio frequency (RF) transistor chiplets on a wafer, the chiplets having interconnected tuning circuits.

[0008] [Figure 2A] 1D is a schematic diagram of the electronic assembly of FIG. 1C, isolating an example of an interconnected tuning circuit with a stabilization network circuit.

[0009] [Figure 2B]FIG. 1D is a schematic diagram of the electronic assembly of FIG. 1C, isolating an example of an interconnection tuned circuit with a neutralization network to improve stability or introduce positive feedback to increase transistor gain in the presence of interconnects to the wafer.

[0010] [Figure 2C] FIG. 1 is a schematic diagram of an electronic assembly that separates an example of power delivery to and from chiplets via an interconnection tuned circuit that introduces impedance matching.

[0011] [Figure 2D] 1D is a schematic diagram of the electronic assembly of FIG. 1C, isolating an example of an interconnected tuning circuit with a negative feedback or degeneration network such as found in low noise network circuits for tuning transistors.

[0012] [Figure 2E] FIG. 1 is a schematic diagram of an electronic assembly with an example interconnect tuning circuit that isolates the stabilization network circuits of the chiplets in the presence of an interconnect network.

[0013] [Figure 2F] 1 shows a circuit having RF transistor chiplets in a wafer, the chiplets having interconnected tuned circuits.

[0014] [Figure 3A] 1 is a schematic cross-sectional view of a device having heterogeneous integration of radio frequency (RF) transistor chiplets into a wafer, the chiplets having interconnected tuning circuits.

[0015] [Figure 3B] 1 is a schematic cross-sectional view of a device having heterogeneous integration on a wafer of radio frequency (RF) transistor chiplets with interconnected tuning circuits.

[0016] Throughout this description, elements that appear in the figures are assigned a three or four digit reference designator, where the last two digits are unique to the element and the first one or two digits may be the figure number in which the element is first introduced or created. An element not described in connection with a figure can be assumed to have the same properties and function as an element described earlier or later having the same reference number. DETAILED DESCRIPTION OF THE INVENTION

[0017] (Device Description)

[0018] The following describes improved wafers, dies, chips, and their fabrication techniques for electronic assemblies with heterogeneous integration of radio frequency (RF) transistor chips (e.g., chiplets) with interconnection tuning circuits between the wafer and the chips. A host wafer contains circuits and radio frequency (RF) transistor chips within the wafer's cavities, and the chips contain one or more types of network circuits that tune the electrical interconnections between the chips and the wafer. The host wafer can have prefabricated interconnects and integrated circuits, such as passive components that connect to chiplet-level microelectronic transistor chips integrated within the wafer's through-wafer cavities. This may form an assembly for integrated circuit devices where the chips contain active circuits from at least one semiconductor technology and the wafer contains passive (or active) circuits from another semiconductor technology (often a cheaper, larger-scale technology). Using a low-cost, large-diameter integration platform for chips with active devices allows for much faster fabrication of assembled circuits at large scales and at low cost.

[0019] Electronic fabrication circuits can integrate chiplets with one type of component onto a carrier wafer with a different type of component. Electronic fabrication circuits can integrate chiplets with high-performance integrated circuits, such as gallium nitride (GaN) radio frequency (RF) integrated circuits (ICs), onto a host wafer with other integrated circuits, such as silicon-based integrated circuits, in a manner that is inexpensive, has high manufacturing yields, and has short manufacturing cycles. High-performance RF ICs, chips (or chiplets), can have III-V or other types of transistors and passive circuits or components, and can be integrated onto a host wafer with resistors, inductors, capacitors, and matching networks, as well as active devices from another semiconductor technology. For example, the RF IC or chiplet can be one type of semiconductor technology integrated with resistors, inductors, capacitors, matching networks, and active devices from another semiconductor technology that are part of the host wafer.

[0020] A chiplet may be a chip including the circuits, materials, and / or devices described herein. A chiplet may also be a chip or miniature chip having active (i.e., transistor) microelectronic devices, active CMOS devices, active microwave IC devices, and / or active radio frequency (RF) IC devices. A chiplet may also be a chip or miniature chip having surface acoustic wave (SAW), bulk acoustic wave (BAW), or other acoustic wave devices. A chiplet may have a footprint or top surface area that is half, one-third, one-fifth, or less than one-fifth the footprint of a computer processor chip (e.g., 8086, P3, P4, etc.). An active device may include active electronic components and / or active electronic circuits.

[0021] The interconnections between the chiplets and the wafer may be mistuned, for example, because the wafer has a different AC (alternating current) signal frequency than the chiplets. The interconnections between the chiplets and the wafer may be mismatched, for example, because the wafer has an impedance difference from the chiplets, which may result in instability of AC signals, DC (direct current) signals, and / or other electronic signals that are matched to the chiplets or the inputs and / or outputs to the transistors on the chiplets. This lack of tuning may be improved or tuned using the tuning circuits or networks described herein.

[0022] FIG. 1A is a schematic top view 100 of a host wafer 110 for heterogeneous integration of radio frequency (RF) transistor chiplets with tuning circuits for impedance matching. The host wafer 110 has a backside surface 112 and a frontside surface 114, as shown in FIGS. 3A and 3B. The host wafer 110 and / or each cavity 120 has side surfaces 116, such as vertical or sidewall surfaces, between the backside surface 112 and the frontside surface 114. There may be three, four, or more side surfaces 116. Typically, there are four. Wafer capacitors, inductors, and resistors may be tuning circuits for impedance matching of interconnects from the chiplets (see, for example, FIG. 1C).

[0023] The host wafer 110 may be or include (e.g., as a mixture of materials or as a material layer) silicon, silicon germanium, silicon-on-insulator, gallium arsenide, indium phosphide, aluminum nitride, diamond, quartz, or alumina. If the host wafer 110 includes only interconnects and passive components, it can be a dielectric such as quartz, alumina, or another ceramic. The host wafer 110 may have one or more layers of these materials in the form of oxide, crystalline, and polycrystalline and / or amorphous materials. The host wafer 110 may include some or only passive components, such as resistors, capacitors, inductors, through-substrate vias, dielectric layers, and / or metal layers (e.g., signal traces or signal planes). The host wafer 110 may include at least one layer of silicon, silicon carbide (SiC), quartz, or another semiconductor wafer material.

[0024] The host wafer 110 may include areas to be diced into integrated circuits, each having passive integrated components (e.g., signal traces, interconnects and conductive vias, resistors, inductors, and / or capacitors) and single and / or multiple transistors. Silicon is an advantageous choice for the host wafer 110 because of its lower cost than other materials and / or the advantages of known microelectronics manufacturing processes and scaling and manufacturability.

[0025] FIG. 1B is a schematic top view 102 of a radio frequency (RF) transistor chiplet 130 with interconnected tuned circuits for heterogeneous integration into a wafer cavity 120 of a host wafer 110. The chiplet 130 has a front side 132 (e.g., front surface) and a back side 134 (e.g., back surface), as shown in FIGS. 3A and 3B. Each chiplet 130 has a side surface 136, such as a vertical surface or a sidewall surface, between the front surface 132 and the back surface 134. There may be three, four, or more side surfaces 136. Typically, there are four side surfaces. The number of side surfaces 136 of each chiplet 130 may be the same as the number of surfaces 116 of the cavity in the host wafer 110. Each chiplet 130 may include the circuitry described with reference to FIGS. 1C through 3B.

[0026] The chiplets 130 may each be or include (e.g., as a mixture of materials or as a layer of materials) silicon (Si), silicon germanium (SiGe), silicon-on-insulator, gallium arsenide (GaAs), indium phosphide (InP), aluminum nitride, quartz, alumina, or gallium nitride (GaN). The chiplets 130 may have layers of one or more of these materials in the form of oxide, crystalline, and polycrystalline and / or amorphous materials. There may be different electrical components or types of chiplets 130 fabricated separately from one another. The chiplets 130 may include GaN, InP, or GaAs, or any other electrical components known in the industry, and may be fabricated on a substrate such as Si, SiGe, InP, GaAs, alumina, or diamond, or any other substrate known in the industry.

[0027] Chiplets 130 or types of chiplets 130 may include transistors used for RF switches, transmit and / or receive circuits, and power switches, amplifiers, and circuits using GaAs, InP, GaN, etc., and the host wafer may include transistors such as Si CMOS transistors. Chiplet transistors may have smaller, more expensive electrical components than the electrical components of the host wafer 110. The number of chiplets 130 embedded in or on a single host wafer 110 may be one, tens, hundreds, or hundreds of thousands. The number of chiplets 130 embedded in a single host wafer 110 may be between one and 100. The host wafer 110 may have more passive components, lower-cost components, and routing (e.g., traces, conductive vias, and interconnects) than the chiplets 130. The host wafer 110 may be fabricated using a different microelectronic fabrication technology or process than those used to fabricate the chiplets 130.

[0028] The chiplets 130 and the host wafer 110 can be made of different materials. For example, the wafer 110 can be a silicon wafer, and the chiplets 130 can be III-nitride material component chips. The chiplets 130 can each be or include an integrated circuit having passive integrated components (e.g., signal traces, interconnects and conductive vias, resistors, inductors, and / or capacitors), single transistors, and / or multiple transistors.

[0029] Chiplets 130 each include transistor circuitry and at least one interconnect to contact pads on the front side 132 of chiplet 130. Chiplets 130 may be high-end pre-fabricated active device chiplets that are integrated into host wafer 110 by pick-and-place assembly on a temporary wafer with an adhesive laminate or simply on the adhesive laminate.

[0030] FIG. 1C is a schematic circuit diagram of an electronic assembly 106 having heterogeneous integration of radio frequency (RF) transistor chiplets 130 on a host wafer 110, where the chiplets 130 have an interconnect tuned circuit 140 with passive circuitry. The wafer 110 includes resistors, indicated by the schematic symbol labeled Rw, capacitors, indicated by the schematic symbol labeled Cw, inductors, indicated by the schematic symbol labeled Lw, and grounds, indicated by the schematic symbol labeled GNDw. In some cases, the wafer capacitors and inductors represent electrical properties of interconnects, such as interconnects 155 and / or 255, as indicated by their CLC networks under resistor Rw. Here, the CLC networks may represent interconnects between the chiplets and the wafer. These properties may be part of what is being tuned and / or part of the interconnect tuned circuit on the chiplets and / or wafer. Resistor Rw may be considered a separate interconnect tuned circuit on the wafer 110. The wafer capacitors, inductors, and resistors may be tuning circuits for matching the impedance of the interconnects from the chiplets. The wafer circuitry may be described as passive (e.g., R, C, L, non-transistor) devices for the purpose of either tuning or matching networks. Other passive devices may be in or on the wafer. In some cases, the wafer 110 includes only passive non-transistor devices. In other cases, the wafer circuitry may also include active devices that are not radio frequency (RF) transistor devices.

[0031] Chiplet 130 includes resistors R1, R2, and R3, capacitors C1 and C2, inductor L1, and transistors T1 and T2. Transistor T1 has a source S1, a drain D1 that can be considered a transistor output OUT1, and a gate G1 that can be considered a transistor input IN1. Transistor T2 has a source S2, a drain D2 that can be considered a transistor output OUT2, and a gate G2 that can be considered a transistor input IN2. Chiplet circuits may be described as having both passive (e.g., R, C, L) and active (e.g., at least transistors T1 and T2) devices. Other passive and / or active devices may be present in or on the chiplet.

[0032] In some cases, the input signal to transistor T1 and / or transistor T2, or an input signal to a chiplet such as input INx (where x is a number as indicated herein), or another input signal to the chiplet, also includes a second ground signal such as GNDr1 or GNDr2, or another ground signal from the chiplet to the transistor or wafer 110.

[0033] The differential input port between G1 / IN1 and G2 / IN2 and the differential output port between D1 / OUT1 and D2 / OUT2 may be used to increase the power generated in a given chiplet area. In this case, S22 may be a “reflection” of the output power when port 2 or OUT2 is connected to a load (not shown). In some cases, the output signal from transistor T1 and / or transistor T2, or an output signal from a chiplet such as input OUTx (e.g., x is a number shown herein), or another output signal from the chiplet, also includes a second ground signal such as GNDr1 or GNDr2, or another ground signal to the chiplet or from the transistor or wafer 110. Here, the input to the transistor or chiplet may have port 1 between the gate of the transistor and GNDr1, and may have the output of the transistor between the drain of the transistor and GNDr1. Input port 1 may have a reflection of input power from a source characterized by S11, and output port 2 may have a reflection of output power at a load (e.g., LD1) characterized by S22, the forward propagation (gain) of the wave from port 1 to port 2 being S21, and the reverse propagation (isolation) of the wave from port 2 to port 1 being S12.

[0034] The available gain G of the S-parameter network A is given by the S-parameters and source impedance as follows:

number

[0035] The one-way gain U is given by, for any lossless embedded network of network 140,

number

[0036] These S-parameters are useful for characterizing how stable a circuit is. A family of stability circles exists across all frequencies and input powers. A circuit is unconditionally stable if and only if the mu (μ) factor remains greater than 1 for all possible operating conditions of the stability circle, e.g.,

number

[0037] That is, any of the circuit-less network 140 on wafer 110 (other than the network of on-wafer inductors L3-L8 in FIG. 2C) can make the transistor or chiplet unconditionally stable by making μ greater than 1 under operating conditions, such as when the transistor or chiplet is amplifying or passing an RF signal.

[0038] Each of transistors T1 and T2 may be a radio frequency (RF) transistor device. Each of transistors T1 and T2 may operate at radio frequencies (e.g., amplify, pass, and / or switch) and / or may be an RF wave transistor device. Each may operate on electronic signals having frequencies between 10 MHz and 300 GHz, between 30 GHz and 300 GHz, or between 10 MHz and 10 GHz. Transistors T1 and T2 may be millimeter wave or microwave transistor elements. Each of transistors T1 and T2 may be a single-ended RF amplifier, such as used to create an amplifier chain, an amplifier-based receiver, a mixer, a switch, or a frequency multiplier. Each of transistors T1 and T2 may be part of a differential amplifier, arranged in parallel with a shared drain and source, but with separate gate or base connections for a frequency multiplier, or a series connection of devices for a cascode. Furthermore, transistors T1 and / or T2 may be part of a switched pair of transistors for an RF switch or mixer. A total of four transistors may be used in a single chiplet for the FET ring mixer. Each of transistors T1 and T2 may be a heterojunction bipolar transistor (HBT), but in such a case, each has a base, emitter, and collector instead of a gate, source, and drain. Each of transistors T1 and T2 may be used in common gate mode by grounding both gates and using the source as an input. Each of transistors T1 and T2 may be used with an input at the source and an output at the drain.

[0039] 1C, transistor T1 is an RF amplifier with a differential amplifier signal phase output, and transistor T2 is another RF amplifier with a differential amplifier signal phase output that is 180 degrees out of phase with the signal phase of transistor T1. Transistors T1 and T2 may be two differential RF transistors, and there may be an interconnection from these transistors to contact pads 138 on the front surface of chiplet 130.

[0040] Wafer 110 may also include a circuit network for providing a virtual ground at GNDr1, such as an AC ground, and a circuit for applying a DC bias voltage applied to node N1 between resistors R1 and R2. Wafer 110 may also include a GNDr2, such as an AC ground, and a DC bias voltage applied to one end of resistor R3 opposite node N1 between resistors R1 and R2.

[0041] The assembly 106 also includes interconnects 155 between the contacts 118 of the wafer 110 and the contacts 138 of the chiplets 130. The contacts may be contact pads or other electrical connections to the wafer or chiplet circuitry. The interconnects 155 may be traces (e.g., on a PCB), wires, or other conductive connections between the contacts. The electrical interconnects 155 electrically connect the wafer circuitry to the chiplet circuitry. At the boundary (e.g., sidewall) between the wafer and the chiplet, there may be similar interconnects and contact pairs for each electrical connection required at that boundary.

[0042] Electrical interconnects 155 electrically connect the circuit devices of the wafer to the transistors of the chiplets. The interconnects between the chiplets and the wafer can be mistuned, such as by having mismatches in stability, AC signals, DC signals, impedance, frequency, and / or other electronic signal matching with the inputs and / or outputs to the chiplets or transistors on the chiplets. This lack of tuning can be improved or tuned using tuning circuit 140. In particular, interconnect tuning circuit 140 reduces this electrical mistuning of passive devices and transistors caused by the electrical interconnects that can affect circuit performance, and reduces the uncertainty in the electrical impedance and frequency of signals passed across the interconnects, improving circuit performance.

[0043] Interconnect tuning circuit 140 may be any or all of the resistors, inductors, and capacitors shown on chiplet 130 or other chiplets herein. In some cases, it may also include an inductor on the wafer, as shown in FIG. 2C. Interconnect tuning circuit 140 may include at least one of a stabilization network (e.g., a network of electronic circuits), a gain boosting network, a power delivery network, and / or a low-noise network. Each of these networks may be an embedded network embedded in wafer 110 as part of the chiplet.

[0044] 1C may be present in greater or lesser numbers with respect to chiplets 130, wafer 110, and / or interconnect tuned circuits 140. Although only one is shown in FIG. 1C, multiple chiplets 130 may be present within a cavity in wafer 110. There may be 10 to 1000 such chiplets present within a wafer.

[0045] FIG. 2A is a schematic diagram of the electronic assembly 106 of FIG. 1C , isolating an example of the stabilization network circuit 142 of the interconnection tuning circuit 140. The circuit 142 may be a network of electronic circuits with a passive circuit including at least one of resistors R1, R2, and / or R3. The circuit 142 may include only resistors R1 and R2. In other cases, the circuit 142 includes all of resistors R1, R2, and R3. The R3 resistor is introduced to provide common-mode stability or to provide feedback to a virtual ground on the drain / output circuit. The circuit 142 may optionally include grounds GNDr1 and / or GNDr2. The circuit 142 may optionally include one or more of inductor L1, capacitor C1, and / or capacitor C2. The stabilization network circuit 142 may be a stabilization network circuit for transistors T1 and / or T2, regardless of the electrical characteristics or mistuning of the interconnection circuits 155 and / or 255. Furthermore, resistor R3 may not be grounded to GNDr1, but may instead be connected to the drains D1 and / or D2 of transistors T1 and / or T2 through some external circuit present in the wafer. In some cases, resistors R1, R2, and R3 are not grounded to ground GNDr1 or GNDr2 (but may be grounded to a "virtual" ground) and are used to provide DC bias to gates G1 and G2 without affecting the RF frequency performance of the differential circuit. Ground GNDr1 or GNDr2 may provide a DC bias voltage to gates G1 and G2 through resistors R1, R2, and R3. Thus, resistors R1, R2, and R3 provide stabilization of the DC bias to gates G1 and G2, such as by setting a DC bias on the gates of the transistors.

[0046] In some cases, circuit 142 may include at least one resistor R1 between input IN1 of transistor T1 and node N1 to ground GNDr1, at least one resistor R2 between input IN2 of transistor T2 and node N1, and at least one resistor R3 between node N1 and ground GNDr2, where ground GNDr1 may be a first AC ground enabling a DC voltage that provides a desired first DC bias to inputs IN1 and IN2, and GNDr2 may be a second AC ground and DC voltage that provides a desired second DC bias to the inputs IN1 and IN2.

[0047] In some cases, circuit 142 may include at least one resistor R1 (and optionally R2) between input IN1 and input IN2, and at least one resistor R2 (and optionally R1) between input IN2 and input IN1, as shown in FIG. 1C. Optionally, capacitors C1 and C2 may be present between these inputs and the output, as shown in FIG. 1C. Optionally, inductor L1 may be present between S1 and S2, as shown in FIG. 1C.

[0048] Any one, two, or all three of these resistors R1, R2, and R3 may provide desired DC bias and common-mode stability at the inputs IN1 and IN2 compared to without the resistors. Any one, two, or all three of these resistors R1, R2, and R3 may provide desired impedance matching at the input and output of each transistor T1 and T2 compared to without the resistors.

[0049] In some cases, these resistors R1 and R2 may provide desired differential mode (e.g., when the operation or output of transistor T2 is 180 degrees out of phase with transistor T1) stability to inputs IN1 and IN2 compared to without these resistors, and may provide desired impedance matching to the input and output of each transistor T1 and T2 compared to without these resistors. This stability reduces undesirable changes in power levels, noise output, and / or oscillations of the transistor outputs. Here, resistors R1 and R2 may provide desired shunt resistance to ground (e.g., GNDr1) used for stabilization.

[0050] In some cases, resistor R3 (and optionally a capacitor such as C1 in series with resistor R3) may provide desired common-mode (e.g., the operation or output of transistor T2 is 0 degrees out of phase with or in phase with transistor T1) stability to inputs IN1 and IN2 compared to without these resistors, and may provide desired common-mode impedance matching to the inputs and outputs of each transistor T1 and T2 compared to without these resistors. This stability reduces undesirable changes in power levels, noise output, and / or oscillations of the transistor outputs. Here, resistor R3 may provide desired series feedback (e.g., to components of a chiplet or wafer electrically connected to the transistor outputs) used for common-mode stabilization.

[0051] DC stability and / or impedance matching create a chiplet that is unconditionally stable with respect to signals received on interconnect 155 from the wafer, thereby enabling the active device transistors T1 and T2 of chiplet 130 to be unconditionally stable as well. Stabilization of transistors T1 and T2, as described for transistors, may incorporate lossy components such as resistors R1, R2, and R3, as well as reactive components such as capacitors C1, C2, and inductor L1, to stabilize transistors T1 and T2 over a particular operating frequency band. Stabilization can be applied not only to single transistors, but also to the example of a differential pair of transistors T1 and T2. In this case, both differential and common-mode stability is ensured via network circuit 142 implemented on the active chiplet.

[0052] FIG. 2B is a schematic diagram of the electronic assembly 106 of FIG. 1C , isolating an example of a gain-boosting network circuit 144 of the interconnect tuning circuit 140. The circuit 144 may be a network of electronic circuits having passive circuits including at least one of capacitors C1 and / or C2. The circuit 144 may also include both capacitors C1 and C2. The circuit 144 may optionally include grounds GNDr1 and / or GNDr2. The circuit 142 may optionally include one or more of resistors R1, R2, and / or R3, as shown in FIG. 1C . The circuit 144 may also be a neutralization network to improve the stability of transistors T1 and / or T2 or to introduce positive feedback to transistors T1 and / or T2 to increase the gain of the transistors in the presence of or through interconnects 155 and / or 255 to the wafer.

[0053] In some cases, circuit 144 may include at least one capacitor C1 between input IN2 of transistor T2 and output OUT1 of transistor T1, and at least one capacitor C2 between input IN1 of transistor T1 and output OUT2 of transistor T2, which counteract the parasitic gate-drain capacitances of transistors T1 and T2.

[0054] In some cases, circuit 144 may include at least one resistor R1 and R2 between input IN1 and input IN2, as shown in Figure 1C. Optionally, there may be an inductor L1 between S1 and S2, as shown in Figure 1C.

[0055] Both of these capacitors C1 and C2 may provide desired gain boosting and / or “neutralization” (e.g., electrically isolating the input IN from the output OUT of each of the chiplet's transistors T1 and T2 compared to without the capacitors). Either or both of these capacitors C1 and C2 may provide desired impedance matching of the impedance the transistor sees at its input IN and output OUT from the wafer 110 compared to without the capacitors. In some cases, the network circuit 144 implemented on the active chiplet 130 can achieve a desired specific optimization for the gain of the transistors T1 and T2. For example, both of these capacitors C1 and C2 may provide desired unidirectionality to improve the gain of the transistors by eliminating reverse signal flow through the transistors (e.g., causing S12 = 0) compared to without the capacitors. In other words, each of transistors T1 and T2 can be unidirectionalized so that the reverse isolation (the inverse transfer function from S12-OUT to IN) is zero. Either or both of these cross-coupling capacitors C1 and C2 may provide the desired negative capacitance to cancel the Cgd (gate-to-drain capacitance) of the transistors compared to without the capacitors. When transistor T2 operates in differential mode, 180 degrees out of phase with transistor T1, the cross-coupling capacitors C1 and C2 act as negative capacitors for transistors T1 and T2, thereby canceling the Cgd of each respective transistor compared to without the capacitors. Another gain-boosting technique or circuit (not shown) can also be used to increase the gain beyond the unidirectional gain. The limit for either or both of these gain boosting techniques is to reach 4U (e.g., four times the maximum unidirectional gain of T1 and T2) while remaining unconditionally stable.

[0056] In other embodiments, either or both of these capacitors C1 and C2 may be replaced with an inductor, such as those described herein, between the gate of one of transistors T1 and T2 and the drain of the other of transistors T1 and T2.

[0057] 2C is a schematic top view of electronic assembly 200 isolating example power supply circuits 145, 146, and 147 of interconnected tuned circuit 140 with the passive circuits of chiplets 133, 134, and 135, each having active transistor T1. In some cases, one of power delivery and efficiency circuits 145, 146, or 147 is also on a chiplet with active transistor T2, such as when chiplets 133, 134, and 135 have both transistor T1 as shown in FIG. 2C and transistor T2 with one of circuits 133, 134, or 135 (see, e.g., assembly 106). Each of circuits 145, 146, and 147 may be an example of a power delivery circuit to and from chiplets 133, 134, and 135 via an interconnect network, including via interconnects 155 and / or 255 that introduce impedance matching through interconnects 155 and / or 255 from the wafer to transistor T1, etc.

[0058] More or fewer of the electrical and / or circuit components shown for chiplets 133, 134, and 135, wafer 110, and / or network circuits 133, 134, or 135 may be present. The circuits of chiplets 133, 134, and 135 may be described as having both passive (e.g., R, C, L) and active (e.g., at least transistor T1) devices. Other passive and / or active devices may be present in or on the chiplets. While only three chiplets are shown, there may be many chiplets present within the cavity of wafer 110. There may be tens to thousands of such chiplets present within a wafer.

[0059] Each of chiplets 133, 134, and 135 may represent a version of chiplet 130. Each of circuits 145, 146, or 147 may represent a version of circuit 140.

[0060] Interconnect 255 is an example of an interconnect as described by contact 118, interconnect 155, and contact 138. Electrical interconnect 255 electrically connects wafer circuitry to chiplet circuitry. At the boundary (e.g., sidewall) between the wafer and the chiplet, there may be an interconnect similar to interconnect 255 for each electrical connection required at that boundary.

[0061] In some cases, circuit 145, 146, or 147 may include at least one capacitor C5 or C7 between gate G1 of transistor T1 and ground GNDr1, and at least one capacitor C4 or C6 between drain D1 of transistor T1 and output OUT6 or OUT7 of chiplets 133 and 134.

[0062] Circuit 145 may be an electronic network including at least two capacitors C3 and C4 and two inductors L2 and L3. Inductor L2 is connected between gate G1 and ground GNDr1 and / or other active or passive circuits on wafer 110. Inductor L3 is connected between load LD1 and a node between drain D1 and capacitor C4. Capacitor C3 is connected between input IN6 and a node between inductor L2 and gate G1. Capacitor C4 is connected between drain D1 and output OUT6. Inductor L2 may be used to provide a DC bias to gate G1, and inductor L3 may be used to provide a DC bias to drain D1. Capacitors C3 and C4 may be used to isolate the transistor from other parts of the circuit and / or prevent DC current from flowing into the termination ports.

[0063] The load LD1 may be a 50 ohm load, which is the convention used in the definition of S-parameters that describe the flow of power into and out of a transistor.

[0064] In the illustrated case, inductors L2 and L3 are on wafer 110, perhaps because they are larger in size than the capacitors. In other cases, inductors L2 and L3 are on chiplet 133.

[0065] Inductors L2 and L3 and capacitors C3 and C4 may create an electrical network that improves power delivery and efficiency for transistor T1 (e.g., at output OUT6) by transforming the impedance of the source and / or load into an impedance seen by the transistor that maximizes delivered power or power-added efficiency compared to without the inductors and capacitors. As an impedance transformation network, any of circuits 145, 146, and 147 is an electrical network that takes one impedance (Z1) at one port (such as the circuit's input IN or output OUT) and transforms it into another impedance (Z2) at a second port (such as the other of the circuit's input IN or output OUT). In the case of transistor T1, they may maximize output power (e.g., at output OUT6) under load impedance mismatch (e.g., of LD1) or introduce load modulation for power efficiency under different output power conditions compared to without the inductors and capacitors.

[0066] Circuit 146 may be an electronic network including at least two capacitors C5 and C6 and two inductors L4 and L5. Capacitor C5 is connected between gate G1 and ground GNDr1. Inductor L5 is connected between load LD1 and a node between drain D1 and capacitor C6. Inductor L4 is connected between input IN7 and a node between capacitor C5 and gate G1. Capacitor C6 is connected between drain D1 and output OUT7. Inductor L4 may be used to provide a DC bias to gate G1, and inductor L5 may be used to provide a DC bias to drain D1. Capacitors C5 and C6 may be used to isolate the transistor from other parts of the circuit and / or prevent DC current from flowing into the termination ports.

[0067] In the illustrated case, inductors L4 and L5 are located on wafer 110, perhaps because they are larger in size than the capacitors. In other cases, inductors L4 and L5 are located on chiplet 134.

[0068] Inductors L4 and L5 and capacitors C5 and C6 may provide desired increased power delivery and efficiency for transistor T1 (e.g., at output OUT7) through impedance transformation compared to without the inductors and capacitors. In the case of transistor T1, they may maximize output power (e.g., at output OUT7) under load impedance mismatch (e.g., of LD1) or introduce load modulation for power efficiency under different output power conditions compared to without the inductors and capacitors.

[0069] Circuit 147 may be a network of electronic circuits including at least one capacitor C7 and three inductors L6, L7, and L8. In some cases, capacitor C7 is on the host wafer 110 and not within chiplet 135. Inductor L7 is connected between load LD1 and a node between drain D1 and inductor L8. Inductor L6 is connected between input IN8 and a node between capacitor C7 and gate G1. Inductor L8 is connected between drain D1 and output OUT8.

[0070] In the illustrated case, inductors L6-8 are located on wafer 110, possibly because they are larger in size than the capacitors. In other cases, inductors L6-8 are located on chiplet 135.

[0071] Inductors L6, L7, and L8 and capacitor C7 may provide desired tuning through impedance transformation to improve power delivery and efficiency for transistor T1 (e.g., at output OUT8) compared to without the inductors and capacitors. In the case of transistor T1, they may maximize output power (e.g., at output OUT8) under load impedance mismatch (e.g., of LD1) or introduce load modulation for power efficiency under different output power conditions compared to without the inductors and capacitors. By moving the inductors to the host wafer 110, substantial reductions in cost and time are achieved. In some cases, inductors are cheaper and have fewer defects when formed on the wafer 110 rather than on the chiplets because the wafer is a cheaper and easier-to-process semiconductor material.

[0072] Power delivery and efficiency circuits 145, 146, and 147 may also be used on one or both of transistors T1 and / or T2, as shown in FIG. 1C.

[0073] 2D is a schematic top view of the electronic assembly 106 of FIG. 1C , isolating an example of a low-noise network circuit 148 of the interconnect tuning circuit 140. The circuit 148 may be a network of electronic circuits with a passive circuit including at least one inductor L1. The circuit 148 may include only the inductor L1. In other cases, the circuit 148 includes both the inductor L1 and the capacitor C1 and / or C2. The circuit 148 may be an interconnect tuning circuit with negative feedback, or may be a degeneration network through the interconnects 155 and / or 255, such as found in a low-noise network circuit for tuning transistors T1 and / or T2.

[0074] In some cases, the circuit 148 may include at least one inductor L1 between the source S1 of the transistor T1 and the source S2 of the transistor T2, which may have a value between 5 pH and 500 pH.

[0075] In some cases, circuit 148 may also include at least one capacitor C1 between input IN2 of transistor T2 and output OUT1 of transistor T1, and at least one capacitor C2 between input IN1 of transistor T1 and output OUT2 of transistor T2.

[0076] Inductor L1 may provide the desired tuning for low noise operation while simultaneously matching the transistors for low noise and / or gain matching.

[0077] Inductor L1 can act as a local "ac ground" that prevents ground currents from flowing through the interconnect. By defining the ground on 148, the interconnect does not affect the differential behavior of the circuit.

[0078] In other embodiments, inductor L1 may be replaced by a capacitor, such as capacitor C1, between the sources of transistors T1 and T2. In other embodiments, inductor L1 may be replaced by an AC ground, such as ground GNDr1 or GNDr2.

[0079] In some cases, to accurately apply transistor models, the chiplet's high frequency (AC) ground must be established, such as by GNDr1 and / or GNDr2. Heterogeneous integration adds parasitics that alter the AC ground. An important feature of network 140 is the ability to use differential circuits within the chiplet to establish a local ground. Reactive or resistive source-connected networks, such as either network 140, create a well-defined AC ground.

[0080] FIG. 2E is a schematic top view of an electronic assembly 250 isolating an example of stabilization network circuits 241, 242, and 243 of an interconnected tuned circuit 140 having passive circuits for chiplets 230, 231, and 232, each having an active transistor T1. More or fewer of the electrical and / or circuit components shown for chiplets 230, 231, and 232, wafer 110, and / or stabilization network circuits 241, 242, and 243 may be present. The circuits of chiplets 230, 231, and 232 may be described as having both passive (e.g., R, C, L) and active (e.g., at least transistor T1) devices. Other passive and / or active devices may be present within or on the chiplets. While only three chiplets are shown, numerous chiplets may be present within the cavity of wafer 110. There may be tens to thousands of such chiplets present within a wafer. Each of circuits 241, 242, and 243 may be an isolation stabilization network circuit for chiplets 230, 231, and 232, respectively, in the presence of an interconnect network extending through interconnects 155 and / or 255.

[0081] Each of chiplets 230, 231, and 232 may represent a version of chiplet 130. Each of circuits 241, 242, and 243 may represent a version of circuit 140.

[0082] Circuit 241 may be a network of electronic circuits including at least one resistor R4 between gate G1 and ground GNDr1, and includes an input IN3 electrically coupled to a node between gate G1 and resistor R3, an output OUT3 at drain D1, and a load LD1 at a node between drain D1 and output OUT3.

[0083] Resistor R4 may provide a desired DC bias and DC stability at input IN3 compared to without the resistor. Resistor R4 may provide a desired impedance match at input IN3 and output OUT3 of transistor T1 compared to without the resistor.

[0084] Circuit 242 may be a network of electronic circuits including at least one resistor R5 connected in series with one capacitor C8 between gate G1 and output OUT4. Although the resistor is shown closer to the gate than the capacitor, the order of these components may be reversed. Circuit 242 includes an input IN4 electrically coupled to a node between gate G1 and resistor R5, an output OUT4 at drain D1, and a load LD1 at a node between drain D1, the end of capacitor C8, and output OUT4.

[0085] Resistor R5 and capacitor C8 may provide stabilization across a range of frequencies between input IN4 and / or output OUT4 compared to without the resistor and capacitor. Resistor R5 and capacitor C8 may provide a desired DC and / or AC impedance match at input IN4 and output OUT4 of transistor T1 compared to without the resistor and capacitor. Resistor R5 and capacitor C8 may provide series RC feedback between the gate and drain for DC and / or AC bias compared to without the series RC feedback.

[0086] In some cases, the electrical connection between the output OUT4 and the node between the capacitor C5 and the load LD1 may include passive or active devices.

[0087] Circuit 243 may be a network of electronic circuits including at least one resistor R6 between output OUT5 and load LD1. Circuit 243 includes an input IN5 electrically coupled to gate G1, an output OUT5 at a node between drain D1 and output OUT5, and load LD1 at the end of resistor R6 away from the node between drain D1 and output OUT5.

[0088] Resistor R6 may provide a desired DC bias and DC stability at output OUT5 compared to without the resistor. Resistor R6 may provide a desired impedance match at input IN5 and output OUT5 of transistor T1 compared to without the resistor.

[0089] The DC stability and / or impedance matching of the stabilization network circuits 241, 242, and 243 makes the chiplets 230, 231, and 232 unconditionally stable for signals received on the interconnect 255 from the wafer 110, thereby enabling the active device transistor T1 to also be unconditionally stable. Stabilization of transistor T1 may incorporate lossy components, such as additional resistors, as described for transistors, and reactive components, such as capacitors and / or inductors, to stabilize transistor T1 over a specific operating frequency band. This stabilization can be applied to a differential pair of transistors as well as a single transistor. In this case, both differential and common-mode stability is ensured via the network circuits 241, 242, and 243 implemented on the active chiplets 230, 231, and 232.

[0090] Stabilization network circuits 241, 242, and 243 may also be used on one or both of transistors T1 and / or T2, as shown in Figure 1C. Any of the network circuits in circuit 140 may be an impedance matching network.

[0091] FIG. 2F shows circuits 260-269 having transistors T1 and / or T2 as RF transistors, with an input IN, an output OUT, an AC ground (which may be a DC voltage bias) indicated by a triangle ground symbol, a load LO, a switch control signal S, and an input / output I / O.

[0092] FIG. 2F shows circuits 260 and 261 with transistor T1 as a single-ended RF amplifier with inputs at its gate and source, respectively, and an output at its drain.

[0093] FIG. 2F also shows a circuit 262 with transistors T1 and T2 in a series connection of devices for an RF cascode with an input at the gate of transistor T1 and an output at the drain of transistor T2.

[0094] Next, FIG. 2F also shows circuit 263 with both transistors T1 and T2 as a differential RF amplifier with an input at the gate and an output at the drain of each transistor.

[0095] Here, FIG. 2F also shows circuit 264 with both transistors T1 and T2 as a frequency multiplier with inputs at the gates of each transistor and outputs tied to the drains of both transistors.

[0096] Additionally, FIG. 2F also shows circuit 266 with two sets of transistors T1 and T2 as a total of four transistors on a single chiplet as an RF FET ring mixer or provider of frequency conversion with two inputs IN1 and IN2, two outputs OUT1 and OUT2, and two loads LO1 and LO2.

[0097] Next, FIG. 2F also shows a circuit 267 having a transistor T1 as an RF switch transistor for an RF switch or mixer with an input at its source, a switch control signal S1 at its gate, and an output at its drain.

[0098] FIG. 2F also shows a circuit 268 having transistors T1 and T2 in series as an RF switch transistor for an RF switch or mixer with an input output I / O at the drain of each transistor and a switch control signal at the gate of each transistor.

[0099] Finally, FIG. 2F also shows a circuit 269 having transistors T1 and T2 as part of an RF switch transistor for an RF switch or mixer with an input at the source of transistor T1, an output at the drains of transistors T1 and T2, and a switch control signal at the gate of each transistor.

[0100] Any of the tuning circuits 140-148 and / or 241-243, such as those shown in FIGS. 1C and 2A-2E, may be applied to any of the circuits 260-269. Chiplets exhibiting gains such as those illustrated in 260-263 require stabilization networks to ensure robust operation in the presence of interconnects to the tuning circuits. Chiplets producing power such as those illustrated in 260-264 have improved performance with tuning networks such as those illustrated by the examples 140-148 and / or 241-243 that produce the desired fundamental or harmonic tuning networks. Switching networks including mixers and RF switches, such as those illustrated in 265-269, can benefit from the network technology of FIG. 1C to prevent signal power loss on the chiplets and, in some cases, loss due to the interconnect network.

[0101] 3A is a schematic cross-sectional view of a device 300 having heterogeneous integration of radio frequency (RF) transistor chiplets 130 within a wafer 110, the chiplets having interconnected tuning circuits 140. Device 300 may include one or more of any or all of the devices of FIGS.

[0102] The device 300 may be an electronic assembly having an encapsulation material layer 370 having a top surface 372 and a back surface 374. The device 300 has a host wafer 110 having a back surface 112 and a front surface 114, with the back surface 112 of the wafer bonded to the top surface 372 of the encapsulation material layer 370, except for a cavity 120 in the wafer 110 formed across multiple regions 376 of the top surface 372. The cavity may extend from the back surface 112 through the wafer to the front surface 114. The cavity has side surfaces 116. The back surface 112 of the wafer may be directly attached to and in contact with the top surface 372. The bond between the back surface 112 and the top surface 372 may be a covalent bond, a chemical bond, or an atomic bond.

[0103] The chiplet 130 has a backside 134 and a frontside 132, and the backside 134 of the chiplet 130 is directly bonded to at least portions 378 of multiple regions 376 on a top surface 372 of the encapsulation material layer. The portions 378 may be the footprint of the chiplet 130 on the top surface 372 within the cavity 120. A gap 350 between the sides 116 and 136 may be the difference between the regions 376 and the portions 378. The backside 134 may be directly attached to and in contact with the top surface 372. The bond between the backside 134 and the top surface 372 may be a covalent bond, a chemical bond, or an atomic bond.

[0104] Cavity 120 may be a through-substrate hole or may be a through-substrate hole etched into the wafer in area 376. Chiplets 130 may be embedded in wafer 110 in the substrate hole or cavity 120.

[0105] The lateral material 360 extends between the side surface 136 of the chiplet 130 and the side surface 116 of the wafer or cavity. The lateral material 360 may mechanically and chemically bond the side surface 136 of the chiplet 130 to the side surface 116 of the wafer. The lateral material 360 may form a mechanical and / or chemical bond to the side surface 136 and the side surface 116. In some cases, the lateral material 360 is a molding compound and the bond is a mechanical-chemical bond.

[0106] Material 360 may be a dielectric material. Material 360 may not be a metal and may be an electrical insulator. Material 360 may be or include a material that is not electrically conductive, may not be a semiconductor, may be a plastic, may not be an alloy, or may be a biomaterial. Material 360 may be an epoxy. Material 360 may be an electrically insulating epoxy with electrically insulating particles. Material 360 may be an epoxy with silica or SiO2 particles.

[0107] In other cases, lateral material 360 is not a dielectric material. In these cases, lateral material 360 may be a metal, conductor, alloy, or semiconductor. Material 360 may be epoxy. Material 360 may be conductive epoxy with conductive particles. Material 360 may be epoxy with metal particles. In these cases, a dielectric layer or space (e.g., air) exists between material 360 and interconnects 155 and / or 255.

[0108] Lateral material 360 is disposed in gaps 350 between each side surface 136 of a chiplet 130 and the corresponding side surface 116 of the wafer cavity in which each chiplet 130 is disposed. Gap 350 has a width gw that is 1 / 5 (one-fifth) to 10 times the thickness tw of wafer 110 or chiplet 130.

[0109] The thickness tw of the wafer may be between 20 and 200 microns, may be between 50 and 125 μm, or may be 75 μm. The thickness of one, many, or all of the chiplets may be the same as the thickness of the wafer.

[0110] The thickness te of the encapsulating material layer may be 3 to 100 microns, or 5 to 25 microns, or 15 μm.

[0111] Each chiplet 130 has three to six sides, or may have four sides. The sides may have a straight, curved, or wavy profile when viewed from a top perspective. The cavity 120 may have the same number of sides corresponding to the shape of the sides of the chiplets 130.

[0112] Encapsulating material layer 370 may be a highly thermally conductive backside metallization layer that improves heat transfer from chiplets 130 to wafer 110. Layer 370 may also be a thermal plane that improves heat transfer away from chiplets 130 by increasing heat transfer from chiplets 130 to layer 370 and / or wafer 110. Layer 370 is a material in direct contact with chiplets 130 that enhances thermal conduction between the material of chiplets 130 and the material of layer 370. In some cases, encapsulating material layer 370 has a thermal expansion coefficient that is one or more of the thermal expansion coefficients of wafer 110 and chiplets 130.

[0113] In other cases, the encapsulation material layer 370 is not present and the chiplets 130 are bonded to the wafer 110 using lateral material. The chiplets 130 may also be bonded to the wafer 110 using only lateral material.

[0114] The interconnects 155 may be formed directly on the lateral material 360 or may be formed thereon (e.g., formed on a dielectric or air gap) and may connect the electrical (e.g., power, ground, and / or signal) contacts 138 of the chiplets 130 to the contacts 118 of the wafer 110. The interconnects 155 may be formed directly on the lateral material (e.g., without a dielectric / air gap) and may include direct interconnect routing or traces extending from the chiplet contacts 138 to the wafer contacts 118 and electrical routing. The interconnect routing 155 may include low-loss, high-performance DC, RF, and mm-wave routing from the chiplet contacts 138 directly onto the lateral material 360 and to the wafer contacts 118. The interconnects 155 may be directly on the material 360 by being bonded and / or directly attached (e.g., contacting) to the top surface of the lateral material 360.

[0115] In some cases, wafer 110 includes an electronic integrated circuit (not shown), at least one integrated circuit contact 118 (e.g., a contact pad) formed on the wafer front side 114, and at least one through-wafer cavity 120 having a side surface 116 that joins the backside 112 to the front side 114. In some cases, chiplets 130 are held within through-wafer cavity 120 by lateral material 360 that attaches at least one side surface 116 of through-wafer cavity 120 to at least one side surface 136 of chiplet 130. In some cases, lateral material 360 fills cavity gaps 350, thereby attaching a majority of the side surface 136 of chiplet 130 to the side surface 116 of through-wafer cavity 120. However, material 360 does not attach backside 134 of chiplet 130 to top surface 372 of layer 370.

[0116] A passivation layer (not shown) may be disposed over most of the front surface 114 of the wafer 110. Conductive vias (e.g., TWVs) disposed through the passivation layer may connect active and / or passive circuitry of the wafer 110 to contacts 118 (e.g., contact pads) on the front surface 114. The wafer 110 may be a silicon wafer or substrate, allowing for utilization of known manufacturing processes and manufacturability for large wafer diameters.

[0117] It should be noted that wafer 110 can include any integrated circuits (active or passive) enabled by the selected fabrication process (e.g., a CMOS fabrication process). In some cases, the thickness of one or more integrated circuit layers can be, for example, a small fraction of the thickness t of wafer 110 (e.g., between 1 / 10 and 1 / 1000 of the thickness of wafer 110, e.g., a 50 nm thick, 50 μm thick wafer). In some cases, the thickness of wafer 110 can be reduced after fabrication of integrated circuits on the wafer, for example, before etching through-wafer cavities 120 or after filling gaps 350 with lateral material 360.

[0118] The chiplet 130 may include one or more transistors having terminals connected to at least one integrated circuit contact 138 (e.g., a contact pad) by, for example, a conductive via (not shown). The chiplet 130 may include a substrate and an integrated circuit layer formed on the substrate, with the integrated circuit layer having a thickness that is, for example, a small fraction of the thickness of the substrate (e.g., 1 / 10 to 1 / 1000 of the thickness of the substrate). In some cases, the overall thickness of the chiplet 130 is less than the overall thickness of the host wafer 110. In some cases, the lateral material 360 contacts the side surface 136 of the chiplet 130 along a majority of its height (at least 50% of the height starting near the top surface of the chiplet 130). Preferably, the lateral material 360 contacts essentially all of the side surface 136 of the chiplet 130. Preferably, the lateral material 360 completely fills the gap 350 to a level that is essentially flush with the front surface 114 of the host wafer 110.

[0119] In some cases, side surface material 360 and / or layer 370 hold chiplet 130 such that chiplet front side 132 is flush with front surface 114. "Flush" may be understood to mean that two surfaces are in the same plane or have a small or negligible height difference relative to one another. The two surfaces may be flush, such as resulting from a process that permanently attaches chiplet 130 to side surface 116 of through-wafer cavity 120, with both chiplet front side 132 and front surface 114 temporarily attached to adhesive laminate 340. The two surfaces may also be flush, such as resulting from polishing or CMP of those surfaces after temporarily removing adhesive laminate 340.

[0120] It is contemplated that the host wafer 110 may be vertically diced at dicing lines (indicated by vertical bars in Figures 3A and 3B) along the perimeter 386 of the wafer around at least one chiplet to form a chip having at least one chiplet and an area of ​​the wafer surrounding the at least one chiplet.

[0121] 3A and 3B may show how interconnect structures 155 and 255 may be placed directly on and contact lateral material 360 or other dielectric material between chiplets 130 and wafer 110. Electrical interconnects electrically connect passive devices on the wafer with transistors on the chiplets. The interconnects between chiplets and wafers may mistune transistors, such as by introducing mismatches in stability, AC signals, DC signals, impedance, frequency, and / or reactivity of other electronic signals matching the input and / or output to the chiplets or transistors on the chiplets. To avoid this mistuning, on-chiplet networks have provided robust characteristics. An advantage of any one or more of the interconnect tuning circuits 140 is that they reduce this electrical mistuning of passive devices and transistors caused by electrical interconnects, which can affect circuit performance, reducing uncertainty in the electrical interconnects and improving circuit performance.

[0122] Chiplets 130 are also preferably pre-tested to verify their functionality and / or performance, resulting in significantly improved yields for the final device 300 or diced devices over the integration of component chips where component functionality is not verified until after integration.

[0123] Advantageously, by allowing different electrical components of a chiplet 130 to be fabricated separately from one another from the wafer 110, the chiplets 130 and their electronic components on the wafer 110 can be tested separately before assembly. If the manufacturing yield of a particular electrical component chiplet 130 or one of the components of the wafer 110 is low, the component can be replaced to improve the manufacturing yield of the assembled electrical component to produce a finished product device 300 or die thereof that includes the chiplet 130 together within the cavity of the wafer 110. For example, if the manufacturing yield of an electrical component of a particular chiplet type of chiplet 130 is low, that component can be rejected and replaced with a different chiplet to improve the manufacturing yield of that electrical component chiplet type and produce a finished product device 300 or die thereof that includes the chiplet 130 and wafer 110 without spending the time and expense of remanufacturing the entire assembly of the wafer 110.

[0124] Furthermore, because embodiments allow different electrical components of chiplet 130 to be fabricated separately from each other from wafer 110, all of the component types of chiplet 130 and wafer 110 do not need to be subjected to steps in the fabrication of all the different electrical components of chiplet 130 that could potentially damage other components of chiplet 130 or wafer 110.

[0125] Thus, embodiments can reduce manufacturing costs by using small component chips in chiplets 130 that have specific functions and are made of specialized, expensive materials in combination with integrated circuits in other chiplets 130 and / or wafer 110 that have more general functions and are made of less expensive, general materials.

[0126] According to embodiments, chiplets 130 may include GaN, InP, or GaAs electrical components and may be fabricated on substrates such as Si, SiGe, InP, GaAs, alumina, or diamond. In some cases, the electrical components or integrated circuits of host wafer 110 may include metal routing and passive components fabricated on a wafer scale. In some cases, interconnects 155 may be fabricated using conductors made from thin films, thick plated interconnects, multilayers, etc. The interconnects may also be fabricated using, for example, back-end steps of the manufacturing process.

[0127] 3B is a schematic cross-sectional view of a device 301 having heterogeneous integration of radio frequency (RF) transistor chiplets 130 on a wafer 310, with the chiplets having interconnected tuning circuits 140. Device 301 may include one or more of any or all of the devices of FIGS. 1A-2F. Compared to wafer 110, wafer 310 does not have cavity 120, but instead has chiplets attached to the top surface of wafer 310.

[0128] In this embodiment, the chiplets 130 are mounted or bonded to the top surface 114 of the wafer 310 rather than in the cavities 120. In this case, there may be no cavities for the chiplets. The interconnects 155 and 255 between the chiplets and the wafer are on or above the side surface 136 rather than on or above the side surface material 360. However, the interconnects may have the same mistuning as mentioned. Note that the above concepts also apply with respect to the presence of the interconnects 155 and 255 between the chiplets and the wafer, the mistuning of those interconnects, the various interconnect tuning circuits 140 for those interconnects, and the problems and advantages provided by the interconnect tuning circuits as described herein. [Example]

[0129] (Example)

[0130] Examples of the technology herein include an electronic assembly for heterogeneous integration of radio frequency (RF) transistor chiplets with interconnections to or between tuning circuits, the assembly comprising: a host wafer having a first circuit including a passive device intended for one of a tuning or matching network; at least one chiplet having a second circuit including at least two RF transistors or two RF switch devices and a passive tuning circuit for each of the at least two RF transistors or two RF switch devices, each passive tuning circuit including at least one of a stabilization network, a gain boosting network, a power delivery network, or a low noise network; and an electrical interconnect between the chiplet and the wafer, the electrical interconnect electrically connecting the first circuit to the second circuit.

[0131] Examples include the RF transistor device operating in or being part of one of a single-ended amplifier, a differential amplifier, a balanced amplifier, a Doherty amplifier, connected via parallel devices with separate gate or base connections for frequency multiplication, a ring of devices for frequency mixing, or multiple devices to form an RF switch.

[0132] An embodiment includes an interconnect electrically connecting a passive device and a transistor, and a passive tuning circuit reducing electrical mistuning of the transistor caused by the electrical interconnect, which degrades transistor performance and increases uncertainty in circuit operation.

[0133] Examples include each transistor device having a gate, a source, and a drain, each transistor device having an input at the gate and an output at the drain, a first transistor device of each chiplet being a first RF amplifier and having a first signal phase output of the differential amplifier, and a second transistor device of each chiplet being a second RF amplifier and having a second signal phase output of the differential amplifier, the second signal phase being 180 degrees out of phase with the first signal phase.

[0134] An embodiment includes the stabilization network including: a) a first resistor between a first input of the first transistor device and a bias node; and a second resistor between a second input of the second transistor device and the bias node, the node being to a first AC ground and a DC voltage that provides a first DC bias for the first input and the second input; and b) a resistor between the node and a second AC ground and a DC voltage that provides a second DC bias for the first input and the second input.

[0135] Embodiments include where the unilateralizing or gain boosting network includes: a) at least one capacitor between the first input of the first transistor and the second output of the second transistor; and b) at least one capacitor between the second input of the second transistor and the first output of the first transistor.

[0136] Embodiments include the power delivery network including: a) at least one capacitor between the gate of the first transistor and a first AC ground and a DC voltage providing a first DC bias to the gate of the first transistor; and b) at least one capacitor between the drain of the first transistor and an output of the first chiplet.

[0137] An embodiment includes the low noise network including at least one inductor between the source of the first transistor and the source of the second transistor.

[0138] Examples include the wafer including at least one of resistors, capacitors, inductors, through-substrate vias, dielectric layers, and metal layers; the wafer including at least one layer of silicon (Si), silicon dioxide (SiO2), silicon carbide (SiC), quartz, or gallium arsenide; each chiplet including at least two RF transistors and interconnects from the transistors to contact pads on the front surface of the chiplet; and each chiplet being a high-end pre-fabricated transistor chiplet.

[0139] Examples of the technology herein include an electronic circuit device comprising: a host wafer having a first circuit including a passive device intended for one of a tuning or matching network; a plurality of chiplets, each of the chiplets having a second circuit including two radio frequency (RF) transistor devices and a passive tuning circuit for each of the two RF transistor devices, each of the passive tuning circuits including at least one of a stabilization network, a gain boosting network, a power delivery network, or a low noise network; and an electrical interconnect between the chiplets and the wafer, electrically connecting the first circuit to the second circuit.

[0140] Examples include the RF transistor device being part of one of the following: a differential or balanced amplifier, a parallel device with separate gate and base connections for frequency multiplication, a ring of devices for frequency conversion, or an RF switch network.

[0141] An embodiment includes an interconnect electrically connecting a passive device and a transistor, and a tuning circuit reducing electrical mistuning of the transistor caused by the electrical interconnect, which degrades transistor performance and increases uncertainty in circuit operation.

[0142] Examples include each transistor device having a gate, a source, and a drain, a first transistor device of each chiplet being a first RF amplifier and having a first signal phase output of the differential amplifier, and a second transistor device of each chiplet being a second RF amplifier and having a second signal phase output of the differential amplifier, the second signal phase being 180 degrees out of phase with the first signal phase.

[0143] 14. The electronic circuit device of claim 13, wherein the stabilization network includes: a) a first resistor between a first input of the first transistor device and a node; and a second resistor between a second input of the second transistor device and a node, the node being relative to a first AC ground and a DC voltage providing a first DC bias for the first input and the second input; b) a resistor between the node and a second AC ground and a DC voltage providing a second DC bias for the first input and the second input; the gain boosting network includes: a) at least one capacitor between the first input of the first transistor and the second output of the second transistor; and b) at least one capacitor between the second input of the second transistor and the first output of the first transistor; the power delivery network includes: a) at least one capacitor between a gate of the first transistor and the first AC ground and a DC voltage providing a first DC bias for the gate of the first transistor; and b) at least one capacitor between a drain of the first transistor and the output of the first chiplet; and the low noise network includes at least one inductor between a source of the first transistor and a source of the second transistor.

[0144] An embodiment includes a host wafer having a front side and a back side and a cavity formed in the wafer through a plurality of regions of the top surface of the host wafer, the cavity having a side of the wafer, a plurality of chiplets having a back side and a front side disposed within the cavity, and the host wafer being diced vertically along the periphery of the wafer around at least one chiplet to form a chip having at least one chiplet and a region of the wafer surrounding the at least one chiplet.

[0145] Examples of the technology herein include a method of forming an electronic assembly for heterogeneous integration of radio frequency (RF) transistor chiplets with interconnections to or between tuning circuits, the method including: bonding to an encapsulation layer a host wafer having a first circuit including passive devices for one of a tuning or matching network; bonding to the encapsulation layer at least one chiplet having a second circuit including at least two RF transistors or two RF switch devices and a passive tuning circuit for each of the at least two RF transistors or two RF switch devices, each passive tuning circuit including at least one of a stabilization network, a gain boosting network, a power delivery network, or a low noise network; and forming electrical interconnections between the chiplet and the wafer, the electrical interconnections electrically connecting the first circuit to the second circuit.

[0146] Examples include the RF transistor device operating in or being part of one of a single-ended amplifier, a differential amplifier, a balanced amplifier, a Doherty amplifier, connected via parallel devices with separate gate or base connections for frequency multiplication, a ring of devices for frequency mixing, or multiple devices to form an RF switch.

[0147] Examples include an interconnect electrically connecting a passive device to a transistor, and a passive tuning circuit reducing electrical mistuning of the transistor caused by the electrical interconnect, which degrades transistor performance and increases uncertainty in circuit operation.

[0148] Examples include each transistor device having a gate, a source, and a drain, each transistor device having an input at the gate and an output at the drain, a first transistor device of each chiplet being a first RF amplifier and having a first signal phase output of the differential amplifier, and a second transistor device of each chiplet being a second RF amplifier and having a second signal phase output of the differential amplifier, the second signal phase being 180 degrees out of phase with the first signal phase.

[0149] An embodiment includes the stabilization network including: a) a first resistor between a first input of the first transistor device and a node; and a second resistor between a second input of the second transistor device and a node, the node being relative to a first AC ground and a DC voltage providing a first DC bias for the first input and the second input; b) a resistor between the node and a second AC ground and a DC voltage providing a second DC bias for the first input and the second input; the gain boosting network including: a) at least one capacitor between the first input of the first transistor and the second output of the second transistor; and b) at least one capacitor between the second input of the second transistor and the first output of the first transistor; the power delivery network including: a) at least one capacitor between a gate of the first transistor and the first AC ground and a DC voltage providing a first DC bias for the gate of the first transistor; and b) at least one capacitor between a drain of the first transistor and an output of the first chiplet; and the low noise network including at least one inductor between a source of the first transistor and a source of the second transistor.

[0150] Examples include the wafer including at least one of resistors, capacitors, inductors, through-substrate vias, dielectric layers, and metal layers; the wafer including at least one layer of silicon (Si), silicon dioxide (SiO2), silicon carbide (SiC), quartz, or gallium arsenide; each chiplet including at least two RF transistors and interconnects from the transistors to contact pads on the front surface of the chiplet; and each chiplet being a high-end pre-fabricated transistor chiplet.

[0151] An embodiment includes a host wafer having a front side and a back side and a cavity formed in the wafer through multiple regions of the top surface of the host wafer, the cavity having a side surface of the wafer, the at least one chiplet being a plurality of chiplets, each chiplet having a back side and a front side disposed within the cavity, each chiplet having a second circuit, and further including forming a lateral material between the side surface of the chiplet and the cavity side surface of the wafer, the lateral material bonding the side surface of the chiplet to the cavity side surface of the wafer, and an electrical interconnect between the chiplet and the wafer above the lateral material.

[0152] An embodiment further includes dicing the electronic assembly vertically along the periphery of the wafer around the at least one chiplet to form chips each having at least one chiplet, interconnects, and an area of ​​the wafer surrounding the at least one chiplet.

[0153] (Conclusion)

[0154] Throughout this description, the embodiments and examples shown should be considered exemplars, not limitations, on the devices and procedures disclosed or claimed. While many of the examples presented herein include specific combinations of method acts or system elements, it should be understood that those acts and their elements can be combined in other ways to achieve the same purpose. With respect to flowcharts, additional steps may be included or fewer steps may be performed, and the steps shown may be combined or further modified to achieve the methods described herein. Acts, elements, and features discussed only in connection with one embodiment are not intended to be excluded from a similar role in other embodiments.

[0155] As used herein, "plurality" means two or more. As used herein, a "set" of items may include one or more of such items. As used herein, whether in the written specification or claims, terms such as "comprising," "including," "having," "containing," "involving," and the like, are to be understood as open, i.e., including, but not limited to, terms such as "comprising," "including," "having," "containing," "involving," and the like. With respect to the claims, only the transitional phrases "consisting of" and "consisting essentially of," respectively, are closed or semi-closed transitional phrases. The use of ordinal numbers such as "first," "second," "third," etc. to modify claim elements in the claims does not, of itself, imply any priority, precedence, or ordering of a claim element relative to other elements, nor any chronological order in which the actions of a method are performed, but is merely used as a label to distinguish claim elements with a certain name from other elements with the same name (other than the use of ordinal numbers). As used herein, "and / or" means that the listed items are alternative forms, but that these alternative forms also include any combination of the listed items.

Claims

1. 1. An electronic assembly for heterogeneous integration of radio frequency (RF) transistor chiplets with interconnections to or between tuning circuits, said assembly comprising: a host wafer having a first circuit including passive devices intended for one of a tuning or matching network; at least one chiplet having a second circuit including at least two RF transistors or two RF switch devices and a passive tuning circuit for each of the at least two RF transistors or two RF switch devices, each passive tuning circuit including at least one of a stabilization network, a gain boosting network, a power delivery network, or a low noise network; an electrical interconnect between the chiplet and the wafer, the electrical interconnect electrically connecting the first circuit to the second circuit; An electronic assembly comprising:

2. 10. The electronic assembly of claim 1, wherein the RF transistor device operates in and is part of one of a single-ended amplifier, a differential amplifier, a balanced amplifier, a Doherty amplifier connected via parallel devices with separate gate or base connections for frequency multiplication, a ring of devices for frequency mixing, or multiple devices to form an RF switch.

3. the interconnect electrically connects the passive device and the transistor; 10. The electronic assembly of claim 1, wherein the passive tuning circuit reduces electrical mistuning of the transistor caused by the electrical interconnections that degrade transistor performance and increase uncertainty in circuit operation.

4. 10. The electronic assembly of claim 1, wherein each transistor device has a gate, a source, and a drain, each transistor device having an input at the gate and an output at the drain, a first transistor device of each chiplet is a first RF amplifier and has a first signal phase output of a differential amplifier, and a second transistor device of each chiplet is a second RF amplifier and has a second signal phase output of the differential amplifier, the second signal phase being 180 degrees out of phase with the first signal phase.

5. 5. The electronic assembly of claim 4, wherein the stabilization network includes: a) a first resistor between a first input of the first transistor device and a bias node; a second resistor between a second input of the second transistor device and the bias node, the node being to a first AC ground and a DC voltage that provides a first DC bias for the first input and the second input; and b) a resistor between the node and a second AC ground and a DC voltage that provides a second DC bias for the first input and the second input.

6. 5. The electronic assembly of claim 4, wherein the unilateralizing or gain-boosting network includes: a) at least one capacitor between the first input of the first transistor and the second output of the second transistor; and b) at least one capacitor between the second input of the second transistor and the first output of the first transistor.

7. 5. The electronic assembly of claim 4, wherein the power delivery network includes: a) at least one capacitor between the gate of the first transistor and a first AC ground; and a DC voltage providing a first DC bias to the gate of the first transistor; and b) at least one capacitor between the drain of the first transistor and an output of a first chiplet.

8. 5. The electronic assembly of claim 4, wherein the low noise network includes at least one inductor between the source of the first transistor and the source of the second transistor.

9. 10. The electronic assembly of claim 1, wherein the wafer includes at least one of resistors, capacitors, inductors, through-substrate vias, a dielectric layer, and a metal layer; the wafer includes at least one layer of silicon (Si), silicon dioxide (SiO2), silicon carbide (SiC), quartz, or gallium arsenide; each chiplet includes at least two RF transistors and the interconnects from the transistors to contact pads on a front surface of the chiplet; and each chiplet is a high-end pre-fabricated transistor chiplet.

10. a host wafer having a first circuit including passive devices intended for one of a tuning or matching network; a plurality of chiplets, each of the chiplets having a second circuit including two radio frequency (RF) transistor devices and a passive tuning circuit for each of the two RF transistor devices, each of the passive tuning circuits including at least one of a stabilization network, a gain boosting network, a power delivery network, or a low noise network; an electrical interconnect between the chiplet and the wafer, the electrical interconnect electrically connecting the first circuit to the second circuit; An electronic circuit device comprising:

11. 11. The electronic circuit device of claim 10, wherein the RF transistor device is part of one of a differential or balanced amplifier, a parallel device with separate gate and base connections for frequency multiplication, a ring of devices for frequency translation, or an RF switch network.

12. the interconnect electrically connects the passive device and the transistor; 11. The electronic circuit device of claim 10, wherein the tuning circuit reduces electrical mistuning of the transistor caused by the electrical interconnects, which degrades transistor performance and increases uncertainty in circuit operation.

13. 11. The electronic circuit device of claim 10, wherein each transistor device has a gate, a source, and a drain, a first transistor device of each chiplet is a first RF amplifier and has a first signal phase output of a differential amplifier, and a second transistor device of each chiplet is a second RF amplifier and has a second signal phase output of the differential amplifier, the second signal phase being 180 degrees out of phase with the first signal phase.

14. the stabilization network includes: a) a first resistor between a first input of the first transistor device and a node; a second resistor between a second input of the second transistor device and the node, the node being to a first AC ground and a DC voltage providing a first DC bias for the first input and the second input; and b) a resistor between the node and a second AC ground and a DC voltage providing a second DC bias for the first input and the second input; the gain boosting network includes: a) at least one capacitor between the first input of the first transistor and the second output of the second transistor; and b) at least one capacitor between the second input of the second transistor and the first output of the first transistor; the power delivery network includes: a) at least one capacitor between the gate of the first transistor and a first AC ground; and a DC voltage providing a first DC bias to the gate of the first transistor; and b) at least one capacitor between the drain of the first transistor and an output of a first chiplet; 14. The electronic circuit device of claim 13, wherein the low noise network includes at least one inductor between the source of the first transistor and the source of the second transistor.

15. the host wafer having a front surface and a back surface, and a cavity formed in the wafer through a plurality of regions of the top surface of the host wafer, the cavity having a side surface of the wafer; the plurality of chiplets having a backside and a frontside disposed within the cavity; 11. The electronic circuit device of claim 10, wherein the host wafer is diced vertically along a periphery of the wafer around at least one chiplet to form a chip having the at least one chiplet and an area of ​​the wafer surrounding the at least one chiplet.

16. 1. A method of forming an electronic assembly for heterogeneous integration of radio frequency (RF) transistor chiplets with interconnections to or between tuning circuits, comprising: bonding a host wafer having a first circuit including passive devices for one of a tuning or matching network to the encapsulation layer; bonding at least one chiplet having a second circuit including at least two RF transistors or two RF switch devices and a passive tuning circuit for each of the at least two RF transistors or two RF switch devices to the encapsulation layer, each passive tuning circuit including at least one of a stabilization network, a gain boosting network, a power delivery network, or a low noise network; forming electrical interconnects between the chiplets and the wafer, the electrical interconnects electrically connecting the first circuit to the second circuit; A method comprising:

17. 17. The method of claim 16, wherein the RF transistor device operates in and is part of one of a single-ended amplifier, a differential amplifier, a balanced amplifier, a Doherty amplifier connected via parallel devices with separate gate or base connections for frequency multiplication, a ring of devices for frequency mixing, or multiple devices to form an RF switch.

18. the interconnect electrically connects the passive device and the transistor; 17. The method of claim 16, wherein the passive tuning circuit reduces electrical mistuning of the transistor caused by the electrical interconnections that degrade transistor performance and increase uncertainty in circuit operation.

19. 17. The method of claim 16, wherein each transistor device has a gate, a source, and a drain, each transistor device having an input at the gate and an output at the drain, a first transistor device of each chiplet is a first RF amplifier and has a first signal phase output of a differential amplifier, and a second transistor device of each chiplet is a second RF amplifier and has a second signal phase output of the differential amplifier, the second signal phase being 180 degrees out of phase with the first signal phase.

20. the stabilization network includes: a) a first resistor between a first input of the first transistor device and a node; a second resistor between a second input of the second transistor device and the node, the node being to a first AC ground and a DC voltage providing a first DC bias for the first input and the second input; and b) a resistor between the node and a second AC ground and a DC voltage providing a second DC bias for the first input and the second input; the gain boosting network includes: a) at least one capacitor between the first input of the first transistor and the second output of the second transistor; and b) at least one capacitor between the second input of the second transistor and the first output of the first transistor; the power delivery network includes: a) at least one capacitor between the gate of the first transistor and a first AC ground; and a DC voltage providing a first DC bias to the gate of the first transistor; and b) at least one capacitor between the drain of the first transistor and an output of a first chiplet; 17. The method of claim 16, wherein the low noise network includes at least one inductor between the source of the first transistor and the source of the second transistor.

21. 17. The method of claim 16, wherein the wafer includes at least one of resistors, capacitors, inductors, through-substrate vias, a dielectric layer, and a metal layer; the wafer includes at least one layer of silicon (Si), silicon dioxide (SiO2), silicon carbide (SiC), quartz, or gallium arsenide; each chiplet includes at least two RF transistors and the interconnects from the transistors to contact pads on a front surface of the chiplet; and each chiplet is a high-end pre-fabricated transistor chiplet.

22. the host wafer having a front surface and a back surface, and a cavity formed in the wafer through a plurality of regions of the top surface of the host wafer, the cavity having a side surface of the wafer; the at least one chiplet is a plurality of chiplets, each chiplet having a backside and a frontside disposed within the cavity, each of the chiplets having the second circuit; forming a lateral material between a side surface of the chiplet and a side surface of the cavity of the wafer, the lateral material bonding the side surface of the chiplet to the side surface of the cavity of the wafer; The method of claim 16 , wherein the electrical interconnect is between the chiplet and the wafer above the lateral material.

23. 17. The method of claim 16, further comprising: dicing the electronic assembly vertically along a periphery of the wafer around the at least one chiplet to form chips each having at least one chiplet, the interconnects, and an area of ​​the wafer surrounding the at least one chiplet.

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