Chip hybrid simulation method based on common verification methodology and image processing algorithm

Abstract

This application discloses a chip hybrid simulation method based on a common verification methodology and an image processing algorithm. The method includes the steps of: launching a verification platform after receiving a chip simulation task; inputting Excite data into a design module under test and performing simulation processing on the target chip to obtain simulation output data; sending the simulation output data and Excite data to an image processing model for processing; performing format conversion on the simulation output data and Excite data to obtain a simulation data stream and an Excite data stream; processing the Excite data stream to obtain an image algorithm output data stream; and comparing the simulation data stream with the image algorithm output data stream to obtain a verification result. This application solves the problem that the method for performing simulation verification on a chip in the related art isolates the interconnection and connectivity between the image algorithm model and the UVM simulation verification platform, which is prone to data errors and errors in the algorithm processing flow, and further reduces the simulation efficiency and accuracy of the UVM platform.

Description

[Technical Field]

[0001] [CROSS-REFERENCE TO RELATED APPLICATIONS] This application claims priority from a Chinese patent application filed with the China Patent Office on December 29, 2023, bearing application number 202311862988.8 and entitled "Chip hybrid simulation method based on common verification methodology and image processing algorithm," the entire contents of which are incorporated herein by reference.

[0002] [Technical field] The present application relates to the technical field of chip simulation control, and in particular to a chip hybrid simulation method based on a common verification methodology and image processing algorithm. [Background technology]

[0003] In the chip field, more and more consumer electronic products (e.g., PCs, laptops, tablet PCs, displays, TVs, etc.) require image processing and optimization to achieve more perfect display effects, reduce power consumption, and improve refresh rates.

[0004] To ensure the timely delivery of electronic products, high quality, high stability, and high efficiency of chips have become the competitive advantages of various electronic products. As the image resolution of display screens becomes larger and the speed becomes faster, the image processing algorithms become more complex, bringing unprecedented efficiency and accuracy problems to chip front-end simulation verification work.

[0005] Traditionally, simulation verification of image processing chips has typically been performed using the following method: After researching a specific image processing algorithm, algorithm engineers create an algorithm model in a programming language (e.g., C, Python, MATLAB, etc.) to verify the algorithm and output the algorithm data. Chip verification engineers then build a UVM simulation verification platform to simulate the module under test (DUT) and output the simulation data. Finally, a one-to-one comparison of the two data sets is performed to obtain a comparison result for the entire design. This chip verification method isolates the interconnectivity and connectivity between the algorithm model and the UVM simulation verification platform, which can lead to data errors and errors in the algorithm processing flow, reducing the efficiency and accuracy of the UVM platform's simulation and making it difficult to multiplex and accelerate subsequent test cases.

[0006] In the above related art, the method for performing simulation verification on a chip isolates the interconnectivity and connectivity between the image algorithm model and the UVM simulation verification platform, which is prone to causing data errors and errors in the algorithm processing flow, and further reduces the simulation efficiency and accuracy of the UVM platform. To address this problem, no effective solution has yet been proposed. Summary of the Invention [Problem to be solved by the invention]

[0007] The embodiments of the present application provide a chip hybrid simulation method based on a common verification methodology and image processing algorithm to solve the problem that, at least in related art, the method for performing simulation verification on a chip isolates the interconnectivity and connectivity between the image algorithm model and the UVM simulation verification platform, which is prone to causing data errors and errors in the algorithm processing flow, and further reduces the simulation efficiency and accuracy of the UVM platform. [Means for solving the problem]

[0008] According to one aspect of an embodiment of the present application, after receiving a chip simulation task, a step of generating a startup command based on the chip simulation task to trigger the startup of a verification platform based on a common verification methodology, wherein an image processing model is integrated in the verification platform; after a simulation operating environment of the verification platform is operated, a step of inputting Excite data into a design under test module and using the Excite data to perform a simulation process on a target chip corresponding to the chip simulation task in the design under test module, thereby obtaining simulation output data; and a step of acquiring the Excite data and the simulation output data, transmitting the Excite data and the simulation output data to the image processing model, and using the image processing model to perform an analysis process on the output data, thereby obtaining a pre-verification result. The present invention provides a chip hybrid simulation method based on a common verification methodology and an image processing algorithm, the method including the steps of: obtaining a simulation result for the target chip; performing format conversion on the simulation output data and the Excite data in the image processing model to obtain a simulation data stream and an Excite data stream that can be identified by an image processing algorithm in the image processing model; obtaining an image algorithm output data stream by processing the Excite data stream using the image processing algorithm; and comparing the simulation data stream in the image processing model with the image algorithm output data stream to obtain a verification result for the target chip based on the comparison result, wherein the verification result indicates whether the actual function of the target chip is consistent with functional description information.

[0009] Preferably, the chip hybrid simulation method based on the common verification methodology and image processing algorithm further includes the steps of: obtaining the design module under test by calling and designing a logic code of the design module under test, before generating a startup command based on the chip simulation task to trigger the startup of a verification platform based on the common verification methodology, the logic code being a code pre-created according to chip simulation needs; determining a plurality of components required to generate the verification platform based on the functional description information of the target chip, the plurality of components being components required to simulate the target chip; and packaging the plurality of components using a methodology architecture corresponding to the verification platform and connecting the packaged components to obtain the verification platform including the design module under test and the plurality of components packaged and connected.

[0010] Preferably, after the simulation operating environment of the verification platform is operated, the step of inputting Excite data into a design module under test and using the Excite data to perform simulation processing on a target chip corresponding to the chip simulation task in the design module under test to obtain simulation output data includes the steps of triggering a top-level setting module in the verification platform to be activated, using the top-level setting module to set registers of the design module under test according to the function description information of the target chip, and using the top-level setting module to set up a simulation environment of the verification platform; and triggering a scene exciter in the verification platform to be activated to generate the Excite data, inputting the Excite data into the design module under test, using the Excite data to drive the design module under test, and performing simulation processing on the target chip to obtain the simulation output data.

[0011] Preferably, the step of performing format conversion on the simulation output data and the Excite data in the image processing model to obtain a simulation data stream identifiable by an image processing algorithm in the image processing model includes the steps of: inputting the Excite data into the design under test module, and using the Excite data to perform simulation processing on the target chip in the design under test module, triggering to activate a logic monitor of the verification platform to collect the Excite data and the simulation output data, and inputting the Excite data and the simulation output data into the image processing model; and, after determining that the image processing model has received the simulation output data, using a data processing module in the image processing model to perform format conversion on the simulation output data to obtain the simulation data stream.

[0012] Preferably, the chip hybrid simulation method based on the common verification methodology and image processing algorithm further includes the steps of: obtaining configuration information of a register model in the verification platform and installation information of a simulation environment in the verification platform by using the image processing algorithm to process the exciting data stream before obtaining an image algorithm output data stream; and transmitting the configuration information and the installation information to a configuration module of the image processing model, and using the configuration module to preprocess the configuration information and the installation information, thereby pairing and aligning the configuration module with a top-level configuration module of the verification platform.

[0013] Preferably, the step of obtaining an image algorithm output data stream by processing the Excite data stream using the image processing algorithm includes a step of obtaining the image algorithm output data stream by performing analytical processing of a predetermined dimension on the Excite data stream using setting information of the image processing algorithm and a register model in the verification platform, wherein the predetermined dimension includes at least one of pixel depth, color temperature, contrast, color vividness, and over-smoothing.

[0014] Preferably, the step of comparing the simulation data stream with the image algorithm output data stream in the image processing model and obtaining a verification result for the target chip based on the comparison result includes the steps of: obtaining a comparison result by comparing the simulation data stream with the image algorithm output data stream in the image processing model; determining that the actual function of the target chip is consistent with functional description information when the comparison result indicates that the simulation data stream and the image algorithm output data are completely consistent or the number of mismatches between the simulation data stream and the image algorithm output data is less than a predetermined threshold; and determining that the actual function of the target chip is inconsistent with functional description information when the comparison result indicates that the number of mismatches between the simulation data stream and the image algorithm output data is equal to or greater than a predetermined threshold.

[0015] Preferably, the chip hybrid simulation method based on a common verification methodology and an image processing algorithm further includes a step of comparing the simulation data stream in the image processing model with the image algorithm output data stream, obtaining a verification result of the target chip based on the comparison result, and then storing the verification result in a log.

[0016] According to another aspect of the embodiment of the present application, a trigger unit receives a chip simulation task, generates a startup command based on the chip simulation task, and triggers the startup of a verification platform based on a common verification methodology, the verification platform including an image processing model integrated therein; a first acquisition unit, after a simulation operation environment of the verification platform is operated, inputs Excite data into a design under test module, and performs simulation processing on a target chip corresponding to the chip simulation task in the design under test module using the Excite data, thereby obtaining simulation output data; and a second acquisition unit, after the simulation operation environment of the verification platform is operated, inputs Excite data into a design under test module, and performs simulation processing on a target chip corresponding to the chip simulation task in the design under test module using the Excite data, thereby obtaining simulation output data; and a third acquisition unit for performing format conversion on the simulation output data and the Excite data in the image processing model to obtain a simulation data stream and an Excite data stream that are identifiable by an image processing algorithm in the image processing model; a fourth acquisition unit for processing the Excite data stream using the image processing algorithm to obtain an image algorithm output data stream; and a fifth acquisition unit for comparing the simulation data stream in the image processing model with the image algorithm output data stream to obtain a verification result of the target chip based on a comparison result, wherein the verification result indicates whether the actual function of the target chip is consistent with functional description information.

[0017] Preferably, the chip hybrid simulation device based on the common verification methodology and image processing algorithm further includes: a sixth acquisition unit for obtaining the design module under test by calling and designing the logic code of the design module under test before generating a startup command based on the chip simulation task and triggering the startup of a verification platform based on the common verification methodology, the logic code being a code pre-created according to chip simulation needs; a determination unit for determining a plurality of components required to generate the verification platform based on the functional description information of the target chip, the plurality of components being components required to simulate the target chip; and a seventh acquisition unit for obtaining the verification platform including the design module under test and the plurality of components packaged and connected by using a methodology architecture corresponding to the verification platform to package the plurality of components and connect the packaged components.

[0018] Preferably, the first acquisition unit includes: a first trigger module for triggering a top-level setting module in the verification platform to activate, using the top-level setting module to set registers of the test target design module based on the functional description information of the target chip, and using the top-level setting module to set up a simulation environment of the verification platform; and a second trigger module for triggering a scene exciter in the verification platform to generate the excitation data, inputting the excitation data into the test target design module, using the excitation data to drive the test target design module, and performing simulation processing on the target chip to obtain the simulation output data.

[0019] Preferably, the third acquisition unit includes: a third trigger module for triggering the logic monitor of the verification platform to activate to collect the excitement data and the simulation output data, and inputting the excitement data and the simulation output data into the image processing model during the process of inputting the excitement data into the design module under test and using the excitement data to perform simulation processing on the target chip in the design module under test; and a first acquisition module for obtaining the simulation data stream by using a data processing module in the image processing model to perform format conversion on the simulation output data after determining that the image processing model has received the simulation output data.

[0020] Preferably, the chip hybrid simulation device based on the common verification methodology and image processing algorithm further includes: an eighth acquisition unit for acquiring setting information of a register model in the verification platform and installation information of a simulation environment in the verification platform by using the image processing algorithm to process the exciting data stream before obtaining an image algorithm output data stream; and a processing unit for sending the setting information and the installation information to a setting module of the image processing model, and using the setting module to pre-process the setting information and the installation information, thereby pairing and matching the setting module with a top-level setting module of the verification platform.

[0021] Preferably, the fourth acquisition unit includes a second acquisition module for obtaining the image algorithm output data stream by performing analytical processing of a predetermined dimension on the excitation data stream using setting information of the image processing algorithm and a register model in the verification platform, wherein the predetermined dimension includes at least one of pixel depth, color temperature, contrast, color vividness, and over-smoothing.

[0022] Preferably, the fifth acquisition unit includes: a third acquisition module for obtaining a comparison result by comparing the simulation data stream and the image algorithm output data stream in the image processing model; a first determination module for determining that the actual function of the target chip is consistent with functional description information when the comparison result indicates that the simulation data stream and the image algorithm output data are completely consistent or the number of mismatches between the simulation data stream and the image algorithm output data is less than a predetermined threshold; and a second determination module for determining that the actual function of the target chip is inconsistent with functional description information when the comparison result indicates that the number of mismatches between the simulation data stream and the image algorithm output data is equal to or greater than a predetermined threshold.

[0023] Preferably, the chip hybrid simulation device based on the common verification methodology and image processing algorithm further includes a storage unit for comparing the simulation data stream in the image processing model with the image algorithm output data stream, obtaining a verification result of the target chip based on the comparison result, and then storing the verification result in a log, wherein the verification result is for indicating whether the actual function of the target chip is consistent with the function description information.

[0024] According to another aspect of the embodiment of the present application, there is further provided a chip hybrid simulation system based on a common verification methodology and an image processing algorithm, which uses a chip hybrid simulation method based on any of the above-described common verification methodologies and image processing algorithms.

[0025] According to another aspect of the embodiment of the present application, there is further provided a computer-readable storage medium storing a program for executing a chip hybrid simulation method based on any of the above-described common verification methodologies and image processing algorithms.

[0026] According to another aspect of an embodiment of the present application, there is further provided a processor for executing a program, which, when the program is executed, executes a chip hybrid simulation method based on any of the common verification methodologies and image processing algorithms described above. [Effects of the Invention]

[0027] In an embodiment of the present application, after receiving a chip simulation task, a startup command is generated based on the chip simulation task to trigger the startup of a verification platform based on a common verification methodology. Here, an image processing model is integrated into the verification platform. After the simulation operating environment of the verification platform is activated, Excite data is input to a design module under test, and the Excite data is used to perform a simulation process on a target chip corresponding to the chip simulation task in the design module under test, thereby obtaining simulation output data. The Excite data and simulation output data are also acquired, and sent to an image processing model. The image processing model performs an analysis process on the output data, thereby obtaining a simulation result for the target chip. Furthermore, format conversion is performed on the simulation output data and the Excite data in the image processing model, thereby obtaining a simulation data stream and an Excite data stream that can be identified by an image processing algorithm in the image processing model. The Excite data stream is then processed using an image processing algorithm to obtain an image algorithm output data stream. The simulation data stream in the image processing model is compared with the image algorithm output data stream, and a verification result for the target chip is obtained based on the comparison result. Here, the verification result indicates whether the actual function of the target chip is consistent with the functional description information.According to the above technical proposal, by integrating the image algorithm model and the UVM simulation verification platform, while using the chip simulation verification platform to perform simulation processing on the target chip, the input data used in the simulation and the simulation output data can be input to the image processing model, and the image processing model can be used to perform algorithmic processing on the input data. This achieves the objective of comprehensively verifying whether the actual function of the target chip is consistent with its function description information based on the simulation output result and the processing result of the image algorithm model. Therefore, the technical effect of interconnecting the image algorithm model and the UVM simulation verification platform to avoid data errors and algorithm processing flow errors can be achieved. Therefore, the embodiments of the present application improve the simulation efficiency and accuracy of the UVM platform and further solve the problem that the method of performing simulation verification on a chip in the related art isolates the interconnection and connection between the image algorithm model and the UVM simulation verification platform, which is likely to cause data errors and algorithm processing flow errors and further reduces the simulation efficiency and accuracy of the UVM platform. [Brief explanation of the drawings]

[0028] The drawings described herein are provided for a further understanding of the present application and constitute a part of the present application, and the illustrative embodiments and the description thereof are intended to interpret the present application without unduly limiting the present application.

[0029] [Figure 1] 1 is a block diagram illustrating a hardware structure of a mobile terminal in a chip hybrid simulation method based on a common verification methodology and an image processing algorithm according to an embodiment of the present application. [Figure 2] 1 is a flowchart of a chip hybrid simulation method based on a common verification methodology and an image processing algorithm according to an embodiment of the present application. [Figure 3] FIG. 1 illustrates a chip simulation verification platform according to an embodiment of the present application. [Figure 4] 1 is a flowchart of a chip hybrid simulation method based on a preferred common verification methodology and image processing algorithm according to an embodiment of the present application. [Figure 5] FIG. 1 is a diagram showing a chip simulation verification flow according to an embodiment of the present application. [Figure 6] FIG. 1 illustrates a chip hybrid simulation device based on a common verification methodology and image processing algorithm according to an embodiment of the present application. DETAILED DESCRIPTION OF THE INVENTION

[0030] In order to help those skilled in the art understand the technical solution of the present application better, the technical solution in the embodiments of the present application will be described below clearly and completely with reference to the drawings in the embodiments of the present application, but it goes without saying that the embodiments described below are only a part of the embodiments of the present application, not all of the embodiments of the present application. Other embodiments that a person skilled in the art can obtain based on the embodiments of the present application without any inventive effort are also included in the scope of protection of the present application.

[0031] In the specification and claims of this application, as well as in the drawings, terms such as "first," "second," etc., are used to distinguish between similar objects and do not necessarily dictate a particular order or priority. It should be understood that such terms may be interchanged to allow the embodiments of this application described herein to be performed in orders other than those illustrated or described herein. Furthermore, terms such as "comprise" and "have," and any variations thereof, are intended to cover non-exclusive inclusions, such that, for example, a process, method, system, product, or apparatus comprising a series of steps or units is not limited to the explicitly listed steps or units, but may also include other steps or units not explicitly listed or inherent in the process, method, product, or apparatus.

[0032] As described in the background art, the related art's method for performing simulation verification on a chip isolates the interconnectivity and connectivity between the image algorithm model and the UVM simulation verification platform, which is prone to data errors and algorithm processing flow errors, and further reduces the simulation efficiency and accuracy of the UVM platform. To address these deficiencies, the present application provides a chip hybrid simulation method based on a common verification methodology and image processing algorithm.

[0033] Hereinafter, the technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application.

[0034] The method according to the present invention may be implemented in a mobile terminal, a computer terminal, or a similar computing device. For example, FIG. 1 illustrates a block diagram showing the hardware structure of a mobile terminal for implementing the chip hybrid simulation method based on the common verification methodology and image processing algorithm according to the present invention. As shown in FIG. 1, the mobile terminal may include one or more processors 102 (only one processor is shown in FIG. 1 ) (the processor 102 may include, but is not limited to, a processing device such as a microprocessor (MCU) or a field programmable logic device (FPGA)) and a memory 104 for storing data. The mobile terminal may also include a transmission device 106 and an input / output device 108 for communication functions. As will be appreciated by those skilled in the art, the structure shown in FIG. 1 is merely illustrative and does not limit the structure of the mobile terminal. For example, the mobile terminal may include more or fewer components than those shown in FIG. 1 or may have a different configuration than those shown in FIG. 1.

[0035] The memory 104 can store software programs and modules of application software, such as computer programs (e.g., computer programs corresponding to the common verification methodology and the chip hybrid simulation method based on the image processing algorithm in the embodiments of the present application). The processor 102 executes various functional applications and data processing to realize the above-described methods by running the computer programs stored in the memory 104. The memory 104 may include high-speed random access memory or non-volatile memory (e.g., one or more magnetic storage devices, flash memory, or other non-volatile solid-state drives). In some examples, the memory 104 may further include memory located remotely from the processor 102, and these remote memories may be connected to the mobile terminal via a network. Examples of such networks include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof. The transmission device 106 is for transmitting and receiving data via a network. A specific example of such a network may include a wireless network provided by a communication supplier of the mobile terminal. In one example, the transmission device 106 includes a network interface controller (NIC) that is connected to other network devices via a base station and can communicate with the Internet. In one example, the transmission device 106 may be a radio frequency (RF) module for wirelessly communicating with the Internet.

[0036] According to an embodiment of the present application, there is provided a method embodiment of a chip hybrid simulation method based on a common verification methodology and an image processing algorithm. Note that the steps shown in the flowcharts in the drawings may be performed, for example, by a computer system in which a set of computers can execute instructions, and although a logical order is shown in the flowcharts, in some cases the steps shown or described may be performed in an order different from that shown or described herein.

[0037] FIG. 2 is a flowchart of a chip hybrid simulation method based on a common verification methodology and an image processing algorithm according to an embodiment of the present application. As shown in FIG. 2, the method includes the following steps:

[0038] In step S202, after receiving a chip simulation task, generate an activation command based on the chip simulation task to trigger the activation of a verification platform based on a common verification methodology, in which an image processing model is integrated into the verification platform.

[0039] Preferably, the Universal Verification Methodology (UVM) is a standard verification methodology for integrated circuit design, which is derived from the Open Verification Methodology and provides a higher degree of automation.

[0040] According to the above embodiment of the present application, the chip hybrid simulation method based on the common verification methodology and image processing algorithm further includes, before the above step S202, i.e., before generating a startup command based on a chip simulation task to trigger the startup of a verification platform based on the common verification methodology, the following steps: obtain a design module under test by invoking and designing the logic code of the design module under test, where the logic code is a code pre-created according to chip simulation needs; determine a plurality of components required to generate a verification platform based on functional description information of the target chip, where the plurality of components are components required to simulate the target chip; and package the plurality of components using a methodology architecture corresponding to the verification platform and connect the packaged components to obtain a verification platform including the design module under test and the packaged and connected components.

[0041] The above embodiment of the present application will be described in detail below with reference to Figure 3, which is a diagram illustrating a chip simulation verification platform according to the embodiment of the present application. As shown in Figure 3, before starting chip simulation, a chip simulation verification platform based on UVM is established. The platform mainly includes a top-level module (test_top) and a module under test. The top-level environment of the top-level module includes a top-level configuration (top_cfg), an image processing model (alg_model), a register model (reg_model), an algorithm agent (alg_agent), a logic monitor (dut_monitor), a scene exciter (video_seq), etc. Next, simulation software, scripts, file paths, etc. need to be installed.

[0042] The function of each module in the chip simulation verification platform will be explained below.

[0043] 1) Top-level module (test_top): It is responsible for constructing the entire simulation environment, calling the logic code of the design module under test (DUT), and packaging components such as the top-level environment (top_env), top-level configuration (top_cfg), register model (reg_model), and registers (i.e., registers in the DUT module) based on the UVM methodology architecture, and connecting each module to form the overall simulation environment.

[0044] 2)Top-level environment (top_env): It is responsible for calling the top-level module (test_top), register model (reg_model), image processing model (alg_model), algorithm agent (alg_agent), etc., and provides configuration information (including video image color depth, length, number of frames, number of pixels, register setting bus type, rate, and number of lanes), module enable, module connection, data transmission, etc. to each type of module, and incorporates it into the top-level environment (top_env) module. During the simulation process, it automatically calls the function methods in the modules to realize the module functions.

[0045] 3) Top level settings (top_cfg): It is responsible for providing various settings for the entire algorithm function module, mainly including environment settings, flow settings, data stream settings, register function settings, comparison mechanism settings, etc.

[0046] 4) Register model (reg_model): It is responsible for providing a register model for the entire simulation environment, and realizes read / write, reset, dynamic setting, static setting, etc. The register model here is the UVM simulation verification platform.

[0047] 5) Image processing model (alg_model): It is responsible for calling algorithm program models created based on PYTHON, and analyzes and compares algorithm processing data and DUT output data based on register setting information.

[0048] 6) Algorithm Agent (alg_agent): It is responsible for instantiating the logical monitor (dut_monitor) and scene exciter (video_seq), as well as connecting modules together. The instantiation module directly calls the module name to incorporate it into the algorithm agent and use the internal function methods of the instantiation module.

[0049] 7) Logical monitor (dut_monitor): It is responsible for monitoring the input and output data of the logic code and transmitting it to the image processing model.

[0050] 8) Scene Exciter (video_seq): It is responsible for generating the algorithm model and the input exciting data of the DUT, and by introducing the register model (reg_model) and the top-level configuration (top_cfg) settings such as color depth, length, number of frames, number of pixels of the video image, it generates input signals such as bit data stream, DE, vsync, hsync, etc., and connects to the DUT module interface.

[0051] In step S204, after the simulation operating environment of the verification platform is operated, Excite data is input into the test object design module, and the Excite data is used to perform simulation processing on the target chip corresponding to the chip simulation task in the test object design module, thereby obtaining simulation output data.

[0052] Preferably, the simulation output data can be used as a reference for verifying whether the actual function of the target chip is consistent with the function description information.

[0053] In this embodiment, after the simulation operating environment of the verification platform is operated, a scene exciter in the verification platform can be triggered to start to generate exciting data, and then the exciting data is used as a driving force for the design module under test to perform a simulation process on the target chip.

[0054] FIG. 4 is a flowchart of a preferred embodiment of a chip hybrid simulation method based on a common verification methodology and an image processing algorithm. As shown in FIG. 4, when chip simulation begins, the simulation software version, file path, environment variables, etc. are first set. Then, a simulation script is run on the system terminal. In this case, a simulation verification platform based on the UVM methodology is established, which is divided into two parts: a logic code DUT and an environment integration component. These components mainly include a top-level module (test_top), a top-level environment (top_env), a top-level configuration (top_cfg), a register model (reg_model), an image processing model (alg_model), and an algorithm agent (alg_agent).

[0055] Next, after the entire simulation environment is constructed, the simulation platform automatically starts the simulation process, and performs image algorithm model processing, DUT synchronous simulation, data exchange, etc. in real time. Finally, the simulation platform automatically processes data, analyzes and compares all data information, register setting information, etc., analyzes the simulation results and data content, and finally confirms the accuracy of the design simulation. After that, the simulation process is terminated and the simulation data log is recorded, and the simulation files and waveforms are saved.

[0056] According to the above embodiment of the present application, after the simulation operating environment of the verification platform is operated, the above step S204 of inputting Excite data into the design module under test and using the Excite data to perform simulation processing on the target chip corresponding to the chip simulation task in the design module under test to obtain simulation output data includes the steps of triggering to activate a top-level setting module in the verification platform, using the top-level setting module to set the registers of the design module under test according to the functional description information of the target chip, and using the top-level setting module to set up the simulation environment of the verification platform; and triggering to activate a scene exciter in the verification platform to generate Excite data, inputting the Excite data into the design module under test, using the Excite data to drive the design module under test, and performing simulation processing on the target chip to obtain simulation output data.

[0057] As shown in Figure 3 above, after the verification platform simulation environment is running, it launches the top-level configuration (top_cfg) module and configures all registers and sets up the environment (the configuration includes environment configuration, flow configuration, data stream configuration, register function configuration, and comparison mechanism configuration), and sends the corresponding configuration parameters to the image processing model (alg_model), algorithm agent (alg_agent) and register model (reg_model). After the algorithm agent (alg_agent) receives the configuration data, it launches the logic monitor (dut_monitor) and scene exciter (video_seq), and sends the generated exciting data (video_data) to the design under test (DUT).

[0058] Note that the registers in this example refer to the registers within the chip and are not related to UVM. The registers in this example and the register model in UVM use similar settings, but each processes the data it needs to process. The reason for using the chip's registers and the UVM's register model to process data jointly is to avoid the risk of both the simulation process and the image processing algorithm using incorrect data if a problem occurs in the setting data, which would invalidate the verification results for the target chip.

[0059] In step S206, the exciting data and the simulation output data are obtained, and the exciting data and the simulation output data are sent to an image processing model, and the image processing model is used to perform analysis processing on the output data, thereby obtaining a simulation result for the target chip.

[0060] As shown in Figure 3 above, while the design module under test (DUT) continuously receives exciting data (video_data), the logic monitor (dut_monitor) continuously operates, constantly sampling the input and output data of the DUT, and transmitting the data to the image processing model (alg_model), which processes the data and input information and outputs the comparison result.

[0061] In step S208, format conversion is performed on the simulation output data and the Excite data in the image processing model to obtain a simulation data stream and an Excite data stream that can be identified by the image processing algorithm in the image processing model.

[0062] When processing the data, compatibility issues must be taken into consideration. To ensure that subsequent steps are carried out smoothly, the acquired simulation output data and Excite data must be converted into a simulation data stream and Excite data stream that can be identified by the image processing algorithm in the image processing model (alg_model) by performing format conversion on the acquired simulation output data and Excite data.

[0063] According to the above embodiment of the present application, the above step S208 of performing format conversion on the simulation output data and Excite data in the image processing model to obtain a simulation data stream that can be identified by the image processing algorithm in the image processing model includes the steps of: inputting the Excite data into the design under test module and using the Excite data to perform simulation processing on the target chip in the design under test module, triggering the logic monitor of the verification platform to start up to collect the Excite data and the simulation output data, and inputting the Excite data and the simulation output data into the image processing model; and after determining that the image processing model has received the simulation output data, using the data processing module in the image processing model to perform format conversion on the simulation output data to obtain a simulation data stream.

[0064] The above embodiment of the present application will be described in detail below with reference to Fig. 5. Fig. 5 is a diagram showing a chip simulation verification flow according to the embodiment of the present application. As shown in Fig. 5, the image processing model (alg_model) receives the Excite data and the simulation output data, and then transmits them to the data processing (data_pro) module for matching and analysis (format conversion), and then sends them to the comparator module (Comparator Module) to obtain the simulation data stream and the Excite data stream.

[0065] The data processing (data_pro) module here is mainly responsible for extracting pixels from the excitation data and simulation output data output from the DUT, packetizing them, and storing them in a queue in byte order, in order to verify the pass / fail of the target chip by comparing the two after the image processing model processes the input data and obtains the processing results.

[0066] In step S210, an image processing algorithm is used to process the Excite data stream to obtain an image algorithm output data stream.

[0067] Preferably, the image algorithm output data stream is a data stream in a specific format required for subsequent verification against the target chip.

[0068] After obtaining the data streams (simulation data streams and image algorithm output data streams, i.e., data_in) in a specific format, they are transmitted to the PYTHON algorithm model, and the ideal data after image analysis and processing can be output immediately without consuming simulation time during the operation process of the PYTHON algorithm model, and the data can be output to the comparison module of the image processing algorithm model according to the specific format.

[0069] In the embodiment of the present application, the image processing algorithm includes a PYTHON algorithm, but is not limited to this and may be other types of algorithms.

[0070] According to the above embodiment of the present application, the chip hybrid simulation method based on the common verification methodology and the image processing algorithm further includes, before the above step S210, i.e., before using the image processing algorithm to process the exciting data stream to obtain the image algorithm output data stream, the following steps: obtaining configuration information of the register model in the verification platform and installation information of the simulation environment in the verification platform; and transmitting the configuration information and installation information to a configuration module of the image processing model, and using the configuration module to preprocess the configuration information and installation information, thereby pairing and aligning the configuration module with the top-level configuration module of the verification platform.

[0071] As shown in Figure 5 above, when the data processing (data_pro) module performs format conversion processing on the Excite data and simulation output data (data_out), the image processing model (alg_model) further transmits the setting information of the top-level setting (top_cfg) and register model (reg_model) to the setting (cfg) module for preprocessing, which mainly includes register name, register domain value, register address, register setting bus type, rate, and number of lanes, etc. By pairing and matching this basic information with the top-level setting (top_cfg) module, the final required processing state setting data can be obtained.

[0072] According to the above embodiment of the present application, the step S210 of obtaining an image algorithm output data stream by processing the Excite data stream using an image processing algorithm includes a step of obtaining an image algorithm output data stream by performing a predetermined dimension analysis process on the Excite data stream using the image processing algorithm and the setting information of the register model in the verification platform, wherein the predetermined dimension includes at least one of pixel depth, color temperature, contrast, color vividness, and over-smoothing.

[0073] As shown in Figure 5 above, the image processing algorithm model (alg_model) can directly call a program written in the programming language PYTHON to perform data processing and analysis on the input image of a specific format. The processing and analysis process mainly performs processing calculations on the pixel depth, color temperature, contrast, color vividness, and smoothness of the video image so that the video data can meet the requirements of the chip.

[0074] In addition, during the simulation process, the image processing algorithm model (alg_model) synchronously collects input and output data (i.e., Excite data and simulation output data) operating on the DUT, and synchronously introduces the input data (Excite data) and register setting data (register name, register domain value, register address, register setting bus type, rate, and number of lanes, etc.) into the PYTHON algorithm model.

[0075] In step S212, the simulation data stream in the image processing model is compared with the image algorithm output data stream, and a verification result of the target chip is obtained based on the comparison result, where the verification result is for indicating whether the actual function of the target chip is consistent with the function description information.

[0076] After the PYTHON algorithm model outputs data to a comparison module of the image processing algorithm model according to a specific format, the comparison module compares the simulation data stream with the image algorithm output data stream, and then obtains a verification result for the target chip based on the comparison result, and verifies whether the actual function of the target chip is consistent with its function description information.

[0077] According to the above embodiment of the present application, the above step S212 of comparing the simulation data stream and the imaging algorithm output data stream in the imaging processing model and obtaining a verification result of the target chip based on the comparison result includes the steps of: comparing the simulation data stream and the imaging algorithm output data stream in the imaging processing model to obtain a comparison result; determining that the actual function of the target chip is consistent with the function description information if the comparison result indicates that the simulation data stream and the imaging algorithm output data are completely consistent or the number of mismatches between the simulation data stream and the imaging algorithm output data is less than a predetermined threshold; and determining that the actual function of the target chip is inconsistent with the function description information if the comparison result indicates that the number of mismatches between the simulation data stream and the imaging algorithm output data is equal to or greater than a predetermined threshold.

[0078] Preferably, the above-mentioned predetermined threshold value is used to determine whether the actual function of the target chip is consistent with the function description information, and the specific numerical value can be obtained through a large number of experiments, and the numerical value is not specifically limited here.

[0079] As shown in Figure 5 above, the PYTHON algorithm model processes and analyzes image data on the Excite data stream and the simulation data stream, and then transmits the analysis results to the comparison module, which then analyzes and compares the final data to obtain the overall results of the image processing chip simulation verification.

[0080] For example, if the number of mismatches between the simulation data stream and the image algorithm output data stream exceeds 5 (5 is used as the predetermined threshold), the actual function of the target chip does not match its function description information, that is, the chip can be considered to belong to the failed chip; if the number of mismatches between the simulation data stream and the image algorithm output data stream is less than 5 (5 is used as the predetermined threshold), the actual function of the target chip matches its function description information, that is, the chip can be considered to belong to the passed chip.

[0081] According to the above embodiment of the present application, the chip hybrid simulation method based on the common verification methodology and the image processing algorithm further includes, after the above step S212, i.e., after comparing the simulation data stream in the image processing model with the image algorithm output data stream and obtaining the verification result of the target chip based on the comparison result, a step of storing the verification result in a log.

[0082] The image processing algorithm model comparison module receives the data output by the DUT and the Python algorithm model, compares the data, and prints the comparison results in a log directory. The output data adopts a unified data byte packetization format, mainly including video format data type, data depth, and pixel point byte data.

[0083] As described above, after receiving a chip simulation task through the above steps, a startup command is generated based on the chip simulation task to trigger the startup of a verification platform based on a common verification methodology. Here, an image processing model is integrated into the verification platform. After the simulation operating environment of the verification platform is activated, Excite data is input to a design module under test, and the Excite data is used to perform a simulation process on a target chip corresponding to the chip simulation task in the design module under test, thereby obtaining simulation output data. The Excite data and simulation output data are also acquired, and sent to an image processing model. The output data are analyzed using the image processing model, thereby obtaining a simulation result for the target chip. Furthermore, format conversion is performed on the simulation output data and the Excite data in the image processing model, thereby obtaining a simulation data stream and an Excite data stream that can be identified by an image processing algorithm in the image processing model. The Excite data stream is then processed using an image processing algorithm to obtain an image algorithm output data stream. The simulation data stream in the image processing model is compared with the image algorithm output data stream, and a verification result for the target chip is obtained based on the comparison result. Here, the verification result indicates whether the actual function of the target chip is consistent with the function description information.Therefore, by integrating the image algorithm model and the UVM simulation verification platform, the chip simulation verification platform can be used to perform simulation processing on the target chip, while the input data and simulation output data used in the simulation can be input into the image processing model, and the image processing model can be used to perform algorithmic processing on the input data.Therefore, based on the simulation output results and the processing results of the image algorithm model, it can be comprehensively verified whether the actual function of the target chip is consistent with its function description information.Therefore, by interconnecting the image algorithm model and the UVM simulation verification platform, the technical effect of avoiding data errors and errors in the algorithm processing flow is achieved, and the simulation efficiency and accuracy of the UVM platform is improved.

[0084] Therefore, the technical solution provided by the above embodiments of the present application solves the problem that the method for performing simulation verification on a chip in the related art isolates the interconnectivity and connectivity between the image algorithm model and the UVM simulation verification platform, which is prone to causing data errors and errors in the algorithm processing flow, and further reduces the simulation efficiency and accuracy of the UVM platform.

[0085] Although the above-described method embodiments are expressed as a combination of a series of operations for the sake of simplicity, it will be apparent to those skilled in the art that the present application is not limited to the order of operations described, and that certain steps may be performed in other orders or simultaneously according to the present application. It will also be apparent to those skilled in the art that the embodiments described in the specification are preferred embodiments, and that the operations and modules are not necessarily essential to the present application.

[0086] From the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be realized by a combination of software and a necessary general-purpose hardware platform, and of course, can also be realized by hardware, and in many cases, the former is a more preferred embodiment. Based on this understanding, the technical solution of the present application can be essentially embodied in the form of a software product, or a part that contributes to the prior art can be embodied in the form of a software product, which is stored in a storage medium (e.g., ROM / RAM, magnetic disk, optical disk) and includes some instructions for causing a terminal device (which may be a mobile phone, a computer, a server, a network device, etc.) to execute the methods described in each embodiment of the present application.

[0087] According to an embodiment of the present application, there is further provided a chip hybrid simulation device based on the common verification methodology and image processing algorithm for implementing the chip hybrid simulation method based on the above common verification methodology and image processing algorithm. FIG. 6 is a diagram showing a chip hybrid simulation device based on the common verification methodology and image processing algorithm according to an embodiment of the present application. As shown in FIG. 6, the device includes a trigger unit 601, a first acquisition unit 603, a second acquisition unit 605, a third acquisition unit 607, a fourth acquisition unit 609, and a fifth acquisition unit 611. The chip hybrid simulation device based on the common verification methodology and image processing algorithm will be described in detail below.

[0088] The trigger unit 601 is for receiving a chip simulation task, and then generating an activation command according to the chip simulation task to trigger activation of a verification platform based on a common verification methodology, where the verification platform is integrated with an image processing model.

[0089] The first acquisition unit 603 is for inputting Excite data into the test target design module after the simulation operating environment of the verification platform is operated, and using the Excite data to perform simulation processing on the target chip corresponding to the chip simulation task in the test target design module, thereby obtaining simulation output data.

[0090] The second acquisition unit 605 is for acquiring the excitation data and the simulation output data, and transmitting the excitation data and the simulation output data to the image processing model, and performing analytical processing on the output data using the image processing model, thereby obtaining the simulation result for the target chip.

[0091] The third obtaining unit 607 is for performing format conversion on the simulation output data and the exciting data in the image processing model to obtain a simulation data stream and an exciting data stream that can be identified by the image processing algorithm in the image processing model.

[0092] The fourth obtaining unit 609 is for processing the exciting data stream using an image processing algorithm to obtain an image algorithm output data stream.

[0093] The fifth obtaining unit 611 is for comparing the simulation data stream in the image processing model with the image algorithm output data stream, and obtaining a verification result of the target chip according to the comparison result, where the verification result is for indicating whether the actual function of the target chip is consistent with the function description information.

[0094] It should be noted that the above trigger unit 601, the first acquisition unit 603, the second acquisition unit 605, the third acquisition unit 607, the fourth acquisition unit 609 and the fifth acquisition unit 611 correspond to steps S202 to S212 in the above embodiments, and the six units are similar to the examples and application scenes realized by the corresponding steps, but are not limited to the contents disclosed in the above embodiments.

[0095] As described above, in the technical solution described in the above embodiment of the present application, after receiving a chip simulation task, a trigger unit generates a startup command based on the chip simulation task to trigger the startup of a verification platform based on a common verification methodology. Here, an image processing model is integrated into the verification platform. After that, after the simulation operating environment of the verification platform is operated, a first acquisition unit inputs Excite data into a design under test module and uses the Excite data to perform simulation processing on a target chip corresponding to the chip simulation task in the design under test module, thereby obtaining simulation output data. Next, a second acquisition unit acquires the Excite data and simulation output data, sends the Excite data and simulation output data to an image processing model, and uses the image processing model to perform analysis processing on the output data, thereby obtaining a simulation result for the target chip. Then, a third acquisition unit performs format conversion on the simulation output data and Excite data in the image processing model, thereby obtaining a simulation data stream and an Excite data stream that can be identified by an image processing algorithm in the image processing model. Furthermore, a fourth acquisition unit processes the Excite data stream using an image processing algorithm, thereby obtaining an image algorithm output data stream. Finally, a fifth obtaining unit can compare the simulation data stream in the image processing model with the image algorithm output data stream, and obtain a verification result of the target chip according to the comparison result, where the verification result is for indicating whether the actual function of the target chip is consistent with the function description information.Thus, by integrating the image algorithm model with the UVM simulation verification platform, the chip simulation verification platform can be used to perform simulation processing on the target chip, while the input data and simulation output data used in the simulation can be input into the image processing model, and the image processing model can be used to perform algorithmic processing on the input data. Based on the simulation output results and the processing results of the image algorithm model, it can be comprehensively verified whether the actual function of the target chip is consistent with its function description information. Therefore, by interconnecting the image algorithm model with the UVM simulation verification platform, the technical effect of avoiding data errors and errors in the algorithm processing flow is achieved, and the simulation efficiency and accuracy of the UVM platform is improved.

[0096] Therefore, the technical solution provided by the above embodiments of the present application solves the problem that the method for performing simulation verification on a chip in the related art isolates the interconnectivity and connectivity between the image algorithm model and the UVM simulation verification platform, which is prone to causing data errors and errors in the algorithm processing flow, and further reduces the simulation efficiency and accuracy of the UVM platform.

[0097] Preferably, the chip hybrid simulation device based on the common verification methodology and image processing algorithm further includes: a sixth acquisition unit for obtaining a design module under test by calling and designing the logic code of the design module under test before generating a startup command based on a chip simulation task to trigger the startup of a verification platform based on the common verification methodology, the logic code being a code pre-created according to chip simulation needs; a determination unit for determining a plurality of components required to generate a verification platform based on functional description information of the target chip, the plurality of components being components required to simulate the target chip; and a seventh acquisition unit for obtaining a verification platform including the design module under test and the plurality of packaged and connected components by using a methodology architecture corresponding to the verification platform to package the plurality of components and connect the packaged components.

[0098] Preferably, the first acquisition unit includes: a first trigger module for triggering to activate a top-level setting module in the verification platform, using the top-level setting module to set registers of the test target design module based on the functional description information of the target chip, and using the top-level setting module to set up a simulation environment of the verification platform; and a second trigger module for triggering to activate a scene exciter in the verification platform to generate excitation data, inputting the excitation data into the test target design module, using the excitation data to drive the test target design module, and performing simulation processing on the target chip, thereby obtaining simulation output data.

[0099] Preferably, the third acquisition unit includes: a third trigger module for triggering the logic monitor of the verification platform to activate during the process of inputting the Excite data into the design module under test and using the Excite data to perform simulation processing on the target chip in the design module under test, to collect the Excite data and the simulation output data, and inputting the Excite data and the simulation output data into the image processing model; and a first acquisition module for obtaining a simulation data stream by using a data processing module in the image processing model to perform format conversion on the simulation output data after determining that the image processing model has received the simulation output data.

[0100] Preferably, the chip hybrid simulation device based on the common verification methodology and image processing algorithm further includes: an eighth acquisition unit for acquiring setting information of the register model in the verification platform and installation information of the simulation environment in the verification platform by using the image processing algorithm to process the exciting data stream before obtaining the image algorithm output data stream; and a processing unit for sending the setting information and installation information to the setting module of the image processing model, and using the setting module to pre-process the setting information and installation information, thereby pairing and matching the setting module with the top-level setting module of the verification platform.

[0101] Preferably, the fourth acquisition unit includes a second acquisition module for obtaining an image algorithm output data stream by performing analytical processing of a predetermined dimension on the excite data stream using setting information of the image processing algorithm and the register model in the verification platform, wherein the predetermined dimension includes at least one of pixel depth, color temperature, contrast, color vividness, and over-smoothing.

[0102] Preferably, the fifth acquisition unit includes: a third acquisition module for obtaining a comparison result by comparing the simulation data stream and the image algorithm output data stream in the image processing model; a first determination module for determining that the actual function of the target chip is consistent with the function description information when the comparison result indicates that the simulation data stream and the image algorithm output data are completely consistent or the number of mismatches between the simulation data stream and the image algorithm output data is less than a predetermined threshold; and a second determination module for determining that the actual function of the target chip is inconsistent with the function description information when the comparison result indicates that the number of mismatches between the simulation data stream and the image algorithm output data is equal to or greater than the predetermined threshold.

[0103] Preferably, the chip hybrid simulation device based on the common verification methodology and image processing algorithm further includes a storage unit for comparing the simulation data stream in the image processing model with the image algorithm output data stream, obtaining a verification result of the target chip based on the comparison result, and then storing the verification result in a log.

[0104] According to another aspect of the embodiment of the present application, there is further provided a chip hybrid simulation system based on a common verification methodology and an image processing algorithm, which uses a chip hybrid simulation method based on any one of the above common verification methodologies and image processing algorithms.

[0105] According to another aspect of the present invention, there is further provided a computer-readable storage medium storing a program for executing a chip hybrid simulation method based on any one of the above common verification methodologies and image processing algorithms.

[0106] Preferably, in this embodiment, the computer-readable storage medium may be located in any one of a group of computer terminals in a computer network, or in any one of a group of communication devices.

[0107] Preferably, in this embodiment, the computer-readable storage medium includes the steps of: after receiving a chip simulation task, generating a startup command based on the chip simulation task to trigger the startup of a verification platform based on a common verification methodology, wherein the verification platform has an image processing model integrated therein; after the simulation operating environment of the verification platform is operated, inputting Excite data into a design module under test, and using the Excite data to perform simulation processing on a target chip corresponding to the chip simulation task in the design module under test, thereby obtaining simulation output data; and obtaining the Excite data and the simulation output data, and sending the Excite data and the simulation output data to an image processing model, and using the image processing model to process the output data. the image processing model to obtain a simulation result for the target chip; performing format conversion on the simulation output data and the Excite data in the image processing model to obtain a simulation data stream and an Excite data stream that are identifiable by an image processing algorithm in the image processing model; processing the Excite data stream using the image processing algorithm to obtain an image algorithm output data stream; and comparing the simulation data stream and the image algorithm output data stream in the image processing model to obtain a verification result for the target chip based on the comparison result, wherein the verification result indicates whether the actual function of the target chip is consistent with the function description information.

[0108] Preferably, in this embodiment, the computer-readable storage medium is configured to store program codes for executing the steps of: obtaining a design module to be tested by invoking and designing a logic code of the design module to be tested, where the logic code is a code pre-created according to chip simulation needs; determining a plurality of components required to generate a verification platform based on functional description information of the target chip, where the plurality of components are components required to simulate the target chip; and packaging the plurality of components using a methodology architecture corresponding to the verification platform and connecting the packaged plurality of components to obtain a verification platform including the design module to be tested and the plurality of packaged and connected components.

[0109] Preferably, in this embodiment, the computer-readable storage medium is configured to store program code for executing the steps of triggering a top-level setting module in the verification platform to be activated, using the top-level setting module to set registers of the design module under test based on the functional description information of the target chip, and using the top-level setting module to set up a simulation environment of the verification platform; and triggering a scene exciter in the verification platform to be activated to generate excitation data, inputting the excitation data into the design module under test, using the excitation data to drive the design module under test, and performing simulation processing on the target chip, thereby obtaining simulation output data.

[0110] Preferably, in this embodiment, the computer-readable storage medium is configured to store program code for executing the steps of: inputting Excite data into a design module under test and using the Excite data to perform simulation processing on a target chip in the design module under test, triggering the logic monitor of the verification platform to activate to collect Excite data and simulation output data, and inputting the Excite data and simulation output data into an image processing model; and after determining that the image processing model has received the simulation output data, using a data processing module in the image processing model to perform format conversion on the simulation output data to obtain a simulation data stream.

[0111] Preferably, in this embodiment, the computer-readable storage medium is configured to store program code for executing the steps of obtaining configuration information of a register model in the verification platform and installation information of a simulation environment in the verification platform, and sending the configuration information and installation information to a configuration module of the image processing model, and using the configuration module to preprocess the configuration information and installation information, thereby pairing and aligning the configuration module with the top-level configuration module of the verification platform.

[0112] Preferably, in this embodiment, the computer-readable storage medium is configured to store program code for performing a step of obtaining an image algorithm output data stream by performing analytical processing of a predetermined dimension on the excitation data stream using setting information of an image processing algorithm and a register model in the verification platform, wherein the predetermined dimension includes at least one of pixel depth, color temperature, contrast, color vividness, and over-smoothing.

[0113] Preferably, in this embodiment, the computer-readable storage medium is configured to store program code for executing the steps of: obtaining a comparison result by comparing the simulation data stream and the image algorithm output data stream in the image processing model; determining that the actual function of the target chip is consistent with the function description information if the comparison result indicates that the simulation data stream and the image algorithm output data are completely consistent or the number of mismatches between the simulation data stream and the image algorithm output data is less than a predetermined threshold; and determining that the actual function of the target chip is inconsistent with the function description information if the comparison result indicates that the number of mismatches between the simulation data stream and the image algorithm output data is equal to or greater than the predetermined threshold.

[0114] Preferably, in this embodiment, a computer readable storage medium is provided to store program code for performing the step of storing the verification result in a log.

[0115] According to another aspect of an embodiment of the present application, there is further provided a processor for executing a program, the processor executing a chip hybrid simulation method based on any one of the above common verification methodologies and image processing algorithms when the program is executed.

[0116] The numbers of the above-mentioned embodiments of the present application are merely for the purpose of explanation and do not represent the superiority or inferiority of the embodiments.

[0117] In the above embodiments of the present application, the description of each embodiment focuses on different aspects, and for parts not described in detail in one embodiment, reference can be made to the relevant descriptions in other embodiments.

[0118] It should be understood that the technical contents disclosed in some embodiments provided in this application can be realized in other ways. The above-described device embodiments are merely illustrative. For example, the division of the units can be based on logical functions, but in actual implementation, division can be performed in other ways. For example, multiple units or components can be combined or integrated into another system, or some features can be omitted or not implemented. The shown or discussed mutual couplings, direct couplings, or communicative connections can be achieved through an interface, and the indirect couplings or communicative connections of units or modules can be achieved through electrical or other methods.

[0119] The units described as separate components may or may not be physically separated, and the components described as units may or may not be physical units, may be located in one place, or may be distributed among multiple units, and some or all of the units may be selected according to actual needs to achieve the objectives of the technical solution of this embodiment.

[0120] Furthermore, each functional unit in each embodiment of the present application may be integrated into a single processing unit, each unit may exist physically separately, or two or more units may be integrated into a single unit. The integrated unit may be realized by hardware or a software functional unit.

[0121] When the integrated unit is realized as a software functional unit and sold or used as an independent product, it may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application may be embodied essentially, or the part that contributes to the prior art, or all or part of the technical solution, as a software product, and the computer software product is stored in a storage medium and includes some instructions for causing a computer device (such as a personal computer, a server, or a network device) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes various media capable of storing program code, such as a USB hard disk, a ROM (Read-Only Memory), a RAM (Random Access Memory), a removable hard disk, a magnetic disk, or an optical disk.

[0122] The above is merely a preferred embodiment of the present application, and those skilled in the art may make some improvements and modifications without departing from the principles of the present application, and these improvements and modifications should also be considered to be included in the scope of protection of the present application.

Claims

1. After receiving a chip simulation task, generating an activation command based on the chip simulation task to trigger activation of a verification platform based on a common verification methodology, wherein an image processing model is integrated into the verification platform; After the simulation operating environment of the verification platform is operated, inputting Excite data into a test object design module, and using the Excite data to perform a simulation process on a target chip corresponding to the chip simulation task in the test object design module, thereby obtaining simulation output data; obtaining the Excite data and the simulation output data, and transmitting the Excite data and the simulation output data to the image processing model, and performing analysis processing on the output data using the image processing model to obtain a simulation result for the target chip; performing format conversion on the simulation output data and the Excite data in the image processing model to obtain a simulation data stream and an Excite data stream that can be identified by an image processing algorithm in the image processing model; processing the Excite data stream using the image processing algorithm to obtain an image algorithm output data stream; comparing the simulation data stream in the image processing model with the image algorithm output data stream to obtain a verification result of the target chip based on the comparison result, the verification result being for indicating whether the actual function of the target chip is consistent with function description information; A chip hybrid simulation method based on common verification methodology and image processing algorithm.

2. before generating a startup command based on the chip simulation task to trigger a verification platform based on a common verification methodology to be started; Obtaining the test target design module by calling and designing a logic code of the test target design module, the logic code being a code pre-created according to chip simulation needs; determining a plurality of components required to generate the verification platform based on the functional description information of the target chip, the plurality of components being components required to simulate the target chip; packaging the plurality of components using a methodology architecture corresponding to the verification platform and connecting the packaged components to obtain the verification platform including the design under test module and the packaged and connected components; A chip hybrid simulation method based on the common verification methodology and image processing algorithm of claim 1.

3. After the simulation operating environment of the verification platform is operated, inputting Excite data into a test object design module, and using the Excite data to perform a simulation process on a target chip corresponding to the chip simulation task in the test object design module to obtain simulation output data, Triggering a top-level configuration module in the verification platform to be activated, and using the top-level configuration module to configure registers of the design module under test according to the functional description information of the target chip, and using the top-level configuration module to set up a simulation environment of the verification platform; triggering a scene exciter in the verification platform to generate the excitation data, inputting the excitation data into the design under test module, driving the design under test module using the excitation data, and performing a simulation process on the target chip to obtain the simulation output data; A chip hybrid simulation method based on the common verification methodology and image processing algorithm of claim 1.

4. The step of obtaining a simulation data stream that can be identified by an image processing algorithm in the image processing model by performing format conversion on the simulation output data and the excitation data in the image processing model includes: inputting the Excite data into the test object design module, and using the Excite data to perform a simulation process on the target chip in the test object design module, triggering a logic monitor of the verification platform to start up, collecting the Excite data and the simulation output data, and inputting the Excite data and the simulation output data into the image processing model; and after determining that the image processing model has received the simulation output data, using a data processing module in the image processing model to perform format conversion on the simulation output data to obtain the simulation data stream. A chip hybrid simulation method based on the common verification methodology and image processing algorithm of claim 1.

5. prior to the step of processing the excitation data stream using the image processing algorithm to obtain an image algorithm output data stream; acquiring configuration information of a register model in the verification platform and installation information of a simulation environment in the verification platform; Sending the setting information and the installation information to a setting module of the image processing model, and using the setting module to pre-process the setting information and the installation information, thereby pairing and matching the setting module with a top-level setting module of the verification platform; A chip hybrid simulation method based on the common verification methodology and image processing algorithm of claim 1.

6. processing the excitation data stream using the image processing algorithm to obtain an image algorithm output data stream, performing a predetermined dimension analysis process on the excitation data stream using the image processing algorithm and setting information of a register model in the verification platform to obtain the image algorithm output data stream, wherein the predetermined dimension includes at least one of pixel depth, color temperature, contrast, color vividness, and over-smoothing; A chip hybrid simulation method based on the common verification methodology and image processing algorithm of claim 1.

7. The step of comparing the simulation data stream in the image processing model with the image algorithm output data stream and obtaining a verification result of the target chip based on the comparison result includes: obtaining a comparison result by comparing the simulation data stream with the image algorithm output data stream in the image processing model; determining that the actual function of the target chip is consistent with the function description information when the comparison result indicates that the simulation data stream and the image algorithm output data are completely consistent, or the number of mismatches between the simulation data stream and the image algorithm output data is less than a predetermined threshold; determining that the actual function of the target chip is inconsistent with function description information when the comparison result indicates that the number of inconsistencies between the simulation data stream and the image algorithm output data is equal to or greater than a predetermined threshold; A chip hybrid simulation method based on the common verification methodology and image processing algorithm according to any one of claims 1 to 6.

8. after comparing the simulation data stream in the image processing model with the image algorithm output data stream to obtain a verification result of the target chip based on the comparison result; further comprising storing the verification results in a log. A chip hybrid simulation method based on the common verification methodology and image processing algorithm of claim 7.

9. a trigger unit configured to receive a chip simulation task, and then generate an activation command according to the chip simulation task to trigger activation of a verification platform based on a common verification methodology, wherein the verification platform has an image processing model integrated therein; a first acquiring unit, configured to input Excite data into a test object design module after the simulation operating environment of the verification platform is operated, and use the Excite data to perform a simulation process on a target chip corresponding to the chip simulation task in the test object design module, thereby obtaining simulation output data; a second acquisition unit configured to acquire the excitation data and the simulation output data, and transmit the excitation data and the simulation output data to the image processing model, and use the image processing model to perform analysis processing on the output data, thereby obtaining a simulation result for the target chip; a third acquisition unit configured to perform format conversion on the simulation output data and the excitation data in the image processing model to obtain a simulation data stream and an excitation data stream that are identifiable by an image processing algorithm in the image processing model; a fourth acquisition unit configured to process the excitation data stream using the image processing algorithm to obtain an image algorithm output data stream; a fifth acquisition unit configured to compare the simulation data stream in the image processing model with the image algorithm output data stream, and obtain a verification result of the target chip based on the comparison result, the verification result being for indicating whether the actual function of the target chip is consistent with function description information; A chip hybrid simulation device based on a common verification methodology and image processing algorithm.

10. A processor for executing a program, A processor that, when the program is executed, executes a chip hybrid simulation method based on the common verification methodology and image processing algorithm according to any one of claims 1 to 8.

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