Row decoder and row address scheme in memory systems

Abstract

Numerous examples of row address decoding schemes are disclosed. In one example, a memory system includes m banks of nonvolatile memory cells, each of the m banks containing n or fewer sectors, each sector containing p rows, and a row decoder that receives a row address containing r bits, and (i) identifies the row using the least significant t bits in the r bits, (ii) identifies the bank using the next u least significant bits, and (iii) identifies the sector using the next v least significant bits, where m ≤ 2 u n≦2 v , and p≦2 t That is the case.

Description

[Technical Field]

[0001] (Claiming priority) This application claims priority to U.S. Patent Application No. 18 / 206,488, filed June 6, 2023, entitled "Row Decoder and Row Address Scheme in a Memory System," and to U.S. Provisional Patent Application No. 63 / 457,751, filed April 6, 2023, entitled "Row Address Decoding Scheme for Memory Banks Comprising Any Number of Sectors."

[0002] (Field of Invention) Numerous examples of row address decoding schemes that uniquely identify each row in a memory system by bank, sector, and row within a sector are disclosed. [Background technology]

[0003] Prior art includes non-volatile memory. For example, U.S. Patent No. 5,029,130 ​​("Patent No. 130"), incorporated herein by reference, discloses an array of split-gate non-volatile memory cells, a type of flash memory cell. Such a memory cell 110 is shown in Figure 1. Each memory cell 110 includes a source region 14 and a drain region 16 formed in a semiconductor substrate 12, with a channel region 18 between the source region 14 and the drain region 16. A floating gate 20 is formed insulated above a first portion of the channel region 18 (and controlling the conductivity of the first portion of the channel region 18) and extends above a portion of the source region 14. A word line terminal 22 (typically coupled to a word line) has a first portion disposed above a second portion of the channel region 18 and insulated from (and controlling the conductivity of) the second portion, and a second portion extending above the floating gate 20. The floating gate 20 and the word line terminal 22 are insulated from the substrate 12 by a gate oxide. Bit line 24 is connected to drain region 16.

[0004] By applying a positive high voltage to the word line terminal 22, the memory cell 110 is erased (electrons are removed from the floating gate), causing the electrons on the floating gate 20 to pass through the intermediate insulator via a Fowler-Nordheim (FN) tunnel from the floating gate 20 to the word line terminal 22.

[0005] The memory cell 110 is programmed by source-side injection (SSI) with hot electrons by applying a positive voltage to the word line terminal 22 and a positive voltage to the source region 14 (electrons are added to the floating gate). The electron flow flows from the drain region 16 towards the source region 14. The electrons are accelerated and generate heat when they reach the gap between the word line terminal 22 and the floating gate 20. Some of the heated electrons are injected into the floating gate 20 via the gate oxide due to the electrostatic attraction from the floating gate 20.

[0006] The memory cell 110 is read by applying a positive read voltage to the drain region 16 and the word line terminal 22 (turning on the portion of the channel region 18 below the word line terminal). When the floating gate 20 is positively charged (i.e., electrons are erased), the portion of the channel region 18 below the floating gate 20 is also turned on, and current flows through the channel region 18, which is detected as the erased state, i.e., the "1" state. When the floating gate 20 is negatively charged (i.e., electrons are programmed), the portion of the channel region below the floating gate 20 is almost or completely off, and no (or very little) current flows through the channel region 18, which is detected as the programmed state, i.e., the "0" state.

[0007] Table 1 shows typical voltage / current ranges that may be applied to the terminals of the memory cell 110 to perform read, erase, and program operations. Table 1: Operation of flash memory cell 110 in Figure 1 [Table 1]

[0008] Other types of flash memory cells, other split-gate memory cell configurations, are available in the art. For example, Figure 2 shows a four-gate memory cell 210 including a source region 14, a drain region 16, a floating gate 20 above a first portion of the channel region 18, a selection gate 22 (typically coupled to a word line WL) above a second portion of the channel region 18, a control gate 28 above the floating gate 20, and an erase gate 30 above the source region 14. This configuration is described in U.S. Patent No. 6,747,210, which is incorporated herein by reference for all purposes. Here, all gates are non-floating gates, except for the floating gate 20; that is, they are electrically connected to or can be connected to a voltage source. Programming is performed by heated electrons injecting themselves from the channel region 18 into the floating gate 20. Erasing is performed by electrons tunneling from the floating gate 20 to the erase gate 30.

[0009] Table 2 shows typical voltage / current ranges that may be applied to the terminals of the memory cell 210 to perform read, erase, and program operations. Table 2: Operation of flash memory cell 210 in Figure 2 [Table 2]

[0010] Figure 3 shows a different type of split-gate flash memory cell, a 3-gate memory cell 310. Memory cell 310 is identical to memory cell 210 in Figure 2, except that memory cell 310 does not have a separate control gate. The erase operation (erasure occurs through the use of the erase gate) and read operation are the same as those in Figure 2, except that no control gate bias is applied. The programming operation is also performed without a control gate bias; as a result, a higher voltage is applied to the source line during programming to compensate for the lack of control gate bias.

[0011] Table 3 shows typical voltage / current ranges that may be applied to the terminals of the memory cell 310 to perform read, erase, and program operations. Table 3: Operation of the flash memory cell 310 in Figure 3 [Table 3]

[0012] Figure 4 shows a different type of flash memory cell, a stacked gate memory cell 410. Memory cell 410 is similar to memory cell 110 in Figure 1, except that the floating gate 20 extends above the entire channel region 18, and the control gate 22 (coupled here to the word line) extends above the floating gate 20, separated by an insulating layer (not shown). Erase is performed by FN tunneling of electrons from the FG to the substrate, programming is performed by channel hot electron (CHE) injection in the region between the channel 18 and the drain region 16, and read operations are performed by electrons flowing from the source region 14 to the drain region 16, similar to the read operation of memory cell 110, which has a higher control gate voltage.

[0013] Table 4 shows typical voltage ranges that can be applied to the terminals of the memory cell 410 and the circuit board 12 for performing read, erase, and program operations. Table 4: Operation of the flash memory cell 410 in Figure 4

Table 4

[0014] The methods and means described in this specification can be applied to other non-volatile memory technologies including, but not limited to, FINFET split gate flash or stacked gate flash memory, NAND flash, SONOS (silicon-oxide-nitride-oxide-silicon, charge trap in nitride), MONOS (metal-oxide-nitride-oxide-silicon, metal charge trap in nitride), ReRAM (resistive ram), PCM (phase change memory), MRAM (magnetic ram), FeRAM (ferroelectric ram), CT (charge trap) memory, CN (carbon-tube) memory, OTP (one time programmable, capable of only one program at binary or multi-level), and CeRAM (correlated electron ram).

[0015] Non-volatile memory cells are arranged in an array including rows and columns of non-volatile memory cells. In a simple configuration, a single physical array encompasses all of the non-volatile memory cells of the memory system and extends over the same range as the logical array presented to components external to the memory system, such as a CPU utilizing the memory system. In a more complex configuration, multiple physical arrays are used and include the non-volatile memory cells of the memory system. In this situation, the logical array can be mapped to the multiple physical arrays.

[0016] In yet another configuration, multiple banks are used and include the non-volatile memory cells of the memory system. A bank can include a single physical array or multiple physical arrays. Instead of using a single physical array, by dividing the logical array among different banks, the overall speed of the system can be increased, the overall leakage of the memory system can be reduced, and the margin for read or program operations can be enhanced (since read or program operations are not overly affected by memory cell leakage), and parasitic capacitance can be reduced. However, since a portion of the address will be allocated to identify the bank for an operation, it has the drawback of requiring additional address decoding.

[0017] FIG. 5 shows a prior art memory system 500. Memory system 500 includes a logical array 550 formed from banks 501, 502, 503, and 504. In one example, logical array 550 can store 8 Mb of data. In this example, banks 501, 502, 503, and 504 each store 2 Mb of data and include 512 rows and 4096 bit lines.

[0018] Referring to FIG. 6, the prior art banks 501, 502, 503, and 504 can include sectors. In this example, banks 501, 502, 503, and 504 each include N + 1 sectors called sector 0, sector 1,..., sector (N - 1), and sector N. Each sector includes two or more consecutive rows of memory cells within the bank.

[0019] Figure 7 shows a prior art memory system 700. The memory system 700 comprises a logic array 750 formed from banks 701, 702, 703, and 704. The memory system 700 further comprises column multiplexers 705, 706, 707, and 708, sense amplifiers and column drivers 709 and 710, high voltage (HV) decoders and latches 712, 713, 714, and 715, and row decoders 711 and 712. The banks 701, 702, 703, and 704 form a logic array of non-volatile memory cells arranged in rows and columns. Column multiplexer 705 operates on the columns of bank 701, column multiplexer 706 operates on the columns of bank 702, column multiplexer 707 operates on the columns of bank 703, and column multiplexer 708 operates on the columns of bank 704. Row decoder 711 operates on the rows of banks 701 and 702, and row decoder 712 operates on the rows of banks 703 and 704. Sense amplifiers and column drivers 709 perform sense operations on the outputs received from column multiplexers 705 and 707 during read operations (i.e., to read "1" or "0" stored in the memory cell) and control the current applied to the columns of banks 701 and 703 through column multiplexers 705 and 707 during programming operations. The sense amplifier and column driver 710 perform sense operations on the outputs received from column multiplexers 706 and 708 during read operations and control the current applied to the columns of banks 702 and 704 through column multiplexers 706 and 708 during programming operations. The HV decoders and latches 712, 713, 714, and 715 provide high voltages to the rows of banks 701, 702, 703, and 704, respectively, during, for example, program or erase operations.

[0020] Conventional systems assign several rows within the logical array 750 to each bank 701, 702, 703, and 704, and the number of rows is a power of 2, i.e., 2 nHere, n is an integer and is the number of address bits required to decode any particular row in a bank. For example, if a logical array can store 32Mb, then logical array 750 may contain 8192 rows × 4096 columns, which can be divided into 16 banks of 512 rows × 4096 bit lines per bank (in addition to banks 701, 702, 703, and 704, other banks not shown may be used), 512 = 2 9 , where n=9. In this example, the row address requires 13 address bits XA[12:0], of which the bank address requires four of those bits, such as XA[12:9] (representing bits at bit positions 12, 11, 10, and 9 within the 13 address bits, with bit positions ranging from bit position 12 to bit position 0), to distinguish between 16 different banks. Here, the total number of rows is 512. * 16 = 8192 = 2 13 Banks 701, 702, 703, and 704 optionally contain sectors.

[0021] In a simpler example involving 16 rows, these 16 rows can be divided among four banks according to the addressing scheme shown in Table 5. Table 5: Bank assignment of 16 rows [Table 5]

[0022] In the example in Table 5, the number of rows in each bank is a power of 2 (i.e., 2 nTherefore, the two most significant bits (MSBs) in the row address, XA[3] and XA[2], can be used as bank identifiers, where XA[3:2]=00 indicates bank 0, XA[3:2]=01 indicates bank 1, XA[3:2]=10 indicates bank 2, and XA[3:2]=11 indicates bank 3. In this way, the row address can be decoded very quickly to identify the appropriate bank for read, program, or erase operations. If each bank contains sectors formed by two rows per sector, XA[1] ​​can be used to identify within a particular bank, and XA[0] can be used to identify a row within a particular sector. However, this method does not work if a sector is formed by a different number of rows, for example, three rows, nor does it work if a bank contains a different number of sectors.

[0023] This approach assumes that the number of rows allocated to the bank is a power of 2 (i.e., 2 n If not, then in that situation, bank identification will not work because it does not properly correspond to the number of bits in the row address. Also, this approach is not suitable if the total number of rows is 2 r If not equal to , r is the number of row address bits, for example r=9, then the total number of rows is 512 (i.e., 2 9 If it is 510 instead of ), it will not work. For example, in the example in Table 5, if six rows were instead assigned to each bank, the addressing scheme shown in Table 5 would not function to uniquely identify each bank and row. Furthermore, since sectors contain rows that are physically contiguous with each other, it is desirable for any addressing and decoding scheme to keep the rows of a sector within the same bank, which adds to the challenge. For example, a sector may have a number of rows that is a multiple of two, since two contiguous rows share one or more of the erase gate lines and control gate lines.

[0024] Table 6 shows an example where 36 rows are assigned to four banks. Note that 36 is not a power of 2. In this example, banks 0 and 1 each have 10 rows, and banks 2 and 3 each have 8 rows. In such a scheme, the conventional row decoding method would be insufficient. Therefore, a conventional system may use combinational logic on four or five of the most significant bits of the row address to identify the bank of a particular row. For example, bank 3 can be represented by XA[5:2]=

[0111] OR

[1100] , bank 2 by XA[5:2]=

[0101] OR

[0110] , bank 1 by XA[5:1]=

[0101] OR XA[5:2]=

[0011] OR

[0100] , and bank 0 by XA[5:1]=

[0000] OR

[0001] OR

[0100] . The combinational logic required to implement this decoding function is complex and will require a considerable amount of die space. Table 6: Bank assignment of 36 rows [Table 6]

[0025] If each bank contains sectors formed by two rows per sector, then XA[1] ​​can be used to identify a particular bank, and XA[0] can be used to identify a row within a particular sector. However, this method does not work if a sector is formed by a different number of rows, for example, three rows, nor does it work if a bank contains a different number of sectors.

[0026] A new address decoding scheme is desired that can handle situations where the number of rows allocated to a bank is not a power of two, and where sector rows can be kept within the same bank. [Overview of the Initiative]

[0027] Numerous examples of row address decoding schemes that uniquely identify each row in a memory system by bank, sector, and row within a sector are disclosed. The row addressing schemes described herein can handle situations where the number of sectors is odd or even, where a bank contains either an odd or even number of sectors, and where the total number of rows in a bank is a power of 2 or not.

[0028]

[0029]

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[0031]

[0032]

[0033]

[0034]

[0035]

[0036]

[0037] [Brief explanation of the drawing]

[0038] [Figure 1] This shows a prior art split-gate flash memory cell. [Figure 2] This shows another prior art split-gate flash memory cell. [Figure 3] This shows another prior art split-gate flash memory cell. [Figure 4] This shows a stacked gate flash memory cell of prior art. [Figure 5] This shows a memory system with logical arrays stored in multiple banks. [Figure 6] Figure 5 shows the components of the memory system. [Figure 7] This indicates a bank with multiple sectors. [Figure 8] This shows a memory system with multiple banks. [Figure 9] This shows another memory system with multiple banks. [Figure 10] This shows the address decoding scheme. [Figure 11] Here's another address decryption method. [Modes for carrying out the invention]

[0039] In the examples described herein, a row address includes multiple bits, where a first set of bits is used to identify a bank, a second set of bits is used to identify a sector within a bank, and a third set of bits is used to identify a row within a sector. However, unlike the prior art, the addressing scheme described herein can handle situations where the number of sectors is either odd or even, where a bank contains either an odd or even number of sectors, and where the total number of rows in a bank is a power of two or not.

[0040] Figure 8 shows an exemplary memory system in which one or more banks contain an even number of sectors, one or more banks contain an odd number of sectors, the banks contain a different number of sectors, and the memory system contains a total number of rows that is not a power of two. In this example, there are four banks and 18 sectors, and each sector contains two rows. Here, banks 801 and 803 are each allocated five sectors, and banks 802 and 804 are each allocated four sectors. Since each sector has two rows, the least significant bit XA[0] will be used to decode the rows within each sector. That is, since a sector contains two rows, XA[0]=0 will indicate one row and XA[0]=1 will indicate the other row.

[0041] The memory system 800 comprises a logic array 850 formed from banks 801, 802, 803, and 804. The memory system 800 further comprises column multiplexers 805, 806, 807, and 808, sense amplifiers and column drivers 809 and 810, row decoders 811, 812, 813, and 814, and high-voltage decoders and latches 815, 816, 817, 818, 819, and 820. Banks 801, 802, 803, and 804 each comprise arrays of non-volatile memory cells arranged in rows and columns, respectively. The non-volatile memory cells can be split-gate flash memory cells such as memory cells 110, 210, and 310 in Figures 1, 2, and 3, or stacked-gate flash memory cells such as memory cell 410 in Figure 4. Bank 801 comprises sectors 0, 1, 2, 3, and 4; Bank 802 comprises sectors 10, 11, 12, and 13; Bank 803 comprises sectors 5, 6, 7, 8, and 9; and Bank 804 comprises sectors 14, 15, 16, and 17. In Figure 8, the sector number is the global sector number, which is a unique number that identifies a sector from among all sectors in all banks.

[0042] Column multiplexer 805 operates on the columns of bank 801, column multiplexer 806 operates on the columns of bank 802, column multiplexer 807 operates on the columns of bank 803, and column multiplexer 808 operates on the columns of bank 804.

[0043] Row decoder 811 operates on rows in bank 801 corresponding to sectors 0, 1, 2, and 3, and rows in bank 802 corresponding to sectors 10, 11, 12, and 13; row decoder 813 operates on rows in bank 801 corresponding to sector 4; row decoder 812 operates on rows in bank 803 corresponding to sectors 5, 6, 7, and 8, and rows in bank 804 corresponding to sectors 14, 15, 16, and 17; and row decoder 814 operates on rows in bank 803 corresponding to sector 9.

[0044] The sense amplifier and column driver 809 performs sense operations on the outputs received from column multiplexers 805 and 807 during read operations and controls the current applied to the columns of banks 801 and 803 through column multiplexers 805 and 807 during programming operations. The sense amplifier and column driver 810 performs sense operations on the outputs received from column multiplexers 806 and 808 during read operations and controls the current applied to the columns of banks 802 and 804 through column multiplexers 806 and 808 during programming operations.

[0045] HV decoder and latch 815 provides high voltage (for example, for program or erase operations) to rows in bank 801 corresponding to sectors 0, 1, 2, and 3; HV decoder and latch 816 provides high voltage to rows in bank 802 corresponding to sectors 10, 11, 12, and 13; HV decoder and latch 817 provides high voltage to rows in bank 803 corresponding to sectors 5, 6, 7, and 8; HV decoder and latch 818 provides high voltage to rows in bank 804 corresponding to sectors 14, 15, 16, and 17; HV decoder and latch 819 provides high voltage to rows in bank 801 corresponding to sector 4; and HV decoder and latch 820 provides high voltage to rows in bank 803 corresponding to sector 9.

[0046] Table 7 shows the bank assignment scheme implemented by row decoders 811, 812, 813, and 814 in the example shown in Figure 8. Table 7: Bank assignments for 36 rows [Table 7]

[0047] In the example in Table 7, XA[2:1] is used to identify the bank, XA[5:3] is used to identify the sector within the bank (each sector within the bank is also assigned a global sector number, which is the sector number across all banks), and XA[0] is used to identify the row within the sector. In particular, no additional combinational logic is required to identify the bank from the row address, and decoding is performed by row decoders 811, 812, 813, and 814.

[0048] Figure 9 shows an exemplary memory system in which one or more banks contain an even number of sectors, one or more banks contain an odd number of sectors, the banks contain a different number of sectors, and the memory system contains a total number of rows that is not a power of two. In this example, there are four banks and 17 sectors, and each sector contains two rows. Here, bank 901 is allocated five sectors, and banks 902, 903, and 904 are each allocated four sectors. Since each sector has two rows, the least significant bit XA[0] is used to decode the rows within each sector. That is, since a sector contains two rows, XA[0]=0 indicates one row and XA[0]=1 indicates the other row. It is desirable that the sense amplifiers and column drivers 909 and 910 have balanced upper and lower bit lines. Therefore, if an upper bank such as bank 901 contains five sectors, it is desirable that a lower bank such as bank 903 also contains five sectors. Since bank 901 contains 5 sectors and bank 903 contains 4 sectors, a dummy sector 921 is added to bank 903. The dummy sector 921 is not used to store data.

[0049] The memory system 900 comprises a logic array 950 formed from banks 901, 902, 903, and 904. The memory system 900 further comprises column multiplexers 905, 906, 907, and 908, sense amplifiers and column drivers 909 and 910, row decoders 911, 912, 913, and 914, and high-voltage decoders and latches 915, 916, 917, 918, 919, and 920. Banks 901, 902, 903, and 904 each comprise arrays of non-volatile memory cells arranged in rows and columns, respectively. The non-volatile memory cells can be split-gate flash memory cells such as memory cells 110, 210, and 310 in Figures 1, 2, and 3, or stacked-gate flash memory cells such as memory cell 410 in Figure 4. Bank 901 comprises sectors 0, 1, 2, 3, and 4; Bank 902 comprises sectors 9, 10, 11, and 12; Bank 903 comprises sectors 5, 6, 7, 8, and a dummy sector 921; and Bank 904 comprises sectors 13, 14, 15, and 16.

[0050] Column multiplexer 905 operates on the columns of bank 901, column multiplexer 906 operates on the columns of bank 902, column multiplexer 907 operates on the columns of bank 903, and column multiplexer 908 operates on the columns of bank 904.

[0051] Row decoder 911 operates for rows in bank 901 corresponding to sectors 0, 1, 2, and 3, and rows in bank 902 corresponding to sectors 9, 10, 11, and 12; row decoder 913 operates for rows in bank 901 corresponding to sector 4; row decoder 912 operates for rows in bank 903 corresponding to sectors 5, 6, 7, and 8, and rows in bank 904 corresponding to sectors 13, 14, 15, and 16. Row decoder 914 corresponds to rows in bank 903 corresponding to dummy sector 921. Row decoder 914 is optional and is included to allow the possibility that dummy sector 921 can be converted to a normal sector used for storing and retrieving data.

[0052] The sense amplifier and column driver 909 performs a sense operation on the outputs received from column multiplexers 905 and 907 during readout operations and controls the current applied to the columns of banks 901 and 903 through column multiplexers 905 and 907 during programming operations. The sense amplifier and column driver 910 performs a sense operation on the outputs received from column multiplexers 906 and 908 during readout operations and controls the current applied to the columns of banks 902 and 904 through column multiplexers 906 and 908 during programming operations.

[0053] HV decoder and latch 915 provides high voltage (e.g., for program or erase operations) to rows in bank 901 corresponding to sectors 0, 1, 2, and 3; HV decoder and latch 916 provides high voltage to rows in bank 902 corresponding to sectors 9, 10, 11, and 12; HV decoder and latch 917 provides high voltage to rows in bank 903 corresponding to sectors 5, 6, 7, and 8; HV decoder and latch 918 provides high voltage to rows in bank 904 corresponding to sectors 13, 14, 15, and 16; and HV decoder and latch 919 provides high voltage to rows in bank 901 corresponding to sector 4. HV decoder and latch 920 corresponds to rows in bank 903 corresponding to dummy sector 921. HV decoder and latch 920 is optional and is included to allow the possibility that dummy sector 921 can be converted into a normal sector used for storing and retrieving data. In Figure 9, the sector number is the global sector number, which is a unique number that identifies a sector from among all sectors in all banks.

[0054] Table 8 shows the bank assignment scheme implemented by row decoders 911, 912, 913, and 914 for this example. Table 8: Bank assignments for 34 rows [Table 8]

[0055] In this example, XA[2:1] is used to identify a bank, XA[5:3] is used to identify a sector within a bank (each sector within a bank is also assigned a global sector number that is the sector number across all banks), and XA[0] is used to identify a row within a sector. In particular, no additional combinational logic is required to identify a bank from the row address, and decoding is performed by row decoders 911, 912, 913, and 914.

[0056] FIG. 10 shows an address decoding scheme 1000 implemented by row decoder 1002. In one example, row decoders 811, 813, 813, and 814 of FIG. 8, and row decoders 911, 912, 913, and 914 of FIG. 9 are instances of row decoder 1002 according to address decoding scheme 1000. Thus, row decoder 1002 can operate as row decoders 811, 812, 813, and 814 within memory system 800 of FIG. 8, and as row decoders 911, 912, 913, and 914 of FIG. 9. Row address 1001 includes r bits and is provided to row decoder 1002 (which is an example of row decoders 811, 813, 813, and 814 of FIG. 8, and row decoders 911, 912, 913, and 914 of FIG. 9 as shown), and row decoder 1002 asserts various control signals corresponding to the sector, bank, and row identified by row address 1001.

[0057] Under address decoding scheme 1000, the t least significant bits within row address 1001 identify a row within a sector, the u next least significant bits within row address 1001 identify a bank within the memory system, the v next least significant bits within row address 1001 identify a sector within a bank, and t + u + v ≤ r (for example, one or more bits within the r bits can be used for another purpose). Generally, when the system includes m banks of non-volatile memory cells, each bank includes n or fewer sectors, and each sector includes p rows, t, u, and v are selected to satisfy the following conditions. m ≤ 2 u n≦2 v p ≤ 2 t

[0058] For example, when m=4, n=5, and p=2 (as in the example in Figure 8 and Table 7), u=2, v=3, and t=1. This makes sense because four banks can be identified by 2 bits (00, 01, 10, and 11), five sectors can be identified by 3 bits (e.g., 000, 001, 010, 011, 100), and two rows can be identified by 1 bit (0, 1).

[0059] The address decoding scheme 1000 is n * This is effective for configurations that were not possible with conventional systems, such as configurations where p is not a power of 2, n is odd, banks contain a different number of sectors, and the total number of rows is not a power of 2.

[0060] Figure 11 shows an address decoding method 1100 that can be performed using the row decoder 1002 of Figure 10. The first operation is to receive a row address containing r bits by the row decoder 1002 (1101). The second operation is to use the row decoder to identify one row out of p rows of nonvolatile memory cells in a logic array formed by m banks using the least significant t bits in the r bits, to identify one bank out of m banks using the next u least significant bits in the r bits, and to identify one sector out of n sectors in the bank using the next v least significant bits, where m ≤ 2 u n≦2 v , and p≦2 t (1102).

[0061] It should be noted that, as used herein, the terms “over” and “on” both encompass “directly” (no intermediate material, element, or gap is located between them) and “indirectly to” (intermediate material, element, or gap is located between them). Similarly, the term “adjacent” includes “directly adjacent” (no intermediate material, element, or gap is located between them) and “indirectly adjacent” (intermediate material, element, or gap is located between them); “attached” includes “directly attached” (no intermediate material, element, or gap is located between them) and “indirectly attached to” (intermediate material, element, or gap is located between them); and “electrically coupled” includes “directly electrically coupled” (no intermediate material or element electrically connecting the elements together between them) and “indirectly electrically coupled to” (intermediate material or element electrically connecting the elements together between them). For example, forming an element "on top of a substrate" may include forming the element directly on the substrate without any intermediate materials / elements between them, and forming the element indirectly on the substrate with one or more intermediate materials / elements between them.

Claims

1. It is a memory system, A set of m banks of multiple non-volatile memory cells, each of the m banks containing n or fewer sectors, and each of the sectors containing p rows, A row decoder that takes a row address containing r bits, (i) uses the least significant t bits in the r bits to identify a row, (ii) uses the next u least significant bits to identify a bank, and (iii) uses the next v least significant bits to identify a sector, where m ≤ 2 ｕ n ≤ 2 ｖ , and p ≤ 2 ｔ This is a memory system.

2. n ＊ The memory system according to claim 1, wherein p is not a power of 2.

3. The memory system according to claim 1, wherein n is an odd number.

4. The memory system according to claim 1, wherein the non-volatile memory cell includes a split-gate flash memory cell.

5. The memory system according to claim 1, wherein the non-volatile memory cell includes a stacked gate flash memory cell.

6. The memory system according to claim 1, wherein the number of sectors in one bank is even.

7. The memory system according to claim 1, wherein the number of sectors in one bank is odd.

8. The memory system according to claim 1, wherein the number of sectors in one bank is different from the number of sectors in another bank.

9. The total number of rows in the aforementioned memory system is 2 ｒ The memory system according to claim 1, which is not equal to.

10. It is a method, The row decoder receives a row address containing r bits, The row decoder includes the steps of: using the least significant t bits in the r bits to identify one row in p rows of a plurality of nonvolatile memory cells in a logic array formed by m banks; using the next u least significant bits in the r bits to identify one bank in the m banks; and using the next v least significant bits to identify one sector in n sectors within the bank, where m ≤ 2 ｕ n ≤ 2 ｖ , and p ≤ 2 ｔ The method.

11. n ＊ The method according to claim 10, wherein p is not a power of 2.

12. The method according to claim 10, wherein n is an odd number.

13. The method according to claim 10, wherein the non-volatile memory cell includes a split-gate flash memory cell.

14. The method according to claim 10, wherein the non-volatile memory cell includes a stacked gate flash memory cell.

15. The method according to claim 10, wherein the number of sectors in the bank is even.

16. The method according to claim 10, wherein the number of sectors in the bank is odd.

17. The method according to claim 10, wherein the number of sectors in one bank is different from the number of sectors in another bank.

18. The total number of rows mentioned above is 2 ｒ The method according to claim 10, which is not equal to.

19. It is a memory system, A set of m banks of multiple non-volatile memory cells, each of the m banks containing n or fewer sectors, and each of the sectors containing p rows, A row decoder that receives a row address containing r bits and uses those r bits to identify a row, and includes The total number of rows in the aforementioned m banks is not a power of 2 in the system.

20. The system according to claim 19, wherein at least two of the m banks include a different number of sectors.

21. The system according to claim 19, wherein the row decoder uses a subset of the r bits to identify a bank in the m banks.

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