Memory array of 3D NOR memory strings equipped with word line selection device

Abstract

The memory circuit of this disclosure comprises an array of thin-film ferroelectric memory transistors formed by a plurality of NOR memory strings intersecting a plurality of local word line (LWL) structures, and a word line selection transistor associated with each LWL structure to isolate each LWL structure from its associated global word line. The global word line is arranged orthogonally to the array of NOR memory strings and aligned with a set of LWL structures provided across a plurality of stacks of NOR memory strings. During operation, the word line selection transistor selectively connects a selected LWL structure to its associated global word line. The remaining LWL structures associated with the same global word line remain unconnected and unselected. In this way, parasitic capacitance on the global word line is reduced, as is unintended disturbance to other unselected memory transistors.

Description

Technical Field

[0001] The present invention relates to memory circuits, high-density memory structures, and methods for manufacturing them. In particular, the present invention relates to a memory array of a NOR memory string provided with a word line selection device.

Background Art

[0002] A NOR memory string comprises storage transistors that share a common source region and a common drain region, and each storage transistor can be individually addressed and accessed. U.S. Patent No. 10,121,553 (Patent Document 1), issued on November 6, 2018, entitled "Capacitively Coupled Non-Volatile Thin-Film Transistor NOR String in a Three-Dimensional Array," discloses a storage transistor (or memory transistor) configured as a three-dimensional array of NOR memory strings formed on the upper plane of a semiconductor substrate. The entire disclosure of Patent Document 1 is incorporated herein by reference for any purpose. The NOR memory string disclosed in Patent Document 1 comprises a number of thin-film storage transistors that share a common bit line and a common source line. In particular, Patent Document 1 discloses a NOR memory string comprising (i) a common source region and a common drain region extending longitudinally along the horizontal direction, and (ii) gate electrodes for storage transistors extending vertically. Herein, the term "vertical" refers to a direction perpendicular to the surface of the semiconductor substrate, and the term "horizontal" refers to a direction parallel to the surface of the semiconductor substrate. In such a three-dimensional array, NOR memory strings are arranged on multiple planes (e.g., eight or sixteen planes) on the upper side of the semiconductor substrate, and the NOR memory strings on each plane are arranged in a matrix. In the case of charge-trapped storage transistors, data is stored in each storage transistor using a charge storage film as the gate dielectric material. For example, the charge storage film includes a tunnel dielectric layer, a charge trapping layer, and a blocking layer, which can be realized as a multilayer structure of silicon oxide (or oxynitride), silicon-rich nitride, and silicon oxide stacked in that order, and is called an ONO layer. An electric field applied to the charge storage film changes the threshold voltage of the storage transistor by adding charge to or removing charge from the charge trapping layer of the charge storage film, thereby encoding a given logic state within the storage transistor.

[0003] Advances in electrically polarizable materials ("ferroelectric materials"), particularly those used in semiconductor manufacturing processes, suggest new potential applications in ferroelectric memory circuits. High-density memory arrays realized using three-dimensional arrays of NOR memory strings of ferroelectric memory transistors are disclosed, for example, in U.S. Patent Application No. 17 / 936,320 (Patent Document 2), filed September 28, 2022, entitled "Memory Structure Including Three-Dimensional NOR Memory Strings of Junctionless Ferroelectric Memory Transistors and Method for Manufacturing the Same." The entire disclosure of Patent Document 2 is incorporated herein by reference for all purposes. Patent Document 2 describes a memory structure including randomly accessible ferroelectric memory transistors configured as horizontal NOR memory strings. The NOR memory strings are formed on a semiconductor substrate in a plurality of scalable memory stacks of thin-film memory transistors. In some examples, these three-dimensional memory stacks are manufactured using a method that includes the steps of forming operational trenches for vertical local word lines and forming auxiliary trenches by back-side selective etching to facilitate back-array metal substitution and channel isolation. A three-dimensional array of NOR-type memory strings of thin-film ferroelectric transistors is disclosed, for example, in U.S. Patent Application No. 17 / 812,375, “Three-Dimensional Memory String Array of Thin-Film Ferroelectric Transistors” (Patent Document 3), filed on 13 July 2022. The entire disclosure of Patent Document 3 is incorporated herein by reference. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] U.S. Patent No. 10,121,553 [Patent Document 2] U.S. Patent Application No. 17 / 936,320 [Patent Document 3] U.S. Patent Application No. 17 / 812,375 [Patent Document 4] U.S. Patent Application No. 18 / 419,385

[0005] This disclosure provides memory circuits or memory structures comprising three-dimensional NOR memory strings of thin-film ferroelectric memory transistors, and methods for manufacturing them. This disclosure is substantially described with reference to, for example, at least one figure, and is more fully described in the claims.

[0006] In some embodiments, the present disclosure provides a memory circuit. The memory circuit of the present disclosure comprises an array of thin-film ferroelectric memory transistors formed by a plurality of NOR memory strings intersecting a plurality of local word line structures. The plurality of NOR memory strings are arranged as a plurality of stacks comprising vertically aligned NOR memory strings. Each NOR memory string has a common drain line and a common source line. The memory circuit of the present disclosure also comprises a plurality of local word line structures. The plurality of local word line structures comprises a group comprising a plurality of local word line structures. The local word line structures within each group are arranged along the NOR memory strings of at least one stack. Each local word line structure extends vertically along the vertically aligned NOR memory strings in at least one stack and has a channel layer and a gate conductor layer separated from each other by a ferroelectric gate dielectric layer. The thin-film ferroelectric memory transistors are formed at the locations where the common drain line and common source line of each local word line structure intersect with each NOR memory string. The gate conductor layer of each local word line structure functions as a common gate terminal for thin-film ferroelectric memory transistors in vertically aligned NOR memory strings within each stack that intersect with each local word line structure.

[0007] Furthermore, the memory circuit of the present disclosure comprises a plurality of global word lines arranged orthogonally to a plurality of NOR memory strings. Each global word line is aligned with a set of local word line structures provided across a plurality of stacks. The memory circuit of the present disclosure also comprises a plurality of word line selection transistors. The plurality of word line selection transistors comprises a group consisting of a plurality of word line selection transistors. Each group of word line selection transistors is arranged along a NOR memory string of at least one stack. Each word line selection transistor is provided between each local word line structure and its associated global word line and has a source terminal which is the gate conductor layer of the associated local word line structure, a drain terminal which is connected to the associated global word line, and a gate terminal which is connected to receive its respective selection gate signal. Each group of word line selection transistors is controlled by the same selection gate signal. When a global word line is asserted and a set of associated local word line structures is selected, each group of word line selection transistors is activated by its respective selection gate signal to electrically connect the asserted global word line to the common gate terminal of its associated local word line structure, thereby activating one of the local word line structures in the set of local word line structures.

[0008] In other embodiments, the present disclosure provides a three-dimensional memory structure formed on a plane of a semiconductor substrate. The three-dimensional memory structure of the present disclosure comprises an array of thin-film ferroelectric memory transistors configured as a plurality of stacks of NOR memory strings. Each stack is separated from adjacent stacks along a first direction by trenches. The plurality of stacks extend along a second direction substantially parallel to the plane of the semiconductor substrate. The NOR memory strings of each stack are stacked on top of each other along a third direction substantially orthogonal to the plane of the semiconductor substrate. Each NOR memory string has a common drain layer formed spaced apart from a common source layer. Local word line structures are provided in contact with the stacks of NOR memory strings and spaced apart from each other in the second direction. Each local word line structure extends in the third direction. Each local word line structure has a channel layer in contact with the NOR memory strings in the associated stack, a ferroelectric gate dielectric layer formed adjacent to the channel layer, and a gate conductor layer provided within the local word line structure adjacent to the ferroelectric gate dielectric layer. The gate conductor layer functions as a common gate terminal for thin-film ferroelectric memory transistors within the NOR memory strings in each stack associated with the local word line structure.

[0009] Furthermore, the three-dimensional memory structure of this disclosure comprises a plurality of word line selection transistors. Each word line selection transistor is associated with a given local word line structure. Each word line selection transistor has a source terminal which is the gate conductor layer of the local word line structure associated with it, a drain terminal which is connected to one of the plurality of global word lines, and a gate terminal which is connected to receive its respective selection gate signal. When a first global word line of the plurality of global word lines is asserted and a set of local word line structures associated with it is selected, the first word line selection transistor is activated by the first selection gate signal to electrically connect the asserted first global word line to the common gate terminal of the local word line structure associated with it, thereby activating one of the local word line structures in the set of local word line structures. [Overview of the project] [Means for solving the problem]

[0010] The above and other advantages, aspects and novel features of the present invention, as well as details of the exemplary embodiments thereof, will be better understood by referring to the following description and accompanying drawings. [Brief explanation of the drawing]

[0011] Various embodiments of the present invention are disclosed in the following detailed description and accompanying drawings. While the drawings depict various embodiments of the present invention, the present invention is not limited to the embodiments depicted. It should be understood that in the drawings, similar reference numerals indicate similar structural elements. Furthermore, it should be understood that the depictions in the drawings are not necessarily drawn to a consistent scale.

[0012] [Figure 1] Figure 1 is a perspective view of a memory structure including a three-dimensional array of NOR memory strings in several embodiments. [Figure 1A]Figure 1A is a perspective view of a memory structure including a three-dimensional array of NOR memory strings in several embodiments. [Figure 2] Figure 2 is a schematic diagram showing a memory circuit incorporating a local word line selection transistor that can be constructed using the memory structure of Figure 1 in several embodiments. [Figure 3] Figure 3 is a perspective view of a three-dimensional memory device for implementing a portion of the memory circuit shown in Figure 2 in several embodiments. [Figure 4] Figure 4 is a top view showing a portion of the three-dimensional memory device of Figure 3 in several embodiments. Similar components in Figures 3 and 4 are given the same reference numerals. [Figure 5] Figure 5 is a perspective view of a three-dimensional memory device for implementing a portion of the memory circuit shown in Figure 2 in another embodiment. [Figure 6] Figure 6 is a cross-sectional view of a memory device of a NOR memory string incorporating word line selection transistors in several embodiments. [Figure 7A] Figure 7A shows a manufacturing process for a memory structure comprising a word line selection transistor integrally formed with a three-dimensional memory array of memory transistors in several embodiments. [Figure 7B] Figure 7B shows a manufacturing process for a memory structure comprising a word line selection transistor integrally formed with a three-dimensional memory array of memory transistors in several embodiments. [Figure 7C] Figure 7C shows a manufacturing process for a memory structure comprising a word line selection transistor integrally formed with a three-dimensional memory array of memory transistors in several embodiments. [Figure 7C1] Figure 7C1 shows a manufacturing process for a memory structure comprising a three-dimensional memory array of memory transistors and a word line selection transistor formed integrally with it, in several embodiments. [Figure 7C2]FIG. 7C2 shows a manufacturing process of a memory structure including a word line selection transistor integrally formed with a three-dimensional memory array of memory transistors in some embodiments. [Figure 7D] FIG. 7D shows a manufacturing process of a memory structure including a word line selection transistor integrally formed with a three-dimensional memory array of memory transistors in some embodiments. [Figure 7E] FIG. 7E shows a manufacturing process of a memory structure including a word line selection transistor integrally formed with a three-dimensional memory array of memory transistors in some embodiments. [Figure 7F] FIG. 7F shows a manufacturing process of a memory structure including a word line selection transistor integrally formed with a three-dimensional memory array of memory transistors in some embodiments. [Figure 7G] FIG. 7G shows a manufacturing process of a memory structure including a word line selection transistor integrally formed with a three-dimensional memory array of memory transistors in some embodiments. [Figure 7H] FIG. 7H shows a manufacturing process of a memory structure including a word line selection transistor integrally formed with a three-dimensional memory array of memory transistors in some embodiments. [Figure 7I] FIG. 7I shows a manufacturing process of a memory structure including a word line selection transistor integrally formed with a three-dimensional memory array of memory transistors in some embodiments. [Figure 7J] FIG. 7J shows a manufacturing process of a memory structure including a word line selection transistor integrally formed with a three-dimensional memory array of memory transistors in some embodiments. [Figure 7K] FIG. 7K shows a manufacturing process of a memory structure including a word line selection transistor integrally formed with a three-dimensional memory array of memory transistors in some embodiments. <000009Figure 7K1 shows a manufacturing process for a memory structure comprising a word line selection transistor integrally formed with a three-dimensional memory array of memory transistors in several embodiments. [Figure 7K2] Figure 7K2 shows a manufacturing process for a memory structure comprising a three-dimensional memory array of memory transistors and a word line selection transistor formed integrally with it, in several embodiments. [Figure 7L] Figure 7L shows a manufacturing process for a memory structure comprising a word line selection transistor integrally formed with a three-dimensional memory array of memory transistors in several embodiments. [Figure 7M] Figure 7M shows a manufacturing process for a memory structure comprising a word line selection transistor integrally formed with a three-dimensional memory array of memory transistors in several embodiments. [Figure 7N] Figure 7N shows a manufacturing process for a memory structure comprising a word line selection transistor integrally formed with a three-dimensional memory array of memory transistors in several embodiments. [Figure 7O] Figure 7O shows a manufacturing process for a memory structure comprising a word line selection transistor integrally formed with a three-dimensional memory array of memory transistors in several embodiments. [Figure 8A] Figure 8A shows an alternative process for performing selective gate isolation in another embodiment. [Figure 8B] Figure 8B shows an alternative process for performing selective gate isolation in another embodiment. [Figure 8C] Figure 8C shows an alternative process for performing selective gate isolation in another embodiment. [Figure 8D] Figure 8D shows an alternative process for performing selective gate isolation in another embodiment. [Figure 8E] Figure 8E shows an alternative process for performing selective gate isolation in another embodiment. [Figure 8F]Figure 8F shows an alternative process for performing selective gate isolation in another embodiment. [Modes for carrying out the invention]

[0013] In embodiments of the present disclosure, the memory circuit comprises an array of thin-film ferroelectric memory transistors formed by an array of NOR memory strings intersecting local word line structures, and a global word line. The global word line is arranged orthogonally to the array of NOR memory strings and aligned with a set of local word line structures provided across multiple stacks of NOR memory strings. The memory circuit of the present disclosure comprises a word line selection transistor associated with each local word line structure to isolate each local word line structure from its associated global word line. When operating, the word line selection transistor selectively connects the selected local word line structure to its associated global word line. The remaining local word line structures associated with the same global word line remain unconnected and therefore unselected. By connecting only a subset of local word lines to the asserted global word line, parasitic capacitance on the global word line is reduced, and unintended disturbance to other unselected memory transistors is also reduced. Furthermore, the reduction in parasitic capacitance on the global word line shortens the charging time of the global word line, thereby reducing the latency of the memory device.

[0014] In some embodiments, the word line selection device is a vertical thin-film transistor formed on an array of memory stacks, and is referred to herein as the “word line selection transistor”. Furthermore, in some embodiments, the word line selection transistor is a non-memory type transistor and has a gate electrode formed using a conductive layer used to form the common bit line of the NOR memory string.

[0015] In some embodiments of this disclosure, the ferroelectric memory transistor is a thin-film ferroelectric field-effect transistor (FeFET) having a ferroelectric polarization layer as the gate dielectric layer. The ferroelectric polarization layer, also referred to as the "ferroelectric gate dielectric layer," is formed adjacent to a semiconductor oxide layer as the channel region. The ferroelectric memory transistor includes a source region and a drain region. Both the source and drain regions are formed from a metallic conductive material and are in electrical contact with the semiconductor oxide channel region. The ferroelectric memory transistor thus formed is a junction-less transistor that does not have a p / n junction in the channel, and the threshold voltage changes due to the polarization of the ferroelectric, thereby regulating the mobile carriers in the oxide semiconductor channel layer. In the memory structure of this disclosure, the ferroelectric memory transistors in each NOR memory string are controlled by individual control gate electrodes formed in the local word line structure, thereby enabling individual addressing and access of each memory transistor. In some embodiments, the ferroelectric polarization layer is formed from a doped hafnium oxide material, and the semiconductor oxide channel region is formed from an amorphous metal oxide semiconductor material.

[0016] In this specification, the term “storage transistor” is used interchangeably with the term “memory transistor” to refer to the transistor device formed in the memory structure described herein. In some embodiments, the memory structure of this disclosure, which includes a NOR memory string of randomly accessible memory transistors (or storage transistors), can have applications in a computer system as main memory where the storage location is directly accessible by the computer system's processor, for example, in the role previously played by conventional random access memory (RAM), such as dynamic RAM (DRAMS) and static RAM (SRAM). For example, the memory structure of this disclosure can be applied to a computer system to function as random access memory to support the operation of a microprocessor, a graphical processor, and an artificial intelligence processor. In other embodiments, the memory structure of this disclosure can also be applied to form a storage system, such as a solid-state drive, or an alternative storage system to a hard drive, to provide long-term data storage to a computer system.

[0017] As used herein, the term “semiconductor oxide layer” (also referred to as “oxide semiconductor layer” or “metal oxide semiconductor layer”) refers to a thin-film semiconductor material made from a conductive metal oxide such as zinc oxide or indium oxide, or any suitable conductive metal oxide having a charge carrier with electron mobility that can be modified or regulated by appropriate preparation or inclusion of appropriate impurities.

[0018] In embodiments of the present disclosure, the memory device comprises a memory stack (also referred to as a "stack"), each memory stack including a plurality of NOR memory strings formed by stacking them vertically on each other. In some embodiments, each NOR memory string is formed by a group of thin films continuously deposited on a plane of a semiconductor substrate, each group of thin films referred to herein as an "active layer." The active layers of each NOR memory string are stacked on each other, and each active layer is separated from other active layers by an interlayer insulating layer. Each active layer includes a common drain line and a common source line, which are vertically spaced apart from each other by a channel spacer dielectric layer. Both the common source line and the common drain line extend horizontally.

[0019] The memory transistors within each NOR memory string share a common source line and a common drain line. In some embodiments, the channel layer, gate dielectric layer, and gate conductor layer of the memory transistor are formed perpendicular to the common source line and common drain line of each NOR memory string. In this way, the memory transistors are formed in multiple parallel planes of each stack. The memory transistors are formed at the locations where the gate conductor layer intersects with the common source line and common drain line of the memory string. The gate conductor layer is also referred to herein as the local word line (LWL). As stated above, the term “perpendicular” refers to a direction perpendicular to the surface of the semiconductor substrate, and the term “horizontal” refers to any direction parallel to the surface of the semiconductor substrate. Furthermore, as used herein, “local word line structure” refers to a columnar structure on which the channel layer, gate dielectric layer, and gate conductor layer are formed, as will be discussed in detail later. The memory transistors are formed at each location where the local word line structure intersects with the common source line and common drain line of the memory string. In some embodiments, the local word lines are formed within the operational trenches between the memory stacks. The operating trench is also referred to herein as the “local word line trench” or “LWL trench.” The gate conductor layer is also referred to herein as the local word line (LWL), and the operating trench is also referred to herein as the “LWL trench.” That is, the operating trench or local word line trench (LWL trench) is a trench on which the gate conductor layer of the local word line is formed and on which a memory transistor is fabricated.

[0020] In this embodiment, the memory transistors in the NOR memory string are ferroelectric field-effect transistors that include a ferroelectric thin film (also referred to as a ferroelectric polarization layer, ferroelectric gate dielectric layer, or ferroelectric layer) as the gate dielectric layer. In a ferroelectric field-effect transistor (FeFET), the polarization direction of the ferroelectric gate dielectric layer is controlled by an electric field applied between the transistor's drain terminal and its gate electrode, and the threshold voltage of the FeFET changes with the change in polarization direction. In some embodiments, the electric field is applied to both the drain and source terminals of the transistor, relative to the transistor's gate electrode. For example, an FeFET can be programmed to have one of two threshold voltages, and each threshold voltage of the FeFET can be used to encode a given logic state. For example, the two threshold voltages of an FeFET can be used to encode a "programmed" state and an "erased" state, each representing a specified logic value. In one embodiment, the programmed state is associated with a lower threshold voltage, and the erased state is associated with a higher threshold voltage. In some embodiments, three or more threshold voltages may be set to represent three or more memory states in each FeFET.

[0021] In this description, for the sake of facilitating reference to the drawings, a Cartesian coordinate system is used, as shown in the figures, in which the Z direction is perpendicular to the plane of the semiconductor surface, and the X and Y directions are perpendicular to the Z direction. Furthermore, the drawings provided herein are idealized depictions for illustrating embodiments of the present disclosure and are not intended to be actual depictions of any particular component, structure, or apparatus. The drawings are not drawn to a constant scale, and some layer thicknesses and dimensions may be exaggerated for clarity. Deformations from the illustrated shapes are also expected. For example, areas depicted as box shapes may generally have rough and / or nonlinear features. Illustrated acute angles may be rounded. Similar reference numerals refer to similar components throughout.

[0022] Figures 1 and 1A are perspective views of a memory structure including a three-dimensional array of NOR memory strings in several embodiments. The memory structure can be used to realize part of a semiconductor memory device in some examples. In some embodiments, the semiconductor memory device is configured using a three-dimensional array of NOR memory strings of ferroelectric memory transistors formed on a semiconductor substrate, as described in Patent Document 2. Referring to Figure 1, the memory structure 10 includes a number of active layers 16 formed on the plane of a semiconductor substrate 12. An insulating layer 14 is provided between the semiconductor substrate 12 and the active layers 16 formed thereon. The active layers 16 are stacked in the Z direction (i.e., along the direction perpendicular to the plane of the substrate 12). Each active layer 16 is separated from each other by an interlayer insulating layer 15. The active layers 16 are divided into narrow strips ("active strips") in the X direction, which are stacked together to form a stack 17 ("active stack") of active strips extending in the Y direction. The active stack 17 is also referred to herein as a memory stack.

[0023] In this embodiment, each active stack 17 of the memory structure 10 is separated from each other by narrow trenches including an operating trench 18 (also referred to as an "LWL trench") and an auxiliary trench 19. Specifically, each active stack 17 is separated from each other by alternatingly arranged operating trenches 18 and auxiliary trenches 19. In this specification, the operating trench 18 is a narrow trench provided between adjacent active stacks 17. Memory transistors are formed by providing local word line structures within the operating trench 18. The auxiliary trench 19 is a narrow trench provided between active stacks 17 where memory transistors are not formed.

[0024] Each active layer 16 includes first and second low-resistance conductive layers (e.g., tungsten (W) lined with titanium nitride (TiN)) separated from each other by a channel spacer dielectric layer (e.g., silicon oxide). In an intermediate processing step, the active layers may include a sacrificial layer (e.g., silicon nitride) which will later be replaced by a conductive layer. In a subsequent processing step, the channel layer, gate dielectric layer, and gate conductor layer are formed in an operating trench 18 between adjacent active stacks. The gate conductor layer and gate dielectric layer, and optionally the channel layer, are formed as columnar structures extending in the Z direction. In this specification, the gate conductor layer is also referred to as a “local word line”. In this specification, the combination of the channel layer, gate dielectric layer, and gate conductor layer is collectively referred to as a “local word line (LWL) structure 13”. The first and second conductive layers of each active strip form the drain region ("common drain line" or “common bit line") and source region ("common source line") of the memory transistor, respectively. In this embodiment, the memory transistors are formed along the vertical side surfaces (sidewalls) of the active stack 17 facing the operating trench 18. Specifically, the memory transistors 20 are formed at the intersection of the active strip and the local word line structure 13. The local word line structures 13 within each operating trench 18 are separated from each other in the Y direction by dielectric-filled shafts.

[0025] Figure 1A shows a detailed structure of a memory transistor 20 formed on the memory structure 10 shown in Figure 1 in several embodiments. Specifically, Figure 1A shows a pair of memory transistors 20-1 and 20-2 fabricated on two adjacent faces of an active stack 17, also referred to as a memory stack. Referring to Figure 1A, the memory transistor 20 includes a first conductive layer 22 forming a drain region (common drain line or common bit line) and a second conductive layer 24 forming a source region (common source line), the first conductive layer 22 and the second conductive layer 24 being separated from each other by a channel spacer dielectric layer 23. The memory transistor 20 further includes a channel layer 26, a gate dielectric layer 27, and a gate conductor layer 28 formed on the sidewall (vertical side) of the memory stack. The channel layer 26 is formed perpendicularly along the sidewall of the memory stack and is in contact with both the first conductive layer 22 and the second conductive layer 24. The memory transistor 20 is insulated from adjacent memory transistors in the memory stack by an interlayer insulating layer 15. In this configuration, memory transistors sharing a common source line and a common bit line form a NOR memory string (also referred to herein as a "horizontal NOR memory string" or "HNOR memory string") along each active strip (in the Y direction).

[0026] In embodiments of this disclosure, the memory transistors within the memory structure 10 are junction-less ferroelectric memory transistors. Therefore, each memory transistor 20 includes only conductive layers as source and drain regions, and does not include semiconductor layers. The first and second conductive layers are formed using a low-resistivity metallic conductive material. In some embodiments, the first and second conductive layers are metallic layers such as a titanium nitride (TiN)-lined tungsten (W) layer, a titanium nitride (TiN)-lined molybdenum (Mo) layer, a tungsten (W) layer lined with tungsten nitride (WN), a molybdenum (Mo) layer lined with molybdenum nitride (MoN), a linerless tungsten layer, a linerless molybdenum layer, a linerless cobalt layer, or other metallic layers. The channel spacer dielectric layer 23 between the first and second conductive layers may be a low-dielectric dielectric layer such as silicon oxide (SiO2). The channel layer 26 is a semiconductor oxide layer. In some embodiments, the channel layer 26 is formed using amorphous oxide semiconductor material such as indium gallium zinc oxide (InGaZnO or IGZO), indium zinc oxide (IZO), indium tungsten oxide (IWO), or indium tin oxide (ITO), or other such semiconductor oxide material. The semiconductor oxide channel region has the advantage of high electron mobility, and therefore has high switching performance and no concern about electron or hole tunneling. For example, the IGZO film has a thickness of 10.0 to 100.0 cm, depending on the relative composition of indium, gallium, zinc, and oxygen. 2 It has an electron mobility of / V.

[0027] To form a ferroelectric memory transistor, the memory transistor 20 includes a ferroelectric gate dielectric layer or ferroelectric polarization layer 27 in contact with the channel layer 26. The ferroelectric polarization layer 27 functions as a storage layer of the memory transistor. The ferroelectric polarization layer can be deposited using atomic layer deposition (ALD) technology and may have a thickness of 1 nm to 14 nm. In some embodiments, an interface layer 25 may be provided between the channel layer 26 (semiconductor oxide layer) and the ferroelectric polarization layer 27. The interface layer 25 is a thin layer and may have a thickness of 0.5 nm to 2 nm. In some embodiments, the interface layer is formed using a material having a high dielectric constant (K) (also referred to as a "high-K" material). In some embodiments, the interface layer 25 may be a silicon nitride (Si3N4) layer, a silicon oxynitride layer, or an aluminum oxide (Al2O3) layer. In one embodiment, if an interface layer is present and the ferroelectric polarization layer 27 has a thickness of 4 to 5 nm, the interface layer may have a thickness of 1.5 nm. The inclusion of the interface layer 25 in Figure 1A is illustrative and not intended to limit the scope. The interface layer 25 is optional and may be omitted in other embodiments of this disclosure. In other embodiments, if the interface layer 25 is provided, it may be formed as a multilayer of different dielectric materials. In this specification, a high dielectric constant material or high K material refers to a material having a dielectric constant higher than that of silicon dioxide (SiO2).

[0028] In some embodiments, the ferroelectric polarization layer 27 is formed from a doped hafnium oxide material such as zirconium-doped hafnium oxide (HfZrO or "HZO"). In other embodiments, the hafnium oxide may be doped with silicon (Si), iridium (Ir), or lanthanum (La). In some embodiments, the ferroelectric polarization layer 27 is a material selected from zirconium-doped hafnium oxide (HZO), silicon-doped hafnium oxide (HSO), aluminum zirconium-doped hafnium oxide (HfZrAlO), aluminum-doped hafnium oxide (HfO2:Al), lanthanum-doped hafnium oxide (HfO2:La), hafnium-zirconium oxynitride (HfZrON), hafnium-zirconium aluminum oxide (HfZrAlO), and any hafnium oxide containing zirconium impurities.

[0029] The ferroelectric polarization layer 27 has one side in contact with the channel layer 26 and the other side in contact with the gate conductor layer 28. In some embodiments, the gate conductor layer 28 includes a conductive liner 28a as an adhesive layer and a low-resistance conductor 28b. In some embodiments, the conductive liner 28a is a titanium nitride (TiN) layer, a tungsten nitride (WN) layer, or a molybdenum nitride (MoN) layer, and the low-resistance conductor 28b is formed using tungsten, molybdenum, or other metals. In some embodiments, the conductive liner 28a is not required, and the gate conductor layer 28 includes only a linerless low-resistance conductor 28b, such as a tungsten or molybdenum layer. In another example, the gate conductor layer 28 can be formed using only titanium nitride (TiN) as the low-resistance conductor 28b. In other embodiments, the low-resistance conductor 28b may be a highly doped n-type or p-type polysilicon and can be used with or without a conductive liner. The gate conductor layer 28, which includes a conductive liner 28a (if present) and a low-resistance conductor 28b, forms the control gate electrode of the memory transistor and functions as a local word line within the memory structure 10.

[0030] The channel layer 26 (semiconductor oxide layer) configured in this way forms an N-type unipolar channel region in which the first conductive layer 22 and the second conductive layer 24, which form the drain and source terminals, are in direct contact with the channel region. The ferroelectric memory transistor formed in this way is normally in an ON state (i.e., a conducting state) and is a depletion-mode device that can be turned OFF (i.e., a non-conducting state) by depleting the N-type carriers in the channel region. The threshold voltage of the ferroelectric memory transistor is a function of the thickness (X direction) of the channel layer 26 (semiconductor oxide layer). That is, the threshold voltage of the ferroelectric memory transistor is the voltage required to deplete the carriers within the thickness of the semiconductor oxide channel region and shut off the ferroelectric memory transistor.

[0031] Each memory transistor 20 is insulated from adjacent memory transistors along the active stack (in the Z direction) by an interlayer insulating layer 15. In this embodiment, the interlayer insulating layer 15 is a dielectric layer such as silicon dioxide (SiO2) or another dielectric material having a similar dielectric constant. In some cases, the interlayer insulating layer 15 may include an optional void liner 15b to cover or passivate the exposed surface of the active strip, with the remaining space filled with a dielectric layer 15a. In some embodiments, the void liner 15b is a silicon nitride layer or an aluminum oxide (Al2O3) layer. The thickness of the void liner 15b may be 1 nm to 3 nm. In Figure 1A, each component may be exaggerated for illustrative purposes only. Please understand that the depictions in this and other figures are not necessarily to scale. In embodiments of the present disclosure, the interlayer insulating layer 15 is also used to provide physical isolation between the channel layer 26 of a memory transistor in the same memory stack and the channel layer of a memory transistor above or below it, thereby providing isolation between each memory transistor in the memory stack.

[0032] In other embodiments of the present disclosure, the interlayer insulating layer 15 is provided as a gap insulator formed by a gap cavity and an optional gap liner. For example, the interlayer insulating layer 15 includes a gap liner 15b, and the remaining cavity forms a gap insulator cavity 15a. The gap liner 15b is a dielectric layer used to cover or passivate the exposed surface of the gap insulator cavity 15a. The gap insulator cavity 15a thus formed functions as the interlayer insulating layer 15, providing effective insulation between adjacent memory transistors 20 along the memory stack.

[0033] Returning to Figure 1, in the illustrated exemplary embodiment, the memory structure 10 includes a dielectric layer 44 that fills an auxiliary trench 19 located outside the interlayer insulating layer 15. In some embodiments, the dielectric layer 44 is a dielectric layer such as silicon oxide (SiO2). In other embodiments, the auxiliary trench 19 is capped by a dielectric capping layer, and the remaining cavity is used to form a void cavity.

[0034] In embodiments of this disclosure, a three-dimensional array of NOR memory strings of ferroelectric memory transistors can be applied to realize a non-volatile memory device or a quasi-volatile memory device. For example, a quasi-volatile memory has an average retention time of 100 milliseconds or more, e.g., about 10 minutes, or several hours, while a non-volatile memory device has a minimum data retention time of more than 5 years. The ferroelectric memory transistor 20 as a quasi-volatile memory requires occasional refresh to restore the intended programmed polarization state and erased polarization state. For example, the ferroelectric memory transistor 20 in the memory structure 10 is refreshed every few minutes or hours. In particular, the ferroelectric memory transistors of this disclosure can be used to fabricate quasi-volatile memory devices with refresh intervals on the order of several hours, which are significantly longer than the refresh intervals of DRAMs, which require very frequent refreshes such as tens of milliseconds.

[0035] It should be noted that the memory structures of this disclosure are provided to illustrate an exemplary memory structure comprising a three-dimensional array of NOR memory strings of ferroelectric memory transistors. The memory structure 10 shown in Figures 1 and 1A is illustrative and not intended to be limiting. Those skilled in the art will understand that the word line selection device of this disclosure can also be applied to other memory structures comprising a three-dimensional array of NOR memory strings of ferroelectric memory transistors.

[0036] Referring again to Figure 1, in order to complete the memory circuit, various types of circuits to support the operation of the HNOR memory string are formed inside or on the surface of the semiconductor substrate 12. Such circuits are referred to as “under-array circuits” (“CuA”) and include digital and analog circuits such as decoders, drivers, sense amplifiers, sequencers, state machines, exclusive OR circuits, memory caches, multiplexers, voltage level shifters, voltage sources, latches and registers, and connectors, which perform iterative local operations such as processing random addresses, activation, erase, program, read, and refresh commands with the memory array formed on the semiconductor substrate 12. In some embodiments, the transistors within the CuA are constructed using control circuit-optimized processes, such as advanced fabrication processes optimized for forming low-voltage, high-speed logic circuits. In some embodiments, the CuA is constructed using fin-type field-effect transistors (FinFETs) or gate-all-around field-effect transistors (GAAFETs) to achieve compactness of the circuit layer and improved transistor performance.

[0037] In some embodiments, CuA provides a data path to and from the memory array, and further provides a data path to a memory controller which may be built on the same semiconductor substrate as CuA. Alternatively, the memory controller may reside on a separate semiconductor substrate, in which case CuA and its associated data paths are electrically connected to the memory controller using various bonding techniques. In some embodiments, the memory controller includes a control circuit for accessing and operating memory transistors in the memory array to which it is connected, performing other memory control functions such as data routing and error correction, and providing an interface function with a system that interacts with the memory array.

[0038] The memory structure 10 in Figure 1 shows the structure of a three-dimensional array of NOR memory strings in several embodiments. In some embodiments, the memory structure 10 is fabricated in a process that realizes advantageous features of the memory structure. First, the memory structure 10 is formed such that the memory transistors in the three-dimensional array of NOR memory strings are individually isolated from other memory transistors. Specifically, each memory transistor is isolated from each other vertically by an interlayer insulating layer, as shown in Figure 1, and also horizontally by insulating the channel layer from each local word line structure 13. Individually isolating the memory transistors can improve the performance characteristics of the memory transistors. Second, channel isolation between active layers in the memory stack can be achieved by conformally depositing the channel layer and then etching the back surface of the channel through access openings formed by the sacrificial layer. As a result, a simplified and more reliable process for forming the channel layer is provided. Third, after removing the interlayer sacrificial layer for channel isolation, the cavity remaining between the active layers can form void insulation between the active layers, thereby achieving better insulation than most dielectric materials.

[0039] In embodiments of this disclosure, the memory structure includes a memory array portion constructed as described above to form a three-dimensional array of NOR memory strings. To complete the memory device, the memory structure includes stepped portions provided at the ends (in the Y direction) of the memory strings. Thin-film memory transistors of the NOR memory strings are formed within the memory array portion, and the stepped portions provided on both sides of the memory array portion include stepped structures that provide connections via conductive vias to a common bit line and optionally a common source line of the NOR memory strings. In some embodiments, the common source line is pre-charged to function as a virtual voltage reference source during programming, reading, and erasing operations, thereby eliminating the need for continuous electrical connections to support circuits during such operations. Herein, the common source line is described as electrically floating, meaning there is no continuous electrical connection to the common source line. In embodiments of this disclosure, various processing steps can be used to form the stepped structures within the memory structure. The processing steps for forming the stepped structures can be performed before, after, or between the processing steps for forming the memory array portion.

[0040] The memory structure 10 in Figure 1 shows the structure of a memory array including a three-dimensional array of NOR memory strings. The memory structure 10 can be used as a building block for fabricating high-capacity and high-density memory devices. In embodiments of this disclosure, the memory structure 10 represents modular memory units referred to as “tiles,” and the memory device is formed using an array of modular memory units. In exemplary embodiments, the memory device is configured as a two-dimensional array of tiles arranged along the X and Y directions, and each tile includes a three-dimensional array of ferroelectric memory transistors having support circuits formed beneath each tile. More specifically, the memory device includes multiple memory arrays of thin-film ferroelectric memory transistors configured as a two-dimensional array of “tiles” (i.e., the tiles are arranged in a matrix) formed on a planar semiconductor substrate. Each tile may be configured to be addressed individually and independently, or it may form larger memory segments (e.g., rows of tiles or two-dimensional blocks of tiles) and be configured to be addressed on a per-memory segment basis.

[0041] This configuration enables the memory device of the present disclosure to implement a tile-based architecture including an array or arrangement of tiles of memory transistors that can operate independently and simultaneously, each tile including memory transistors arranged in a three-dimensional array and a local modular control circuit that operates the memory transistors within the tile. The tile-based architecture of the present disclosure enables simultaneous memory access across multiple tiles within the memory device, thereby enabling independent and simultaneous memory operations across multiple tiles. Tile-based simultaneous access to the memory device has the advantage of increasing memory bandwidth and reducing the tail latency of the memory device by ensuring high availability of memory transistors.

[0042] In embodiments of the present disclosure, the memory device of the present disclosure is configured to include a word line selection transistor that connects local word lines (i.e., gate conductor layers within the local word line structure) to a global word line. The word line selection transistor is used to select or activate only the relevant local word line from among all local word lines connected to the global word line. This reduces parasitic capacitance on the global word line and, as a result, improves the latency of the memory device.

[0043] Figure 2 is a schematic diagram showing a memory circuit incorporating local word line selection transistors that can be constructed using the memory structure of Figure 1 in several embodiments. Figure 3 is a perspective view of a three-dimensional memory device for implementing some of the memory circuits of Figure 2 in several embodiments. Similar components in Figures 2 and 3 are given the same reference numerals. First, referring to Figure 2, the memory circuit 30 includes an array of active stacks 32 (active stacks 32-0 to 32n) that form an array of NOR memory strings 38 across a plurality of active stacks. In each active stack 32, the NOR memory strings 38 of ferroelectric memory transistors 34 are formed in multiple layers (layers 0 to p). That is, in each active stack 32, the NOR memory strings 38-0 to 38p are formed stacked on top of each other. Each NOR memory string 38 includes m+1 ferroelectric memory transistors 34 connected in parallel between bit lines BLx,y and source lines SLx,y. The gate terminals of the ferroelectric memory transistors 34 are connected to each local word line LWL0 to LWLm.

[0044] More specifically, in each active stack 32, the gate terminals of the memory transistors 34 in the vertically aligned NOR memory strings 38 across multiple layers 0 to p are connected to the same local word line LWLx (i.e., one of LWL0 to LWLm). The local word lines LWLx across the entire array of the active stack 32 are connected to the same global word line GWLx (i.e., one of GWL0 to GWLm). In this memory circuit 30, n+1 NOR memory strings 38 in each layer constitute k memory pages. Therefore, each memory page has (n+1) / k memory transistors or (n+1) / k bits. Each memory access operation is performed on a memory page basis, and therefore each memory access operation is performed on the selected memory transistor associated with a given memory page.

[0045] Figure 3 shows an exemplary memory device 40 that can be used to implement a portion of the memory circuit 30 (Figure 2). Referring to Figure 3, the memory device 40 includes memory transistors formed on a substrate 41. The substrate 41 may include logic circuits (also referred to as array sub-circuits) for operating the memory transistors, as described above. In the configuration shown in Figure 3, the memory device 40 includes active stacks 32-0 and 32-1 formed adjacent to a first set of local word line structures 43. The memory device 40 further includes active stacks 32-2 and 32-3 formed adjacent to a second set of local word line structures 43. Each active stack 32 includes an array of NOR memory strings 38, i.e., memory strings 38-0 to 38-p, formed stacked on top of each other in a p+1 layer. A conductive layer 46 within each NOR memory string forms a common drain layer or common bit line of the memory string. Each local word line structure 43 includes a local word line LWLx, which is the gate conductor layer of a memory transistor vertically aligned within the memory string 38 formed in a p+1 layer. Figure 3 shows local word lines LWL0 and LWL1. The global word line is formed on the upper side of the memory stack and extends in a direction that crosses the memory string. Local word lines LWLx aligned in the Y direction are connected to their corresponding identical global word lines GWLx. For example, local word lines LWL0 of the first and second sets of local word line structures 43 are connected to global word line GWL0, and local word lines LWL1 of the first and second sets of local word line structures 43 are connected to global word line GWL1.

[0046] Referring to Figure 2, during operation, a given global word line GWLx is activated, and a section of memory transistor 34 connected to local word lines LWLx across p+1 memory strings 38 and n+1 active stacks (also referred to as a "slice of memory transistors") is selected. For example, activating the global word line GWL1 selects a slice of memory transistor 34 connected to local word lines LWL1 across memory strings 38-0 to 38-p and memory stacks 32-0 to 32-n. Specifically, bit lines BLx,y associated with the selected memory pages within the slice of memory transistor 34 are activated to perform memory operations.

[0047] In embodiments of this disclosure, the memory circuit 30 includes word line selection transistors 36 provided at each local word line LWLx, which connect each local word line LWLx to each global word line GWLx. For example, word line selection transistors 36-0,m connect local word line LWLm in the active stack 32-0 to global word line GWLm. In another example, word line selection transistors 36-n,0 connect local word line LWL0 in the active stack 32n to global word line GWL0. In this way, each global word line GWLx is selectively connected to its associated local word line LWLx in the slice of the memory transistor. Specifically, the word line selection transistors 36 are controlled by their respective selection gate signals SGx (SG0 to SGn, etc.) to selectively connect a subset of local word lines in the slice of the memory transistor to its associated global word line. In other words, when a subset of word line selection transistors 36 is selected and turned on by their respective selection gate signals SGx, it connects the local word line LWLx associated with the selected memory page to the activated global word line GWLx. The other unselected word line selection transistors 36 remain off, and each local word line remains unconnected to its associated global word line. Consequently, the parasitic capacitance formed on each activated global word line is significantly reduced, thereby reducing the latency of the memory circuit.

[0048] In other words, if the memory circuit does not have a word line selection transistor, each time a global word line is activated, the global word line must drive all local word lines connected to it (i.e., LWL0 to LWLn). The local word lines associated with the selected memory page are only a portion of the local word lines (LWL0 to LWLn), and the local word lines associated with the unselected memory page form parasitic capacitance to the global word line. Furthermore, activating the local word lines of the unselected memory page may cause disturbance of the data values ​​stored in the unselected memory transistor. According to embodiments of this disclosure, the memory circuit 30 includes a word line selection transistor for selectively connecting the global word line to each local word line. Therefore, during each memory access operation, only the local word lines of the selected memory page are connected to the activated global word line. Since the local word lines associated with the unselected memory page are not connected to the global word line, they do not form parasitic capacitance to the global word line. Furthermore, since the gate terminals of the unselected memory transistors are not activated, disturbance of the unselected memory transistors is avoided. In this scheme, disturbance occurs only to unselected memory transistors in unselected memory pages associated with activated local word lines, but such cases are limited.

[0049] In one example, the memory circuit has 2048 memory stacks or bit lines (n+1=2048) and 16 layers or memory strings (p+1=16) within each memory stack. Each bit line is divided into 4 memory pages (k=4). Thus, each page has 512 bit lines. Each NOR memory string has 4096 memory transistors. Thus, each NOR memory string has 4096 global word lines (m+1=4096). In this embodiment, the memory device includes one local word line structure shared by two adjacent memory stacks. Thus, each global word line is selectively connected to 1024 local word lines. When each global word line is activated, one of the 4 memory pages is selected, and the word line selection transistor connects the local word line of the selected memory page to the activated global word line. In this way, during each memory access operation, the activated global word line is connected to only 512 local word lines and accesses 512 memory transistors. The remaining 512 local word lines are not connected to the activated global word lines. This configuration halves the parasitic capacitance that forms on the global word lines.

[0050] In embodiments of this disclosure, the word line selection transistor 36 is a vertical thin-film transistor. In these embodiments, the word line selection transistor 36 is used to transfer the word line voltage. Since ferroelectric memory transistors can operate at low voltages, the word line selection transistor 36 does not require a large drive capability to transfer the word line voltage. For example, the word line voltage of a ferroelectric memory transistor may be 3V. In this case, the word line selection transistor only needs to be a 4V transistor to transfer the 3V word line voltage. In another example, the word line voltage is 2V and the bit line is biased to -1V. In this case, the word line selection transistor only needs to be a 3V transistor to transfer the 3V word line voltage.

[0051] Continuing with reference to Figures 2 and 3, in some embodiments, each word line selection transistor 36 has a source terminal connected to its respective local word line LWLx (i.e., the gate conductor layer of each local word line structure) and a drain terminal connected to its respective global word line GWLx. For example, in the exemplary embodiment shown in Figure 3, the drain terminal of each word line selection transistor has a via 44 connected to a conductive wire 45 forming its respective global word line. Each word line selection transistor 36 has a gate terminal formed by a gate conductor layer 37. In this embodiment, the gate conductor layer 37 extends in the same direction as the common drain layer (or bit line) 46 of the NOR memory string 38. In some embodiments, the gate conductor layer 37 is formed in the same manner as the conductor layer forming the common drain layer. In this embodiment, the gate dielectric layer 48 and channel layer 49 of the word line selection transistor 36 are formed on the upper side of the columnar local word line structure. The word line selection transistor 36 is formed at the intersection of the gate conductor layer 37 and gate dielectric layer 48 and the channel layer 49.

[0052] Figure 4 is a top view showing a portion of the three-dimensional memory device of Figure 3 in several embodiments. Similar components in Figures 3 and 4 are given the same reference numerals. Referring to Figure 4, the memory device 40 includes NOR memory strings formed as part of a memory stack spaced apart from each other in the X direction and extending in the Y direction. In Figure 4, bit line 46 is shown to represent one of the NOR memory strings of the memory stack. Specifically, the top bit line of the memory stack is shown in Figure 4.

[0053] In this embodiment, local word line structures (LWL structures) are formed in alternate trenches in trenches formed between adjacent memory stacks, and are spaced apart from each other in the Y direction within each trench. Memory transistors are formed at the intersections of each memory string in the memory stack and the local word line structures. In this embodiment, local word line structures for local word lines LWL0 to LWL4 are shown.

[0054] According to embodiments of this disclosure, the word line selection transistors are formed on the upper side of the memory stack and on a columnar local word line structure. In these embodiments, the gate conductor layer 37 of the word line selection transistors is formed using the same conductor layer as the bit lines or source lines of the NOR memory strings. Thus, as shown in Figure 4, the gate conductor layer 37 overlaps with the bit lines 46 of the memory stack. The gate conductor layer 37 transmits each selection gate signal SG0 to SGn to control each word line selection transistor, i.e., to control the on / off state of the word line selection transistors. The word line selection transistors are provided to connect local word lines to each global word line. The global word line GWL is formed in a conductive layer 45, such as a metal layer. The global word line GWL extends in the X direction and traverses the bit lines and gate conductor layer 37 of the word line selection transistors. With this configuration, each global word line GWL is connected to the same local word line in each trench in the Y direction. In other words, the global word line GWL0 is connected to the local word line LWL0, which spans the entire memory stack, and the global word line GWL4 is connected to the local word line LWL4, which spans the entire memory stack.

[0055] In the memory device 40, the n+1 bit lines in each layer are divided into k memory pages. In this embodiment, each layer of bit lines is divided into four memory pages. For this purpose, each memory access activates a bit line associated with one memory page. In the example shown in Figure 4, bit lines BL0 to BL3 are assigned to each of memory pages 0 to 3. Bit lines BL0 to BL3 can be the first data bits of each memory page and are selectively connected to the first sense amplifier SA0. Similarly, bit lines BL4 to BL7 are assigned to each of memory pages 0 to 3. Bit lines BL4 to BL7 can be the second data bits of each memory page and are selectively connected to the second sense amplifier SA1.

[0056] In the embodiments described above, the gate terminals of the word line selection transistors are provided on individual gate conductor layers 37. The word line selection transistors are formed at the intersection of the gate conductor layer 37 and the gate dielectric / channel layer structure. Therefore, the selection gate signal SGx activates the word line selection transistor associated with only one memory stack. In another embodiment, the selection gate signal SGx is configured to activate the word line selection transistors associated with a pair of adjacent memory stacks.

[0057] Figure 5 is a perspective view of a three-dimensional memory device for implementing a portion of the memory circuit of Figure 2 in another embodiment. Similar components in Figures 3 and 5 are given the same reference numerals. Referring to Figure 5, the memory device 40a comprises a word line selection transistor 36 associated with a pair of adjacent memory stacks and a shared gate conductor layer 37a. Each shared gate conductor layer 37a controls the word line selection transistor 36 formed on both sides of the gate dielectric / channel layer structure. The configuration with shared gate conductor layers 37a shown in Figure 5 achieves certain manufacturing simplifications without compromising the advantages of incorporating word line selection transistors. Specifically, because adjacent memory stacks share the same local word line, the word line selection transistors of adjacent memory stacks can be controlled by the same selection gate signal without changing the functionality of the memory operation. In practice, bit lines in adjacent memory stacks are typically assigned to different memory pages and are not selected in the same memory operation.

[0058] Figure 6 is a cross-sectional view of a memory device of a NOR memory string incorporating word line selection transistors in several embodiments. Referring to Figure 6, in some embodiments, the memory structure 50 comprises word line selection transistors formed on the upper side of a three-dimensional memory array 53. In embodiments of this disclosure, the three-dimensional memory array 53 includes a NOR memory string formed within an array of memory stacks. In some embodiments, the memory array 53 is manufactured using a memory structure disclosed in U.S. Patent Application No. 17 / 936,320 (Patent Document 2), filed September 28, 2022, concurrently pending and by the same applicant, entitled "Memory Structure Including a Three-Dimensional NOR Memory String of Junctionless Ferroelectric Memory Transistors and Method for Manufacturing the Same". The entire disclosure of Patent Document 3 is incorporated herein by reference. In another embodiment, the memory array 53 is manufactured using a memory structure disclosed in U.S. Patent Application No. 18 / 419,385 (Patent Document 4), filed on January 22, 2024, concurrently pending and by the same applicant, entitled “Method for Manufacturing a Three-Dimensional Memory Array of Thin-Film Ferroelectric Transistors Using a High Aspect Ratio Local Word Line Damascene Process.” The entire disclosure of Patent Document 4 is incorporated herein by reference. In some embodiments, the memory array 53 can be manufactured in a variety of ways, and the method of manufacturing the memory array 53 is not important to the implementation of this disclosure.

[0059] In this exemplary embodiment, the memory array 53 includes an array of memory stacks formed on a semiconductor substrate 52. Circuits may be formed on the semiconductor substrate 52, and such circuits are referred to as under-array circuits (CuA). An insulating layer 54 may be provided between the semiconductor substrate 52 and the memory array formed on the substrate. The insulating layer 54 also functions as an etching stop layer in the manufacturing process of forming the memory array. The memory array 53 includes alternately stacked active layers 51 and interlayer insulating layers 60. Each active layer 51 includes a first conductive layer 62 that forms a common drain layer or common bit line of the NOR memory string, and a second conductive layer 64 that forms a common source layer or common source line of the NOR memory string. The first conductive layer 62 is separated from the second conductive layer 64 by a channel spacer dielectric layer 63. The memory array 53 includes one or more dummy layers formed as the bottom or top layer of the memory stack. In this embodiment, the memory array 53 includes a conductive layer 61a as the bottom dummy layer. Furthermore, the dummy layer 61a functions as an anchor layer for the memory stack formed thereon. In this embodiment, the memory array 53 further includes a conductive layer 61b as the uppermost dummy layer. One or more insulating layers are provided on the memory array as an array insulating layer. In this embodiment, the array insulating layer includes an oxide layer 71 and a silicon oxycarbide (SiOC) layer 72.

[0060] The memory array 53 further includes trenches that separate the memory stacks from each other. Specifically, the memory array 53 includes local word line trenches LWT on which local word line structures are formed, and auxiliary trenches AXT on which active structures are not formed. The local word line structures are formed at equal intervals in the Y direction. The local word line structures form ferroelectric memory transistors at positions where they intersect with the active layers 51. In the local word line trenches LWT, each local word line structure includes a channel layer 66, a ferroelectric gate dielectric layer 67, and a gate conductor layer 68. In some examples, the gate conductor layer 68 has a conductive liner 68a (e.g., titanium nitride (TiN)) as an adhesive layer and a low-resistance conductor 68b. In some embodiments, an interface layer 65 is provided between the channel layer 66 and the ferroelectric gate dielectric layer 67. The channel layers 66 are separated from each active layer 51 by being separated from each other, for example in the Z direction. The ferroelectric memory transistors 34 are formed at each position where the active layer 51 and the local word line structure intersect.

[0061] In embodiments of this disclosure, word line selection transistors are formed on the upper side of the memory array 53. After the completion of the manufacturing process of the memory array 53, an additional manufacturing process is performed to form vertical thin-film transistors that function as word line selection transistors for local word lines within the local word line structure. Specifically, the word line selection transistors are formed on the upper side of the array insulating layers (oxide layer 71 and SiOC layer 72). In some embodiments, the word line selection transistors are formed using a multilayer structure 55 similar to the layers forming the memory array 53. In this embodiment, the word line selection transistors are formed within a multilayer structure 55 that includes an insulating layer 74, an insulating layer 76, and a conductive layer 75 sandwiched between the insulating layers 74 and 76. The conductive layer 75 forms a gate conductor layer that functions as the gate terminal of the word line selection transistor. In some embodiments, the conductive layer 75 is formed using the same material as the common drain layer 62 and the common source layer 64. For example, the conductive layer 75 may be a tungsten layer with a titanium nitride liner. The insulating layers 74 and 76 may be any dielectric layers, such as silicon dioxide layers (SiO2). The multilayer structure 55 further includes a capping dielectric layer 78. For example, the capping dielectric layer 78 can be a silicon oxycarbide (SiOC) layer.

[0062] The channel structure of the local word line selection transistor has the same periodicity as the local word line structure (formed in alignment with the local word line structure) so as to overlap the local word line structure of the memory array 53. Each channel structure includes a gate dielectric layer 92 adjacent to the multilayer structure 55 and a channel layer 93 adjacent to the gate dielectric layer. The remaining space of the channel structure is filled with a dielectric layer 94, such as a silicon oxide layer (SiO2). The channel layer 93 of each word line selection transistor is in electrical contact with the gate conductor layer 68 of the associated local word line structure. The gate conductor layer 68 of the local word line structure associated with each channel structure functions as the source terminal of the word line selection transistor. The multilayer structure 55 includes a top insulating layer 96 formed above the capping dielectric layer 78 and conductive via structures 98 formed on the top insulating layer 96. Conductive via structures 98 are provided for each channel structure of the local word line transistor. In some embodiments, the conductive via structures 98 are filled with a conductive material such as tungsten or copper. Each conductive via structure 98 is in electrical contact with the channel layer 93 of each word line selection transistor and functions as the drain terminal of the word line selection transistor. In this embodiment, the gate conductor layer 68 of the local word line structure is referred to as the source terminal of the word line selection transistor, and the conductive via structure 98 is referred to as the drain terminal of the word line selection transistor. The source and drain terminals of the field-effect transistor are interchangeable, and it should be understood that the references to source and drain terminals used herein are merely illustrative. In this configuration, the gate conductor layer 75 (conductive layer 75) of the multilayer structure 55 completely or partially surrounds the channel structure, and the word line selection transistor 36 is formed at the intersection of the gate conductor layer 75 and the channel structure.

[0063] A conductive layer 99, such as a metal layer, is formed on the upper side of the multilayer structure 55 and is in electrical contact with a conductive via structure 98. The conductive layer 99 traverses the memory structure 50 in the X direction and functions as a global word line of the memory structure 50. In some embodiments, the conductive layer 99 is a copper layer with or without a conductive liner layer. In such a configuration, each global word line 99 is in contact with a set of conductive via structures 98 aligned in the Y direction. The global word lines 99 can be connected to the gate conductor layer 68 of the local word line structures by selectively activating a word line selection transistor 36 in a given column of local word line structures in the Y direction.

[0064] In some embodiments, the gate dielectric layer 92 of the word line selection transistor is formed of a non-memory dielectric. In some examples, the gate dielectric layer 92 is hafnium oxide (HfO), aluminum oxide (Al), or silicon dioxide (SiO2). In another example, a low-temperature dielectric layer is used. In yet another example, the gate dielectric layer 92 is a dielectric material having a dielectric constant of 3.9 or less. In some embodiments, the channel layer 93 of the word line selection transistor is formed of the same material as the channel layer of the ferroelectric memory transistor. In some examples, the channel layer 93 is formed using an amorphous oxide semiconductor material such as indium gallium zinc oxide (InGaZnO or IGZO), indium zinc oxide (IZO), indium tungsten oxide (IWO), or indium tin oxide (ITO), or other such oxide semiconductor materials. A notable feature of the memory devices of this disclosure is that both the memory transistor and the word line selection transistor are junction-less thin-film transistors. The oxide semiconductor channel layer allows the source layer, drain layer, and conductive layer to be directly connected to the channel of the transistor. In this way, word line selection transistors can be formed as additional multilayer structures and incorporated into the memory array.

[0065] In embodiments of this disclosure, the gate conductor layer 75 may be formed to surround the channel structure in order to form the word line selection transistor shown in Figure 5. In other embodiments, as shown in Figure 3, the gate conductor layer 75 is isolated and configured to contact only a portion of the channel structure. The exact configuration of the gate conductor layer 75 is not important to the implementation of this disclosure, as the local word lines of the associated local word line structure serve as gate terminals to a pair of memory transistors in each layer formed by two adjacent active layers. In each global word line activation, once a set of word line selection transistors is selected, the global word line signals are connected to the selected local word lines, and the bit lines (common drain layer) of the selected memory page are selected to perform memory operations.

[0066] In some embodiments, the word line selection transistor is formed in the process of forming the precharge transistor in the manufacturing process of the memory device. In other embodiments, the word line selection transistor is formed in another step in the manufacturing process of the memory device. An exemplary manufacturing process for forming the word line selection transistor is described below.

[0067] Figures 7A to 7O (including Figures 7C1, 7C2, 7K1, and 7K2) illustrate the manufacturing process of a memory structure comprising a three-dimensional memory array of memory transistors and a word line selection transistor formed integrally with it, in several embodiments. Referring to Figure 7A, in embodiments of the present disclosure, the memory structure 50 comprises a word line selection transistor formed on a memory array. The memory array was manufactured using the method described with reference to Figure 6, although this will not be repeated in detail. Similar components in Figures 6, 7A, and subsequent figures are given the same reference numerals and will not be described further. Figure 7A includes two figures, Figure (i) and Figure (ii). Figure (i) is a horizontal cross-sectional view (i.e., an XY plan view) along the conductive layer indicated by line AA' in Figure (ii), and Figure (ii) is a vertical cross-sectional view (i.e., an XZ plan view) along the plane indicated by line AA' in Figure (i). Figure 7A shows a memory array 53 comprising a junctionless ferroelectric memory transistor, as described with reference to Figure 6. Specifically, Figure 7A shows the manufacturing process of the memory array 53, and Figure (i) of Figure 7A shows a top view of the memory array including the active layer 51 formed in the memory stack between the auxiliary trench 79 and the local word line trench LWT, where the local word line structures are formed spaced apart from each other in the Y direction and insulated from each other by dielectric-filled pillars 98. Referring to Figures 7B and later, the portion of the manufacturing process of the memory array 53 related to the formation process of the word line selection transistors will be described.

[0068] Referring to Figure 7B, a multilayer structure 55 is formed by sequentially depositing insulating layers and conductive layers on the upper side of the memory array 53, specifically on the upper side of the array insulating layer (oxide layer 71 and SiOC layer 72). In this embodiment, the multilayer structure 55 includes a first dielectric layer 74 deposited on the SiOC layer 72 of the array insulating layer, a conductive layer 75 deposited on the first dielectric layer 74, and a second dielectric layer 76 deposited on the conductive layer 75. Next, a capping dielectric layer 78 is formed on the multilayer structure 55. The conductive layer 75 becomes a gate conductor layer that forms the gate terminal of the word line selection transistor. In some embodiments, the first dielectric layer 74 and the second dielectric layer 76 are silicon dioxide layers (SiO2), the conductive layer 75 is a tungsten layer with a titanium nitride liner, and the capping dielectric layer 78 is a silicon oxycarbide (SiOC) layer. In some embodiments, the first dielectric layer 74 and the conductive layer 75 each have a thickness of 30 nm or less. The thickness of each layer constituting the multilayer structure 55 may be the same as or different from each other. In some embodiments, the capping dielectric layer 78 has a thickness of 40 nm or more.

[0069] Referring to Figure 7C, an opening 80 is formed in the multilayer structure 55 to form the channel structure of the word line selection transistor. In this embodiment, the opening 80 has the same periodicity as the local word line structure (is formed in alignment with the local word line structure) so as to overlap the local word line structure formed in the memory array 53. Figures 7C1 and 7C2 are top or horizontal cross-sectional views of the multilayer structure 55 and show two embodiments for forming the opening 80. The multilayer structure 55 is cut by a capping dielectric layer 78. In one embodiment, referring to Figure 7C1, a mask layer is applied to form the opening 80 so as to overlap the local word line structure (is formed in alignment with the local word line structure) so as to overlap the local word line structure. The multilayer structure 55 is etched using an anisotropic dry etching process or the like to form the opening 80 and expose the local word line structure formed in the memory array below it. In another embodiment, referring to Figure 7C2, the opening 80 may be formed in a two-step process. First, a first mask layer is applied to form a trench within the multilayer structure that overlaps the local word line structure. The multilayer structure 55 is etched using an anisotropic dry etching process or the like to form a trench within the multilayer structure. Next, a dielectric layer 81 is filled into the trench. Then, a second mask layer is applied to form an opening 80 in the dielectric layer 81, exposing the local word line structure formed in the memory array below it. Specifically, in both embodiments of Figure 7C1 and Figure 7C2, the gate conductor layer within each local word line structure is exposed so as to be in electrical contact with the channel layer of the word line selection transistor.

[0070] After forming the opening 80 in this manner, a gate dielectric layer 92 is deposited on the multilayer structure 55, as shown in Figure 7D. In this embodiment, the gate dielectric layer 92 is an aluminum oxide (Al2O3) layer. In this embodiment, the gate dielectric layer 92 is conformally deposited using a process such as atomic layer deposition (ALD). Therefore, the gate dielectric layer 92 is formed on all exposed surfaces of the memory structure 50. After conformally depositing the gate dielectric layer 92, the gate insulating layer 92 is anisotropically etched to remove the deposited material from the horizontal surface of the memory structure 50, as shown in Figure 7E. As a result, the gate dielectric layer 92 remains only on the side walls of the opening 80.

[0071] After the formation of the gate dielectric layer 92, the channel layer 93 is deposited. In some embodiments, the channel layer 93 is formed by a two-step deposition process. In an optional first deposition process, room-temperature physical vapor deposition (PVD) is used. For example, the IGZO layer is deposited at room temperature using the PVD method. Room-temperature deposition using the PVD method is preferable because it avoids oxidation of the exposed metal layer in the gate conductor layer of the local word line structure below it. Generally, deposition using the PVD method is non-conformal deposition, and is deposited only on the horizontal surface of the memory structure 50, and not on the vertical sidewalls of the opening 80. In this way, the IGZO layer is deposited on the exposed gate conductor layer 68 of the local word line structure using the PVD method, thereby facilitating contact between the gate conductor layer 68 and the metal layer. In the second deposition process, atomic layer deposition (ALD) technique is used to deposit the channel material. For example, as shown in Figure 7F, the IGZO layer is deposited conformally on the memory structure 50 using the ALD technique, thereby forming the channel layer 93.

[0072] Next, as shown in Figure 7G, a dielectric layer 94 is deposited on the surface of the memory structure 50, and the dielectric layer 94 fills the remaining space of the opening 80. For example, the dielectric layer 94 can be a silicon dioxide (SiO2) layer. After this deposition step, excess material is removed from the top of the memory structure 50, for example, using chemical mechanical polishing (CMP). The resulting memory structure 50 is shown in Figure 7H. Specifically, the polishing step is stopped at the channel layer 93, leaving the channel layer 93 connected to all the channel structures formed within the opening 80 on the memory structure 50.

[0073] As shown in Figure 7I, a channel layer separation process is performed to remove the channel layer material on the memory structure 50. In one embodiment, the channel layer 93 is an oxide semiconductor material such as IGZO, and the channel layer separation process is performed by a wet etching process.

[0074] Next, a selection gate isolation process is performed to separate the gate conductor layer 75 of the word line selection transistor into each memory stack. Referring to Figure 7J, trenches 84 extending in the Y direction are formed in the multilayer structure 55 in order to separate the multilayer structure 55 into each memory stack. In this embodiment, the trenches 84 are formed in alignment with the positions of each auxiliary trench 79. By forming them in this way, the gate conductor layer 75 is formed in a strip shape for each memory stack of the memory array. Next, as shown in Figure 7K, a dielectric layer 95 such as a silicon oxide layer (SiO2) is filled into the trenches 84. The word line selection transistor 36 is formed at the position where the gate conductor layer 75 of each memory stack intersects with the channel structure including the gate dielectric layer 92 and the channel layer 93.

[0075] Figures 7K1 and 7K2 are top or horizontal cross-sectional views of the multilayer structure 55, showing the structure obtained as a result of the selection gate isolation process in two embodiments shown in Figures 7C1 and 7C2, respectively. Specifically, Figures 7K1 and 7K2 show horizontal cross-sectional views of the word line selection transistor in the gate conductor layer 75. First, referring to Figure 7(K1), the channel structure of the word line selection transistor is formed aligned with the local word line structure in the memory array. Trenches filled with dielectric layers 95 isolate the multilayer structure into sections. In the embodiment shown in Figure 7K1, the gate conductor layer 75 is continuous across two memory stacks. That is, the gate conductor layer 75 surrounds the channel structure and is associated with two adjacent memory stacks located between two adjacent auxiliary trenches. In the embodiment shown in Figure 7K2, the gate conductor layer 75 is isolated by pre-formed trenches. Through a selective gate isolation process, the gate conductor layer 75 is further isolated in a strip-like manner by trenches filled with dielectric layers 95 that overlap each memory stack. That is, the gate conductor layer 75 is formed adjacent to channel structures that are spaced apart from each other by dielectric layers 81 (dielectric-filled pillars).

[0076] The manufacturing of the word line selection transistor proceeds with the formation of the drain terminal. As shown in Figure 7L, a top insulating layer 96 is deposited on the memory structure 50. For example, the top insulating layer 96 is a silicon dioxide layer (SiO2). Next, as shown in Figure 7M, an opening 82 is formed to expose the channel structure formed in the multilayer structure 55. Subsequently, as shown in Figure 7N, a conductive material is filled into the opening 82 to form a conductive via structure 98. In one example, the conductive material is copper. Finally, as shown in Figure 7O, a conductive layer 99 is deposited on the memory structure 50 and patterned to form the global word line. This forms the drain terminal of the word line selection transistor 36.

[0077] Figures 8A-8F show alternative processes for performing selective gate isolation in another embodiment. Referring to Figure 8A, the manufacturing process has completed the formation of the multilayer structure 55 and the channel structure as shown in Figure 7I. Subsequently, the top insulating layer 96 is deposited. Next, as shown in Figure 8B, an opening 82 is formed to expose the channel structure formed in the multilayer structure 55. Subsequently, as shown in Figure 8C, a conductive material is filled into the opening 82 to form a conductive via structure 98. In one example, the conductive material is copper.

[0078] Next, as shown in Figure 8D, trenches 84 extending in the Y direction are formed in the multilayer structure 55 to separate it into individual memory stacks. Then, as shown in Figure 8E, dielectric layers 95, such as silicon oxide (SiO2), are filled into the trenches 84. Finally, as shown in Figure 8F, conductive layers 99 are deposited on the memory structure 50 and patterned to form global word lines. This forms the drain terminals of the word line selection transistors 36.

[0079] In this detailed description, process steps described in one embodiment may be used in another embodiment even if they are not explicitly described in another embodiment. Where this specification refers to a method including two or more defined steps, the defined steps may be performed in any order or simultaneously, unless the context indicates or specific instructions are otherwise provided herein. Furthermore, unless the context indicates or specific instructions are otherwise provided, the method may also include one or more other steps performed before any defined step, between two defined steps, or after all defined steps.

[0080] In this detailed description, various embodiments or examples of the present invention can be carried out in various forms, such as processes, apparatus, systems, and compositions of materials. A detailed description of one or more embodiments of the present invention is provided above, along with accompanying drawings illustrating the principles of the present invention. Although the present invention has been described in relation to such embodiments, the present invention is not limited to any embodiment. Various modifications and variations are possible within the scope of the present invention. The scope of the present invention is limited only by the appended claims, and the present invention encompasses various alternative forms, modifications, and equivalents. In order to provide a complete understanding of the present invention, numerous specific details are described herein. These details are provided for illustrative purposes only, and the present invention can be carried out in accordance with the claims without some or all of these specific details. For clarity, technical matters known in the art relating to the present invention are not described in detail so as not to unnecessarily obscure the present invention. The present invention is defined by the appended claims.

Claims

1. It is a memory circuit, An array of thin-film ferroelectric memory transistors formed by a plurality of NOR memory strings intersecting a plurality of local word line structures, wherein the plurality of NOR memory strings are arranged as a plurality of stacks including vertically aligned NOR memory strings, and each NOR memory string has a common drain line and a common source line, A plurality of local word line structures, comprising a group comprising a plurality of the local word line structures, wherein the local word line structures within each group are arranged along the NOR memory string of at least one stack, and each local word line structure extends vertically along the vertically aligned NOR memory string in at least one stack and has a channel layer and a gate conductor layer separated from each other by a ferroelectric gate dielectric layer, and the thin-film ferroelectric memory transistor is formed at the intersection of the common drain line and the common source line of each local word line structure and each NOR memory string, and the gate conductor layer of each local word line structure functions as a common gate terminal of the thin-film ferroelectric memory transistor in the vertically aligned NOR memory string in each stack that intersects with each local word line structure, A plurality of global word lines arranged orthogonally to the plurality of NOR memory strings, wherein each of the plurality of global word lines is aligned with the set of local word line structures provided across the entire plurality of stacks, A plurality of word line selection transistors, comprising a group of the plurality of word line selection transistors, each group of the word line selection transistors arranged along the NOR memory string of at least one of the stacks, each word line selection transistor having a source terminal which is the gate conductor layer of the associated local word line structure and provided between each local word line structure and the associated global word line, a drain terminal connected to the associated global word line, and a gate terminal connected to receive the respective selection gate signal, and each group of the word line selection transistors is controlled by the same selection gate signal, A memory circuit in which, when the global word line is asserted and a set of associated local word line structures is selected, each group of word line selection transistors is activated by the respective selection gate signals to electrically connect the asserted global word line to the common gate terminal of the associated local word line structure, thereby activating one of the local word line structures from the set of local word line structures.

2. A memory circuit according to claim 1, The aforementioned plurality of word line selection transistors are thin-film transistors, Each of the word line selection transistors has a channel layer and a gate dielectric layer. The gate dielectric layer is formed between the channel layer and the gate terminal. A memory circuit in which the channel layer of the word line selection transistor and the channel layer of the thin-film ferroelectric memory transistor are formed of the same material.

3. A memory circuit according to claim 1, Each group of word line selection transistors includes a channel structure having the same periodicity as the local word line structure, so as to overlap the local word line structure associated with it. Each of the channel structures is a memory circuit having a channel layer and a gate dielectric layer surrounding the channel layer.

4. A memory circuit according to claim 3, The gate terminals of the plurality of word line selection transistors have a conductive layer formed on the upper side of the stack of the NOR memory string. A memory circuit in which each of the conductive layers is in contact with the channel structure within each group of word line selection transistors.

5. A memory circuit according to claim 3, A memory circuit in which the gate terminals of the plurality of word line selection transistors are formed on the upper side of the stack of the NOR memory string and have a conductive layer surrounding the channel structure within each group of word line selection transistors.

6. A memory circuit according to claim 1, When a first global word line is formed across the multiple stacks of the NOR memory string and asserted to select a first subset of the thin-film ferroelectric memory transistors that intersect with a first set of local word line structures, A memory circuit in which a first group of word line selection transistors is activated to select a second subset of the thin-film ferroelectric memory transistors within a first subset of the thin-film ferroelectric memory transistors associated with the activated local word line structure, while the remaining ferroelectric memory transistors within the first subset remain unselected.

7. A memory circuit according to claim 6, A memory circuit in which the second subset of thin-film ferroelectric memory transistors includes memory transistors in one stack of the NOR memory strings relating to the first set of local word line structures having a gate conductor layer electrically connected to the first global word line asserted via the first group of word line selection transistors.

8. A memory circuit according to claim 6, A memory circuit comprising a second subset of thin-film ferroelectric memory transistors, each comprising memory transistors in two stacks of the NOR memory string, relating to a first set of local word line structures having a gate conductor layer electrically connected to a first global word line asserted via the first group of word line selection transistors.

9. A memory circuit according to claim 1, A memory circuit in which each NOR memory string within each stack is isolated from adjacent NOR memory strings within the same stack by an insulating layer.

10. A memory circuit according to claim 1, In each of the local word line structures, the channel layer is formed adjacent to each NOR memory string in the stack and is discontinuous between adjacent NOR memory strings, wherein the memory circuit is configured such that the channel layer is adjacent to each NOR memory string in the stack.

11. A memory circuit according to claim 1, The array of thin-film ferroelectric memory transistors is configured as multiple pages of the thin-film ferroelectric memory transistors, When the global word line is asserted and a set of local word line structures aligned with the global word line is selected, A memory circuit in which a first subset of the word line selection transistors is activated by each selection gate signal to electrically connect the asserted global word line to the common gate terminal of the associated local word line structure, thereby activating the local word line structure associated with a given page of the thin-film ferroelectric memory transistor.

12. A three-dimensional memory structure formed on a semiconductor substrate, An array of thin-film ferroelectric memory transistors configured as a plurality of stacks of NOR memory strings, wherein each stack is separated from adjacent stacks along a first direction by trenches, the plurality of stacks extend along a second direction substantially parallel to the plane of a semiconductor substrate, the NOR memory strings of each stack are stacked on top of each other along a third direction substantially orthogonal to the plane of the semiconductor substrate, each NOR memory string has a common drain layer formed spaced apart from a common source layer, and the local word line structure is in contact with the stacks of the NOR memory strings. The local word line structures are arranged apart from each other in the second direction, and each local word line structure extends in the third direction, and each local word line structure has a channel layer in contact with the NOR memory string in the stack associated therewith, a ferroelectric gate dielectric layer formed adjacent to the channel layer, and a gate conductor layer provided in the local word line structure adjacent to the ferroelectric gate dielectric layer, wherein the gate conductor layer functions as a common gate terminal for the thin-film ferroelectric memory transistors in the NOR memory string in each stack associated with the local word line structure, and the array of thin-film ferroelectric memory transistors, A plurality of word line selection transistors, each of which is associated with a given local word line structure, and each of which has a source terminal which is the gate conductor layer of the associated local word line structure, a drain terminal connected to one of a plurality of global word lines, and a gate terminal connected to receive a selection gate signal, the plurality of word line selection transistors, A three-dimensional memory structure wherein, when a first global word line among the plurality of global word lines is asserted and a set of associated local word line structures is selected, a first word line selection transistor is activated by a first selection gate signal to electrically connect the asserted first global word line to the common gate terminal of the associated local word line structure, thereby activating one of the local word line structures from the set of local word line structures.

13. A three-dimensional memory structure according to claim 12, Each of the thin-film ferroelectric memory transistors in the NOR memory string includes a drain terminal formed by the common drain layer as a bit line, a source terminal formed by the common source layer, and a gate terminal formed by the gate conductor layer of the local word line structure that contacts the NOR memory string. Each of the memory transistors is a three-dimensional memory structure formed at the intersection of the NOR memory string and the local word line structure.

14. A three-dimensional memory structure according to claim 12, The aforementioned plurality of word line selection transistors are thin-film transistors, Each of the word line selection transistors has a channel layer and a gate dielectric layer. The gate dielectric layer is formed between the channel layer and the gate terminal. A three-dimensional memory structure in which the channel layer of the word line selection transistor and the channel layer of the thin-film ferroelectric memory transistor are formed of the same material.

15. A three-dimensional memory structure according to claim 12, A three-dimensional memory structure wherein the plurality of global word lines extend in the first direction and have the same periodicity as the local word line structure.

16. A three-dimensional memory structure according to claim 12, The first global word line is formed across the plurality of stacks of the NOR memory string and, when asserted to select a first subset of the thin-film ferroelectric memory transistors that intersect with a first set of local word line structures, A three-dimensional memory structure in which a first group of word line selection transistors is activated to select a second subset of the thin-film ferroelectric memory transistors within a first subset of the thin-film ferroelectric memory transistors associated with the activated local word line structure, while the remaining ferroelectric memory transistors within the first subset remain unselected.

17. A three-dimensional memory structure according to claim 16, A three-dimensional memory structure comprising a second subset of thin-film ferroelectric memory transistors, each comprising memory transistors in one stack of the NOR memory strings, relating to a first set of local word line structures having a gate conductor layer electrically connected to a first global word line asserted via the first group of word line selection transistors.

18. A three-dimensional memory structure according to claim 16, A three-dimensional memory structure comprising a second subset of thin-film ferroelectric memory transistors, each comprising memory transistors in two stacks of the NOR memory string, relating to a first set of local word line structures having a gate conductor layer electrically connected to a first global word line asserted via the first group of word line selection transistors.

19. A three-dimensional memory structure according to claim 12, The plurality of word line selection transistors include a group composed of the plurality of word line selection transistors, Each group of the word line selection transistors is arranged along the NOR memory string of the stack, The plurality of word line selection transistors include a channel structure having the same periodicity as the local word line structure, so as to overlap the local word line structure. Each of the channel structures is a three-dimensional memory structure having a channel layer and a gate dielectric layer surrounding the channel layer.

20. A three-dimensional memory structure according to claim 19, The gate terminals of the plurality of word line selection transistors have a conductive layer formed on the stack of the NOR memory strings. A three-dimensional memory structure in which each of the conductive layers is in contact with the channel structure within each group of the word line selection transistors.

21. A three-dimensional memory structure according to claim 19, A three-dimensional memory structure having a conductive layer surrounding the channel structure within each group of word line selection transistors, wherein the gate terminals of the plurality of word line selection transistors are formed on the upper side of the stack of the NOR memory string.

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