Self-aligned lithography-lithography mandrel cutting process for advanced FINFET interconnects

Abstract

A method for fabricating a semiconductor device includes the step of providing a semiconductor structure having a dielectric stack and a mandrel layer positioned on the dielectric stack. An array of sacrificial mandrel features is patterned within the mandrel layer and above the insulating layer of the dielectric stack. A self-aligned non-mandrel cut is formed adjacent to one of the sacrificial mandrel features. The sacrificial mandrel features are removed. One or more self-aligned mandrel cuts are formed in one or more of a plurality of trenches. Non-mandrel openings are formed above the insulating layer. Continuous line openings are etched within the dielectric stack, where non-mandrel cuts interrupt the first of the continuous line openings and mandrel cuts interrupt the second of the continuous line openings. Metal lines are formed in the continuous line openings except where the non-mandrel cuts and mandrel cuts are located.

Description

Technical Field

[0001] The present invention generally relates to semiconductor device fabrication, and more specifically to a self-aligned litho-etch-litho-etch (SALELE) mandrel cut process for evolved FINFET interconnects.

Background Art

[0002] In semiconductor device manufacturing, multiple self-aligned patterning processes are used as practical solutions for the manufacturing process. For example, a back-end-of-line (BEOL) interconnect structure can be used to connect device structures fabricated on a substrate during front-end-of-line (FEOL) processing. The self-aligned patterning process used to form the BEOL interconnect structure includes a linear mandrel that acts as a sacrificial feature to establish a feature pitch. Non-mandrel lines are arranged as linear spaces between sidewall spacers formed adjacent to the sidewalls of the mandrel. After the mandrel is removed to define the mandrel line, the sidewall spacers are used as an etching mask to etch a pattern based on the mandrel line and non-mandrel lines into the underlying hard mask. The pattern is subsequently transferred from the hard mask to the interlayer dielectric layer to define trenches in which wires of the BEOL interconnect structure are formed.

[0003] A mandrel cut can be formed in the mandrel. A non-mandrel cut can be formed along the non-mandrel line and can include a portion of the spacer material used to form the sidewall spacers. The mandrel cut and non-mandrel cut are included in the pattern that is transferred to the hard mask and subsequently transferred to the hard mask to form trenches in the interlayer dielectric layer.

Summary of the Invention

[0004] Generally, embodiments provide processes and devices for forming mandrel cut features after a mandrel delamination process. Non-mandrel cuts may be formed before mandrel delamination. As understood, the mandrel and non-mandrel cuts are self-aligned, but since the mandrel cuts are performed after spacer deposition, variations in critical dimensions can be controlled, if not eliminated. For example, a spacer pinch-off process may not need to be performed. Instead, the mandrel and non-mandrel cut sections can be patterned using self-alignment techniques. This allows for more even spacing between continuous lines and cuts (e.g., they can be arranged in this way).

[0005] According to one embodiment of the present invention, a method for fabricating a semiconductor device is provided. The method includes the step of providing a semiconductor structure having a dielectric stack and a mandrel layer positioned on the dielectric stack. An array of sacrificial mandrel features is patterned within the mandrel layer and above the insulating layer of the dielectric stack. A self-aligned non-mandrel cut is formed adjacent to one of the sacrificial mandrel features. The sacrificial mandrel features are removed. The removal of the sacrificial mandrel features creates a plurality of trenches. After the removal of the sacrificial mandrel features, a self-aligned mandrel cut is formed in one of the plurality of trenches. A non-mandrel opening is formed above the insulating layer. A continuous line opening is etched within the dielectric stack. A non-mandrel cut is positioned to interrupt the first of the continuous line openings. A self-aligned mandrel cut is positioned to interrupt the second of the continuous line openings. A metallic line is formed in the continuous line openings, except where the self-aligned non-mandrel cut and the self-aligned mandrel cut are located.

[0006] In one embodiment, a self-aligned mandrel spacer is formed on the sidewall of the sacrificial mandrel feature. The thickness of the mandrel spacer is easily controlled and not subject to variation due to pinch-off. As a result, the edges of the spacer wall become more consistent.

[0007] According to another embodiment of the present invention, a semiconductor chip device is provided. The semiconductor device includes a substrate. A dielectric interconnect layer is positioned on top of the substrate. A plurality of metal lines are positioned on the dielectric interconnect layer. A self-aligned mandrel cut is present on at least one of the metal lines. A self-aligned non-mandrel cut is present on at least one of the metal lines.

[0008] In one embodiment, the spacing between multiple metal lines is evenly distributed. This even spacing prevents unintended bridging between the metal lines and cuts in the lines.

[0009] According to another embodiment of the present invention, a semiconductor device interconnect layer is provided. The semiconductor device interconnect layer includes a dielectric substrate. A first metallic line extends in a first direction of the dielectric substrate. A second metallic line extends in a first direction. The second metallic line is parallel to the first metallic line. A first dielectric region is located in a first space between the first and second metallic lines. A self-aligned mandrel cut is present on the first metallic line. A non-mandrel cut is present on the second metallic line.

[0010] In one embodiment, the first dielectric region and the second dielectric region are self-aligned with respect to the first and second metal lines. This feature avoids pitch walking, which can occur when the spacer thickness between the cut and the metal lines is not constant and is arbitrary.

[0011] According to one embodiment of the present invention, a method for fabricating a semiconductor device is provided. The method includes the step of providing a semiconductor structure having a dielectric stack, an interconnect layer in the dielectric stack, and a mandrel layer positioned on the dielectric stack. An array of mandrels is patterned within the mandrel layer and above the insulating layer of the dielectric stack. A self-aligned non-mandrel cut is formed adjacent to one of the mandrels. The mandrels are removed, creating a plurality of parallel trenches. A self-aligned mandrel cut is formed in one of the plurality of trenches. A non-mandrel opening is formed above the insulating layer. The non-mandrel opening is parallel to the plurality of trenches. A continuous line is formed in the interconnect layer. A continuous line is formed in the plurality of trenches and the non-mandrel opening. The first of the continuous lines includes a non-mandrel cut. The second of the continuous lines includes a mandrel cut.

[0012] In one embodiment, the mandrel cut is positioned offset from the non-mandrel cut. Offset cuts with a constant critical dimension are possible when the cut is formed before or after mandrel delamination. When attempting to offset the cut using a pinch-off method, variations in the critical dimension of the cut occur because the fabrication scale is generally performed in ranges of 7 nanometers or smaller in the future.

[0013] The techniques described herein may be implemented in several ways. Exemplary implementations are provided below with reference to the following figures. [Brief explanation of the drawing]

[0014] The drawings are illustrative embodiments. They do not illustrate all embodiments. Other embodiments may be used in addition or in place of others. Details that may be obvious or unnecessary may be omitted for space saving or for more effective illustration. Some embodiments may be put into practice with and / or without using all of the illustrated components or steps. When the same number appears in different drawings, it refers to the same or similar component or step.

[0015] [Figure 1] Figure 1A is a schematic cross-sectional view consistent with embodiments of the present invention, showing the initiation of film deposition for a semiconductor device.

[0016] Figure 1B is a top view of the formation shown in Figure 1A.

[0017] [Figure 2] Figure 2A is a schematic cross-sectional view of a mandrel formation lithography process consistent with embodiments of the present invention.

[0018] Figure 2B is a top view of the formation shown in Figure 2A.

[0019] [Figure 3] Figure 3A is a schematic cross-sectional view of a mandrel etching process consistent with an embodiment of the present invention.

[0020] Figure 3B is a top view of the formation shown in Figure 3A.

[0021] [Figure 4] Figure 4A is a schematic cross-sectional view of a spacer film deposition process consistent with the embodiments of the present invention.

[0022] Figure 4B is a top view of the formation shown in Figure 4A.

[0023] [Figure 5] Figure 5A is a schematic cross-sectional view of a spacer etch-back process consistent with an embodiment of the present invention.

[0024] Figure 5B is a top view of the formation in Figure 5A.

[0025] [Figure 6] Figure 6A is a schematic cross-sectional view of the masking of the formation in Figure 5A for NMN cutting using a lithography etch-back process, consistent with an embodiment of the present invention.

[0026] Figure 6B is a top view of the formation in Figure 6A.

[0027] [Figure 7] Figure 7A is a schematic cross-sectional view of a filling process for NMN cutting, consistent with an embodiment of the present invention.

[0028] Figure 7B is a top view of the formation in Figure 7A.

[0029] [Figure 8] Figure 8A is a schematic cross-sectional view of the formation in Figure 7A after application of a chemical vapor deposition process, consistent with an embodiment of the present invention.

[0030] Figure 8B is a top view of the formation in Figure 7A.

[0031] [Figure 9] Figure 9A is a schematic cross-sectional view of the formation in Figure 8A after application of a mandrel stripping process, consistent with an embodiment of the present invention.

[0032] Figure 9B is a top view of the formation in Figure 9A.

[0033] [Figure 10] Figure 10A is a schematic cross-sectional view of the masking of the formation in Figure 9A for mandrel cutting using a lithography etch-back process, consistent with an embodiment of the present invention.

[0034] Figure 10B is a top view of the formation in Figure 10A.

[0035] [Figure 11] Figure 11A is a schematic cross-sectional view of the mandrel cut filling in Figure 10A, consistent with the embodiments of the present invention.

[0036] Figure 11B is a top view of the formation shown in Figure 11A.

[0037] [Figure 12] Figure 12A is a schematic cross-sectional view of the masking of the formation in Figure 11A, consistent with the embodiments of the present invention.

[0038] Figure 12B is a top view of the formation shown in Figure 12A.

[0039] [Figure 13] Figure 13A is a schematic cross-sectional view showing the removal of the forming mask in Figure 12A, consistent with embodiments of the present invention.

[0040] Figure 13B is a top view of the formation shown in Figure 13A.

[0041] [Figure 14] Figure 14A is a schematic cross-sectional view showing the formation in Figure 13A after a reactive ion etching process, consistent with embodiments of the present invention.

[0042] Figure 14B is a top view of the formation shown in Figure 14A.

[0043] [Figure 15] Figure 15A is a schematic cross-sectional view showing the formation in Figure 14A after the interlayer dielectric etching process, consistent with the embodiments of the present invention.

[0044] Figure 15B is a top view of the formation shown in Figure 15A.

[0045] [Figure 16] Figure 16A is a schematic cross-sectional view showing the formation in Figure 15A after the masking removal process, consistent with embodiments of the present invention.

[0046] Figure 16B is a top view of the formation shown in Figure 16A.

[0047] [Figure 17] Figure 17A is a schematic cross-sectional view showing the formation in Figure 16A after the plating process, consistent with the embodiments of the present invention.

[0048] Figure 17B is a top view of the formation shown in Figure 17A. [Modes for carrying out the invention]

[0049] In conventional patterning processes, controlling mandrel dimensions at different feature locations can be a challenge. As fabrication techniques move to the 7-nanometer scale, the ability to uniformly control mandrel and non-mandrel features across the wafer becomes highly dependent on controlling critical dimensions of mandrel cuts and providing uniform space. Spacer features are generally used to define the space between mandrel and non-mandrel lines.

[0050] If the critical dimension for the mandrel cut is too large, the cut cannot be sufficiently pinched off by the spacer. As a result, bridging of non-mandrel lines between features may occur. However, arbitrarily adjusting the spacer thickness to prevent pitch variation of the critical dimension between features (also known as "pitch walking") is not a reliable solution. If the critical dimension for the mandrel cut is too small, it is not possible to pattern the critical dimension for the cut. The absence of a mandrel pattern can also create the problem of mandrel line bridging. As the patterning scale decreases, the critical dimensions of the mandrel cut and spacer thickness can easily vary across each structure patterned on the die throughout the wafer. Variation in critical dimensions can impose further problems in forming uniform patterning features of the unique cuts (holes).

[0051] Generally, this disclosure describes a process for providing a semiconductor device that includes forming pillar-based mandrel cuts as non-mandrel features before and after mandrel delamination is performed. The process avoids the need to use pinch-off of spacer material between mandrels in the conventionally performed mandrel cutting stage. As a result, the mandrel and non-mandrel cuts can be self-aligned, thereby providing better consistency in the spacing between cuts and interconnects. It also avoids defects such as breaks in the spacer material that occur during pinch-off. The spacer material decouples unintended bridges between adjacent structures.

[0052] For the sake of brevity, conventional techniques for fabricating semiconductor devices and integrated circuits (ICs) may or may not be described in detail herein. Furthermore, various tasks and process steps described herein can be incorporated into more comprehensive procedures or processes that have additional steps or functions not described in detail herein. In particular, since the various steps in the fabrication of semiconductor devices and semiconductor-based ICs are well known, for the sake of brevity, many conventional steps are described only briefly herein or are omitted entirely without providing details of the well known processes.

[0053] In the embodiments for carrying out the following inventions, many specific details are given as examples to provide a complete understanding of the relevant teachings. However, it is clear that these teachings can be practiced without such details. In other examples, well-known methods, procedures, components, and / or circuits are described relatively broadly without detail to avoid unnecessarily ambiguous aspects of these teachings.

[0054] In one embodiment, spatially related terminology such as “front,” “back,” “top,” “bottom,” “down,” “below,” “up,” “side,” “left,” “right,” and similar terms are used in reference to the orientation of the diagram being described. Since components of embodiments of this disclosure can be positioned in numerous different orientations, the terminology of orientation is used for illustrative purposes without limitation. It will be understood that the spatially relative terminology is intended to encompass different orientations of the device in use or operation, in addition to the orientation shown in the diagram. For example, if the device in the diagram is rotated, an element described as “below” or “beneath” another element or feature will be oriented “above” that other element or feature. Thus, for example, the term “below” may encompass both downward and upward orientations. Similarly, an element described as “above” another element may mean that the element is positioned above the element below it, but not necessarily in direct contact with it. The device may be oriented in a different way (rotated 90 degrees, or viewed or referenced in another direction), and spatially relative descriptors used herein should be interpreted accordingly.

[0055] As used herein, the terms “lateral,” “planar,” and “horizontal” describe an orientation parallel to the first surface of the chip or substrate. In this disclosure, the “first surface” may be the uppermost layer of a semiconductor device in which individual circuit devices are patterned in the semiconductor material.

[0056] As used herein, the term “perpendicular” describes an orientation in which a chip, chip carrier, chip substrate, or semiconductor body is positioned perpendicular to the first surface.

[0057] As used herein, the terms “coupled” and / or “electrically coupled” do not necessarily mean that the elements must be directly coupled together—intermediate elements may be provided between “coupled” or “electrically coupled” elements. In contrast, when one element is referred to as “directly connected” or “directly coupled” to another element, there are no intermediary elements. The term “electrically connected” refers to a low-resistance electrical connection between electrically connected elements. The phrase “electrically connected” does not necessarily mean that the elements must be in direct physical contact together; intermediary elements may be provided between “connected” or “electrically connected” elements.

[0058] Terms such as "first," "second," etc., may be used herein to describe various elements, and these elements should not be limited by these terms. These terms are used solely to distinguish one element from another. For example, without departing from the scope of the exemplary embodiments, a first element may be called a second element, and similarly, a second element may be called a first element. Describing elements as "first" or "second," etc., does not necessarily imply that there is an order or priority for any of the elements. Where used herein, the term "and / or" includes any and all combinations of one or more of the associated enumeration items.

[0059] Exemplary embodiments are described herein with reference to schematic cross-sectional views of idealized or simplified embodiments (and intermediate structures). As a result, variations in, for example, manufacturing techniques and / or tolerances from the illustrated shapes can be anticipated. Therefore, the areas illustrated in the figures are of a schematic nature, and their shapes do not necessarily represent the actual shapes of the areas of the device, nor do they limit the scope. It should be understood that the figures and / or drawings accompanying this disclosure are illustrative, non-limiting, and not necessarily drawn to scale.

[0060] Other embodiments may be used, and it is understood that structural or logical modifications may be made without departing from the scope defined by the claims. The description of embodiments is not limiting. In particular, elements of the embodiments described below may be combined with elements of different embodiments. definition

[0061] Mandrel: A linear or ridge-like projection formed on a substrate. In this disclosure, the mandrel defines one of the lines on which an interconnect is formed in the underlying layer.

[0062] Interconnect: A structure that electrically connects two or more circuit elements (such as transistors).

[0063] Self-alignment: Patterning of the alignment of one structure with respect to another structure.

[0064] Continuous line: Metal or other conductive trace or interconnect.

[0065] Discontinuity: A break or interruption in a continuous line.

[0066] Sacrifice: A structure formed as a placeholder feature that will be removed to define a new or different feature.

[0067] Substrate: A reference to a substrate may refer to a material that provides a support structure for features within or on top of the substrate material. When used below, there may be more than one substrate in the embodiments shown. Also, since the embodiments below are generally shown in cross-section, it should be understood that the substrate for a layer with patterned features may not be visible in the figures in order to highlight the features of the layer. Exemplary manufacturing method

[0068] The following describes a general method for forming semiconductor devices using pillar-based mandrel cuts as non-mandrel cuts before and after a mandrel stripping process. The fabrication of devices described herein may include a multi-step sequence of photolithography and / or chemical processing steps to facilitate the stepwise fabrication of electron-based systems, devices, components, and / or circuits in, for example, semiconducting and / or superconducting devices (e.g., integrated circuits). For example, device 100 can utilize photolithography, microlithography, nanolithography, nanoimprint lithography, photomasking techniques, patterning techniques, photoresist techniques (e.g., positive photoresist, negative photoresist, hybrid photoresist, and / or other photoresist techniques), etching techniques (e.g., reactive ion etching (RIE), dry etching, wet etching, ion beam etching, plasma etching, laser cautery, and / or other etching techniques), vapor deposition techniques, sputtering techniques, plasma ashing techniques, heat treatment (e.g., fast thermal annealing, furnace annealing, thermal oxidation, and / or other heat treatments), chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), molecular beam epitaxy (MBE), electrochemical deposition (ECD), and chemical-mechanical planarization. They can be fabricated on one or more substrates (e.g., a silicon (Si) substrate and / or another substrate) by using techniques including, but not limited to, planarization (CMP), back grinding techniques, and / or other techniques for fabricating integrated circuits.

[0069] Figure 1A is a schematic cross-sectional view of semiconductor device 100 at an intermediate stage of fabrication. A stack of substrate 105 and dielectric layers is formed on top of the substrate 105, which includes a first insulating layer 115, a spacer layer 120, and a second insulating layer 125. In some embodiments, an interconnect layer 110 may be formed on the base semiconductor substrate 105 before the formation of the first insulating layer 115. The interconnect layer 110 may be made from a silicon oxycarbonitride (SiCNO) film or other similar dielectric. At the intermediate stage of fabrication shown, the interconnect layer 110 does not yet contain any interconnect structure. Interconnect structures, such as continuous lines, will be formed as a result of the subject process disclosed herein.

[0070] In one embodiment, the base semiconductor substrate 105, formed from, for example, silicon, or other types of semiconductor substrate materials commonly used in bulk semiconductor fabrication, such as, for example, single-crystal Si, silicon germanium (SiGe), III-V compound semiconductors, II-VI compound semiconductors, or semiconductor-on-insulator (SOI), may be a bulk semiconductor substrate. III-V compound semiconductors include materials having at least one group III element and at least one group V element, such as aluminum gallium arsenide (AlGaAs), aluminum gallium nitride (AlGaN), aluminum arsenide (AlAs), indium aluminum arsenide (AlIAs), aluminum nitride (AlN), gallium antimonide (GaSb), aluminum gallium antimonide (GaAlSb), gallium arsenide (GaAs), gallium antimonide (GaAsSb), gallium nitride (GaN), indium antimonide (InSb), indium arsenide (InAs), indium gallium arsenide (InGaAs), indium gallium arsenide phosphide (InGaAsP), indium gallium nitride (InGaN), indium nitride (InN), indium phosphide (InP), and one or more combinations of alloys containing at least one of the aforementioned materials. The alloy combinations may include binary (two elements, e.g., gallium(III) arsenide (GaAs)), ternary (three elements, e.g., InGaAs) and quaternary (four elements, e.g., indium aluminum gallium phosphide (AlInGaP)) alloys. The dielectric layer 130 for forming the mandrel line may be deposited on top of the second insulating layer 125.

[0071] Figures 2A and 2B show the formation of an etching mask for patterning the second insulating layer 125. An organic planarization layer (OPL) or oxide diffusion layer (ODL) 135 may be deposited on top of the dielectric layer 130. Masking rows 140 may be formed on top of layer 135. Figures 3A and 3B show the results of the etching process, where the masking rows 140 and layer 135 are removed, etching the dielectric layer 130 and leaving the sacrificial mandrel feature 132. Etching may be stopped at the second insulating layer 125.

[0072] Figures 4A and 4B show the conformal deposition of spacer material 138 surrounding the sacrificial mandrel feature 132. The spacer material 138 may be the same material as the spacer layer 120, and therefore the same cross-hatching pattern is used for both layers. Figures 5A and 5B show the results of etch-back of the spacer material 138 from the upper edge of the sacrificial mandrel feature 132 and from the top of the second insulating layer 125 and the space between the sacrificial mandrel features 132. The resulting formation provides a self-aligned mandrel spacer 142 with respect to the sidewall of each sacrificial mandrel feature 132. In some embodiments, the thickness of the mandrel spacer 142 on the sidewall of the sacrificial mandrel feature 132 is formed uniformly. As can be understood, the thickness of the mandrel spacer 142 can be controlled so as to provide a uniform and constant spacing between the featured mandrel and non-mandrel cut lines on the spacer layer 120.

[0073] Figures 6A and 6B illustrate the process of forming a non-mandrel cut line. A temporary insulating layer 145 and an etching mask 150 may seal the top of the sacrificial mandrel feature 132 (indicated by "L", "C", and "R" respectively to represent the left, center, and right positioning of each mandrel feature), the spacer sidewall 142, and the top of the exposed section of the second insulating layer 125. A trench 152 may be left open between the central sacrificial mandrel feature 132C and the left sacrificial mandrel feature 132L. The right sacrificial mandrel feature 132R may be completely sealed. The exposed trench 152 will be used to form a placeholder for the self-aligned non-mandrel cut line. As can be understood, the thickness of the non-mandrel cut line is controlled at this level of fabrication by defining the width of the trench 152 and the amount of etching previously performed on the spacer material 138 on the sides of the sacrificial mandrel feature 132.

[0074] Figures 7A and 7B show the removal of the temporary insulating layer 145 and etching mask 150 from above the sacrificial mandrel feature 132 and mandrel spacer 142. The opened trench 152 can be filled with placeholder material 155 (e.g., gap-filling material such as SOG, SiOC, or ALD TiOX) using, for example, electron beam deposition. Figures 8A and 8B show the result of removing the temporary insulating layer 145 and depositing a layer of fluid silicon dioxide 160 into the area left open by the temporary insulating layer 145. A planarization process can be applied to all materials above the second insulating layer 125.

[0075] Figures 9A and 9B show the result of peeling off the sacrificial mandrel feature 132, leaving an empty trench 156. Figures 10A and 10B show the process of forming a self-aligned mandrel cut line with the adjacent mandrel spacer 142. The process involves masking the area excluding the central trench 156 left from the mandrel peeling. Masking can be repeated using an insulating layer 145 and an etching mask 150 (as previously used, as shown in Figures 6A and 6B). The exposed central trench 156 defines a self-aligned mandrel cut line with respect to the adjacent sidewalls of the mandrel spacer 142. In some embodiments, the mandrel cut line may be self-aligned with respect to the sidewalls of non-mandrel cut lines. Figures 11A and 11B show filling the central trench 156 for the mandrel cut line with placeholder material 165. It can be understood that the critical dimensions of the final mandrel line are defined by the trench width and the controlled thickness of the adjacent mandrel spacers 142. The temporary insulating layer 145 and etching mask 150 can be removed. As can be seen more clearly in Figure 11B, the critical dimensions of the mandrel and non-mandrel cut lines are controlled with respect to the surrounding mandrel spacers 142.

[0076] Figures 12A and 12B illustrate the process of forming a non-mandrel opening. The process involves masking the area excluding the trench 162 formed after selective etching and removal of the lines of fluid silicon dioxide 160 (e.g., using a temporary insulating layer 145). The placeholder material 155 for the non-mandrel cut is resistant to the etching chemicals used and remains protected even when exposed, as shown in Figure 12B. The etching process forms a non-mandrel opening beneath a second insulating layer 125.

[0077] Figures 13A and 13B show the process of forming additional non-mandrel opening lines beneath the second insulating layer 125. Figures 14A and 14B show the process of etching down placeholder material 155 for the non-mandrel cut line, placeholder material 165 for the mandrel cut line, mandrel spacer 142, and any remaining fluid silicon dioxide 160. Etching is formed in and through both the second insulating layer 125 and the spacer layer 120, and the first insulating layer 115 may be exposed along the formed lines.

[0078] Figures 15A and 15B show the dielectric etching process to remove the second insulating layer 125 and form an opening through both the first insulating layer 115 and the substrate 105. The opening will define a continuous line in the interconnect layer 120. Figures 16A and 16B show further etch-down to remove the first insulating layer 115.

[0079] Figures 17A and 17B show metallization applied to an opening to form metal lines 175. In the shown example, first, second, third, fourth, and fifth metal lines 175 are shown. Other embodiments may include more or fewer metal lines 175. The metal lines 175 represent, for example, continuous lines in the interconnect layer 110 (or another layer) within a semiconductor device. The first, second, third, fourth, and fifth metal lines 175 may extend in the same direction. The first, second, third, fourth, and fifth metal lines 175 may be formed parallel to each other. The spacing between the metal lines 175 may be evenly distributed. The first of the metal lines 175 includes a mandrel cut 185. The second of the metal lines 175 includes a non-mandrel cut 170. The third, fourth, and fifth metal lines 175 may be the result of a previously formed non-mandrel opening and do not include cuts. It will be understood that other embodiments may include cuts in any of the metal lines 175. In some embodiments, the metal line 175 shown including cuts 170 and 180 may not necessarily have cuts. In yet another embodiment, the metal line 175 may include one or more cuts. The resulting non-mandrel cut 170 may be positioned to self-align with the adjacent sidewall of the interconnect layer 110. The resulting mandrel cut 180 may be positioned to self-align with the adjacent sidewall of the interconnect layer 110.

[0080] The areas of dielectric material between adjacent metal lines 175 can be evenly distributed to create a constant spacing. This may be the result of patterning some of the non-mandrel lines so that the final result provides a first dielectric region and a second dielectric region that are self-aligned with respect to the first and second metal lines 175. In some embodiments, the width of the first dielectric region is equal to the width of the second dielectric region. In some embodiments, the etching process previously described may provide openings so that the metal lines 175 are arranged in a staggered array. For example, the ends of the first metal line 175 may be offset from the ends of the second metal line 175. As can be seen, the non-mandrel cuts 170 and 185 cut the metal lines 175 without clipping any neighboring lines or entering the spacing between the metal lines 175. As shown, embodiments may position the mandrel cut 185 offset from the non-mandrel cut 170. conclusion

[0081] While various embodiments of this instruction have been presented for illustrative purposes, they are not intended to be exhaustive or to be limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the embodiments described. The terminology used herein has been selected to best describe the principles of the embodiments, their practical applications, or any technological improvements over the technology available on the market, or to enable other those skilled in the art to understand the embodiments disclosed herein.

[0082] While the above describes what is considered to be the best-case and / or other examples, it should be understood that various modifications are possible therein, that the subject matter disclosed herein can be implemented in various forms and examples, and that the teachings can be applied to many uses, only some of which are described herein. The following claims are intended to claim any use, modification, and variation that falls within the true scope of these teachings.

[0083] The components, stages, features, objects, benefits, and advantages described herein are for illustrative purposes only. None of them, nor any of the descriptions relating to them, are intended to limit the scope of protection. While various advantages have been described herein, it should be understood that not all embodiments necessarily include all of these advantages. Unless otherwise specified, all measurements, values, ratings, locations, sizes, dimensions, and other specifications described herein, including the following claims, are approximate and not precise. They are intended to be within a reasonable range that is consistent with the functions to which they relate and with what is customary in the art to which they relate.

[0084] Many other embodiments are also contemplated. These include embodiments having fewer, additional, and / or different components, stages, features, objects, benefits, and advantages. These also include embodiments in which the components and / or stages are arranged and / or sequenced separately.

[0085] While the above has been described in conjunction with exemplary embodiments, it should be understood that the term “exemplary” merely means an example, and not the best or optimal. Except as stated immediately above, nothing described or illustrated, whether or not it is included in the claims, is intended to provide to the public any components, stages, features, subjects, benefits, advantages, or equivalents, and should not be construed as such.

[0086] The terms and expressions used herein shall be understood to have the ordinary meanings given to such terms and expressions in relation to their respective fields of study and research, unless otherwise stated herein. Relative terms such as "1" and "2" may be used solely to distinguish one entity or action from another entity or action, without necessarily requiring or implying any actual relationship or order between those entities or actions. The terms "comprises," "comprising," or other variations thereof are intended to describe non-exclusive inclusion, such that a process, method, article, or apparatus containing a list of elements may contain not only those elements, but other elements that are not specific to or expressly described in such process, method, article, or apparatus. The element preceded by "a" or "an" does not, unless further constraints apply, exclude the presence of additional identical elements in a process, method, article, or apparatus containing that element.

[0087] An abstract of this disclosure is provided to enable readers to quickly confirm the nature of the technical disclosure. The abstract is submitted with the understanding that it is not to be used to interpret or limit the scope or meaning of the claims. Furthermore, it is found that in the modes for carrying out the invention described herein, various features are grouped together in various embodiments for the purpose of streamlining the disclosure. This method of disclosure should not be interpreted as reflecting an intention that the claimed embodiments have more features than those explicitly described in each claim. Rather, as the following claims represent, the subject matter of the invention lies in fewer features than all the features of the single embodiment disclosed. For this reason, the following claims are incorporated herein into the modes for carrying out the invention, and each claim stands alone as separately claimed subject matter.

[0088] In preferred embodiments of the present invention as described herein, a semiconductor device interconnect layer is provided comprising: a dielectric substrate; a first metal line extending in a first direction of the dielectric substrate; a second metal line extending in the first direction, wherein the second metal line is parallel to the first metal line; a first dielectric region in a first space between the first and second metal lines; a self-aligned mandrel cut in the first metal line; and a non-mandrel cut in the second metal line. The non-mandrel cut may be positioned self-aligned with respect to an adjacent sidewall of the dielectric substrate. The device further comprises: a third metal line extending in a first direction, wherein the third metal line is parallel to the first and second metal lines; and a second dielectric region in a second space between either the first or second metal line. The first and second dielectric regions may be self-aligned with respect to the first and second metal lines. The width of the first dielectric region may be equal to the width of the second dielectric region.

[0089] A preferred embodiment of the present invention as described herein provides a method for fabricating a semiconductor device, comprising the steps of: providing a semiconductor structure having a dielectric stack, an interconnect layer in the dielectric stack, and a mandrel layer positioned on the dielectric stack; patterning an array of mandrels within the mandrel layer and on top of the insulating layer of the dielectric stack; forming a self-aligned non-mandrel cut adjacent to one of the sacrificial mandrel features; removing the mandrel features, the removal of which creates a plurality of parallel trenches; forming a self-aligned mandrel cut in one or more of the plurality of parallel trenches; forming a non-mandrel opening on top of the insulating layer, the non-mandrel opening being parallel to the plurality of parallel trenches; forming a continuous line in the interconnect layer, the continuous line being formed in the plurality of parallel trenches and non-mandrel openings; a first continuous line of the continuous line including a self-aligned non-mandrel cut; and a second continuous line of the continuous line including a mandrel cut. The method may further comprise the step of forming a mandrel spacer on the sidewall of the mandrel. Mandrel spacers on the side wall may be arranged to evenly space the continuous lines. The ends of the first continuous line may be offset from the ends of the second continuous line.

Claims

1. A step of providing a semiconductor structure having a dielectric stack and a mandrel layer positioned on the dielectric stack; The step of patterning an array of sacrificial mandrel features within the mandrel layer and on top of the insulating layer of the dielectric stack; A step of forming a self-aligned non-mandrel cut adjacent to one of the aforementioned sacrificial mandrel features; In the step of removing the sacrificial mandrel feature, multiple trenches are created by the removal of the sacrificial mandrel feature; The step of forming one or more self-aligned mandrel cuts in one or more of the trenches after removing the sacrificial mandrel features; A step of forming a non-mandrel opening on the upper part of the insulating layer; The step of etching a continuous line opening within the dielectric stack, wherein the self-aligned non-mandrel cut is positioned to interrupt the first of the continuous line openings, and the one or more self-aligned mandrel cuts are positioned to interrupt the second of the continuous line openings; and The step of forming a metal line in the continuous line opening, excluding the locations where the self-aligning non-mandrel cuts and the one or more self-aligning mandrel cuts are located. A method for fabricating a semiconductor device that includes the following features.

2. The method according to claim 1, further comprising the step of forming a self-aligning mandrel spacer on the side wall of the sacrificial mandrel feature.

3. The method according to claim 2, further comprising the step of removing the mandrel spacer before etching the continuous line opening.

4. The method according to claim 2, wherein the thickness of the mandrel spacer on the side wall of the sacrificial mandrel feature is uniformly formed.

5. The method according to claim 1, further comprising the step of filling the self-aligned non-mandrel cut with a first placeholder material.

6. The method according to claim 5, further comprising the step of filling the one or more self-aligning mandrel cuts with a second placeholder material.

7. The method according to claim 6, further comprising the step of removing the first placeholder material and the second placeholder material.

8. The method according to claim 1, further comprising the step of filling one or more of the plurality of trenches with fluid silicon dioxide.

9. The method according to claim 8, further comprising the step of removing the fluid silicon dioxide and forming one or more of the continuous line openings.

10. substrate; A dielectric interconnect layer positioned on top of the aforementioned substrate; Multiple metal lines positioned in the dielectric interconnect layer; Self-aligned mandrel cut in at least one of the aforementioned metal lines; and Self-aligned non-mandrel cut in at least one of the aforementioned metal lines A semiconductor device equipped with the following features.

11. The semiconductor device according to claim 10, wherein the first metal line among the plurality of metal lines is arranged parallel to the second metal line among the plurality of metal lines.

12. The semiconductor device according to claim 10, wherein the spacing between the plurality of metal lines is evenly distributed.

13. The semiconductor device according to claim 10, wherein the plurality of metal lines are arranged in a staggered array.

14. The semiconductor device according to claim 10, wherein the self-aligned mandrel cut is positioned offset from the self-aligned non-mandrel cut.

15. The semiconductor device according to claim 10, wherein the self-aligned mandrel cut is positioned in a self-aligned manner with respect to an adjacent side wall of the dielectric interconnect layer.

16. The semiconductor device according to claim 10, wherein the dielectric interconnect layer has a silicon oxycarbonitride (SiCNO) film.

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