Method and apparatus for converting the precision of floating-point data

Abstract

Embodiments of the present invention relate to the field of chip technology and provide a method and apparatus for precision conversion of floating-point data to reduce conversion errors during conversion from high-precision data to low-precision data. The specific solution involves determining the bit width of the second mantissa field based on the encoded value of the first exponential field, determining the retained encoded value and the discarded encoded value in the first mantissa field, wherein the retained encoded value includes an encoded value that starts from the most significant bit in the first mantissa field and has the same bit width as the bit width of the second mantissa field, and if the encoded value of the first exponential field is greater than or equal to a first pre-set threshold, rounding is performed on the retained encoded value based on the discarded encoded value which starts from the most significant bit and has the pre-set bit width to obtain the encoded value of the second mantissa field, and if the encoded value of the first exponential field is less than the first pre-set threshold, rounding is performed on the retained encoded value based on the most significant bit of the discarded encoded value to obtain the encoded value of the second mantissa field. Embodiments of the present invention are applicable to the process of precision conversion of floating-point data.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of chip technology, particularly to a method and apparatus for precision conversion of floating-point data.

Background Art

[0002] With the development of the field of artificial intelligence (AI), the neural network (NN) has been continuously expanding in scale, and the requirements for computational output for neural network learning are also increasing. Currently, due to the rapid increase in the computational output of model learning, a large overhead has occurred in chip costs. Using existing floating-point (FP) 16 mixed-precision data and brain floating-point (BF) 16 precision data results in excessively high costs. However, by using low-bit data for calculations, lossless learning for large-scale models of transformers can be achieved. Therefore, low-bit floating-point learning is the future trend in the training of large-scale models.

[0003] In the learning process of neural networks, in a mixed-precision calculation scenario, it is necessary to mutually convert floating-point data of different precisions. There is no error in the format conversion from low-precision floating-point data to high-precision floating-point data, while the format conversion from high-precision floating-point data to low-precision floating-point data includes a rounding operation performed on the high-precision floating-point data. As a result, conversion errors occur, affecting the learning accuracy of model learning.

Summary of the Invention

[0004] The embodiments of the present application provide a method and apparatus for precision conversion of floating-point data that reduce conversion errors during conversion from high-precision data to low-precision data.

[0005] To achieve the aforementioned objectives, the following technical solutions are applied in the embodiments of this application.

[0006] According to the first aspect, embodiments of the present application provide a method for converting the precision of floating-point data. The first floating-point data includes a first exponent field and a first mantissa field. The second floating-point data includes a second mantissa field. The precision of the first floating-point data is higher than that of the second floating-point data. The method includes determining the bit width of the second mantissa field based on the encoded value of the first exponential field, and determining the reserved encoded value and the discarded encoded value in the first mantissa field, wherein the reserved encoded value includes an encoded value that starts from the most significant bit in the first mantissa field and has the same bit width as the bit width of the second mantissa field, and if the encoded value of the first exponential field is greater than or equal to a first pre-set threshold, performing a rounding operation on the reserved encoded value based on the discarded encoded value that starts from the most significant bit and has the pre-set bit width to obtain the encoded value of the second mantissa field, and if the encoded value of the first exponential field is less than the first pre-set threshold, performing a rounding operation on the reserved encoded value based on the most significant bit of the discarded encoded value to obtain the encoded value of the second mantissa field.

[0007] Accordingly, high-precision floating-point data is converted to low-precision floating-point data according to the floating-point data precision conversion method provided in this embodiment of the present application. Performing rounding operations on the retained encoded value based on an encoded value where the most significant bit in the discarded encoded value is a pre-set bit width can be understood as a probabilistic rounding method, and performing rounding operations on the retained encoded value based on the most significant bit of the discarded encoded value can be understood as a rounding to the nearest integer method. In data format conversion, the choice between probabilistic rounding and rounding to the nearest integer method can be understood as a hybrid rounding method. If the encoded value of the first exponential field is greater than or equal to a first pre-set threshold, probabilistic rounding is used. If the encoded value of the first exponential field is less than the first pre-set threshold, near-near

[0008] In a possible design, rounding operations include carry-over and truncation operations, and obtaining the encoded value of the second mantissa field by performing rounding operations on the retained encoded value based on an encoded value that starts from the most significant bit in the discarded encoded value and has a pre-set bit width, includes performing a carry-over operation on the least significant bit of the retained encoded value and truncation operations on the discarded encoded value if the encoded value that starts from the most significant bit in the discarded encoded value and has a pre-set bit width is greater than or equal to a second pre-set threshold, and the encoded value obtained by carrying over the retained encoded value is the encoded value of the second mantissa field, or if the encoded value that starts from the most significant bit in the discarded encoded value and has a pre-set bit width is less than a second pre-set threshold, and truncation operations are performed on the discarded encoded value and the retained encoded value is the encoded value of the second mantissa field. The second pre-set threshold is an encoded value that starts from the least significant bit in the discarded encoded value and has a pre-set bit width.

[0009] In this design, in the probabilistic rounding scheme, the second pre-set threshold for comparison is an encoded value that starts from the least significant bit in the discard encoded value and has a bit width equal to the pre-set bit width. The second pre-set threshold is generated without an additional random number generator, and there is no random number generation performance bottleneck, so the efficiency of converting high-precision floating-point data to low-precision floating-point data is improved and hardware overhead is reduced.

[0010] In a possible design, rounding operations include carry-over and truncation operations, and obtaining the encoded value of the second mantissa field by performing rounding operations on the retained encoded value based on the most significant bit of the discarded encoded value includes, if the most significant bit of the discarded encoded value is greater than or equal to a third pre-set threshold, performing a carry-over operation on the least significant bit of the retained encoded value and truncating the discarded encoded value, wherein the encoded value obtained by carrying over the retained encoded value is the encoded value of the second mantissa field, or, if the most significant bit of the discarded encoded value is less than a third pre-set threshold, performing a truncation operation on the discarded encoded value, wherein the retained encoded value is the encoded value of the second mantissa field.

[0011] In this design, the third pre-set threshold may be 0 or 1, and the most significant bit of the discarded encoded value is compared to the third pre-set threshold. This belongs to the rounding scheme. In addition to the rounding scheme, rounding to the nearest even, rounding to the nearest odd, etc., may be included. However, compared to other rounding schemes, the rounding scheme has a smaller hardware implementation, lower power consumption overhead, and higher data resolution.

[0012] In a possible design, a first pre-set threshold is determined by traversing multiple first floating-point data points.

[0013] In this design, the first pre-set threshold is an adjustable parameter, and the accuracy of data format conversion can be improved by setting an appropriate value for the first pre-set threshold.

[0014] In a possible design, the first floating-point data further includes a sign field, and the second floating-point data further includes a sign field, a prefix code field, and a second exponent field. The prefix code field indicates the bit width of the second exponent field, and before determining the bit width of the second mantissa field based on the encoded value of the first exponent field, the method further includes determining the bit width of the prefix code field, the encoded value of the prefix code field, the bit width of the second exponent field, and the encoded value of the second exponent field based on the encoded value of the first exponent field.

[0015] In this design, during data format conversion, the sign field of the second floating-point data may be obtained based on the sign field of the first floating-point data, the prefix code field and second exponent field of the second floating-point data may be obtained based on the first exponent field of the first floating-point data, and the second mantissa field of the second floating-point data may be obtained based on the first mantissa field of the first floating-point data. In the second floating-point data, the precision or bit width of the mantissa field of the second exponent field can be effectively improved because the second exponent field is indicated by a prefix code field with a shorter bit width. Furthermore, since the second floating-point data that provides precision of only one bit mantissa represents a wide value range, an effective balance can be achieved between the bit width, range, and precision of the second floating-point data. In addition, a prefix code coding scheme may be used for the prefix code field, which occupies a small bit width and is convenient for parsing the second exponent field and second mantissa field.

[0016] According to a second aspect, embodiments of the present application provide a precision conversion device for floating-point data. The first floating-point data includes a first exponent field and a first mantissa field. The second floating-point data includes a second mantissa field. The precision of the first floating-point data is higher than that of the second floating-point data. The device includes a bit width calculation unit configured to determine the bit width of the second mantissa field based on the encoded value of the first exponential field, and a mantissa field calculation unit configured to determine a reserved encoded value and a discarded encoded value in the first mantissa field, wherein the reserved encoded value includes an encoded value that starts from the most significant bit in the first mantissa field and has the same bit width as the bit width of the second mantissa field, and a rounding calculation unit that, when the encoded value of the first exponential field is greater than or equal to a first pre-set threshold, performs a rounding operation on the reserved encoded value based on an encoded value that starts from the most significant bit in the discarded encoded value and has the pre-set bit width, to obtain the encoded value of the second mantissa field, wherein the rounding calculation unit is further configured to, when the encoded value of the first exponential field is less than a first pre-set threshold, perform a rounding operation on the reserved encoded value based on the most significant bit of the discarded encoded value, to obtain the encoded value of the second mantissa field.

[0017] For the advantageous effects of the second aspect, please refer to the description of the first aspect.

[0018] In possible designs, rounding operations include carry-over and truncation operations. The rounding unit is further configured such that, if the encoded value in the discarded encoded value, starting from the most significant bit and having a pre-set bit width, is greater than or equal to a second pre-set threshold, it performs a carry-over operation on the least significant bit of the retained encoded value and a truncation operation on the discarded encoded value, and the encoded value obtained by carrying over the retained encoded value is the encoded value of the second mantissa field, or if the encoded value in the discarded encoded value, starting from the most significant bit and having a pre-set bit width, is less than a second pre-set threshold, it performs a truncation operation on the discarded encoded value, and the retained encoded value is the encoded value of the second mantissa field. The second pre-set threshold is the encoded value in the discarded encoded value, starting from the least significant bit and having a pre-set bit width.

[0019] In a possible design, the rounding operation includes carry-over and truncation operations, and the rounding unit is further configured such that if the most significant bit of the discarded coded value is greater than or equal to a third pre-set threshold, it performs a carry-over operation on the least significant bit of the retained coded value and a truncation operation on the discarded coded value, and the coded value obtained by carrying over the retained coded value is the coded value of the second mantissa field, or if the most significant bit of the discarded coded value is less than a third pre-set threshold, it performs a truncation operation on the discarded coded value and the retained coded value is the coded value of the second mantissa field.

[0020] In a possible design, a first pre-set threshold is determined by traversing multiple first floating-point data points.

[0021] In a possible design, the first floating-point data further includes a sign field, and the second floating-point data further includes a sign field, a prefix code field, and a second exponent field. The prefix code field indicates the bit width of the second exponent field, and the bit width calculation unit is further configured to determine the bit width of the prefix code field, the encoded value of the prefix code field, the bit width of the second exponent field, and the encoded value of the second exponent field, based on the encoded value of the first exponent field.

[0022] In accordance with a third aspect, an embodiment of the present application provides a floating-point data precision conversion device including a processor and memory. The memory stores computer instructions, and after executing the computer instructions, the processor performs a floating-point data precision conversion method in any one of the aforementioned aspects and possible embodiments.

[0023] In accordance with the fourth aspect, embodiments of the present application provide a computer-readable storage medium containing computer instructions. When the computer instructions are executed on an electronic device, the electronic device can perform a method for converting the precision of floating-point data in any one of the aforementioned aspects and possible embodiments.

[0024] In accordance with the fifth aspect, embodiments of the present application provide a computer program product. When the computer program product is executed on a computer or processor, the computer or processor can perform a method for converting the precision of floating-point data in any one of the aforementioned aspects and possible embodiments.

[0025] In accordance with the sixth aspect, embodiments of the present application provide a system. The system may include at least one electronic device and a wireless access device in any possible implementation of any one of the aforementioned aspects. The electronic device and the wireless access device may perform a method for converting the precision of floating-point data in any one of the aforementioned aspects and possible implementations.

[0026] Any floating-point data precision conversion device, computer-readable storage medium, computer program product, etc. provided above can be used in the corresponding method provided above. Therefore, for the advantageous effects achievable by a floating-point data precision conversion device, computer-readable storage medium, or computer program product, refer to the advantageous effects in the corresponding method. Details are not described here again.

[0027] These aspects or other aspects in the present application will be more concise and understandable in the following description.

Brief Description of the Drawings

[0028] [Figure 1] It is a diagram of a data structure according to an embodiment of the present application. [Figure 2] It is a diagram of the distribution of exponent field - mantissa field bit widths according to an embodiment of the present application. [Figure 3] It is a diagram of a system or device in which a floating-point data precision conversion device according to an embodiment of the present application is used. [Figure 4] It is a diagram of the structure of a SoC according to an embodiment of the present application. [Figure 5] It is a flowchart of a floating-point data precision conversion method according to an embodiment of the present application. [Figure 6] It is a diagram of the mantissa field of FP32 data converted to HiFloat8 data in the SR rounding method according to an embodiment of the present application. [Figure 7] It is a diagram of the mantissa field of FP16 data converted to HiFloat8 data in the SR rounding method according to an embodiment of the present application. [Figure 8] It is a diagram of the distribution of the hybrid rounding method according to an embodiment of the present application. [Figure 9] It is a flowchart of neural network learning according to an embodiment of the present application. [Figure 10] It is another flowchart of neural network learning according to an embodiment of the present application. [Figure 11] This is another flowchart of neural network learning according to an embodiment of the present invention. [Figure 12] This is a diagram showing the configuration of a floating-point data precision conversion device according to an embodiment of the present invention. [Modes for carrying out the invention]

[0029] To facilitate understanding, several concepts related to the embodiments of this application will be explained using examples for reference. Details are as follows.

[0030] The neural network learning process primarily involves forward computation, backward computation, and weight updates. Computational modes in the learning process include general matrix multiplication (GEMM) and non-general matrix multiplication. Layers corresponding to general matrix multiplication can be called matrix multiplication computation layers, while layers corresponding to non-general matrix multiplication can be called non-matrix multiplication computation layers. Specifically, general matrix multiplication includes convolution, transposed convolution, matrix multiplication (matmul), and batch matrix multiplication (batch matmul). Non-general matrix multiplication includes activation functions, normalization functions, optimization computation, gradient updates, etc. Activation functions include sigmoid, tanh, and relu. Normalization functions include batch normalization, layer normalization, instance normalization, etc.

[0031] Common matrix multiplication can be performed using FP16, BF16, or low-precision data, but non-common matrix multiplication requires the use of high-precision data such as FP32. FP16 is sometimes called half-precision floating-point, BF16 is sometimes called 16-bit brain floating-point, and FP32 is sometimes called full-precision float. Figure 1 shows a diagram of the data structure. Specifically, FP16 contains 16 bits, with the most significant bit being the sign field, the middle 5 bits being the exponent field, and the remaining 10 bits being the mantissa field. The mantissa field represents a decimal number. BF16 also contains 16 bits, with the most significant bit being the sign field, the middle 8 bits being the exponent field, and the remaining 7 bits being the mantissa field. FP32 contains 32 bits, with the most significant bit being the sign field, the middle 8 bits being the exponent field, and the remaining 23 bits being the mantissa field.

[0032] The technical solutions in the embodiments of this application will be described below with reference to the accompanying drawings. In the descriptions of the embodiments of this application, " / " means "or" unless otherwise specified. For example, A / B may represent A or B. In this specification, "and / or" indicates only the association relationship described for related objects, and indicates that three relationships may exist. For example, A and / or B may represent the following three relationships: A only exists, both A and B exist, and B only exists. Furthermore, in the descriptions of the embodiments of this application, "multiple" means two or more.

[0033] The terms “first” and “second” used below are for descriptive purposes only and should not be understood as indicating or implying relative importance, or as implicitly indicating the number of technical features described. Therefore, features limited by “first” or “second” may explicitly or implicitly include one or more features. In the description of embodiments, “multiple” means two or more unless otherwise specified.

[0034] Currently, neural network training is facing increasing demands on computational output. Specifically, the neural network training process initially requires 100 petaflops (1 petaflop is equivalent to 10 trillion mathematical operations per second). In current transformer models, the neural network training process requires 1 billion petaflops. The demands on computational output have increased 10 million times. Therefore, to reduce power consumption during neural network training, two low-precision floating-point data formats, FP8(E5M2) and FP8(E4M3), have been defined in conventional technology. The FP8(E5M2) exponent field has 5 bits, and the FP8(E5M2) mantissa field has 2 bits. The FP8(E4M3) exponent field has 4 bits, and the FP8(E4M3) mantissa field has 3 bits. In the neural network learning process, which includes forward computation, backward computation, and weight calculation, mixed precision is used for training, with two FP8 data formats used for computation in GEMM and FP32 or FP16 used for computation in non-GEMM. In comparing a typical matrix multiplication calculation performed using data in the two aforementioned low-precision floating-point data formats with a typical matrix multiplication calculation using FP16 / BF16 data, it can be understood that the amount of data required for a typical matrix multiplication calculation is halved because the total bit width of the two low-precision floating-point data formats is half the total bit width of FP16 / BF16, thereby reducing the power consumption of the neural network chip.

[0035] However, data precision loss occurs during data format conversion when high-precision floating-point data is converted to the two aforementioned low-precision floating-point data formats for common matrix multiplication calculations. Subsequently, when the data is converted to high-precision data for uncommon matrix multiplication calculations, for example, when the data is converted to the FP16 / BF16 data format, the training accuracy of the neural network decreases. To reduce data precision loss, a scaling operation is introduced into the training process. However, after the scaling operation, distribution statistics need to be collected regarding the data generated by the tensor core, which increases the power consumption of the neural network chip. Furthermore, the two types of low-precision floating-point data have different performance in terms of precision and dynamic range. The user needs to select one data format from the two types of low-precision floating-point data for neural network training. Currently, the method does not allow the user to make a selection, resulting in poor user experience and generalizability.

[0036] In another neural network learning method, block floating-point is defined for representing low-precision data, and mixed precision is used during neural network training, thereby reducing the power consumption of the neural network chip. Specifically, during general matrix multiplication calculations, the data is converted to block floating-point data format before the calculation, and during non-general matrix multiplication calculations, the data is converted to FP32 or FP16 data format before the calculation. While converting the data to block floating-point data format, high-precision data is first divided into multiple blocks, the data distribution in each block is then counted, and the data within each block is finally divided into a common exponent field and a sign field and mantissa field for each data, based on the data distribution. In this case, since the data within each block has a common exponent, the total bit width of each data within the block is reduced, and thus, using data in block floating-point data format for training can reduce the power consumption of the neural network chip.

[0037] However, when data in block floating-point data format is used for training, the block floating-point data format limits the range of data representation, resulting in a loss of data precision and lowering the training accuracy of the neural network. Furthermore, different computational layers of the neural network have different block partitioning schemes, making the algorithmic procedures more complex. In addition, quantization (quant) operations must be introduced before general matrix multiplication calculations, and dequantization (dequant) operations must be introduced after general matrix multiplication calculations, and statistics must be collected for data analysis. This affects the performance of neural network training.

[0038] Accordingly, embodiments of the present invention provide a method for converting the precision of floating-point data. The method relates to data format conversion between first floating-point data and second floating-point data. The precision of the first floating-point data is higher than that of the second floating-point data. The method employs a hybrid rounding scheme. Specifically, a probabilistic rounding scheme is used when the encoded value of the first exponential field is greater than or equal to a first pre-set threshold, and a rounding scheme is used when the encoded value of the first exponential field is less than the first pre-set threshold. Different rounding schemes are provided to reduce conversion errors during data format conversion, improve data conversion efficiency, and improve the learning accuracy of model training.

[0039] The method can be applied to the field of AI. The floating-point data precision conversion method can be applied to chips such as central processing units (CPUs), graphics processing units (GPUs), tensor processing units (TPUs), and neural network processing units (NPUs).

[0040] Specifically, the second floating-point data provided in the embodiments of the present invention may be HiFloat8 data. As shown in Table 1, Table 1 shows the coding scheme for HiFloat8 data. [Table 1]

[0041] 8 is the total bit width of the HiFloat8 data, and the bit width of the mantissa field can be changed. The sign field occupies 1 bit. 0 represents a positive number, and 1 represents a negative number. Alternatively, 1 represents a negative number, and 0 represents a positive number. The prefix code field occupies 2 or 3 bits, and the prefix code field can represent five different pieces of information, and the value of D may be 0, 1, 2, 3, or 4. The bit width of the exponent field changes depending on the value of D, and the mantissa field occupies the remaining bit width. For the prefix code field, integer coding may be used, in which case D is a fixed value. Alternatively for the prefix code field, prefix code coding may be used, in which case D is a finite set of values. In prefix code coding, 2 bits are used to encode the values ​​2, 3, and 4, and 3 bits are used to encode the values ​​0 and 1. The coding scheme for prefix code fields is shown in Table 2. [Table 2]

[0042] Table 2 shows that when the point bit field is 2 bits, the value "4" can be encoded using "11", the value "3" can be encoded using "10", and the value "2" can be encoded using "01". When the point bit field is 3 bits, the value "1" can be encoded using "001", and the value "0" can be encoded using "000". The coding schemes shown in Table 2 are merely illustrative examples and do not constitute a limitation of this embodiment of the present application.

[0043] Furthermore, the formula for the conversion between HiFloat8 data and the decimal value (X) provided in this embodiment of the present application is:

number

[0044] Ec is the center of exponential symmetry and also the bias in FP32 data.

[0045] If D is 0, it indicates that the value of the exponential field is 0. If D is not 0, the signed magnitude value coding is used for the exponential field. Specifically, with the true form (TF) following the sign bit, the code for the exponential field is Ei={Se,1'b1,TF[2:end]}, where Se is the sign bit of the exponential field. If the most significant bit 1'b1 of TF is hidden and not stored, the coded value of the exponential field is Es={Se,TF[2:end]}. The coded value of the exponential field in decimal is Ev=Ei+Ec.

[0046] HiFloat(N,5,Ec) may be configured to be HiFloat(8,5,0), abbreviated as HiFi8, or other configurations may exist. The distribution of HiFloat8 encoded values ​​is shown in Table 3. [Table 3]

[0047] Referring to Tables 1 and 2, as shown in Table 3, when D=0, the bit width of the mantissa field is 8-4-0=4. When D=1, the bit width of the mantissa field is 8-4-1=3. When D=2, the bit width of the mantissa field is 8-3-2=3. When D=3, the bit width of the mantissa field is 8-3-3=2. When D=4, the bit width of the mantissa field is 8-3-4=1. When the bit width of the exponential field is smaller (i.e., the value range is smaller), the bit width occupied by the mantissa field is larger, and the value precision is higher. When the bit width of the exponential field is larger (i.e., the value range is larger), the bit width occupied by the mantissa field is smaller, and the value precision is lower.

[0048] Furthermore, Figure 2 shows the distribution of the exponential field-mantissa field bit widths according to the embodiment of the present application. From Figure 2, it can be seen that the smaller the absolute value of the exponential field, the larger the bit width of the mantissa field. Therefore, the second floating-point data can also be called tapered low-precision floating-point data. Moreover, since tapered low-precision floating-point data can take into account both the dynamic range and data precision of the data, it is possible to reduce conversion errors during the conversion from high-precision data to a low-precision data format and improve learning accuracy.

[0049] In some possible implementations, in addition to the normalized representation described above, the floating-point value X can be chosen to represent various special values ​​through user-defined settings.

[0050] For example, when S=0, D=4, Es=4'b1111=-15, and M=1'b0, X=0 (zero); when S=1, D=4, Es=4'b1111=-15, and M=1'b0, X can represent a value other than a number (not a number, NaN); and when D=4, Es=4'b0111=15, and M=1'b1, X=positive or negative infinity (±∞).

[0051] In the scenario described above, the floating-point data precision conversion method and apparatus in this application may be used in different systems or devices, for example, in the floating-point data precision conversion apparatus 30 shown in Figure 3. Figure 3 is a diagram of a system or device in which the floating-point data precision conversion apparatus is used according to an embodiment of this application. The floating-point data precision conversion apparatus may be a terminal, for example, a server 31, a mobile phone terminal 32, a tablet computer 33, a notebook computer 34, an augmented reality (AR) device (not shown in Figure 3), a virtual reality (VR) device (not shown in Figure 3), or an in-vehicle terminal (not shown in Figure 3). The floating-point data precision conversion method provided in this application may be applied to scenarios related to mixed-precision calculations, such as CPUs, high-performance computing (HPC), and AI, and in the floating-point data precision conversion apparatus 30, for example, a scalar calculation unit, a vector calculation unit, a matrix calculation unit, and a tensor check unit.

[0052] In some embodiments, the floating-point data precision converter provided in this application may be a chip. For example, the chip is a system-on-chip (SoC). Figure 4 is a diagram of the structure of an SoC according to an embodiment of this application. The SoC includes a processor. The processor may be a single-core or multi-core processor, memory, an input / output (I / O) interface, etc. After loading data and an application program into memory, the processor may process the data and perform, for example, the calculation processing described in this application. For example, if the data is FP32 data, the encoded value of the second mantissa field in the second floating-point data may be determined by reading the encoded value of the first exponent field of the FP32 data.

[0053] The method applies to the aforementioned system or device. Below, the procedure for the precision conversion method of floating-point data provided in the embodiments of this application is described.

[0054] Embodiments of the present invention provide a method for converting the precision of floating-point data. Figure 5 is a flowchart of a method for converting the precision of floating-point data according to embodiments of the present invention. The method is applied to convert first floating-point data to second floating-point data. The first floating-point data may include a first exponent field and a first mantissa field, and the second floating-point data may include a second mantissa field. The method includes the following procedure.

[0055] Step 501: The floating-point data precision converter determines the bit width of the second mantissa field based on the encoded value of the first exponent field.

[0056] For example, the precision of the first floating-point data may be higher than that of the second floating-point data, the first floating-point data may be FP32 data or FP16 data, and the second floating-point data may be HiFloat8 data.

[0057] During conversion, the bit width of the mantissa field of the HiFloat8 data is variable. In other words, the bit width of the second mantissa field is variable, ranging from 1 to 4. It can be understood that the larger the bit width of the mantissa field, the higher the precision of the HiFloat8 data.

[0058] For example, the first floating-point data is FP32 data. The encoded value of the first exponent field is 8'b01111100, which represents 124 in decimal. If the bias within the FP32 data (where the bias is 127 for FP32 data) is removed, then the first exponent field of the FP32 data is 2 to the power of -3. Referring to Tables 2 and 3, we can see that the bit width of the second mantissa field is 2.

[0059] Step 502: The floating-point data precision converter determines the retained and discarded coded values ​​in the first mantissa field, the retained coded values ​​including coded values ​​that start from the most significant bit in the first mantissa field and have a bit width equal to the bit width of the second mantissa field.

[0060] For example, the precision of first-order floating-point data is higher than that of second-order floating-point data, and the bit width of the first mantissa field of the first-order floating-point data is greater than the bit width of the second mantissa field of the second-order floating-point data. Therefore, when first-order floating-point data is converted to second-order floating-point data, the bit width of the second mantissa field of the second-order floating-point data is limited, and rounding is required for the encoded value of the first mantissa field. Encoded values ​​in the first mantissa field that start from the most significant bit and have the same bit width as the bit width of the second mantissa field are determined as reserved encoded values, and the remaining encoded values ​​in the first mantissa field other than the reserved encoded values ​​are determined as discarded encoded values.

[0061] The example where the first floating-point data is FP32 is still used. If the encoded value of the first mantissa field is 23'b01000000000000000000000, then the bit width of the second mantissa field is 2, and therefore the reserved encoded value is 2'b01.

[0062] Step 503: If the encoded value of the first exponential field is greater than or equal to the first pre-set threshold, the floating-point data precision converter performs a rounding operation on the retained encoded value based on the encoded value in the discarded encoded value, which starts from the most significant bit and has a pre-set bit width, to obtain the encoded value of the second mantissa field.

[0063] For example, a method of performing rounding operations on a retained coded value based on a coded value that starts from the most significant bit in the discard coded value and has a pre-set bit width can be understood as a stochastic rounding (SR) method. The pre-set bit width can be an integer from 1 to 14. A random number is introduced in the SR rounding method, and the rounding operation is performed on the retained coded value based on the result of comparing the random number with the coded value that starts from the most significant bit in the discard coded value and has a pre-set bit width. The random number in the SR rounding method is related to the discard coded value, no additional random number generator is required, and there is no performance bottleneck in random number generation. Therefore, the SR rounding method not only improves the efficiency of converting high-precision data to low-precision data, but also reduces hardware overhead.

[0064] Step 504: If the encoded value of the first exponent field is less than the first pre-set threshold, the floating-point data precision converter performs a rounding operation on the retained encoded value based on the most significant bit of the discarded encoded value to obtain the encoded value of the second mantissa field.

[0065] For example, a method of performing rounding operations on a retained encoded value based on the most significant bit of a discarded encoded value can be understood as round half away from zero (TA). In TA rounding, the most significant bit of the discarded encoded value may be compared to a pre-set threshold, and the rounding operation is performed on the retained encoded value based on the result of that comparison. Compared to other rounding methods, TA rounding has a smaller hardware implementation area, lower power consumption overhead, and higher data resolution.

[0066] Therefore, SR rounding and TA rounding can be understood as hybrid rounding (HR) methods. In hybrid rounding, SR rounding is used for the small proportion of two-sided data in the Gaussian distribution, i.e., the main data that affects the mean. For the larger proportion of intermediate data, TA rounding is used. Hybrid rounding can be applied to both FP32 and FP16 data. Compared to TA rounding or SR rounding, hybrid rounding provides better mean invariance and lower hardware overhead.

[0067] Optionally, rounding operations include carry-over and truncation operations, and step 503 may include, if the encoded value starting from the most significant bit in the discarded encoded value and having a pre-set bit width is greater than or equal to a second pre-set threshold, the floating-point data precision converter performs a carry-over operation on the least significant bit of the reserved encoded value and a truncation operation on the discarded encoded value, and the encoded value obtained by the carry-over performed on the reserved encoded value is the encoded value of the second mantissa field. If the encoded value starting from the most significant bit in the discarded encoded value and having a pre-set bit width is less than a second pre-set threshold, a truncation operation is performed on the discarded encoded value and the reserved encoded value is the encoded value of the second mantissa field. The second pre-set threshold is the encoded value starting from the least significant bit in the discarded encoded value and having a pre-set bit width.

[0068] For example, in the SR rounding scheme, the pre-set bit width may be an integer from 1 to 14. An example where the pre-set bit width is 14 is used. The second pre-set threshold may be an encoded value that starts from the least significant bit in the discarded encoded value and has a bit width of 14. In this case, the portion of the discarded encoded value used for comparison with the second pre-set threshold is an encoded value that starts from the most significant bit in the discarded encoded value and has a bit width of 14. An example where the encoded value of the first mantissa field is 23'b01000000000000000000000 is still used. In this case, the bit width of the second mantissa field is 2. In this case, the reserved coded value in the first mantissa field is 2'b01, the discarded coded value is 21'b000000000000000000000, the relevant portion of the discarded coded value is 14'b00000000000000, and the second pre-set threshold is 14'b00000000000000. Since the relevant portion of the discarded coded value is equal to the second pre-set threshold, a truncation operation is performed on the discarded coded value, and the coded value obtained by rounding up the reserved coded value is the coded value of the second mantissa field, i.e., the coded value of the second mantissa field is 2'b01.

[0069] In the example, Figure 6 is a diagram of the mantissa field of an FP32 converted to HiFloat8 data in an SR rounding scheme according to an embodiment of the present invention. The least significant bit (LSB) in the mantissa field of the FP32 data is selected to form a 2-bit second pre-set threshold T2 = {LSB, 1'b1}. The first 4 bits of the discarded coded value may be selected to form F2, that is, F2 is the retained coded value, and M is the retained coded value after rounding.

[0070] In another example, Figure 7 shows the mantissa field of FP16 converted to HiFloat8 data in an SR rounding scheme according to an embodiment of the present invention. The least significant bit (LSB) in the mantissa field of FP16 is selected to form a 2-bit second pre-set threshold T2 = {LSB, 1'b1}. The first 4 bits of the discarded coded value may be selected to form F2.

[0071] The SR rounding applicable to the mantissa field in Figures 6 and 7 is defined as M+1 if F2 ≥ T2, and M otherwise. In other words, if F2 is greater than or equal to T2, the round-up operation is performed on the reserved coded value. If F2 is less than T2, the truncation operation is performed on the discarded coded value.

[0072] In another implementation, any bit width in the first mantissa field of the first floating-point data is {a n ,1} or {negate(a n The first bit is used as a second pre-set threshold, as in {1'b0,1'b1}, where the negate operation represents the negation of 0 and 1, so negate(0)=1 and negate(1)=0. The discarded coded value portion in the first mantissa field is compared to the second pre-set threshold to obtain the SR rounding result. In the example, the pre-set bit width is 1 bit. If the most significant bit of the discarded coded value is 0, then {1'b0,1'b1}=0.25, and the truncation operation is performed on the discarded coded value. If the most significant bit of the discarded coded value is 1, then {1'b1,1'b1}=0.75, and the carry operation is performed on the least significant bit of the reserved coded value.

[0073] The error in single data points using the SR rounding method is 0.75 units (ulp) in the least significant digit, which is smaller than the 1 ulp error in standard stochastic rounding. Furthermore, the mean invariance of the SR rounding method is superior to that of standard stochastic rounding when the data is evenly distributed.

[0074] Optionally, rounding operations include carry-over and truncation operations, and step 504 may include, if the most significant bit of the discarded coded value is greater than or equal to a third pre-set threshold, the floating-point data precision converter performs a carry-over operation on the least significant bit of the reserved coded value and a truncation operation on the discarded coded value, and the coded value obtained by the carry-over of the reserved coded value is the coded value of the second mantissa field. If the most significant bit of the discarded coded value is less than a third pre-set threshold, a truncation operation is performed on the discarded coded value and the reserved coded value is the coded value of the second mantissa field.

[0075] For example, in the TA rounding method, the third pre-set threshold can be 1. In the example, if the most significant bit of the discarded coded value is 1, a carry operation is performed on the least significant bit of the retained coded value, and a truncation operation is performed on the discarded coded value. In another example, if the most significant bit of the discarded coded value is 0, a truncation operation is performed on the discarded coded value.

[0076] In the TA rounding method, the third pre-set threshold may alternatively be 0. If the most significant bit of the discarded coded value is greater than 0, a carry operation is performed on the least significant bit of the retained coded value, and a truncation operation is performed on the discarded coded value. The coded value obtained by performing the carry operation on the retained coded value is the coded value of the second mantissa field. If the most significant bit of the discarded coded value is 0 or less, a truncation operation is performed on the discarded coded value, and the retained coded value becomes the first coded value of the second mantissa field.

[0077] Optionally, a first pre-set threshold is determined by traversing multiple first floating-point data points.

[0078] For example, multiple first floating-point data are traversed, i.e., the encoded values ​​of different first exponential fields are traversed, thereby determining that the smallest conversion error is obtained when the first pre-set threshold is 4. Figure 8 is a diagram of the distribution of a hybrid rounding scheme according to an embodiment of the present invention. The exponential value of HiFloat8 is E=[-15,15], where abs(E)=[0,15]. The TA rounding scheme is used when E≧4. The SR rounding scheme is used when E<4.

[0079] Optionally, the first floating-point data further includes a sign field, and the second floating-point data further includes a sign field, a prefix code field, and a second exponent field. The prefix code field indicates the bit width of the second exponent field. The method further includes determining the bit width of the prefix code field, the encoded value of the prefix code field, the bit width of the second exponent field, and the encoded value of the second exponent field based on the encoded value of the first exponent field. For example, in data format conversion, the positive and negative values ​​of the data remain unchanged. Specifically, the bit width and sign value of the sign fields of the first and second floating-point data are the same.

[0080] For the prefix code field and the second exponential field, the exponent value N of the first exponential field can be determined based on the encoded value of the first exponential field. See Table 1. The value of D can be determined based on the exponent value of the first exponential field. In the example, the first floating-point data is FP32 data. Assume that the encoded value of the first exponential field is 8'b01111100, which represents 124 in decimal. If the bias 127 of the FP32 data is removed, we obtain -3 in decimal. -3 is the exponent value N of the first exponential field, and by using the formula D=INT[log2|N|], we can determine that D is 2. By looking at Table 2, we can determine that the bit width of the prefix code field corresponding to 2 is 2, the first encoded value of the prefix code field is 01, and the bit width of the second exponential field is 2. Looking further at Table 3, if D is 2 and the exponent value of the first exponent field is -3, that is, if the exponent code bit Se is 1, then the bit width of the second exponent field is 2, and the encoded value determined for the second exponent field is 2'b11.

[0081] It can be understood that when a carry operation is performed on a reserved coded value, the reserved coded value may overflow. The execution device must first determine whether the reserved coded value obtained by the carry operation overflows. If the reserved coded value obtained by the carry operation overflows, 1 is added to the least significant bit of the coded value of the first exponent field to obtain a new coded value for the first exponent field. The execution device then determines the new bit width of the second exponent field and the new bit width of the prefix code field based on the new coded value of the first exponent field. If the new bit width of the prefix code field is different from the original bit width of the prefix code field, the new coded value of the prefix code field, the new coded value of the second exponent field, the new bit width of the second mantissa field, and the new coded value of the second mantissa field are determined based on the new coded value of the first exponent field. For the new bit width of the prefix code field to be the same as the original bit width of the prefix code field, it is determined whether the new bit width of the second exponent field is the same as the original bit width of the second exponent field. If the new bit width of the second exponential field is smaller than the original bit width of the second exponential field, 1 is added to the bit width of the reserved encoded value, resulting in the new bit width of the second mantissa field and the new encoded value of the second mantissa field. If the new bit width of the second exponential field is larger than the original bit width of the second exponential field, a truncation operation is performed on the least significant bit of the reserved encoded value, resulting in the new bit width of the second mantissa field and the new encoded value of the second mantissa field.

[0082] The floating-point data precision conversion method provided in the embodiments of the present invention can be applied to a neural network learning procedure. The neural network learning procedure includes initialization of model weight parameters, forward computation, backward computation, weight update procedures, and multi-machine, multi-card data communication procedures.

[0083] In the initialization procedure for model weight parameters, weights use a high-precision floating-point data format. Different initialization solutions are used for different application scenarios. For learning and pre-training processes starting from zero, high-precision floating-point data is used for random initialization. The randomization method is either FP16 mixed precision or FP32 precision. For retraining processes based on FP32 or FP16 mixed precision weights, the weight data obtained in the FP32 or FP16 mixed precision learning process is loaded directly. The initialization method for other parameters in the model, such as normalization layer parameters and optimization calculation parameters, is the same as the initialization method for weights during learning and retraining.

[0084] After the weight parameters are initialized, Figure 9 is a flowchart of neural network learning according to the embodiment of the present invention. L-1 represents the learning process corresponding to the matrix multiplication calculation layer before the first matrix multiplication calculation layer, and L+1 represents the learning process corresponding to the matrix multiplication calculation layer after the first matrix multiplication calculation layer. The learning processes of L-1 and L+1 are the same as the learning processes of the data matrix and weight matrix corresponding to the first matrix multiplication calculation layer.

[0085] In the forward calculation procedure, for GEMM operations in the first and intermediate layers of the network, FP32 or FP16 data must be converted to a tapered low-precision floating-point data format and input to the GEMM calculation unit, with FP32 or FP16 data being output. For the activation and normalization layers, FP32 or FP16 data is used for calculations. For the tail layers of the neural network, the FP32 or FP16 data type is consistently maintained. The specific procedure is as follows: Based on the data transformation matrix and weight transformation matrix of the first floating-point data format, a forward calculation is performed on the matrix multiplication calculation layer to obtain the first output transformation matrix in the second floating-point data format. A forward calculation performed on the first output transformation matrix yields the first non-matrix multiplication calculation layer, and the second output matrix in the first floating-point data format is obtained. The second output matrix is ​​used as the input matrix for the next calculation layer after the first non-matrix multiplication calculation layer when a forward calculation is performed.

[0086] In the back-calculation procedure, the back-procedure for tapered low-precision floating-point mixed-precision data is consistent with the back-procedure for FP16 learning. Automatic scaling is performed; that is, the loss is multiplied by an appropriate scaling value, and then back differentiation is performed. In the differentiation of the feature map and weights, the input to GEMM is tapered low-precision floating-point data. The specific procedure is as follows: The first output error gradient matrix in a second floating-point data format is obtained, and this first output error gradient matrix is ​​used to update the parameters corresponding to the first non-matrix multiplication calculation layer. The first non-matrix multiplication calculation layer is backpropagated based on the first output error gradient matrix to obtain the second output error gradient matrix in a first floating-point data format. The second output error gradient matrix is ​​transformed into the second output error gradient transformation matrix in a second floating-point data format, and the first matrix multiplication calculation layer is backpropagated based on the second output error gradient transformation matrix and the transpose of the weight transformation matrix to obtain the third output error gradient transformation matrix in a first floating-point data format. The third output error gradient transformation matrix is ​​used to update the parameters of the first matrix multiplication calculation layer corresponding to the previous calculation layer during the forward computation of the neural network.

[0087] The weight gradient calculation procedure may involve inputting the second output error gradient transformation matrix and the data transformation matrix into the first matrix multiplication calculation layer to obtain weight gradient transformation data in the third data format, and updating the weight matrix based on the weight gradient transformation data.

[0088] In possible embodiments, as shown in Figure 9, the weight matrix and other parameters can be converted into data in a high-precision data format, and the data is backed up and stored in a local storage device. For example, the weight matrix in high-precision data format is stored in the first storage unit w-master, the state parameters of the optimization algorithm are stored in the second storage unit momentum, and the other parameters are stored in the third storage unit other states.

[0089] Furthermore, large-scale model training is typically performed using a multi-machine approach, including data parallelism, model parallelism, pipeline parallelism, and combinations of these three parallelisms. The multi-machine, multi-card training method requires data communication between cards, and communication using tapered low-precision floating-point data can effectively solve the transmission bandwidth problem.

[0090] The first floating-point data can be converted to second floating-point data using various rounding methods in forward and backward calculations. This is not limited to the embodiments of the present invention.

[0091] Example 1: As shown in Figure 9, a hybrid rounding method may be used for forward calculations, and a TA / SR method may be used for backward calculations.

[0092] Example 2: Figure 10 is another flowchart of neural network learning according to an embodiment of the present invention. The TA / SR method may be used for forward computation, and the hybrid rounding method may be used for backward computation.

[0093] Example 3: Figure 11 is another flowchart of neural network learning according to an embodiment of the present invention. A hybrid rounding scheme may be used for forward computation, and a hybrid rounding scheme may be used for backward computation.

[0094] Accordingly, according to the floating-point data precision conversion method provided in the embodiments of this application, learning precision consistent with mixed precision of FP32 or FP16 can be achieved in artificial intelligence network models such as convolutional neural networks or transformer models. In two-sided mode (where the hybrid rounding scheme is used for both forward and backward calculations), the average precision is higher than in one-sided mode (where the hybrid rounding scheme is used for either forward or backward calculations).

[0095] To implement the functions described herein, it may be understood that the electronic device includes corresponding hardware and / or software modules for performing each function. Referring to the example algorithmic steps described in the embodiments disclosed herein, the application may be implemented in hardware or in combination of hardware and computer software. Whether the functions are performed by hardware or by hardware driven by computer software depends on the specific application and design constraints of the technical solution. Those skilled in the art may implement the described functions using different methods for specific applications by referring to the embodiments, but implementation should not be considered to exceed the scope of the application.

[0096] In the embodiment, the electronic device may be divided into functional modules based on the example of the method described above. For example, each functional module may be divided based on each corresponding function, or two or more functions may be integrated into a single processing module. The integrated module may be implemented in hardware form. Note that the module division in the embodiment is just one example and is merely a logical functional division. In actual implementation, other division methods may exist.

[0097] When each functional module is obtained by division based on its corresponding function, Figure 12 is a possible diagram of the configuration of the floating-point data precision converter 1200 in the embodiment described above. As shown in Figure 12, the floating-point data precision converter 1200 may include a bit width calculation unit 1201, a mantissa field calculation unit 1202, and a rounding operation unit 1203.

[0098] The bit width calculation unit 1201 may be configured to support the floating-point data precision converter 1200 in performing step 501, etc., and / or may be used in other processes of the technology described herein.

[0099] The mantissa field calculation unit 1202 may be configured to support the floating-point data precision converter 1200 in performing step 502, etc., and / or may be used in other processes of the technology described herein.

[0100] The rounding unit 1203 may be configured to support the floating-point data precision converter 1200 in performing steps 503, 504, and / or may be used in other processes of the technology described herein.

[0101] Furthermore, all relevant details of the steps in the embodiments of the method described above may be described in the functional description of the corresponding functional module. Details are not described again here.

[0102] Since the floating-point data precision conversion device 1200 provided in this application is configured to perform the floating-point data precision conversion method described above, it can achieve the same effects as the method described above.

[0103] When an integrated unit is used, the floating-point data precision converter 1200 may include a processing module, a storage module, and a communication module. The processing module may be configured to control and manage the operation of the floating-point data precision converter 1200, for example, to support the floating-point data precision converter 1200 in performing steps performed by the bit width calculation unit 1201, the mantissa field calculation unit 1202, and the rounding calculation unit 1203. The storage module may be configured to support the floating-point data precision converter 1200 in storing program code, data, etc. The communication module may be configured to support the floating-point data precision converter 1200 in communicating with other devices, for example, with a wireless access device.

[0104] The processing module may be a processor or a controller. The processor may implement or run various exemplary logic blocks, modules, and circuits described with reference to what is disclosed herein. Alternatively, the processor may be a combination for implementing computing functions, for example, a combination including one or more microprocessors, or a combination of a digital signal processor (DSP) and a microprocessor. The storage module may be memory. The communication module may specifically be a device such as a radio frequency circuit, a Bluetooth chip, or a Wi-Fi chip that interacts with other electronic devices.

[0105] Embodiments of the present invention further provide an electronic device comprising one or more processors and one or more memories. The one or more memories are coupled to one or more processors. The one or more memories are configured to store computer program code, which includes computer instructions. When one or more processors execute computer instructions, the electronic device can perform the aforementioned related method steps to implement the floating-point data precision conversion method of the above embodiments.

[0106] Embodiments of the present invention further provide a computer storage medium that stores computer instructions. When a computer instruction is executed on an electronic device, the electronic device can perform the relevant method steps to implement the floating-point data precision conversion method in the embodiments described above.

[0107] Embodiments of the present invention further provide a computer program product. When the computer program product is executed on a computer, the computer can perform the aforementioned related steps to implement the floating-point data precision conversion method in the embodiments described above.

[0108] Furthermore, embodiments of the present application further provide a device, which may specifically be a chip, component, or module. The device may include a connected processor and memory. The memory is configured to store computer executable instructions, and when the device is operating, the processor may execute the computer executable instructions stored in the memory, enabling the chip to perform the floating-point data precision conversion method performed by the electronic device in the embodiments of the method described above.

[0109] The electronic devices, computer storage media, computer program products, or chips provided in the embodiments are configured to perform the corresponding methods provided above. Therefore, for the advantageous effects that the electronic devices, computer storage media, computer program products, or chips can achieve, please refer to the advantageous effects in the corresponding methods provided above. Further details are not provided here.

[0110] Based on the description of the implementation described above, a person skilled in the art will understand that, for convenience and for the sake of conciseness, the division into functional modules described above is used merely as an illustrative example. In actual applications, the functions described above may be assigned to different functional modules and implemented according to the requirements. In other words, the internal structure of the device is divided into different functional modules to implement all or some of the functions described above.

[0111] It should be understood that in some embodiments provided herein, the disclosed apparatus and methods may be carried out in other ways. For example, the embodiments of the apparatus described are merely examples. For example, division into units or modularization is merely a logical functional division, and in actual implementation, there may be other divisions. For example, multiple units or components may be coupled or integrated into other apparatuses, or some features may be ignored or not performed. Furthermore, the mutual coupling or direct coupling or communication connection indicated or discussed may be carried out through some interface. Indirect coupling or communication connection between apparatuses or units may be carried out electronically, mechanically, or in other forms.

[0112] Units described as separate parts may or may not be physically separate, and the parts shown as units may be one or more physical units, which may be located in one place or distributed in different places. Some or all of the units may be selected based on the actual requirements to achieve the objectives of the solution of the embodiment.

[0113] Furthermore, the functional units in the embodiments of the present invention may be integrated into a single processing unit, each unit may exist physically independently, or two or more units may be integrated into a single unit. The integrated unit may be implemented in hardware form or in the form of a software functional unit.

[0114] When an integrated unit is implemented in the form of a software functional unit and sold or used as a separate product, the integrated unit may be stored in a readable storage medium. Based on this understanding, the technical solution in the embodiments of the present application may be implemented essentially, or in part with respect to related technology, or all or part of the technical solution may be implemented in the form of a software product. The software product is stored in a storage medium and includes several instructions for instructing a device (which may be a single-chip microprocessor, chip, etc.) or processor to perform all or part of the steps of the method described in the embodiments of the present application. The storage medium includes a variety of media capable of storing program code, such as a USB flash drive, a removable hard disk, read-only memory (ROM), random access memory (RAM), a magnetic disk, or an optical disk.

[0115] The above description merely illustrates a specific implementation of the present application and is not intended to limit the scope of protection. Any modification or substitution that a person skilled in the art could easily conceive within the technical scope disclosed herein should fall within the scope of protection. Accordingly, the scope of protection of this application should be subject to the scope of protection of the claims.

[0116] This application claims priority to Chinese Patent Application No. 202310238789.3, filed with the China National Intellectual Property Administration on March 3, 2023, with the title of the invention being "FLOATING-POINT DATA PRECISION CONVERSION METHOD AND APPRATUS," the full text of which is incorporated herein by reference.

Claims

1. A method for converting the precision of floating-point data, In the method, the first floating-point data includes a first exponent field and a first mantissa field, the second floating-point data includes a second mantissa field, and the precision of the first floating-point data is higher than the precision of the second floating-point data, The bit width of the second mantissa field is determined based on the encoded value of the first exponential field, The process involves determining the reserved and discarded coded values ​​within the first mantissa field, wherein the reserved coded values ​​include coded values ​​that start from the most significant bit in the first mantissa field and have a bit width equal to the bit width of the second mantissa field. If the encoded value of the first exponential field is greater than or equal to a first pre-set threshold, rounding is performed on the retained encoded value based on the encoded value in the discarded encoded value, which starts from the most significant bit and has a pre-set bit width, to obtain the encoded value of the second mantissa field, or If the encoded value of the first exponential field is smaller than the first pre-set threshold, rounding is performed on the retained encoded value based on the most significant bit of the discarded encoded value to obtain the encoded value of the second mantissa field. A method of having.

2. The aforementioned rounding operation includes rounding up and rounding down, Based on the discarded coded value, starting from the most significant bit and having a pre-set bit width, a rounding operation is performed on the retained coded value to obtain the coded value of the second mantissa field. If the coded value, which starts from the most significant bit in the discard coded value and has a pre-set bit width, is greater than or equal to a second pre-set threshold, then a carry-up operation is performed on the least significant bit of the retained coded value, a truncation operation is performed on the discard coded value, and the coded value obtained by the carry-up of the retained coded value is the coded value of the second mantissa field, or If the discarded coded value, starting from the most significant bit and having a pre-set bit width, is smaller than the second pre-set threshold, a truncation operation is performed on the discarded coded value, and the retained coded value is the coded value of the second mantissa field. The second pre-set threshold is an encoded value in the discard encoded value, starting from the least significant bit and having a bit width equal to the pre-set bit width. The method according to claim 1.

3. The aforementioned rounding operation includes rounding up and rounding down, Performing a rounding operation on the reserved coded value based on the most significant bit of the discard coded value to obtain the coded value of the second mantissa field is: If the most significant bit of the discarded coded value is greater than or equal to a third pre-set threshold, a carry-up operation is performed on the least significant bit of the retained coded value, a truncation operation is performed on the discarded coded value, and the coded value obtained by the carry-up of the retained coded value is the coded value of the second mantissa field, or If the most significant bit of the discarded coding value is smaller than the third pre-set threshold, a truncation operation is performed on the discarded coding value, including the fact that the retained coding value is the coding value of the second mantissa field. The method according to claim 1.

4. The first pre-set threshold is determined by traversing a plurality of first floating-point data. The method according to any one of claims 1 to 3.

5. The first floating-point data further includes a sign field, the second floating-point data further includes the sign field, a prefix code field, and a second exponent field, the prefix code field indicating the bit width of the second exponent field, Before determining the bit width of the second mantissa field based on the encoded value of the first exponential field, the method: The method further comprises determining the bit width of the prefix code field, the encoded value of the prefix code field, the bit width of the second exponential field, and the encoded value of the second exponential field based on the encoded value of the first exponential field. The method according to claim 1.

6. A device for converting the precision of floating-point data, In the apparatus, where the first floating-point data includes a first exponent field and a first mantissa field, the second floating-point data includes a second mantissa field, and the precision of the first floating-point data is higher than the precision of the second floating-point data, A bit width calculation unit configured to determine the bit width of the second mantissa field based on the encoded value of the first exponential field, A mantissa field calculation unit configured to determine the reserved coded value and the discarded coded value in the first mantissa field, wherein the reserved coded value includes a coded value that starts from the most significant bit in the first mantissa field and has the same bit width as the bit width of the second mantissa field, A rounding unit that, when the encoded value of the first exponential field is greater than or equal to a first pre-set threshold, performs a rounding operation on the retained encoded value based on the encoded value which starts from the most significant bit in the discarded encoded value and has a pre-set bit width, in order to obtain the encoded value of the second mantissa field. It has, The rounding unit is further configured to perform a rounding operation on the reserved coded value based on the most significant bit of the discard coded value when the coded value of the first exponential field is smaller than the first pre-set threshold, in order to obtain the coded value of the second mantissa field. Device.

7. The aforementioned rounding operation includes rounding up and rounding down, The rounding unit described above, If the coded value, which starts from the most significant bit in the discard coded value and has a bit width set in advance, is greater than or equal to a second set threshold, then a carry operation is performed on the least significant bit of the retained coded value, a truncation operation is performed on the discard coded value, and the coded value obtained by the carry operation of the retained coded value is the coded value of the second mantissa field, or If the discarded coded value, starting from the most significant bit and having a pre-set bit width, is smaller than the second pre-set threshold, a truncation operation is performed on the discarded coded value, and the retained coded value is the coded value of the second mantissa field. It is further structured as follows: The second pre-set threshold is an encoded value in the discard encoded value, starting from the least significant bit and having a bit width equal to the pre-set bit width. The apparatus according to claim 6.

8. The aforementioned rounding operation includes rounding up and rounding down, The rounding unit described above, If the most significant bit of the discarded coded value is greater than or equal to a third pre-set threshold, perform a carry-up operation on the least significant bit of the retained coded value, perform a truncation operation on the discarded coded value, and if the coded value obtained by the carry-up of the retained coded value is the coded value of the second mantissa field, If the most significant bit of the discarded coding value is smaller than the third pre-set threshold, a truncation operation is performed on the discarded coding value, and the retained coding value is the coding value of the second mantissa field. It is further composed of The apparatus according to claim 6.

9. The first pre-set threshold is determined by traversing a plurality of first floating-point data. The apparatus according to any one of claims 6 to 8.

10. The first floating-point data further includes a sign field, the second floating-point data further includes the sign field, a prefix code field, and a second exponent field, the prefix code field indicating the bit width of the second exponent field, The bit width calculation unit, Based on the encoded value of the first exponential field, the bit width of the prefix code field, the encoded value of the prefix code field, the bit width of the second exponential field, and the encoded value of the second exponential field are further configured to determine these values. The apparatus according to claim 6.

11. It has a processor and memory, The aforementioned memory stores computer instructions. Upon executing the computer instruction, the processor performs the method according to any one of claims 1 to 5. A device for converting the precision of floating-point data.

12. Includes computer instructions, When the computer instruction is executed on the electronic device, the electronic device can perform the method according to any one of claims 1 to 5. Computer-readable storage medium.

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