FFT processor, FFT computing method, system on chip, integrated circuit, and sensor

Abstract

Disclosed herein are an FFT processor, an FFT computing method, a radar signal processing system-on-chip, an integrated circuit, and an electromagnetic wave sensor. The FFT processor comprises two cascaded FFT kernels, and the FFT processor has at least two operating modes among a large-point-number FFT mode, a pipeline mode and an independent parallel mode, wherein when the FFT processor is in the large-point-number FFT mode, the two FFT kernels are configured to decompose FFT of N points into two instances of FFT; when the FFT processor is in the pipeline mode, the former FFT kernel of the two cascaded FFT kernels is configured to perform distance FFT, and the latter FFT kernel of the two cascaded FFT kernels is configured to perform Doppler FFT; and when the FFT processor is in the independent parallel mode, the two FFT kernels are configured to independently process data of different channels in parallel.

Description

FFT processor, FFT computation method, system on chip, integrated circuit and sensor

[0001] This application claims priority to the Chinese Patent Application No. 202411287415.1, filed on September 13, 2024, and entitled “Signal processing device, integrated circuit, electromagnetic wave device and terminal equipment”, the content of which should be understood as incorporated herein by reference. TECHNICAL FIELD

[0002] The present disclosure relates to radar signal processing technology, in particular to an FFT processor, an FFT computation method, a radar signal processing system on chip, an integrated circuit and an electromagnetic wave sensor. BACKGROUND

[0003] Radar is an electronic system that uses electromagnetic waves to detect targets and obtain information such as distance, speed, and angle. Since its inception in the early 20th century, radar technology has been widely used in military, civilian and scientific research fields, and has become one of the core tools of modern detection and perception. Radar target detection system, as an important part of radar technology, aims to extract target information from complex electromagnetic environment and achieve target detection, tracking and identification.

[0004] Digital Fourier Transform (DFT) operation is a well-defined discrete digital signal operation, whose input and output are a discrete signal vector of equal length. Fast Fourier Transform (FFT) is a realization of DFT. In radar signal processing, Fast Fourier Transform (FFT) has become one of the core algorithms due to its efficiency and versatility. It is involved in many radar signal processing links, such as pulse compression, Doppler processing, high-resolution imaging, beamforming, etc.

[0005] In a radar signal processing system on chip / chip, at least one FFT processor is integrated to meet the needs of performing FFT computation in related links. SUMMARY

[0006] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0007] The embodiments of the present disclosure provide an FFT processor, an FFT calculation method, a radar signal processing system on chip, an integrated circuit and an electromagnetic wave sensor. The FFT processor realizes the expansion of the FFT calculation point number in a serial cascade mode of multiple FFT cores, and based on the independently configurable butterfly operation structure contained in each FFT core, the FFT core of multiple bases is realized on demand, thereby fully meeting the different point number FFT calculation requirements of the related functional modules or operators in the radar chip.

[0008] The embodiments of the present disclosure provide an FFT processor, which can include two FFT cores in cascade, and the FFT processor can have at least two modes of a large point number FFT mode, a pipeline mode and an independent parallel mode; when the FFT processor is in the large point number FFT mode, the two FFT cores (i.e., dual cores) are configured to decompose an N-point FFT into two times of FFT; when the FFT processor is in the pipeline mode, among the two FFT cores, a preceding FFT core in cascade is configured to perform a first FFT, and a following FFT core in cascade is configured to perform a second FFT based on the result of the first FFT; and when the FFT processor is in the independent parallel mode, the two FFT cores are configured to independently and in parallel process data of different channels. The embodiments of the present disclosure also provide an FFT processor including two FFT cores in cascade, and the FFT processor has at least two working modes of a large point number FFT mode, a pipeline mode and an independent parallel mode;

[0009] When the FFT processor is in the large point number FFT mode, the two FFT cores are configured to decompose an N-point FFT into two times of FFT.

[0010] When the FFT processor is in the pipeline mode, among the two FFT cores, a preceding FFT core in cascade is configured to perform a range FFT, and a following FFT core in cascade is configured to perform a Doppler FFT; and

[0011] When the FFT processor is in the independent parallel mode, the two FFT cores are configured to independently and in parallel process data of different channels.

[0012] The embodiments of the present disclosure also provide an FFT processor, which includes:

[0013] At least two FFT cores in serial cascade, the FFT core supports a maximum base of N i FFT calculation;

[0014] The FFT core includes at least one butterfly operation structure, and the FFT core is configured to perform an FFT operation according to a set core operation base M iThe number of butterfly operation structure stages and the radix of each butterfly operation structure in the FFT core participating in performing the current FFT calculation are determined.

[0015] M i <=N i , and i represents the i-th FFT core.

[0016] The embodiments of the present disclosure further provide an FFT calculation method, which comprises:

[0017] According to the number of FFT points to be processed and the calculation capability parameter of the FFT processor, the number of iterations for performing FFT calculation and the actual calculation configuration parameter of the FFT processor in each iteration are determined; wherein the FFT processor comprises at least two FFT cores in series connection, and the FFT core supports a maximum radix of N i for FFT calculation.

[0018] According to the number of iterations, the following steps are performed in each iteration:

[0019] The actual calculation configuration parameter of the current iteration is obtained, and the radix M i of core operation of each FFT core is determined.

[0020] According to the radix M i of core operation, the corresponding FFT core is configured, the FFT processor is started, and the FFT calculation of the current iteration is performed by using the at least two FFT cores in series.

[0021] The radix M i of core operation of the FFT core is used to determine the number of butterfly operation structure stages and the radix of each butterfly operation structure in the FFT core participating in performing the current FFT calculation.

[0022] The calculation capability parameter comprises a maximum supported FFT point number N max ; and the actual calculation configuration parameter comprises an actual calculation FFT point number N act .

[0023] I is the number of FFT cores, M i <=N i , and i represents the i-th FFT core.

[0024] The embodiments of the present disclosure further provide a radar signal processing system-on-chip, which comprises:

[0025] a controller, a plurality of operators and a memory.

[0026] The controller is configured to start at least one of the plurality of operators to perform an operator function.

[0027] The plurality of operators includes an FFT processor including two FFT cores in cascade, and the FFT processor has at least two working modes of a large-point FFT mode, a pipeline mode and an independent parallel mode.

[0028] The FFT processor is configured to obtain a working mode from an FFT processor configuration data storage area set in the memory according to an operator start instruction from the controller, and perform FFT calculation according to the working mode.

[0029] Alternatively,

[0030] The plurality of operators includes an FFT processor including at least two FFT cores in cascade.

[0031] The FFT processor is configured to obtain actual calculation configuration parameters of the current iteration calculation from the FFT processor configuration data storage area set in the memory according to an operator start instruction from the controller, and perform the current iteration FFT calculation according to the actual calculation configuration parameters.

[0032] The embodiment of the present disclosure further provides an integrated circuit, including:

[0033] A digital signal processing module performs FFT calculation based on the FFT calculation method in any embodiment of the present disclosure.

[0034] The embodiment of the present disclosure further provides an electromagnetic wave sensor, including a carrier;

[0035] The radar signal processing system on chip as described in any embodiment of the present disclosure, or the integrated circuit as described in any embodiment of the present disclosure, is arranged on the carrier;

[0036] An antenna is arranged on the carrier and integrated with the radar signal processing system on chip or the integrated circuit as an integrated device or arranged separately.

[0037] The antenna is connected to the radar signal processing system on chip or the integrated circuit, and is used for transmitting the electromagnetic wave signal and / or receiving the echo signal.

[0038] The configurable general FFT processor provided by the embodiment of the present disclosure takes into account multiple factors such as chip hardware cost, calculation efficiency, FFT processor versatility, and storage access bandwidth, and provides an FFT calculation implementation scheme that fully meets the calculation needs of multiple applications for a radar chip.

[0039] Other features and advantages of the present application will be set forth in the following specification, and in part will become apparent to those skilled in the art on examination of the specification or by practice of the application. The other advantages of the present application will be realized and attained by the

[0040] Other aspects can become apparent to those of ordinary skill in the art upon reading and understanding the specification and the appended claims.

[0041] SUMMARY

[0042] The accompanying drawings are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. The drawings are provided for merely for illustrative purposes and are not intended to limit the scope of the application.

[0043] The embodiments of the present application will be described in detail with reference to the drawings, wherein:

[0044] Fig. 1a is a 3-stage butterfly structure for implementing base-8 FFT calculation according to an embodiment of the present application;

[0045] Fig. 1b is a 1-stage butterfly structure for implementing base-2 FFT calculation according to an embodiment of the present application;

[0046] Fig. 1c is a 2-stage butterfly structure for implementing base-4 FFT calculation according to an embodiment of the present application;

[0047] Fig. 2 is a structure diagram of an FFT processor according to an embodiment of the present application;

[0048] Fig. 3a is a diagram of bypassing results of an FFT core according to an embodiment of the present application;

[0049] Fig. 3b is another diagram of bypassing results of an FFT core according to an embodiment of the present application;

[0050] Fig. 4a and Fig. 4b are diagrams of reconfiguring an FFT core and results according to an embodiment of the present application;

[0051] Fig. 5 is a flowchart of an FFT calculation method according to an embodiment of the present application;

[0052] Fig. 6a is a diagram of a base-4 FFT operation structure with an additional set of multipliers according to an embodiment of the present application;

[0053] Fig. 6b is a simplified representation of Fig. 6a;

[0054] Fig. 7 is a diagram of a ping-pong storage area according to an embodiment of the present application;

[0055] Fig. 8 is a diagram of inter-core twiddle factor multiplication according to an embodiment of the present application;

[0056] FIG. 9 is a diagram of a data packet for N-point FFT calculation according to an embodiment of the present application;

[0057] FIG. 10a is a diagram of inter-core data transposition processing according to an embodiment of the present application;

[0058] FIG. 10b is a diagram of data transposition processing between adjacent iteration rounds according to an embodiment of the present application;

[0059] FIG. 11 is a diagram of a radar signal processing system-on-chip architecture according to an embodiment of the present application.

[0060] Detailed Description

[0061] Embodiments of the present disclosure will be described in detail below with reference to the drawings. The embodiments can be implemented in various forms. One of ordinary skill in the art can easily understand that the manner and content can be changed into other forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the content described in the following embodiments. Embodiments in the present disclosure and features in the embodiments can be arbitrarily combined with each other without conflict, if necessary.

[0062] Embodiments of the present application include and contemplate combinations of features and elements known to those of ordinary skill in the art. The embodiments, features, and elements disclosed herein can also be combined with any conventional features or elements to form a unique inventive scheme defined by the claims. Any feature or element of any embodiment can also be combined with features or elements from other inventive schemes to form another unique inventive scheme defined by the claims. Therefore, it should be understood that any feature shown and / or discussed in the embodiments of the present application can be implemented alone or in any appropriate combination. Therefore, the embodiments are not limited other than as set forth in the claims and their equivalents. Furthermore, various modifications and changes can be made within the scope of the appended claims.

[0063] Furthermore, in describing representative embodiments, the specification can have presented the method and / or process as a particular sequence of steps. However, to the extent that the method or process depends on more than one step, the method or process should not be limited to the particular sequence of steps described. Other sequences of steps can be possible, and are within the scope of the present application. Therefore, the particular order in which the steps are presented in the specification is not an indication of the order in which the steps are to be performed. Additionally, the specification can present the steps of the method and / or process in a particular order, which is not necessarily the order in which the steps are performed. The steps of the method and / or process can be performed in any order that is suitable for the particular application.

[0064] An FFT processor is a hardware or software module specially used for efficient calculation of DFT, which is widely used in radar signal processing systems. The FFT processor is a special computing unit for accelerating DFT calculation, and its core idea is to use the divide-and-conquer algorithm (such as the Cooley-Tukey algorithm) to reduce the complexity from O(X 2 ) to O(X×log X), X being the number of FFT points. In order to improve the operation efficiency, the FFT processor implemented in hardware is generally used in the radar signal processing system on chip (SoC). The butterfly operation structure is the core computing unit in the FFT processor, also known as the butterfly operation unit, which is used to implement the radix-N (N=2, 4, or 8, etc.) butterfly operation. Based on the radix-N butterfly operation structure / unit of one level (or layer), the N-point FFT calculation can be realized at one time, and by using the multi-level (or multi-layer) butterfly operation structure / unit cascade mode, the FFT calculation of larger points can be realized. In the FFT calculation, the radix N of the butterfly operation structure / unit determines the divide-and-conquer strategy and the calculation efficiency of the algorithm. By having a larger radix for each butterfly, the number of multiplications and the number of calculation stages can be reduced, meeting the needs of high-performance radar signal systems. However, the implementation complexity of the butterfly operation structure / unit with a larger radix is high. Therefore, in actual hardware design, the number of points to be processed, hardware resources, real-time requirements, and other aspects need to be considered.

[0065] In the FMCW (Frequency-Modulated Continuous Wave) radar, for the intermediate frequency (IF) signal obtained through the mixer, the distance information (i.e., the position of the peak corresponds to the distance of the target) can be extracted by performing one-dimensional FFT (i.e., range FFT) on the ADC sampling data of a single chirp (chirp, frequency modulation pulse); the velocity information (i.e., the position of the peak corresponds to the relative velocity of the target) can be extracted by performing second-dimensional FFT (i.e., Doppler FFT) on the same distance unit (i.e., the same frequency point after range FFT) of multiple chirps; and the angle of the target can be estimated by performing third-dimensional FFT (i.e., beamforming or angle FFT) on the same distance-Doppler unit of multiple receiving antennas (Rx) / receiving channels. That is, a large number of continuous high-throughput FFT operations are required in the signal processing link of a FMCW radar.

[0066] In the pipeline FFT architecture of the application layer, mainly contains the serial FFT architecture and parallel FFT architecture; The serial structure mainly includes single delay feedback (SDF), single delay commutator (SDC), single flow feedforward (SFF) and the like, although it has the advantages of high hardware resource utilization, small area, low power consumption and the like, but its throughput is low, usually only one sample can be processed per clock cycle (efficiency is 1 sample / cycle), especially when processing high data rate of radar, it may become a bottleneck, especially when high point multi-dimensional FFT is needed; The parallel structure mainly includes multi-path delay feedback (MDF), serial commutator (SC), multi-path delay commutator (MDF) and the like, which has the advantages of high throughput and powerful performance, but the hardware resources (such as logic unit, memory, wiring and the like) are consumed greatly, and the power consumption is high, which is unacceptable for radar chips that need tens or even hundreds of receiving channels and are extremely sensitive to cost and power consumption. That is, how to realize high-throughput FFT operation sufficient to meet the real-time processing needs of radar under the limited chip area and power consumption budget has become the current technical pain point.

[0067] Taking a radar chip as an example, according to the different detection accuracies and the calculation needs of different functions, the number of points of FFT calculation is different, and how the hardware implemented FFT processor flexibly meets the needs of multiple applications has an important influence on the universality of the radar chip. It is very important to design and implement an FFT processor that takes into account execution efficiency and hardware cost, is flexible and configurable, and better meets the needs of multiple radar applications.

[0068] Taking a butterfly operation unit based on radix-2 as an example, to realize X-point radix-2 FFT, a total of Y stages of butterfly operation structure Y=log2X, G butterfly operation units X / 2 per stage. For example, a butterfly operation unit based on radix-2 realizes 8-point FFT calculation, which needs 3 stages of butterfly operation structure, 4 per stage, a total of 12. For example, as shown in FIG. 1a, an architecture for realizing 8-point FFT calculation; Each origin connected by a cross arrow, as shown in FIG. 1b, represents a pair of addition and subtraction operations, also known as a butterfly operation unit (butterfly structure), and the W parameter marked on each arrow represents a multiplication operation. The parameter is called a twiddle factor, and the operation is called twiddle multiplication. It can be seen that the FFT calculation architecture shown in FIG. 1a includes a total of 12 butterfly structures, i.e. 24 addition and subtraction operations, 12 twiddle multiplications, which is proportional to 8log28=24.

[0069] Taking the operation structure of the above 8-point FFT as an example, in the 3-stage butterfly structure included in FIG. 1a, only the upper right corner part of the butterfly structure is used to perform operation, as shown in the part of FIG. 1c, 4-point FFT calculation can be implemented, including 4 butterfly structures and 4 twiddle multiplications, which is proportional to 4log24=8; only the upper right corner part of the butterfly structure is used to perform operation, as shown in the part of FIG. 1b, 2-point FFT calculation can be implemented. That is, for the 3-stage butterfly structure for implementing 8-point FFT calculation, the use control of the related butterfly operation unit is also implemented for 4-point and 2-point FFT calculation.

[0070] It can be seen that based on multiple radix-2 butterfly operation units, in a multi-stage hardware cascade manner, the need for large-point FFT calculation can be met. If the 3-stage operation structure shown in FIG. 1a for implementing 8-point FFT calculation is regarded as a whole, more-point FFT calculation can also be further implemented by an iterative running manner based on the whole structure. At this time, the 3-stage FFT butterfly structure for implementing 8-point FFT calculation composed of 12 butterfly operation units can be regarded as a whole, which is called a radix-8 butterfly operation structure / unit. Taking the distance dimension FFT calculation in radar signal processing as an example, 512 / 1024-point FFT calculation is often involved. The FFT processor is implemented in this multi-stage cascade manner, which needs 1280 / 5120 radix-2 butterfly operation units for 5 / 10-stage cascade, which poses a huge challenge to the hardware cost and the chip space occupied.

[0071] In a time-for-space / hardware manner, a radix-8 3-stage (or 3-layer) butterfly operation structure / unit can be used to implement larger-point FFT calculation by an iterative manner. Using a radix-N butterfly operation structure / unit for k times of iteration can implement N^k-point FFT calculation. For example, using a radix-8 butterfly operation structure / unit for 3 times of iteration can implement 8^3=512-point FFT calculation. The iterative structure FFT calculation needs to supplement a group of twiddle multipliers compared with the basic Radix-N structure FFT.

[0072] In order to improve the throughput, a plurality of 8-point FFT cores described above can be configured to cooperate in a pipeline to implement more-point FFT operation. That is, based on the radix-N FFT calculation engine capable of implementing N-point FFT operation, the embodiment of the present application proposes to implement L-point FFT operation by iteration using a radix-N FFT calculation engine, if L is the k-th power of N, only k rounds of iteration are needed, and L / N times of radix-N operation is performed in each round.

[0073] It can be seen that, in order to meet the needs of larger point FFT calculation, the number of physical cascade stages of the butterfly operation structure / unit can be expanded, and the iterative implementation in time based on the limited butterfly operation structure / unit can also be adopted.

[0074] It should be noted that, in the embodiments of the present application, iterative can be defined as using a single FFT calculation engine (such as the FFT processor in the embodiments of the present application) to complete the entire large point FFT calculation in multiple steps through loop iteration, thereby effectively improving flexibility and area efficiency, that is, the iterative architecture can greatly save chip area. The single FFT calculation engine can be a single-core FFT processor, which implements Radix-N FFT calculation, that is, a single-core FFT processor is used for loop iteration to implement large point FFT calculation; the single FFT calculation engine can also be a multi-core cascaded FFT processor, each core of which implements Radix-N FFT calculation, that is, a multi-core cascaded FFT processor is used for loop iteration to implement large point FFT calculation. i The single FFT calculation engine can be a single-core FFT processor, which implements Radix-N FFT calculation, that is, a single-core FFT processor is used for loop iteration to implement large point FFT calculation; the single FFT calculation engine can also be a multi-core cascaded FFT processor, each core of which implements Radix-N FFT calculation, that is, a multi-core cascaded FFT processor is used for loop iteration to implement large point FFT calculation. i The single FFT calculation engine can be a single-core FFT processor, which implements Radix-N FFT calculation, that is, a single-core FFT processor is used for loop iteration to implement large point FFT calculation; the single FFT calculation engine can also be a multi-core cascaded FFT processor, each core of which implements Radix-N FFT calculation, that is, a multi-core cascaded FFT processor is used for loop iteration to implement large point FFT calculation.

[0075] The embodiments of the present disclosure provide an FFT processor, which can include two FFT cores in cascade, and the FFT processor can have at least two modes of a large point number FFT mode, a pipeline mode and an independent parallel mode; when the FFT processor is in the large point number FFT mode, the two FFT cores (i.e. dual cores) are configured to decompose an N-point FFT into two times of FFT; when the FFT processor is in the pipeline mode, among the two FFT cores, a preceding FFT core in cascade is configured to perform a first FFT, and a following FFT core in cascade is configured to perform a second FFT based on a result of the first FFT; and when the FFT processor is in the independent parallel mode, the two FFT cores are configured to independently and in parallel process data of different channels. Wherein, the large point number FFT mode can be equivalent to implement Radix-N^2, i.e. through close series connection of dual cores, a super large point number (such as 4096 points) can be cooperatively completed, and then high resolution FFT is implemented; the pipeline mode can be configured to implement distance FFT and velocity (Doppler) FFT of radar signal processing in sequence, i.e. the output of the distance FFT is taken as a basis for Doppler FFT processing, as shown in FIG. 10a, core 1 can be dedicated to implement the first FFT, and core 2 can be dedicated to implement the second FFT, to form an efficient processing pipeline, thereby matching the radar frame structure. In the independent parallel mode, the dual cores work independently, and can process data of different channels at the same time, thereby improving the parallel capability of the system.

[0076] In the embodiments of the present disclosure, the working mode between the two FFT cores in cascade can be to implement FFT of a larger size by cooperative work as a whole, or to independently implement FFT of a smaller size, or to form a pipeline working mode by taking the output of the preceding FFT core in cascade as the input of the following FFT core in cascade. That is, the two FFT cores can be parallel, partially parallel or sequentially run, to constitute an FFT processor corresponding to the scene requirement.

[0077] Optionally, when the two FFT cores in cascade work as a whole, distance dimension FFT and Doppler dimension FFT of radar signals can be implemented, such as using the current iteration operation for distance dimension FFT, and the next iteration for corresponding Doppler dimension FFT, i.e. through two iterations to respectively implement distance dimension FFT and Doppler dimension FFT. Meanwhile, when the FFT core has sufficient computing power, the preceding FFT core in cascade can also perform distance dimension FFT in radar signal processing, and the following FFT core in cascade can be configured to perform Doppler dimension FFT based on the result of the preceding distance dimension FFT as the input.

[0078] In some example embodiments, the FFT core comprises at least two layers of computation structure; the base of the minimum computation unit (e.g. the base of the butterfly operation in each stage) increases or decreases along the data flow direction between two adjacent layers. For example, for a DIF FFT core, the base of the minimum computation unit decreases along the data input / output dimension between two adjacent layers, while for a DIT FFT core, the base of the minimum computation unit increases (e.g. the base of the butterfly operation in the first stage is 2, the base of the butterfly operation in the second stage is 4, and the base of the butterfly operation in the third stage is 8) along the data input / output dimension between two adjacent layers. In some example embodiments, the FFT core can be a parallel structure, i.e. the base of the FFT core is greater than or equal to 2.

[0079] It should be noted that in some example embodiments, the FFT cores can be cascaded through memory write / read transposition and twiddle factor multiplication, and thus the data flow can be processed in series. In addition, different cores can be time-division multiplexed (iterative) to implement a large-point FFT processing based on fewer physical cores. In some example embodiments, an L-point Radix-N FFT core can comprise a structure formed by a plurality of Radix-N butterfly basic units, control logic, memory, and twiddle factor multipliers, and is used to implement an L-point FFT, where L is greater than N.

[0080] In some example embodiments, at least one of the FFT cores comprises at least two layers of computation structure, and some of the computation layers are configured to be skipped, i.e. when some of the computation layers are configured to be skipped, the core base changes. For example, for an FFT core with a maximum base of N, when some of the computation layers are configured to be skipped, the FFT core can work as a Radix M FFT core with a different base, where M can be a factor of N, i.e. there is an integer ratio r such that Mxr=N.

[0081] In some example embodiments, the FFT processor can further comprise a buffer between the two FFT cores with the maximum core base; when the FFT processor is in the large-point FFT mode or the pipeline mode, the buffer is configured to transpose the output data of the FFT core before the cascade and use the transposed data as the input of the FFT core after the cascade; when the FFT processor is in the independent parallel mode, the buffer is configured to comprise two simplex memories so that the two FFT cores can work simultaneously.

[0082] For example, in order to enable two FFT cores to complete an N^2-point FFT in series, a buffer can be set between the two cores to realize the transposition of data from (N1, N0) order to (N0, N1) order, which can be used to buffer N shots of N outputs from one of the cores, and then the N^2 outputs can be divided into N shots of N outputs according to the extracted order, and the N shots of N outputs are transmitted to the other core as inputs. At the same time, in order to enable the two cores to work simultaneously, the above-mentioned memory can also be set to be able to work in duplex mode, that is, to simultaneously accept the write request from one core and the read request from the other core, and to support the above-mentioned extraction request; or the memory has two simplex memories to work in ping-pong mode, so that at any moment, one of the simplex memories accepts the write request from one core, and the other simplex memory provides the read request from the other core, and the task can also be exchanged every N shots, that is, after N^2 data are written / read at the same time, the task is exchanged.

[0083] The embodiments of the present disclosure provide an FFT processor, as shown in FIG. 2, which includes at least two FFT cores 210 connected in series, and the FFT core 210 supports an FFT calculation with a maximum radix of N i .

[0084] The FFT core includes at least one butterfly operation structure, and the FFT core 210 is configured to determine the number of butterfly operation structures participating in the execution of the FFT calculation and the radix of each butterfly operation structure in the FFT core according to the set core operation radix M i .

[0085] M i <=N i , and i represents the i-th FFT core.

[0086] It should be noted that in the embodiments of the present disclosure, the FFT core is a butterfly calculation unit supporting an N i -point FFT calculation, which includes at least one butterfly operation structure, and within the range of the maximum supported FFT point number, the core operation radix M i is dynamically configured to realize the FFT calculation of the target point number. The FFT processor includes at least two FFT cores connected in series, which can break through the processing point number limit of a single FFT core based on the cascade of multiple FFT cores, and realize the FFT calculation of a large point number. The core operation radices of the multiple FFT cores are independently configured, and the multiple FFT cores operate cooperatively to meet the needs of the target point number FFT calculation. The FFT processor formed by at least one FFT core serves as a basic unit of iterative calculation, and the FFT processor based on the multiple cores performs iterative calculation, which can realize the FFT calculation of a larger point number or multi-dimensional FFT calculation.

[0087] It should be noted that the butterfly operation structure in each stage of the FFT operation core in the embodiments of the present disclosure is a general term for basic Radix-N operation structure / unit, including a 2-input, 2-output structure composed of a rotation factor multiplication, similar to a butterfly structure, such as radix-2 / Radix-2; also including a 3-input, 3-output structure involving more complex rotation factor combinations, and not showing a "butterfly" shape, such as radix-3 / Radix-3; also including a 4-input, 4-output structure, referred to as a "Radix-butterfly" structure, or other structures, not limited to only radix-2 butterfly structure. These butterfly operation structures can be individually or cascaded to build the overall computing structure of the FFT core.

[0088] In some exemplary embodiments, the FFT core supports a maximum radix N i :

[0089] wherein J is the total number of stages of the butterfly operation structure included in the i-th FFT core, X i,j is the radix of the j-th stage of the butterfly operation structure in the i-th FFT core;

[0090] In the case where M i is equal to the radix of a stage of the butterfly operation structure in the FFT core, or the product of the radices of multiple stages of the butterfly operation structure, the FFT core is configured to determine that the stage or the multiple stages of the butterfly operation structure participate in performing the FFT calculation, and bypass other stages of the butterfly operation structure other than the stage or the multiple stages;

[0091] In the case where M i is not equal to the radix of a stage of the butterfly operation structure in the FFT core, nor the product of the radices of multiple stages of the butterfly operation structure, the FFT core is configured to reconfigure the data flow path of the at least one stage of the butterfly operation structure in the FFT core, so that the FFT core performs an FFT calculation with a radix of M i .

[0092] wherein M i is equal to the radix of a stage of the butterfly operation structure in the FFT core, or the product of the radices of multiple stages of the butterfly operation structure, it is understood that the core operation radix M i is obtained by multiplying the radix of the stage or the multiple stages corresponding to the original at least one stage of the butterfly operation structure, and the core operation radix M i is also referred to as a factor radix. M i is not equal to the radix of a stage of the butterfly operation structure in the FFT core, nor the product of the radices of multiple stages of the butterfly operation structure, it is understood that the core operation radix M iThe kernel operation radix M cannot be obtained by the radix of the original at least one butterfly operation structure i Also known as non-factor base. In the case of non-factor base, it is necessary to reconfigure the data flow path of the at least one butterfly operation structure in the FFT core to achieve the effect of changing the radix of the one or more butterfly operation structures.

[0093] Taking the FFT core shown in FIG. 1a as an example, it includes J=3 levels of butterfly operation structures, and the radix of each level of butterfly operation structure is 2, that is, the FFT core shown in FIG. 1a supports a maximum of 2x2x2=8-point FFT calculation. When the FFT core is regarded as a whole, it is referred to as a radix-8 FFT core.

[0094] The kernel operation radix M of each FFT core i It is a configurable parameter within the range of the maximum supported radix. Taking FIG. 1a as an example, M i equals the radix of the one level of butterfly operation structure in the FFT core, or the product of the radices of the multiple levels of butterfly operation structures, that is, M i equals the radix 2 of the one level of butterfly operation structure, or, equals the product 2x2=4 of the radices of the two levels of butterfly operation structures, or, equals the product 2x2x2=8 of the radices of the three levels of butterfly operation structures. Correspondingly, the other two levels are bypassed, the one level of butterfly operation structure is retained to be effective, which is equivalent to the FFT core in the smallest box in FIG. 3a; the other one level is bypassed, the two levels of butterfly operation structures are retained to be effective, which is equivalent to the FFT core in the middle box in FIG. 3a; no bypassing, the three levels of butterfly operation structures are retained to be effective, which is equivalent to the FFT core in the largest box in FIG. 3a.

[0095] It should be noted that in the embodiments of the present application, configurable can refer to configuring the number of points (N) of the FFT, the radix, the data bit width, the window function, the scaling scheme, at least part of the parameters or similar parameters, so as to realize the adaptability of the system and the chip multiplexing purpose. For example, when a radar chip or a radar system faces multiple scenarios (such as the highway and parking scenarios of automatic driving), through the configurable architecture, the radar can dynamically adjust the FFT parameters to realize different resolutions and ranges to adapt to different modes or scenarios, so as to balance the performance and power consumption. Similarly, when the same chip can be used for different radar product lines through configurable parameters, repeated development is not needed, thereby effectively reducing the research and development cost and complexity.

[0096] The FFT algorithm generally includes two basic decomposition ideas in architecture: decimation-in-time (DIT) and decimation-in-frequency (DIF). The two methods differ in operation order, multiplication timing of rotation factors, and sorting of input / output sequences, thereby deriving different hardware implementation architectures. Correspondingly, from the perspective of hardware implementation, the DIT-based FFT and the DIF-based FFT, the two different basic architectures differ in data flow direction, memory access mode, and control logic complexity.

[0097] For example, the DIF-based FFT architecture has the following input / output sequence: input natural sequence, output reverse sequence; the multiplication (rotation factor) needs to be set after the butterfly operation, that is, the data path is first addition and then multiplication; in the logic control, the address generation is relatively regular and easy to control; since the direct input of ADC data can be realized by cooperating with the corresponding address mapping in the back-end processing, the radar data stream is well matched, that is, this architecture is more suitable for ASIC / special chip scenarios, especially for FMCW radar and other input natural sequence stream data processing applications.

[0098] FIG. 3a illustrates an 8-point radix-2 DIF FFT architecture, and FIG. 3b illustrates an 8-point radix-2 DIT FFT architecture. The FFT core in the embodiments of the present application is described by taking the DIF FFT architecture as an example, but can be converted into the DIT FFT architecture by adjusting some parameters according to the actual application scenario requirements. The DIF FFT shown in FIG. 3a is converted at the output end, while the DIT FFT shown in FIG. 3b is converted at the input end. By combining the DIF FFT core in the embodiments of the present application and adjusting the position of data conversion, the DIT FFT can also be realized, which can be used for general processing or DSP FFT operation with strict requirements for output sequence in radar or other fields.

[0099] That is, the FFT processor in the embodiments of the present application has a cascaded dual-core / multi-core configurable hybrid base iteration FFT operation architecture. The algorithm basis can adopt the DIF method, so that it can efficiently process the natural sequence data stream input by the front-end ADC (analog-to-digital converter), simplify the data interface control, and output the sequence by the address mapping processing in the back-end, thereby realizing better hardware efficiency as a whole.

[0100] Still taking FIG. 1a as an example, M i is not equal to the base of the one-stage butterfly operation structure in the FFT core, nor is it equal to the product of the bases of the multi-stage butterfly operation structure. For example, M iequal to 3, or equal to 6, the data flow path of the 3-stage butterfly operation structure shown in Fig. 1a needs to be reconfigured, for example, reconfigured into a two-stage butterfly operation structure of base 2 and base 3, to implement 3-point FFT calculation or 6-point FFT calculation. In this case, M i equal to 3, or equal to 6, the data flow path of the 3-stage butterfly operation structure shown in Fig. 1a needs to be reconfigured, for example, reconfigured into a two-stage butterfly operation structure of base 2 and base 3, to implement 3-point FFT calculation or 6-point FFT calculation. In this case, M i

[0101] Changing the data flow path, i.e. recombining the computing resources in the FFT core, changes the data order and the computing process, and thus implements the FFT core of the non-factor base. The computing resources include the butterfly operation structure and the corresponding rotation factor. More detailed reconfiguration schemes are not exemplified here.

[0102] Each FFT core is configured with a core operation base M i After that, the FFT processor can implement N act point FFT calculation,

[0103] I is the number of FFT cores.

[0104] It can be seen that by serially connecting at least two FFT cores, the number of FFT points that can be processed by an FFT processor can be increased. For example, including 2 FFT cores, each of which is a base-8 FFT core as shown in Fig. 1a, two serial connections can implement a maximum of 8x8=64-point FFT calculation; if three are serially connected, a maximum of 8x8x8=512-point FFT calculation can be implemented.

[0105] In some exemplary embodiments, the FFT processor further includes at least two intra-core rotation factor storage units corresponding to the at least two FFT cores, respectively storing the rotation factors required for the FFT calculation performed inside each FFT core.

[0106] It can be understood that an FFT core implementing M i point FFT calculation needs to use the corresponding rotation factor, which is called intra-core rotation factor. Therefore, a corresponding storage unit is configured to store this data. Each FFT core corresponds to a respective storage unit and the required rotation factor data.

[0107] In some exemplary embodiments, the FFT processor further includes at least one inter-core rotation factor storage unit, each of which stores the rotation factors required for the FFT calculation performed by the adjacent two FFT cores in series.​

[0108] and at least one set of inter-core multipliers, which are configured to perform multiplication of the FFT calculation result of the previous FFT core with a corresponding inter-core rotation factor to obtain the data to be processed of the current FFT core.

[0109] Each set of inter-core multipliers corresponds to the inter-core rotation factor multiplication operation required when two adjacent FFT cores are cascaded.

[0110] It can be understood that two FFT cores are connected in series to implement M i ×M j Point FFT calculation, and the corresponding rotation factor, referred to as an inter-core rotation factor, is also required. Therefore, a corresponding storage unit is configured to store the data. There is one storage unit and the required inter-core rotation factor data for each two adjacent FFT cores.

[0111] In order to further implement more point FFT calculation using the existing butterfly operation structure, iteration calculation can be performed based on the FFT processor, i.e., the FFT processor is triggered multiple times to perform calculation. For example, an FFT processor including two FFT cores, each of which supports a maximum of 4-point FFT calculation, can implement 4×4=16-point FFT calculation using the FFT processor, and can implement 16×16=256-point FFT calculation by iterating the FFT processor twice.

[0112] In some exemplary embodiments, the FFT processor further comprises at least one iteration rotation factor storage unit, each iteration rotation factor storage unit storing a rotation factor required for adjacent two times of iteration execution of the multi-core FFT processor to perform FFT calculation;

[0113] and at least one set of iteration multipliers, which are configured to perform multiplication of the FFT calculation result of the previous iteration with a corresponding iteration rotation factor to obtain the data to be processed of the current iteration.

[0114] Each set of multipliers corresponds to the iteration rotation factor multiplication operation required when two adjacent iterations are performed.

[0115] It can be understood that iteration calculation using one FFT processor to implement large-point FFT calculation also requires a corresponding rotation factor, referred to as an iteration rotation factor. Therefore, a corresponding storage unit is configured to store the data. There is one storage unit and the required rotation factor data between each two rounds of iteration.

[0116] The in-core rotation factor, the inter-core rotation factor, and the iterative rotation factor involved in the embodiments of the present disclosure are determined in advance and stored in the corresponding allocated storage unit according to different FFT calculation needs. It should be noted that in the FFT processor scheme in the embodiments of the present disclosure, the corresponding rotation factor multiplication is involved between the in-core, inter-core, and adjacent iteration numbers, which can be implemented by using the corresponding configured multiplier. The specific aspects of the multiplier are not discussed in detail here.

[0117] By using the FFT processor provided in the embodiments of the present disclosure, under the premise of meeting the FFT calculation point number, the limited number of hardware resources (butterfly operation structure) are flexibly used to meet the needs of various FFT calculations by combining the in-core butterfly structure configuration, the inter-core serial calculation, and the multi-round iteration. The radar chip implemented based on the FFT processor can meet the FFT calculation needs of multiple links in radar signal processing. In some exemplary embodiments, in combination with the FFT calculation needs of mainstream radar applications, the FFT processor includes 2 FFT cores, also known as a serial dual-core configurable FFT processor.

[0118] In the cascaded (or serial) dual-core (Dual-Core Serial) / multi-core architecture in the embodiments of the present disclosure, the FFT processing can be implemented by using two / multiple FFT cores based on the "serial" data flow mode, so as to improve the performance and realize flexible task allocation. Since the two / multiple FFT cores (i.e., the dual-core / multi-core architecture) are used to implement parallel processing of data, the throughput rate of the dual-core architecture can be doubled compared with the serial architecture. At the same time, the dual-core / multi-core architecture capable of parallel processing can implement various cooperative working modes, for example, the dual-core architecture can at least implement: mode one, cooperative calculation of a large FFT by using a decomposition algorithm; mode two, independent operation of two relatively small FFTs by each core to meet the needs of simultaneous processing of the distance dimension and the speed dimension, or different distance ranges and different distance accuracy / resolution in radar; and mode three, one core is dedicated to distance FFT, and the other core is dedicated to Doppler FFT to form an efficient pipeline and further improve the overall throughput rate.

[0119] By using the FFT processor provided in the embodiments of the present disclosure, the present disclosure further provides an FFT calculation method, as shown in FIG. 5, the method includes:

[0120] In step 510, the iteration number of the FFT calculation and the actual calculation configuration parameter of the FFT processor in each iteration are determined according to the to-be-processed FFT point number and the calculation capability parameter of the FFT processor; wherein the FFT processor includes at least two FFT cores in serial cascade, and the FFT core supports the maximum radix N i FFT calculation;

[0121] Step 520, according to the number of iterations, in each iteration, the following steps are performed:

[0122] Step 521, obtaining the actual calculation configuration parameters of this iteration, determining the kernel operation base number M of each FFT core i ;

[0123] Step 522, according to the kernel operation base number M i , configuring the corresponding FFT core, starting the FFT processor, and using the at least two FFT cores to serially perform the FFT calculation of this iteration;

[0124] Wherein, the kernel operation base number M i of the FFT core is used to determine the number of butterfly operation structure stages and the base number of each stage of butterfly operation structure participating in the execution of the FFT calculation in the FFT core;

[0125] The calculation capability parameter includes: the maximum supported FFT point number N max ; and the actual calculation configuration parameter includes: the actual calculation FFT point number N act ;

[0126] I is the number of FFT cores, M i <=N i , and i represents the i-th FFT core.

[0127] By using the FFT calculation method provided in the embodiments of the present disclosure, based on the above-mentioned flexible and configurable FFT processor, the need for a variety of FFT point number operations is realized. Before performing the FFT calculation, whether iteration operation is needed, the number of iterations, and the actual calculation point number of each FFT core in each iteration are determined according to the calculation requirement and the hardware capability parameter of the FFT processor. Further, in the case that the actual calculation point number is less than the maximum supported point number of the FFT core, bypass processing of one or more levels of butterfly operation structure, or data stream path reconfiguration processing is performed. Finally, iteration calculation is performed according to the number of iterations. Wherein, the calculation of a larger FFT point number is realized by iteration execution, the total FFT point number that can be realized is equal to the product of the FFT point number realized in each iteration, and the butterfly operation structure included in the FFT processor in each iteration can remain unchanged, so that the same point number FFT calculation is realized in each iteration. The butterfly operation structure included in the FFT processor in each iteration can also be reconfigured according to the need in each iteration, so that different point number FFT calculation is realized in each iteration.

[0128] In some exemplary embodiments, the configuring the corresponding FFT core according to the kernel operation base number M i includes:

[0129] According to the core operation base number M of each FFT core i The corresponding determined number of stages of butterfly operation structures participating in the execution of the current FFT calculation and the base number of each stage of butterfly operation structures, configure the effective one or more stages of butterfly operation structures in each FFT core for executing the current FFT calculation, and determine the effective serial butterfly operation structure of the FFT processor for executing the current FFT calculation.

[0130] It can be understood that, according to the core operation base number M of each FFT core i The corresponding determined number of stages of butterfly operation structures participating in the execution of the current FFT calculation and the base number of each stage of butterfly operation structures, determine the effective one or more stages of butterfly operation structures in the FFT core for executing the current FFT calculation; that is, first determine the multi-stage structure in each core;

[0131] According to the serial order of the at least two FFT cores, based on the effective multi-stage butterfly operation structure in each FFT core for executing the current FFT calculation, determine the effective serial butterfly operation structure of the FFT processor for executing the current FFT calculation; that is, further determine the overall structure of the multi-core serial.

[0132] It can be seen that, in the overall FFT calculation, according to the total FFT calculation point number (target FFT calculation point number), first determine the iteration round number, and decompose the total FFT calculation point number to the FFT calculation point number required to be implemented in each iteration, and the product of the FFT calculation point numbers implemented in multiple iterations is the total FFT calculation point number. Then, for the at least two FFT cores in each iteration, determine the FFT calculation point number of the current iteration, and decompose the FFT calculation point number required to be implemented in the current iteration to each FFT core, that is, the core operation base number M of each FFT core i The product of the FFT calculation point numbers implemented by the at least two FFT cores is the FFT point number required to be implemented in the current iteration. Further, the number of stages of butterfly operation structures actually participating in the current iteration and the base number of each stage are determined according to the core operation base number M of each core i .

[0133] It should be noted that, compared with the initial full butterfly operation structure in the FFT core, the butterfly operation structure for executing the current calculation is configured according to the core operation base number M i , which is called the effective one or more stages of butterfly operation structures of the FFT core; compared with the initial full butterfly operation structure in the FFT core based on each FFT core, the determined butterfly operation structure for executing the current calculation is configured according to the total FFT calculation point number decomposed to each FFT core, which is called the effective serial butterfly operation structure of the FFT processor.

[0134] The determined valid serial butterfly operation structure is used to perform FFT calculation, realize total FFT point calculation, and output calculation results.

[0135] In some example embodiments, the starting of the FFT processor and the serial execution of the FFT calculation of the current iteration by the at least two FFT cores include:

[0136] In some example embodiments, the starting of the FFT processor and the serial execution of the FFT calculation of the current iteration by the at least two FFT cores include:

[0137] In some example embodiments, the starting of the FFT processor and the serial execution of the FFT calculation of the current iteration by the at least two FFT cores include:

[0138] In some example embodiments, the starting of the FFT processor and the serial execution of the FFT calculation of the current iteration by the at least two FFT cores include:

[0139] It can be seen that, according to the FFT calculation, the FFT calculation in each FFT core is performed according to the obtained intra-core rotation factor, and the operation between adjacent FFT cores is performed according to the obtained inter-core rotation factor. The specific data of these rotation factors is determined in advance and stored according to the FFT calculation requirement and the determined valid multi-core serial butterfly operation structure.

[0140] In some example embodiments, the maximum supported N1=N2 of the two FFT cores in the dual-core FFT processor, the obtained M1=M2 of the core operation radix of the two FFT cores in the valid dual-core FFT processor, or M1≠M2. For the case of inequality, it is also called a dual-core mixed-radix FFT processor. Among them, the general FFT is usually radix-2 (Radix-2) and radix-4 (Radix-4), that is, the point number N is a power of 2 or 4 (such as 1024, 4096, etc.), and the mixed-radix (Mixed-Radix) FFT in the embodiments of the present application allows the point number N to be a product of multiple different radices (for example, N=256=4x4x4x4 or N=360=5x8x9), thereby greatly improving the flexibility of the FFT processor in point number configuration. For FMCW radar, it diversifies the standards and modes, and can combine different FFT point numbers to obtain the optimal resolution in different applications / scenarios (short, medium, long, in-cabin, etc.). At the same time, it can also avoid the waste of resources caused by zero padding to make up the power of 2, such as for calculating a 300-point FFT, the mixed-radix can directly and efficiently calculate, while the zero padding method based on "2" needs to be zero padded to 512 points, wasting 44% of the calculation amount, that is, while avoiding resource waste, it also saves calculation time and power consumption.

[0141] As shown in FIG. 2, at least one of the cascaded FFT core 1 and the FFT core 2 has a hierarchical structure as shown in FIG. 3a, which can work as a Radix M-point FFT with different bases when some of the calculation layers are skipped (i.e., disabled). Here, M is a factor of N, i.e., there is an integer ratio r such that N = M x r. For example, taking a Radix 8 FFT three-layer calculation structure as an example (as shown in FIG. 3a), if it is configured to skip one layer (i.e., disable the layer) in the operation process, it can work as a Radix 4 FFT; if it is configured to skip two layers in the operation process, it can work as a Radix 2 FFT. Correspondingly, if the base of the FFT core 1 is configured as M, the buffer in the embodiments of the present application will correspondingly change from (N, M) row-column order transposition to (M, N) row-column order transposition, and the corresponding FFT core 2 can select the corresponding twiddle factor from the twiddle factor read-only structure based on the ratio of N and M. That is, in the embodiments of the present application, for the FFT processing of the dual-core or multi-core, the processing of multiple-point FFT can be realized by the configuration change of at least one FFT core, i.e., the FFT of M*N points is realized by the cooperation of the dual-core. Meanwhile, the FFT of M0 x M1 points can be further realized by iteration, where M0 and M1 are used to represent that the cores with configurable bases can be configured as different bases in two iterations.

[0142] In some exemplary embodiments, based on the above-mentioned flexible setting of different layers, the operation resources (such as butterfly, twiddle multiplier, etc.) in the iterative Radix structure can also be reorganized (such as rewiring, rerouting, etc.) to change the data order and the calculation process, so as to realize the FFT base of non-factors, i.e., without being limited to the condition that there is an integer ratio r such that N = M x r, to realize the FFT of any M x N points, for example, M = 2, N = 6, to realize the calculation of 12-point FFT.

[0143] In some exemplary embodiments, in the radar chip, it is determined to use a two-core serial FFT processor, which can take into account the requirements of the FFT calculation point number, the hardware cost of the FFT processor, and the FFT calculation efficiency, etc. That is, the FFT processor includes two serially connected FFT cores: FFT core 1 and FFT core 2, which are configured to perform the FFT calculation in the following formula in each iteration when M i = N i

[0144] wherein N = N1 x N2, is the in-core twiddle factor of the FFT core 1, ​an intra-core rotation factor for the FFT core 2, an inter-core rotation factor between the FFT core 1 and the FFT core 2;

[0145] X[k1,k2] = X[k] = X[N1xk2+k1], X is the FFT data to be processed, N is the total number of FFT data points to be processed in the current iteration of the FFT processor, k is the index of the FFT data point to be processed in the current iteration, k1 is the index of the group of the FFT data point to be processed in the current iteration, k2 is the index of the FFT data point to be processed in the current iteration in the current group, k1 = 0, 1, …, N1-1; k2 = 0, 1, …, N2-1.

[0146] wherein N is the number of FFT computation points executed in one iteration of the dual-core FFT processor, N1 and N2 are the core operation bases of the two cores respectively. If multiple iterations are executed, the same or different N, N1 and N2 configurations are used in each iteration.

[0147] In some exemplary embodiments, in each iteration, the starting of the FFT processor and the serial execution of the FFT computation in the current iteration by the at least two FFT cores further include:

[0148] acquiring the transposed data from the calculation result cache area as the FFT data to be processed in the current iteration of the FFT processor according to the set data transposition rule; and / or acquiring the transposed data from the calculation result cache area as the FFT data to be processed in the current iteration of the non-first FFT core among the at least two FFT cores according to the set data transposition rule; wherein the calculation result cache area stores the FFT computation result in the current iteration of the previous FFT core in the serial connection.

[0149] When the FFT cores are serially connected to expand the number of FFT computation points, the next FFT core needs to extract or transpose the result data of the FFT computation of the previous FFT core as needed before processing. The data connection between the cores is realized by shared memory. As shown in FIG. 10a, the FFT data to be processed of the FFT core 2 is obtained by transposing the result data of the FFT computation of the FFT core 1.

[0150] As shown in FIG. 10a, the FFT processor in the embodiment of the present application can include two FFT cores in series, i.e., FFT core 1 and FFT core 2. The output of FFT core 1 is preprocessed, such as twiddle multiplication, and then used as the input of FFT core 2, so as to implement operations such as decomposition of FFT and linear processing of data stream. The factor parameters of the preprocessing, such as twiddle factor, can be stored in a read-only memory, such as a special twiddle memory. In addition, FFT core 1 and FFT core 2 can also be independently operated in parallel, so as to perform independent FFT processing. In this case, the preprocessing-related devices can not be set or used.

[0151] When the FFT processor implements further expansion of the number of FFT calculation points through multiple iterations, the result data of the previous iteration after FFT calculation is extracted or transposed as needed and then processed according to the FFT calculation requirement. The data connection between iterations is implemented by using a shared memory. As shown in FIG. 10b, the data to be processed in the second iteration is obtained by transposing the result data of the first iteration after FFT calculation. For example, the first iteration performs range FFT calculation, and the second iteration performs Doppler FFT calculation.

[0152] The data transposition rule is the same or different in different calculation links. In some example embodiments, the rule is changed according to the actual change of the core operation basis of the current FFT calculation. The rule and its transposition effect are not discussed in detail.

[0153] The FFT processor includes at least two FFT cores. In one iteration calculation, the FFT calculation result of the previous iteration is transposed and used as the data to be processed in the current iteration, which is used as the data to be processed in the first FFT core. The data to be processed in the non-first FFT core is obtained by transposing the FFT calculation result of the current iteration of the previous FFT core in series.

[0154] In some example embodiments, the calculation result buffer includes at least two iteration data partitions. The first iteration data partition is used to store the FFT calculation result of the current iteration, and the second iteration data partition is used to store the FFT calculation result of the previous iteration. In adjacent iterations, the physical buffer areas corresponding to the first iteration data partition and the second iteration data partition are interchanged.

[0155] It can be seen that the iteration data partition is shared by the last FFT core and the first FFT core of two adjacent iterations. The current iteration obtains the FFT calculation result of the last iteration from the iteration data partition, and performs the FFT calculation of the current iteration after transposition. In order to continuously perform the FFT calculation, the two iteration data partitions work in a ping-pong manner. In the current iteration, the FFT processor reads data from the first iteration data partition for transposition processing, and performs the FFT calculation, and writes the calculation result to the second iteration data partition; in the next iteration, the FFT processor reads data from the second iteration data partition for transposition processing, and performs the FFT calculation, and writes the calculation result to the first iteration data partition. Based on this, the pipeline processing of continuous multiple batches of input data can be realized, the overall operation efficiency is improved, and the processing speed can be effectively improved when applied to a radar data processing chip, and the real-time data processing needs can be met.

[0156] In some example embodiments, the calculation result cache area includes at least one pair of inter-core data partitions, each pair of inter-core data partitions being shared by two connected FFT cores, and the pair of inter-core data partitions includes a first inter-core data partition and a second inter-core data partition; the first inter-core data partition is used to store the FFT calculation result of the previous FFT core in the two FFT cores in the current iteration, and the second inter-core data partition is used to store the FFT calculation result of the previous FFT core in the two FFT cores in the last iteration; in two adjacent iterations, the physical cache areas corresponding to the first inter-core data partition and the second inter-core data partition are exchanged.

[0157] It can be seen that the FFT processor includes I serially connected FFT cores, the result buffer includes I-1 pairs of inter-core data partitions, each pair of inter-core data partitions is shared by two connected FFT cores, each pair includes two inter-core data partitions, and the two inter-core data partitions work in a ping-pong manner. Taking a dual-core FFT processor as an example, the result buffer includes 1 pair of inter-core data partitions. In the pth iteration, core 1 writes the FFT calculation result to the first inter-core data partition; in the p+1th iteration, core 1 writes the FFT calculation result to the second inter-core data partition; in the p+2th iteration, core 1 writes the FFT calculation result to the first inter-core data partition; and so on. Correspondingly, core 2 reads data from the first inter-core data partition or the second inter-core data partition for transposition processing, and core 1 and core 2 do not access the same inter-core data partition at the same time point or time interval when performing FFT calculation. As shown in FIG. 7, in order to enable two FFT cores (core 1 and core 2) to serially cooperate to complete an FFT of N^2 points, a buffer is arranged between the two cores to realize the transposition of data from an (N1, N0) row-column order to an (N0, N1) row-column order, that is, N taps of output data from core 1 can be realized, each tap has N output data, and a total of N^2 output data. According to the extracted order, the N^2 data are divided into N taps, each tap has N data, and the N data are transmitted to core 2 as input of core 2. At the same time, in order to enable the two cores to work simultaneously, the memory shown in FIG. 7 can also have a duplex working mode, for example, can simultaneously receive a write request from core 1 and a read request from core 2, and also simultaneously support the above extraction requirement, or a two simplex memory mode can also be used to work in a ping-pong manner, that is, as long as at any time, one simplex memory can accept the write request of core 1, and the other simplex memory can provide the read request of core 2, and at the same time, the two can also be exchanged and run every N taps, that is, after N^2 data are written / read, the two can also be exchanged and run.

[0158] For example, the FFT processor includes two FFT cores, each FFT core is a maximum support radix-4 FFT core, and the dual-core FFT processor can realize 4x4=16-point FFT calculation. The radix-4 butterfly operation structure included in the FFT core can also be a radix-4 direct structure as shown in FIG. 6a. Compared with the radix-4 structure as a whole as shown in FIG. 1c formed by a two-stage radix-2 butterfly structure, 4-1=3 multipliers are added on the left side for inter-core twiddle factor multiplication calculation, which is shown in FIG. 6b. The dual-core serial connection realizes 16-point FFT calculation, and each FFT core performs 16 / 4=4 times of radix-4 FFT calculation. The processing process of 16-point FFT calculation is shown in FIG. 8, wherein the multiplication operation related to the inter-core twiddle factor is between the two vertical lines on the right.

[0159] In some alternative embodiments, as shown in FIG. 8, a Radix-4 FFT is used to perform two rounds of iteration to calculate a 4^2=16-point FFT kernel, i.e., 4 Radix-4 operations are performed in each round of iteration, and the results of the radix calculation in the first round are decimated (data commuted) to serve as the input for the four Radix-4 operations in the second round. As shown in FIG. 8, the three layers of reading nodes (i.e., the black solid dots shown in the figure) along the direction from the input end (i.e., the left side of the figure) to the output end (i.e., the right side of the figure) correspond to the data reading behavior (input end), the data writing-decimation (reading) behavior (middle position), and the data writing behavior (output end) in the order of the working sequence. In this case, since the Radix-4 iteration structure requires simultaneous reading / writing of four data, the bandwidth of the corresponding memory is at least 4 (i.e., greater than or equal to the radix N of the FFT kernel).

[0160] In some exemplary embodiments, in a dual-kernel FFT processor, kernel 1 is an FFT kernel with a radix N1, and kernel 2 is an FFT kernel with a radix N2. An N=N1xN2-point FFT calculation is implemented. That is, an N-point sequence X[n] is divided into N1 segments, each of which is N2 points long, at this time n=N2x n1+n2, n1=0, 1, …, N1-1; n2=0, 1, …, N2-1. Alternatively, X[k] is sampled at intervals of N1, and N2 points are decimated, a total of N1 times, k is the frequency index, k1 is the number of frequency decimations, and k2 is the number of points decimated each time (an N-point sequence is divided into k1 and k2) at this time k=N1x k2+k1, k1=0, 1, …, N1-1; k2=0, 1, …, N2-1. As shown in FIG. 9.

[0161] Taking a dual-kernel Radix-4 FFT processor as an example, the four results of each Radix-4 operation of kernel 1 are used as the input for the four Radix-4 operations of kernel 2; the input for the four Radix-4 operations of kernel 2 is obtained from the results of the four Radix-4 operations of kernel 1, and this process is referred to as data transposition, also referred to as data decimation or data commutation. Decimation is a calculation requirement for a cascaded or iterative FFT structure. In some exemplary embodiments, the eight Radix-4 operations shown in FIG. 6 can be completed by fewer Radix-4 structures in time-sharing manner to reduce the number of butterfly operation structures. The calculation results of kernel 1 are output to the memory, and kernel 2 reads them in the required order to achieve the exchange of data groups.

[0162] The FFT processor constructed by the above-mentioned dual-core base-4 FFT core can perform 16-point FFT calculation in one iteration, and can perform 16^k-point FFT calculation in k iterations, for example, 256-point FFT calculation in two iterations. When the dual-core FFT processor is regarded as an integral FFT calculation unit, it can also be referred to as a base-16 FFT calculation unit / structure. By appropriate configuration, the FFT processor can support 2-point, 4-point, 8-point, 16-point, 256-point, and other FFT point number requirements. When applied to a radar chip, it can fully meet the needs of various FFT calculations.

[0163] In some exemplary embodiments, the dual-core FFT processor is configured to perform two iterations. In the first iteration, the core operation base number M 1,1 of core 1 is 4, and the core operation base number M 2,1 of core 2 is 2. In the second iteration, the core operation base number M 1,2 of core 1 is 2, and the core operation base number M 2,2 of core 2 is 4. Then, by using the FFT processor through two iterations, M 1,1 × M 2,1 × M 1,2 × M 2,2 -point FFT calculation can be achieved.

[0164] It can be known that the maximum support base number of each FFT core is N i , and N i -computed data need to be input in parallel to the corresponding FFT core in order to meet the parallel processing needs. Therefore, the chip needs to support simultaneous reading / writing of N i data. Therefore, the maximum support base number of the designed and implemented FFT core is N i . The memory access bandwidth in the chip needs to be fully considered. Therefore, based on this constraint, the maximum support base number of each calculation core is N i cannot be too large. In order to achieve large-point FFT calculation and maintain appropriate calculation efficiency, a multi-core cascading mode is adopted for expansion. Each additional FFT core needs to correspondingly increase a set of hardware butterfly operation structure. More core FFT processors significantly increase hardware costs and occupy larger chip physical space, which does not meet the requirements of chip miniaturization and micro-miniaturization. Taking a radar chip as an example, only a small number of applications may need large-point FFT calculation. Therefore, the design and implementation of a more core cascaded FFT processor also causes waste of hardware resources.

[0165] Based on the configurable FFT processor provided by the embodiments of the present disclosure, the multi-core FFT processor with a smaller number of cores, in cooperation with iterative control, can achieve further expansion of the FFT calculation points through multiple iterations. Neither hardware resources are wasted, nor hardware costs and chip sizes are effectively controlled, and large-point FFT calculation can also be achieved, fully meeting the needs of various FFT calculations in radar chips.

[0166] In combination with various functional needs of radar signal processing, such as pulse compression, range-DFT, Doppler-DFT, range-Doppler imaging, spectrum analysis, digital beamforming, constant false alarm rate detection, high-resolution angle estimation, clutter suppression, etc., FFT calculation is involved. The FFT processor applied to the radar chip includes two FFT cores, which can be two FFT cores of the same specification, such as two 4x4=16 FFT cores, each of which includes a 2-stage radix-4 butterfly operation structure; or two 2x2x2=8 FFT cores, each of which includes a 3-stage radix-2 butterfly operation structure. Alternatively, they can also be two different FFT cores, such as a 4x4=16 FFT core including a 2-stage radix-4 butterfly operation structure, and a 2x2x3=12 FFT core including a 3-stage radix-2, radix-2, radix-3 butterfly operation structure.

[0167] It can be seen that the FFT processor supporting flexible configuration of calculation core base and iterative operation can meet the FFT calculation needs of multiple functions in the radar chip, which is defined as a functional operator and meets the design requirements of the modular and high-parallel radar signal processing system on chip.

[0168] The embodiments of the present disclosure also provide a radar signal processing system on chip, comprising:

[0169] a controller, a plurality of operators and a memory;

[0170] The controller is configured to start at least one of the plurality of operators to execute an operator function;

[0171] The plurality of operators includes an FFT processor including two FFT cores in cascade, having at least two working modes of a large-point FFT mode, a pipeline mode and an independent parallel mode, as described in any of the embodiments of the present disclosure.

[0172] The FFT processor is configured to obtain a working mode from a set FFT processor configuration data storage area in the memory according to an operator start instruction from the controller, and perform FFT calculation according to the working mode.

[0173] The embodiments of the present disclosure also provide a radar signal processing system on chip, comprising:

[0174] a controller, a plurality of operators, and a memory;

[0175] the controller is configured to start at least one of the plurality of operators to perform an operator function;

[0176] The plurality of operators includes an FFT processor including at least two FFT cores in series, as described in any of the embodiments of the present disclosure.

[0177] The FFT processor is configured to, according to an operator start instruction from the controller, obtain actual calculation configuration parameters for the current iteration calculation from a set FFT processor configuration data storage area in the memory, and perform the current iteration FFT calculation according to the actual calculation configuration parameters.

[0178] In some example embodiments, the FFT processor is further configured to determine a core operation basis of each FFT core in the current iteration calculation according to the actual calculation configuration parameters, and perform the current iteration FFT calculation based on each determined core operation basis of the FFT cores in series.

[0179] In some example embodiments, the FFT processor is further configured to, according to an operator start instruction from the controller, start to perform the current iteration calculation, obtain to-be-processed data for the current iteration from a set second iteration data partition in the memory, and store an FFT calculation result generated in the current iteration to a set first iteration data partition in the memory.

[0180] The to-be-processed data for the current iteration includes input initial data for the current iteration, or data obtained by transposing the FFT calculation result generated in the last iteration according to a set data transposition rule.

[0181] In some example embodiments, the controller is further configured to determine the number of iterations for performing FFT calculation and actual calculation configuration parameters of the FFT processor in each iteration according to the number of to-be-processed FFT points and a calculation capability parameter of the FFT processor, and write the actual calculation configuration parameters to the set FFT processor configuration data storage area in the memory.

[0182] In some example embodiments, the controller is further configured to, according to the determined number of iterations, sequentially start the FFT processor to perform iteration calculation in a corresponding round.

[0183] It can be seen that the controller in the system on chip performs actual computation configuration parameter computation and writes the FFT processor configuration data storage area, which is read by the FFT processor to complete its configuration and then perform corresponding FFT computation. The controller controls the multiple startings of the FFT processor according to the iteration number to realize corresponding multiple iteration control.

[0184] In some exemplary embodiments, the plurality of operators further comprises at least one radar function operator selected from the group consisting of: a pulse compression operator, a range-doppler imaging operator, a DBF operator, a CFAR operator, a synthetic radar aperture imaging operator, and a data read-write operator; and the iteration number is w, w is greater than 1.

[0185] The controller is configured to start the FFT processor in the xth to the x+w-1th time period in turn; and start the radar function operator in the yth time period; y is greater than x+w-1.

[0186] The FFT processor is configured to be started in the xth to the x+w-1th time period, to obtain corresponding to-be-processed data for each iteration computation, to perform FFT computation function, and to write the computation result into the first iteration data partition or the second iteration data partition set in the memory.

[0187] The radar function operator is configured to be started in the zth time period, to obtain the FFT computation result from the first iteration data partition or the second iteration data partition set in the memory, to perform the subsequent operator function of the operator; z is greater than y.

[0188] The time periods can be of the same length or different lengths.

[0189] It can be seen that the controller starts the FFT processor multiple times in multiple time periods in advance, and then controls the corresponding radar function operator to be started after the FFT computation required by the radar function operator is completed, to obtain the computation result data and perform the subsequent operator function.

[0190] In an optional embodiment, each FFT core in the dual-core FFT processor includes a twiddle factor multiplier, a shifter, a conjugator, etc.; and the two FFT cores are serially cascaded through a buffer (cascade data transpose) and are configured to support a series of FFT operations required by radar signal processing. For example, each FFT core can include Radix 8 (which can include a three-layer Radix butterfly structure), one of the FFT cores can be configured to support a configurable base, and the other FFT core can be configured not to support a configurable base.

[0191] For example, the dual-core FFT processor can be configured with a dual-core series supporting factor and non-factor configurable iterative FFT operation architecture, in which one FFT core can support factor configurable base 0 / 2 / 4 / 8, and the other FFT core can configure the base fixed as 8 when operating in 2^n, and configure the base fixed as 6 when operating in 3*2^n.

[0192] For example, for the cascaded dual-core FFT processor, one trigger can implement a maximum of 64pts FFT, and two triggers can implement a maximum of 4096pts FFT operation.

[0193] In the implementation of the present application, the twiddle multiplication in the FFT core can be used to implement multiple rounds of FFT processing for windowing, downsampling, etc. in radar signal processing. The shift adjustment factor can also be set in the FFT core to adjust the signal amplitude, and the conjugator can be used to implement IFFT operation, etc.

[0194] It should be noted that based on the FFT processor described in the embodiments of the present application, when the mixed base configuration is performed, the twiddle multiplication in the circuit needs to be sent in a predetermined order. Multiple triggers are required when using the iterative FFT architecture to perform large size FFT.

[0195] In some example embodiments, the radar function operator further includes one or more of the following:

[0196] The plurality of operators further includes at least one of the following radar function operators: a multiply-accumulate unit (MAC) operator, an inversion (INV) operator, a sequential variational adaptive (SVA) operator, a STATS operator, a constant false alarm rate (CFAR) operator, a detection (DET) operator, a SIFT operator, a remapping (REMAP) operator, and a data move (MOVE) operator.

[0197] In some example embodiments, the plurality of operators further includes a shared memory data access PBUF operator for accessing shared memory data to perform FFT processor input data reading and calculation result writing. The operator uses a shared memory parallel access mechanism to enable multiple address parallel reading and writing.

[0198] It can be seen that, since multiple radar function operators in the radar signal processing system on a chip need to utilize the FFT processor for data calculation, the FFT processor is set as a dedicated operator, the start timing is controlled through the controller, and the access division of the shared storage space based on each operator can fully improve the utilization rate of the dedicated operator (FFT processor). Under the premise of meeting the overall radar signal processing efficiency of the system on a chip and the FFT calculation needs, repeated configuration of multiple types of FFT processor hardware is avoided, and the chip cost is effectively controlled.

[0199] In some example embodiments, the radar signal processing system on a chip, referred to as radar SoC, as shown in FIG. 11, includes a controller 600, multiple operators: signal processing operators, including: multiply-accumulate operators 610, FFT processors 620, INV operators 630, and SVA operators 640; spectrum analysis operators, including: STATS operators 650, CFAR operators 660, and DET operators 660; data processing operators: SIFT operators 680, REMAP operators 690, and MOVE operators 6100; and a memory 700. The connection lines of each operator to the shared memory 700 and the connection lines of each operator to the controller 600 are not shown in FIG. 11 and can be flexibly selected according to the chip architecture. In some example embodiments, the controller is used to control the start, stop, and sequence of each operator, also known as a sequencer.

[0200] In some example embodiments, the multiply-accumulate operator has 16 multiply-accumulate units, denoted as M4MAC.

[0201] In some example embodiments, the FFT processor 620 is a dual-core FFT processor based on base 8, denoted as R8-8FFT, which supports a maximum of 64-point FFT calculation in one iteration.

[0202] In some example embodiments, the radar signal processing system on a chip, also referred to as a radar Soc chip, includes but is not limited to radar chips of various systems such as TDM (Time Division Multiplexing), FMCW (Frequency Modulated Continuous Wave), PMCW (Phase-modulated continuous wave), etc.

[0203] Embodiments of the present application also provide an integrated circuit, including: a digital signal processing module, which performs FFT calculation based on the FFT calculation method of any embodiment of the present disclosure.

[0204] The digital signal processing module includes one or more processors; a storage device for storing one or more programs,

[0205] When the one or more programs are executed by the one or more processors, the one or more processors implement the FFT calculation method as described in any embodiment of the present application.

[0206] The digital signal processing module further comprises an FFT processor based on any embodiment of the present application.

[0207] The present application also provides an electromagnetic wave sensor, comprising:

[0208] A carrier body;

[0209] A radar signal processing system on chip as described in any embodiment of the present application, or an integrated circuit as described in any embodiment of the present application, is arranged on the carrier body;

[0210] An antenna arranged on the carrier body, integrated with the radar signal processing system on chip or the integrated circuit as a single device or arranged separately;

[0211] The antenna is connected to the radar signal processing system on chip or the integrated circuit, and is used for transmitting the electromagnetic wave signal and / or receiving the echo signal.

[0212] Those skilled in the art can understand that all or some of the steps in the method disclosed above, the functional modules / units in the system and the device can be implemented as software, firmware, hardware and appropriate combinations thereof. In the hardware implementation, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component can have multiple functions, or one function or step can be performed by several physical components in cooperation. Some or all of the components can be implemented as software executed by a processor, such as a digital signal processor or a microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer readable medium, which can include computer storage media (or non-transitory media) and communication media (or transitory media). As known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, as known to those skilled in the art, communication media typically includes computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism, and can include any information delivery medium.

[0213] Although the embodiments of the present disclosure have been shown and described above, it should be understood that the above-described embodiments are exemplary, and should not be construed as limiting the present application, and those skilled in the art can make changes, modifications, replacements and variations to the above-described embodiments within the scope of the present application.

Claims

1. A fast Fourier transform (FFT) processor comprising two FFT cores cascaded, the FFT processor having at least two operation modes of a large-point FFT mode, a pipeline mode and an independent parallel mode; when the FFT processor is in the large-point FFT mode, the two FFT cores are configured to decompose an N-point FFT into two FFTs; when the FFT processor is in the pipeline mode, among the two FFT cores, a preceding FFT core is configured to perform a first FFT and a following FFT core is configured to perform a second FFT based on the result of the first FFT; and when the FFT processor is in the independent parallel mode, the two FFT cores are configured to independently process data of different channels in parallel.

2. The FFT processor of claim 1, wherein the FFT cores comprise at least two layers of computation structures; between two adjacent layers, the radix of the minimum computation unit increases or decreases along the data order.

3. The FFT processor of claim 2, wherein at least one of the FFT cores comprises at least two layers of computation structures, and some layers of computation structures are configured to be skipped.

4. The FFT processor of claim 1, further comprising a buffer between the two FFT cores; when the FFT processor is in the large-point FFT mode or the pipeline mode, the buffer is configured to implement transposition of the output data of the preceding FFT core to the input data of the following FFT core; when the FFT processor is in the independent parallel mode, the buffer comprises two unidirectional memories to enable the two FFT cores to work in parallel.

5. A fast Fourier transform (FFT) processor comprising: at least two FFT cores in series, the FFT cores supporting a maximum radix of N i FFT computations; The FFT core includes at least one butterfly operation structure, and is configured to perform the FFT calculation according to a set core operation base M i The number of the butterfly operation structures and the base of each butterfly operation structure participating in the FFT calculation are determined. M i <=N i , i denotes the i-th FFT core.

6. The FFT processor of claim 5, The FFT core supports a maximum base N i : wherein J is the total number of stages of the butterfly operation structure included in the i-th FFT core, X i,j is the radix of the j-th stage of the butterfly operation structure in the i-th FFT core; In M i In case the product of the radix of the one-stage butterfly operation structure or the radix of the multi-stage butterfly operation structure in the present FFT core is equal to the radix of the one-stage butterfly operation structure in the present FFT core, or the product of the radix of the one-stage butterfly operation structure or the radix of the multi-stage butterfly operation structure in the present FFT core is equal to the radix of the one-stage butterfly operation structure in the present FFT core, the FFT core is configured to determine that the one-stage or the multi-stage butterfly operation structure participates in performing the present FFT calculation, and bypasses other stage butterfly operation structures other than the one-stage or the multi-stage. In M i In case the base is not equal to the base of the one stage butterfly operation structure in the FFT core nor to the product of the bases of the multi-stage butterfly operation structures, the FFT core is configured to reconfigure the data flow path of the at least one stage butterfly operation structure in the FFT core to enable the FFT core to perform an FFT computation with a base of M i .

7. The FFT processor of claim 5 or 6, Also included are: at least two intra-core twiddle factor storage units corresponding to the at least two FFT cores, respectively, storing twiddle factors required for performing FFT computation within each FFT core.

8. The FFT processor of claim 5 or 6, Also included are: at least one inter-core twiddle factor storage unit storing twiddle factors required for performing FFT computation by the two FFT cores in series; and at least one set of inter-core multipliers configured to perform multiplication of the result of the FFT computation of the preceding FFT core and the corresponding inter-core twiddle factor to obtain data to be processed by the current FFT core.

9. The FFT processor of claim 5 or 6, Also included are: at least one iteration twiddle factor storage unit storing twiddle factors required for performing FFT computation by the multi-core FFT processor in iteration for two times; and at least one set of iteration multipliers configured to perform multiplication of the result of the FFT computation of the previous iteration and the corresponding iteration twiddle factor to obtain data to be processed by the current iteration.

10. A fast Fourier transform (FFT) computation method, the method comprising: According to the number of FFT points to be processed and a computing capability parameter of an FFT processor, a number of iterations for performing FFT computation is determined, and actual computing configuration parameters of the FFT processor in each iteration are determined; wherein the FFT processor comprises at least two FFT cores in series connection, and each FFT core supports an FFT computation with a maximum radix of N i ​ According to the number of iterations, the following steps are performed in each iteration: Obtaining the actual calculation configuration parameter of this iteration, determining the core operation base number M of each FFT core i ; According to the core operation base M i Corresponding FFT cores are configured, the FFT processor is started, and the FFT calculation of the current iteration is executed in series by using the at least two FFT cores. wherein the core operation base number M of the FFT core i for determining the number of butterfly operation structures and the base number of each butterfly operation structure involved in performing the current FFT calculation in the FFT core. The computing capability parameter comprises: maximum supported FFT point number N max ; the actual computing configuration parameter comprises: actual computing FFT point number N act ; I is the number of FFT cores, M i <=N i i represents the i-th FFT core.

11. The FFT calculation method of claim 10, In each iteration, the core operation basis M is determined according to the core operation basis M i configuring a corresponding FFT core includes: According to the core operation base number M of each FFT core i According to the determined number of butterfly operation structure stages and the base number of each stage of butterfly operation structure corresponding to the current FFT calculation, the effective one or more stages of butterfly operation structure in each FFT core performing the current FFT calculation are configured, and the effective serial butterfly operation structure of the FFT processor performing the current FFT calculation is determined.

12. The FFT calculation method of claim 11, In each iteration, the FFT processor is started, and the FFT calculation of the current iteration is performed in series using the at least two FFT cores, including: Obtaining intra-core rotation factors corresponding to the at least two FFT cores, respectively used for FFT calculation within each FFT core; Obtaining inter-core rotation factors between adjacent FFT cores in the at least two FFT cores, respectively used for serial cascading of the corresponding adjacent FFT cores; Starting the FFT processor, obtaining the data to be processed in the current iteration, inputting the effective serial butterfly operation structure, performing FFT calculation according to the intra-core rotation factors and the inter-core rotation factors, and outputting the corresponding FFT calculation result.

13. The FFT calculation method of claim 12, The FFT processor comprises two serially concatenated FFT cores: FFT core 1 and FFT core 2, in M i = N i case, the FFT computation is performed in each iteration according to the following formula: wherein, N = N1 x N2, for the in-kernel rotation factor of the FFT kernel 1, for the in-kernel rotation factor of the FFT kernel 2, The inter-core rotation factor between FFT core 1 and FFT core 2 is: X[k1,k2]=X[k]=X[N1×k2+k1], X is the data to be processed, N is the total number of points of the FFT data to be processed in the current iteration of the FFT processor, k is the index of the FFT data point to be processed in the current iteration, k1 is the group index of the FFT data point to be processed in the current iteration, k2 is the index of the FFT data point to be processed in the current iteration in the current group, k1=0,1,…,N1–1; k2=0,1,…,N2–1.

14. The FFT calculation method of claim 12 or 13, In each iteration, the FFT processor is started, and the FFT calculation of the current iteration is performed in series using the at least two FFT cores, further including: According to the set data transposition rule, the transposed data is obtained from the calculation result cache area as the data to be processed in the current iteration of the FFT processor; wherein the calculation result cache area stores the FFT calculation result of the last iteration of the FFT processor; And / or, According to the set data transposition rule, the transposed data is obtained from the calculation result cache area as the data to be processed in the current iteration of the non-first FFT core in the at least two FFT cores; wherein the calculation result cache area stores the FFT calculation result of the current iteration of the last FFT core in the serial cascade.

15. The FFT calculation method of claim 14, The calculation result cache area includes at least two iteration data partitions, a first iteration data partition for storing the FFT calculation result of the current iteration of the FFT processor, and a second iteration data partition for storing the FFT calculation result of the last iteration of the FFT processor; in adjacent iterations, the physical cache areas corresponding to the first iteration data partition and the second iteration data partition are exchanged; And / or, The calculation result cache area includes at least one pair of inter-core data partitions, each pair of inter-core data partitions being a shared data storage area for two connected FFT cores, the pair of inter-core data partitions including: A first inter-core data area and a second inter-core data area; The first inter-core data partition is used to store the FFT calculation result of the previous FFT core in the two FFT cores in the current iteration, and the second inter-core data partition is used to store the FFT calculation result of the previous FFT core in the two FFT cores in the previous iteration; in adjacent two iterations, the physical cache areas corresponding to the first inter-core data partition and the second inter-core data partition are interchanged.

16. A radar signal processing system on chip, comprising: a controller, a plurality of operators and a memory; the controller is configured to start at least one of the plurality of operators to execute an operator function; wherein the plurality of operators comprises the FFT processor according to any one of claims 1-4; the FFT processor is configured to obtain a working mode from a set FFT processor configuration data storage area in the memory according to an operator start instruction from the controller, and perform FFT calculation according to the working mode; or, the plurality of operators comprises the FFT processor according to any one of claims 5-9; the FFT processor is configured to obtain actual calculation configuration parameters for the current iteration calculation from the set FFT processor configuration data storage area in the memory according to an operator start instruction from the controller, and perform the current iteration FFT calculation according to the actual calculation configuration parameters.

17. The radar signal processing system on chip according to claim 16, the FFT processor is further configured to start the current iteration calculation according to an operator start instruction from the controller, obtain to-be-processed data for the current iteration from a set second iteration data partition in the memory, and store the FFT calculation result generated in the current iteration to a set first iteration data partition in the memory; wherein the to-be-processed data for the current iteration comprises input initial data for the current iteration, or data obtained by transposing the FFT calculation result generated in the previous iteration according to a set data transposition rule.

18. An integrated circuit, comprising: a digital signal processing module configured to perform FFT calculation based on the method according to any one of claims 10-15.

19. An electromagnetic wave sensor, comprising: a carrier body; the radar signal processing system on chip according to any one of claims 16-17, or the integrated circuit according to claim 18, is arranged on the carrier body; an antenna, which is arranged on the carrier body and integrated with the radar signal processing system on chip or the integrated circuit as an integrated device or arranged separately; wherein the antenna is connected to the radar signal processing system on chip or the integrated circuit, and is used to emit the electromagnetic wave signal and / or receive the echo signal.

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