An Adaptive FFT Processor Module for Large Data Volume Processing

Abstract

This invention belongs to the field of FFT computation acceleration technology, specifically relating to an adaptive FFT operation processor module for handling large amounts of data, including an address generation module, a data rearrangement unit, a twiddle factor storage module, an FFT computation module, and a control module; the FFT computation module includes m-row radix-2 arrays arranged side-by-side. k The MDC module includes a data rearrangement unit comprising a read / write data storage module and a data preprocessing module. The read / write data storage module consists of multiple memories. The data preprocessing module consists of multiple parallel branch switching circuits and multiple shuffling units of varying depths. The twiddle factor storage module stores fixed constant twiddle factors and reuses them based on the number of calculation points. The address generation module uses a program counter to generate address sequences for data read / write. The control module controls the execution of FFT calculations and can adapt to different FFT calculation requirements. This improves the utilization rate of the butterfly operation unit and the overall computational throughput of the architecture.

Description

Technical Field

[0001] This invention belongs to the field of FFT computation acceleration technology, specifically relating to an adaptive FFT operation processor module for processing large amounts of data. Background Technology

[0002] The Fast Fourier Transform (FFT), as a highly efficient algorithm, can transform signals from the time domain to the frequency domain and has extremely wide applications in modern technology. In recent decades, the demand for processing large-scale data has been continuously increasing. For example, image processing requires handling data volumes of up to 2MB, while high-performance SAR real-time processing platforms must handle data volumes of up to 128KB to generate high-resolution images. Therefore, an FFT processing module capable of handling large data volumes is needed for applications with large-scale computational requirements. The hardware implementation technology of FFT has been extensively studied and has mainly developed into two categories: one is a pipelined architecture characterized by high throughput; the other is a storage architecture, which has advantages in hardware area and resource utilization.

[0003] Traditional multi-path delay commutator (MDC) architectures, such as Figure 1 As shown, this architecture allows data to be input into the butterfly unit in parallel, making it suitable for high-throughput scenarios. However, this architecture suffers from the problem that as the number of data points processed increases, the internal buffer also expands accordingly, and computational resources increase. This will require more hardware FIFO resources and ordinary multiplication units (as indicated by the symbols in the diagram). In a specific implementation, if the number of butterfly arithmetic units (each butterfly arithmetic unit consists of a subtraction and an addition arithmetic unit) is... The range of points to be processed is... Between. This indicates that when the actual number of points needs to be processed... The inability to fully utilize all butterfly operation units resulted in One butterfly operation unit is idle. This reflects the problem of low resource utilization in pipeline architectures designed for large number of points when performing FFT calculations with small number of points.

[0004] However, memory-based FFT architectures are suitable for resource-constrained scenarios. A key feature of this architecture is its combination of a set of memory units and multiple processing elements (PEs). The computation involves repeatedly transferring data from memory units to PEs for processing and writing the results back to memory. While this reduces the circuit footprint, the repeated data iteration leads to long computation times and low throughput. Furthermore, to ensure a stable data flow during iterative updates in memory, conflict-free data access techniques should be employed to resolve memory access contention. In addition, related research has introduced permutation circuits, which can rearrange the data read from memory before inputting it into the FFT processing units. However, these circuits are not applicable to high-speed, continuous-stream, and larger-scale FFT applications. Summary of the Invention

[0005] This invention aims to provide an adaptive FFT processing processor module for handling large amounts of data, capable of adapting to FFT computation requirements with varying numbers of points, different degrees of parallelism, and continuous cardinality. It improves the utilization rate of the butterfly processing unit and the overall computational throughput of the architecture.

[0006] The adaptive FFT processing processor module for processing large amounts of data in this invention includes an address generation module, a data rearrangement unit, a rotation factor storage module, an FFT calculation module, and a control module.

[0007] The FFT calculation module includes m row basis-2 rows arranged side by side. k MDC module;

[0008] The data rearrangement unit includes a read / write data storage module and a data preprocessing module;

[0009] The read / write data storage module consists of multiple memory units, each row being radix-2. k The MDC module corresponds to a specific memory, which is used to store data for input to the MDC module according to the settings;

[0010] The data preprocessing module consists of multiple parallel branch switching circuits and multiple shuffling units of different depths. Each shuffling unit contains two multiplexers and two buffer units of the same depth, which are used to receive intermediate computation data from the read and write data storage module and further adjust the arrangement of the data to conform to the input data layout of the MDC module in the next FFT computation stage.

[0011] The rotation factor storage module is used to store fixed constant rotation factors and to reuse the constant rotation factors according to the number of calculation points.

[0012] The address generation module is used to generate address sequences for data reading / writing using the program counter;

[0013] The control module is used to control the above modules / units to perform FFT calculations according to the following strategy:

[0014] In the pipelined architecture mode, based on the number of FFT points to be processed and the parallelism P < m, multiple groups are cascaded through data rearrangement units, each group consisting of P rows of MDC modules, by writing the input data or the calculation output of the previous P-row MDC module into the memory corresponding to the next P-row MDC module.

[0015] In the storage-based architecture mode, based on the number of FFT points to be processed and the parallelism P < m, the data calculated by the P-row MDC modules in this stage is processed by the data rearrangement unit and then input back into the same P-row MDC modules for the FFT calculation in the next stage.

[0016] Furthermore, in the data rearrangement unit, the following strategy is used to adjust the arrangement of data:

[0017] Let N = 2 f Let P be the number of points to be processed in the FFT and P be the parallelism. For any cardinality k, the index of each sample in a sample sequence is calculated using the following formula: Where x i Let x represent the i-th bit dimension. i For ∈{0,1}, the bit dimension change σ is defined as changing the position of each original bit dimension by applying the same transformation rule. The detailed mathematical formula is as follows:

[0018] σ(x f-1 x f-2 …x0)=x σ(f-1) x σ(f-2) …x σ(0) (1)

[0020] Where x σ(f-1) This represents the bit value at position f-1 after transformation;

[0021] Each line of MDC module corresponds to a FFT algorithm computation stage with a maximum radix of k. Calculate N-point FFTs within each stage, where This represents the floor operation, where the actual base in each stage is k. s , s∈{0,1,…,S-1}, are defined as follows:

[0022] k1 = fk(S-1), k2 = ... = k s =k (2)

[0024] In the s-th stage, a row of MDC modules will calculate sequentially. There are 1 data block, and each data block contains 1 data block. There are 1 set of input sample data to be processed, arranged as follows: matrix symbol This represents the u-th input block in stage s, where u is the index number of the data block, as shown in the following formula:

[0025]

[0026] element b r,c The subscripts r and c represent the row and column indices of the data to be processed, respectively. Let b 0,0 =x(u), then it is required that Other elements in the matrix and index u must satisfy b. r,c The constraint condition = x(u+d) is used to operate on the correct sample pairs in MDC. The expression for variable d is as follows:

[0027]

[0028] The range of values ​​for u in different stages s is as follows:

[0029]

[0030] And the increment symbol ε s Defined as:

[0031]

[0032] Where {a:i:b} represents a sequence starting from integer a and increasing to b with a step size of i;

[0033] symbol In stage s, the process described above that changes in the data rearrangement unit is defined as follows: and It can be composed of three consecutive bit-dimensional changes, and its mathematical definition formula is as follows:

[0034]

[0035] in, This indicates the transformation of the bits in the later segment of the address when reading data from memory. This represents the parallel branch transformation in the data preprocessing module. This represents a series of shuffling unit transformations in the data preprocessing module.

[0036] Furthermore, in the strategy, the sequence is initially stored in 2P memory locations, and the sampled data is placed in natural order, that is, in the q-th memory location, it is arranged in the order of data index q(N / 2P), q(N / 2P)+1, ..., (q+1)(N / 2P)-1;

[0037] First, regarding the read / write transformation of memory addresses. The position of each indexed point can be represented as:

[0038]

[0039] Where p = log2 2P, and the parallel sequence (a n-1 ,…,a n-p The ) represents the memory identifier number, while the serial sequence determines the specific location of the data in memory, and the read / write transformation The specific expression is as follows:

[0040]

[0041] The function Cat([u:v],[c:d]) concatenates two bit sequences, one ranging from u to v and the other from c to d. The operation R{.} represents a bit reversal operation. These are variable parameters that indicate the positions to be reversed, such as:

[0042]

[0043] Furthermore, the control module is configured to control the memory to perform read / write operations using the following strategy:

[0044] If the memory is full of intermediate data, it needs to be loaded into the next row of MDC cells. The read address pointer RD loads data from the memory according to the position pointed to by the value of the reversed specified bit at the end of each address; at the same time, the write address pointer WT stores new data at the same position until the original data in the memory is completely replaced by the new data.

[0045] In the next round of data updates, the read / write operations at the same address location must be performed in a progressively increasing manner according to the original address.

[0046] In subsequent rounds of data reading / writing, read / write operations are performed alternately at the same address location based on either the address after bit reversal or the original address.

[0047] Furthermore, the parallel branch switching circuit is used to implement the second bit-dimensional transformation. Perform a complete bit reversal on the parallel dimension; after the data is read from memory, change the parallel branch of the circuit to redirect the data stream to different shuffling unit ports. The corresponding transformation is described by the following formula:

[0048]

[0049] Furthermore, dimensional transformation This is accomplished by the shuffling unit, operating simultaneously on both the parallel and serial dimensions. Furthermore, in the rotation factor storage module, based on the configured parameters k and N, a base of 2 is pre-stored. k The constant rotation factor, the trivial rotation -j, and the nontrivial rotation factor related to the required partial base and the number of computational bits N are used in the FFT computation for each base -2 k The MDC module is called repeatedly as needed. Furthermore, the specific configuration of the nontrivial rotation factor includes letting W... N Here, n is the rotation factor, n is the time index, and η is the frequency index; first, perform a k+1 dimensional linear mapping decomposition on n and η: Assuming the calculation of N points requires the simultaneous use of mixed bases... and base-2 k The algorithm, where k1≤k, states that in the first stage of computing an N-point FFT, the last multiplication unit requires a nontrivial twiddle factor with a base of N. Pre-stored; in the second stage of computing the N-point FFT, the last multiplication unit only needs to be multiplied by the base. rotation factor The rotation factor that needs to be pre-stored during the third-stage calculation is: This process continues until the final stage, where the required pre-stored rotation factor is... This is a constant rotation factor. Furthermore, the data rearrangement unit also includes a read / write address bit inversion module, used to invert a specified number of bits in the latter part of the read / write address given by the address generation module for the memory, according to a setting. Furthermore, it also includes an output data buffer module, used to output the results generated by the FFT calculation module to an external cache unit. The advantage of this invention is that it proposes an adaptive FFT operation processor module for handling large amounts of data, with configurable computational parallelism, number of computation points, and computational radix, exhibiting high flexibility and scalability. This invention, through the use of a segmented rearrangement MDC unit design, adds a data rearrangement unit between each isomorphic MDC unit to meet the computational requirements of the Fast Fourier Transform (FFT). These data rearrangement units are suitable for any number of points and are responsible for gathering the scattered data points in the storage unit, and after preprocessing, orderly sending them to each MDC unit for processing according to the correct interval order of the FFT operation. This significantly reduces the FIFO buffer depth inside the traditional MDC pipeline when processing a large number of data points. This not only enhances the flexibility of the system architecture but also ensures efficient reuse of all resources when performing small-scale calculations. Simultaneously, the data sorting task, previously handled by the internal buffer of the MDC, is now performed by an external data preprocessing module. The segmented rearrangement MDC architecture allows for flexible configuration of different computation modes, fully utilizing idle MDC units and achieving multi-channel parallelism within a pipelined architecture. The segmented rearrangement units can also be used in the storage architecture, re-inputting data processed by the MDC units back into the original memory. These two points fully demonstrate the flexibility of this architecture.

[0050] In some embodiments of this invention, a conflict-free access mechanism is proposed. The data rearrangement unit contains a complete set of address generation rules for memory read / write operations, enabling the next MDC unit to read data from a memory cell while the previous MDC unit writes data to it. This allows for simultaneous read / write operations within the same memory region, and under the condition of satisfying minimum external storage resource constraints, from the perspective of the same batch of data (the writing and reading order is reversed), and from the perspective of the same time point, the read / write pointer transformation mechanism is the same. This ensures a conflict-free read / write address access mechanism within the same register. Correspondingly, a set of address bit change models is proposed, aiming to accurately calculate the number of address bit changes in each row of memory cells under different Fast Fourier Transform input point conditions. This enables in-place transformation, reducing memory cell consumption. Furthermore, a set of shuffling units with different depths is designed to ensure correct data sorting, so that data generated by each MDC unit can be reordered by the data rearrangement unit and accepted by the next MDC unit in the correct interval order.

[0051] In some embodiments of the present invention, an improved base-2 is proposed. k The decomposition algorithm categorizes twiddle factors into three types: constant twiddle factors, non-trivial twiddle factors, and trivial twiddle factors. This allows the MDC unit to be compatible with radix-2 twiddle factors within the same set of hardware resources. k-1 Base-2 k-2 ..., base-2 2 The algorithm significantly reduces the complexity of hardware resources and improves the utilization of complex multiplication units.

[0052] In some embodiments of the present invention, based on the configured parameters k and N, a base of 2 is pre-stored. k The constant twitch factor, the trivial factor, and the nontrivial twitch factor related to the required partial base and the number of computational bits N are used in the FFT calculation for each base-2. k The MDC module is called repeatedly as needed, so it is necessary to reduce the number of rotation factors stored in ROM in advance. Attached Figure Description

[0053] Figure 1 This is a schematic diagram of a traditional MDC pipeline in the background art of this invention;

[0054] Figure 2 This is a schematic diagram of the overall architecture of the adaptive FFT processor module in an embodiment of the present invention;

[0055] Figure 3 This is a schematic diagram of the segmented rearrangement MDC pipeline architecture used in an embodiment of the present invention;

[0056] Figure 4 Base-2 in the embodiments of the present invention k MDC pipeline architecture diagram;

[0057] Figure 5 This is a schematic diagram of the pipeline computing mode and the storage computing mode in the embodiments of the present invention;

[0058] Figure 6 This is a schematic diagram of a conflict-free read / write address translation read / write scheme in an embodiment of the present invention;

[0059] Figure 7 The use of base-2 in the embodiments of the present invention 5 A schematic diagram illustrating the changes in the data flow of 4096 points during algorithm computation. Detailed Implementation

[0060] The present invention will be further described below with reference to the accompanying drawings and embodiments:

[0061] The basic structure of the FFT operation processor module in this example is as follows: Figure 2 As shown, it includes an address generation module, a data rearrangement unit, a twitch factor storage module, an FFT calculation module, an output data buffer module, and a control module.

[0062] In this pipeline architecture, the processor module employs, for example... Figure 3 The segmented rearrangement pipeline architecture shown, in its core module—the FFT calculation module—divides the traditional serial MDC structure into multiple identical MDC modules. All MDC modules are interconnected through data rearrangement units. Each data rearrangement unit provides data to each MDC module and is responsible for processing the data generated by the previous MDC module according to a pre-defined rearrangement setting, ensuring that intermediate results are passed to the next MDC module in the correct index order. In this process, the data rearrangement unit acts as a transfer mechanism, enabling the expansion of MDC modules within the pipeline structure based on different numbers of points.

[0063] When operating within a storage architecture, the data generated by MDC will be rewritten back into the original memory, achieving data alternation within the same memory region.

[0064] The MDC module in this example uses, for example... Figure 4 The high-cardinality MDC architecture shown uses a radix-2 configuration. k The algorithm utilizes k (k≥2)-dimensional linear indices for construction, thus reducing the number of units required for ordinary complex multiplication and enabling the simultaneous processing of 2^k complex numbers. k Point-based FFT data; the high-cardinality MDC architecture adds multiplication units with different attributes, namely constant multiplication units (corresponding to the markings in the figure). Trivial multiplication units (corresponding to the markings in the diagram) ), Non-trivial multiplication units (corresponding to the markings in the diagram) In this context, the trivial multiplication unit can realize the function of imaginary multiplication through circuit transformation. Figure 4 The architecture diagram of the MDC module is shown. Figure 4 (a) Describes the case where the cardinality is odd, while the sub-cardinality is odd. Figure 4 (b) then presents a structure with an even cardinality.

[0065] Figure 5 The figure exemplifies possible rearrangement methods combining the MDC module and the data rearrangement unit in the FFT computation module. The FFT computation module in the figure consists of m row bases -2 k It consists of MDC modules, each of which is directly or indirectly connected to the data rearrangement unit.

[0066] Figure 5 The rearrangement method in (a) enables the m-row MDC module to process consecutive 2 rows in parallel. k Point sampling sequence, each row of the MDC module independently processes a set of 2 k point sequence.

[0067] Figure 5 (b) The rearrangement method is to cascade multiple MDCs containing P MDCs in parallel in each level. The P MDCs in the same level exchange data with each other in the data rearrangement unit. P is called the parallelism. This method increases the number of MDCs in each level. The resulting computing unit can read 2P data at the same time. For the same number of FFT points, the throughput of the architecture is significantly improved at the cost of occupying P times the number of butterfly units. The cascading of only one MDC in each level is a special case of P=1. For the data communication within each MDC when P>1, please refer to reference [4]. The corresponding number of MDCs can be cascaded according to the specific number of FFT points to be processed. Similarly, multiple sets of MDCs can be cascaded independently to process multiple sets of FFT calculations in parallel.

[0068] Figure 5 (c) indicates that all m-line MDC modules are cascaded into a group, and only one group can be processed at a time, with a maximum of 2. mk The sampling sequence.

[0069] It is not hard to see that Figure 5 (a) and Figure 5 The rearrangement methods in (c) can all be understood as... Figure 5 (b) is a special case of the rearrangement method.

[0070] The above rearrangement methods can all be collectively referred to as pipeline architecture patterns, meaning that the FFT calculation does not involve reusing the same set of MDCs. Figure 5 (d) illustrates that when the number of input data points exceeds the processing capacity limit of the m-row cascaded MDC modules, an m-channel execution mode based on the storage architecture will be adopted. In this mode, the data will be processed repeatedly in each row of MDC modules.

[0071] In addition, the single-row MDC unit uses an improved radix-2. k The decomposition algorithm is backward compatible with radix-2. k-1 Base-2 k-2 ..., base-2 2 The calculation can be performed simply by bypassing the redundant butterfly units using a selector.

[0072] Therefore, the adaptive architecture proposed in this example can be parameterized for any number of points N, parallelism P, and radix k by changing the actual number of butterfly operation units (k value) activated within the MDC module, the cascading method and number of MDC modules.

[0073] To ensure that intermediate results can be passed to the next row of MDC modules in the correct index order, the data rearrangement unit includes a read / write data storage module, a data preprocessing module, and a read / write address bit reversal module.

[0074] The read / write data storage module consists of multiple memories; in this example, each MDC module corresponds to two memories. In the pipelined architecture, the data result calculated by the previous MDC module is stored in the memory corresponding to the next MDC module according to the rearrangement settings. In the memory architecture, the data calculated by the current MDC module is processed by the data rearrangement unit and then rewritten into the current MDC module.

[0075] The data preprocessing module consists of multiple parallel branch switching circuits and multiple shuffling units of different depths. Each shuffling unit contains two multiplexers and two buffer units of the same depth. The function of the data preprocessing module is to receive intermediate computation data from the read / write data storage module and further adjust the arrangement of the data to conform to the input data layout of the next-level MDC module.

[0076] To illustrate the specific read / write address transformation and shuffling rules, this example introduces a bit dimension transformation representation method for detailed explanation.

[0077] A sample sequence contains N (N=2) f There are ) sampling points, and the index of each sample is calculated using the following formula: Where x i Let x represent the i-th bit dimension. i ∈{0,1} can be simplified to The symbol ≡ represents the binary representation of the index. The bit dimension change σ is defined as changing the position of each bit dimension by applying the same transformation rule. The detailed mathematical formula is as follows:

[0078] σ(x f-1 x f-2 …x0)=x σ(f-1) x σ(f-2) …x σ(0) (3)

[0080] Where x σ(f-1) This represents the bit value at position f-1 after transformation.

[0081] According to the architecture in this example, one row of MDC modules corresponds to an FFT algorithm computation stage with a maximum cardinality of k. Calculate N-point FFTs within each stage (N=2) f ),in This represents the floor operation, where the actual base in each stage is k. s s∈{0,1,…,S-1} is defined as follows:

[0082] k1 = fk(S-1), k2 = ... = d S =k (4)

[0084] In the s-th stage, a row of MDC modules will calculate sequentially. There are 1 data block, and each data block contains 1 data block. There are 1 set of input sample data to be processed, arranged as follows: matrix symbol This represents the u-th input block in the s-th stage, where u is the index number of the data block, as shown in formula (3):

[0085]

[0086] element b r,c The subscripts r and c represent the row and column indices of the data to be processed, respectively. Let b 0,0 =x(u), then it is required that Other elements in the matrix and index u must satisfy b. r,c The constraint condition = x(u+b) is used to operate on the correct sample pairs in MDC. The expression for variable d is as follows:

[0087]

[0088] In each computational stage s, there are a total of A number of butterfly blocks arrive within a continuous cycle and are sequentially fed into the MDC unit. These blocks are fed through the leading element d in the upper right corner. 0,0 =x(u) to distinguish them. Once the index u is determined, the indices of other elements in the block can be derived using formula (4). In addition, considering the additional condition k0 = 0, the range of values ​​for u in different stages s is as follows:

[0089]

[0090] And the increment symbol ε s Defined as:

[0091]

[0092] Where {a:i:d} represents a sequence starting from integer a and increasing to b with a step size of i.

[0093] On the other hand, symbols This represents the output block after computation by the MDC unit in stage s. To adhere to the computation rules of the FFT algorithm and ensure the correctness of the final result, it should satisfy the computation result of the previous stage. After passing through the external data rearrangement unit, it becomes the input data for the next stage MDC unit. The process described above that changes within the data rearrangement unit is defined as follows: and It can be composed of three consecutive bit-dimensional changes, and its mathematical definition formula is as follows:

[0094]

[0095] This indicates the transformation of the bits in the later segment of the address when reading data from memory. This represents the parallel branch transformation in the data preprocessing module. This represents a series of shuffling unit transformations in the data preprocessing module.

[0096] The sequence is initially stored in 2P memory locations, where P represents the degree of parallelism. Initially, the sampled data is placed in natural order, that is, in the q-th memory location, it is arranged in the order of data indices q(N / 2P), q(N / 2P)+1, ..., (q+1)(N / 2P)-1.

[0097] First, regarding the read / write transformation of memory addresses. The data rearrangement unit in this example also includes a read / write address bit reversal module, which is used to reverse a specified number of bits in the latter part of the address given by the address generation module for reading / writing the memory, according to a setting.

[0098] The position of each indexed point can be represented as:

[0099]

[0100] Where p = log2 2P, and the parallel sequence (a n-1 ,…,a n-p The ) represents the memory identifier number, and the serial sequence determines the specific location of the data in memory. It is not difficult to see that when P=1, only 2 memory bits are needed, using 1 bit for identification, and the read / write transformation... The specific expression is as follows:

[0101]

[0102] The function `Cat([u:v],[c:d])` concatenates two bit sequences, one ranging from u to v and the other from c to d. The operation `R{.}` represents a bit reversal or permutation operation. It is defined as reversing the latter part of the serial address sequence when the condition np-1≥w is met; otherwise, the entire serial address sequence will be reversed.

[0103] This is a variable parameter representing the position to be reversed; its value is determined by the number of points, the number of stages, and the cardinality. A complete mathematical modeling analysis of the FFT computation process yields the following formula, applicable to any number of points N, any number of stages s, any degree of parallelism P, and any cardinality k:

[0104]

[0105] Therefore, the read / write address bit reversal module in this example is used to perform the required bit reversal operation on the serial sequence according to formulas (9) and (10). Then, in order to complete the adjustment of the data arrangement position each time more efficiently, a conflict-free read / write address access scheme is proposed in the read / write data storage module in this example. Figure 6 The following example uses a 3-bit address to illustrate this scheme:

[0106] Assuming the memory is currently full of intermediate data and needs to be loaded into the next row of MDC cells, the address generation module first sends an incrementing address sequence (exemplary addresses 0b000-0b111 in the diagram) to the read / write address bit inversion module. Figure 6 As shown in (a), the read address pointer RD loads data from the memory (Bank) according to the address pointed to by the reversed 3 bits of each address; simultaneously, when new data needs to be stored, the write address pointer WT also stores the new data in the same reversed 3-bit manner. That is to say, the order of new data writing / old data reading address is 0b000→0b100→0b010→0b110…; continuously according to… Figure 6 (a) The reverse read and reverse write process shown is executed until the original data in the memory is completely replaced by the new data, and the new data is stored in the Bank by reversing the address bits.

[0107] In the next round of data updates, it is necessary to follow Figure 6 (b) shows the read / write operation performed by progressively increasing the original address, i.e., the order of new data writing / old data reading is 0b000→0b001→0b010→0b011……; in each subsequent round of data reading / writing, Figure 6 (a) and Figure 6(b) The operations are performed alternately, which means that for the same batch of data, the writing and reading order is reversed, thus effectively realizing the aggregation of the same group of data. To achieve the above process, the data rearrangement unit is equipped with a read / write address bit reversal module, which is used to generate inverted memory access and memory write addresses.

[0108] The data preprocessing module includes multiple parallel branch switching circuits configured in different modes and a series of shuffling units connected at different buffer depths. Each shuffling unit contains two multiplexers and two buffer units of the same depth.

[0109] The parallel branch switching circuit is used to implement the second bit-dimensional transformation. Specifically, it operates on the parallel dimension in formula (8), performing a complete bit reversal on the parallel dimension; after the data is read from the memory, the parallel branch of the circuit is changed to redirect the data stream to different shuffling unit ports. The corresponding transformation can be described by the following formula:

[0110]

[0111] Next, the third bit-dimensional transformation Simultaneously acting on both the parallel and serial dimensions in formula (8), this is the final permutation step before entering MDC computation, primarily used to change the block size. The internal index data order is determined by introducing a parameter h to determine when the permutation occurs between the parallel branches of row i and row i+h, where h ∈ [0, P]. Another parameter l represents the length of the delayed FIFO. The third bit-dimensional transformation is achieved by swapping the l′ = log2l bits of the serial sequence with the h′ = ... of the parallel sequence.

[0112] This is implemented using log2h bits, with specific parameters as follows:

[0113]

[0114] The hardware required to implement this permutation includes two FIFOs of length l and two multiplexers, connected to parallel branches in the i-th and i+h-th rows, respectively. However, only once... Transformation is insufficient to The output data is transformed into input data that meets the requirements. Therefore, in the first After the transformation, a series of shuffling circuits need to be added. This example constructs a mathematical model to determine the number of shuffling units in the combination and the specific values ​​of i and h in each permutation. Ultimately, it is concluded that the number of transformations in the third bit dimension can range from 0 to 6, expressed as...

[0115] To explain the third bit-dimensional transformation in detail, Table-1 lists the transformations for N=2. f This table lists the parameter configurations of a series of shuffling circuits required for the first stage (s=1) of a point FFT with parallelism P=1 and radix k=5. In the table, the symbol "\" indicates that the corresponding shuffling circuit is not required, and the symbol % represents the remainder.

[0116] Table 1

[0117]

[0118] In conclusion, This is used to generate an address based on formula (9) to read data from memory. Then, Used to exchange parallel branches. Then, a series of The combination of these parameters is used to adjust the index order to meet the input computation requirements of the MDC. Finally, the output data is transferred to adjacent memory in the parallel architecture or to the original memory in the memory architecture, serving as the input for the corresponding MDC.

[0119] Figure 7 An example is shown using a 4096-point data sequence x with a base of 2. 5 In the MDC unit, each detailed processing step in the data storage module and data preprocessing module initially stores 4096 data points in the data storage module according to the layout in block 7.1. Through reading from the data storage module and shuffling in the data preprocessing module, the data input into the MDC unit each time can conform to the FFT radix-2. 5 Data computation layout.

[0120] 4096 data points are processed using a pipeline architecture with a parallelism of 1, performing radix-2. 5 The FFT algorithm requires a total of 3 MDC modules, therefore s∈{1,2,3}. According to formula (3), when s=1, u=0, b 0,0 =x(0) is used as the first index element of the data block. Based on formulas (3) and (4), the index values ​​of the remaining elements can be deduced:

[0121] a 0,1 =x(u+d)=x(u+1024×(0×2+1))=x(1024)

[0122] a 1,0 =x(u+d)=x(u+1024×(1×2+0))=x(2048)

[0123] a 1,1 =x(u+d)=x(u+1024×(1×2+1))=x(3072)

[0124] At this point, the first line of MDC receives a time-domain sample block starting with index m=0, arranged as follows:

[0125]

[0126] Corresponding Appendix Figure 7 The data marked with a dashed box in block 7.2 of the Chinese map.

[0127] When s = 2, with b 0,0 =x(0) is used as the first identifier element of the data block. According to formulas (3) and (4), we have:

[0128] b 0,1 =x(u+d)=x(u+32×(0×16+1))=x(32)

[0129] b 0,2 =x(u+d)=x(u+32×(0×16+2))=x(64)

[0130] b 0,3 =x(u+d)=x(u+32×(0×16+3))=x(96) ...

[0132] b 0,15 =x(u+d)=x(u+32×(0×16+15))=x(480)

[0133] b 1,1 =x(u+d)=x(u+32×(1×16+1))=x(544)

[0134] b 1,2 =x(u+d)=x(u+32×(1×16+2))=x(576)

[0135] b 1,3 =x(u+d)=x(u+32×(1×16+3))=x(608) ...

[0137] b 1,15 =x(u+d)=x(s+32×(1×16+15))=x(992)

[0138] At this point, the first input matrix of the second row of MDC is:

[0139]

[0140] Corresponding Appendix Figure 7 The data marked with a dashed box in block 7.5 of the Chinese map.

[0141] Following this logic, when i = 3, the first input matrix of the third row of MDC is:

[0142] Corresponding Appendix Figure 7 The data marked with a dashed box in block 7.9 of the Chinese map.

[0143] It is not difficult to find that the appendix Figure 7 The 4096-point input data stored in the input buffer of the data storage module, represented by blocks 7.1, 7.3, and 7.6 in the middle diagram, does not meet the input requirements of the next-level MDC. Therefore, the aforementioned address reversal reading scheme, supplemented by an external shuffling unit, is used to adjust the order of the input data. Substituting into formulas (2) and (10), it can be seen that when the 4096-point calculation is completed, k1 = 2, k2 = 5, and k3 = 5. At this time... Substituting into formula (9), we can see that before the serial sequence sends data from the input buffer to the first row of MDC cells in the first stage of calculation, The last 11 bits of the address need to be reversed. (See attached diagram.) Figure 7 The four data points marked with dashed boxes in block 7.2 of the middle figure represent the 0th, 1024th, 2048th, and 3072nd data points in the input sequence. The serial sequence is processed before the data is transferred from the input buffer to the second row of MDC cells in the second stage of computation. The last 6 bits of the address need to be reversed, corresponding to the appendix. Figure 7 Within block 7.4 of the Chinese image; however, even after reading the data by reversing the address segment, it still does not conform to the specified format. The input arrangement is such that, therefore, this example also utilizes an additional external shuffling unit to adjust the local ordering of the data. As shown in the appendix... Figure 7 As shown in block 7.5, the data points are rearranged after passing through a delayed shuffling unit with a buffer depth of 16. In summary, the data rearrangement unit uses the method of reversing the address bits to read from memory and the function of multi-level shuffling units, allowing unordered data pairs to be sent to the MDC unit at specific intervals. It is worth noting that in the above example, since the parallelism P=1, the parallel branch switching circuit does not actually function.

[0144] Therefore, by performing the aforementioned address bit reversal data reading / writing and row transformation, it can be ensured that the sampled data points that meet the operation requirements of a single butterfly unit are effectively concentrated in the same area. Then, the final input order is adjusted within the area by the shuffling unit. This can minimize the shuffling depth, thereby reducing the length of the FIFO and reducing the hardware resource requirements.

[0145] The twiddle factors required for FFT calculations can be pre-stored in the ROM of the twiddle factor storage module and then read into the specific multiplication unit for use when needed. However, in some FPGA-based embodiments, under pipelined architecture computing modes, due to the limited Bram and URAM resources in the FPGA, when the radix k is greater than 4, assuming the number of points N to be calculated is greater than 2... 3k At that time, it is not possible to allocate multiple storage locations for N data items simultaneously, with each data item occupying 64 bits of storage space. Therefore, it is necessary to reduce the number of rotation factors pre-stored in the ROM.

[0146] On the other hand, the known base-2 k The algorithm can be derived from the Discrete Fourier Transform (DFT) of length N using the following equation:

[0147]

[0148] Among them W N It is the rotation factor, the superscript n is the time index, and η is the frequency index.

[0149] Specifically, taking k=5 as an example, we first perform a k+1=6-dimensional linear mapping decomposition on n and η:

[0150]

[0151] Substituting the variables from formula (17) into formula (16) yields:

[0152]

[0153] The decomposition expression for the twiddle factor is:

[0154]

[0155] Further expansion of formula (19) yields:

[0156]

[0157] Using the rotation factor merging method described in formula (20), the rotation factors are divided into three categories: constant rotation factor, nontrivial rotation factor, and trivial rotation factor. W is a constant rotation factor that can be pre-stored in ROM. N W is the nontrivial rotation factor associated with N, where -j denotes the trivial rotation factor. In this example, the rotation factor storage module only pre-stores the required portion of the nontrivial rotation factor W associated with N. N The data is then transmitted to the complex multiplier after the last butterfly unit in the MDC, where complex multiplication is performed on the non-trivial twiddle factor and the intermediate calculation results of the butterfly unit, as follows:

[0158] Base-2 k The configuration pattern of the multiplication units in each butterfly unit of the MDC module is closely related to the parity of the radix, such as... Figure 4 As shown in (a), when the base is odd, the first butterfly unit uses a constant rotation factor multiplication unit, followed by a trivial rotation factor multiplication unit in the second butterfly unit. The third butterfly unit again uses a constant rotation factor multiplication unit, consistent with the first unit. This alternating configuration continues until the last butterfly unit. It is noteworthy that the last butterfly unit uses a non-trivial rotation factor multiplication unit. In contrast, as... Figure 4 As shown in (b), when the radix is ​​even, the configuration sequence exhibits different initial patterns. The first butterfly unit uses a trivial twiddle factor multiplication unit, followed by the second butterfly unit using a constant twiddle factor multiplication unit. The third butterfly unit again uses a trivial twiddle factor multiplication unit. This alternating configuration of two different twiddle factors continues until the last butterfly unit. Regardless of whether the radix is ​​odd or even, the last butterfly unit uses a non-twiddle twiddle factor multiplication unit, which also makes the radix-2-based configuration... k The twitch factor multiplication unit in the algorithm's MDC module can perform radix reduction. When k1 < k, the algorithm (bypassing the first k-k1 butterfly operation units through a multiplexer) directly uses the data, for example, radix-2. 5 The MDC unit can execute base-2 4 Base-2 3 Base-2 2 algorithm.

[0159] Assuming the calculation of N points requires the simultaneous use of mixed bases... and base-2 k In the algorithm, if k1≤k, then in the first stage of computing the N-point FFT, the base is decomposed into k1+1 linear dimensions (time index n, frequency index η). Therefore, the last multiplication unit needs to be multiplied by a non-trivial twitch factor with base N. Subsequently, in the second stage of the computation, the N-point FFT can be decomposed into multiple smaller... Point FFT, then decompose the base k into k+1 linear dimensions, so the last multiplication unit in the second stage only needs to be multiplied by the base k. Multiply by the rotation factor, that is: Following this logic, it can be deduced that the rotation factor that needs to be pre-stored during the third stage of calculation is... Because, up to the last stage (the m-th stage), the number of rotation factors that need to be pre-stored is... Since it belongs to the constant rotation factor, the ROM occupied by storing only the constant rotation factor and the non-trivial rotation factor is much smaller.

[0160] For example, taking the calculation of N=512K points of data with a base of k=5 as an example, the above rotation factor reuse method will be explained in detail. It can be seen that performing a complete 512K calculation requires the simultaneous use of a mixed base-2. 4 and base-2 5 The algorithm (k1=4, k2=k3=k4=5) therefore requires the last multiplication unit in stage one to be multiplied by a nontrivial rotation factor with a base of 512K. After decomposing using formula (20), the 512K-point FFT can be simplified to a smaller 512K / 16 = 32K-point FFT. Therefore, in the second stage of the 512K calculation, the last multiplication unit only needs to be multiplied by a nontrivial twiddle factor with a base of 32K, i.e.: By analogy, it can be deduced that the rotation factor in the third stage is... The twitch factor for the fourth stage is It belongs to the constant rotation factor.

[0161] Compared to the previous allocation scheme, the rotation factor storage in the second stage is reduced by 4 times, and in the third stage by 9 times. By observing the data flow of the last butterfly unit in the second and third stages and comparing it with the 32K-point FFT data flow and the 1024-point FFT data flow, it can be found that the rotation factor is reused in blocks as the smallest unit, with each block containing 2 k Given N sample data points and an arbitrary radix k, the algorithm for generating the read address using the multiplexed rotation factor memory is as follows:

[0162]

[0163] The main function of the control module in this example is to generate control signals, selectively activate the MDC unit inside the FFT calculation module, activate the data rearrangement unit, generate the correct memory read and write addresses, and ensure that the data can be correctly loaded and processed and the results can be correctly calculated during the entire program operation.

[0164] The address generation module is used to generate addresses for the data rearrangement unit, the rotation factor storage module, and the output data buffer module using a program counter.

[0165] The output buffer module is responsible for outputting the results generated by the FFT calculation module to the external buffer unit.

[0166] The aforementioned base-2 5The FFT adaptive architecture with m=4 is compared with other storage architectures and pipelining architectures. Compared with the architectures in references [1], [2], and [3], the architecture proposed in this example can perform FFT operations at higher cardinality, and can support up to cardinality -2. 5 This architecture is suitable for scenarios involving large-scale data. A significant advantage of this architecture is its ability to support FFT computations with up to 1 million points, while other research works have a significantly lower maximum number of points than 1 million.

[0167] Table 2 shows the proposed cardinality-2. 5 This paper examines the differences in hardware overhead and computational performance between the proposed adaptive FFT architecture (m=4, P=4) and other storage architectures when using a different storage structure. Compared to previous studies, the number of iterations is reduced by 40%, and the parallelism of the FFT processor is increased, enabling simultaneous FFT computation in eight parallel input branches, thus improving the architecture's throughput. When processing the same number of points, the proposed storage architecture outperforms existing work due to its higher cardinality and parallelism, ultimately reducing execution time by 70% or more.

[0168] Table 2

[0169]

[0170] Table 3 lists the differences in average hardware resource utilization between the pipeline architecture designed in this paper and other pipeline architectures. To ensure the fairness of the experimental results comparison, it is assumed that the computational resource allocation is equal when completing 512K point operations. Based on the proposed radix-2... 5 The pipelined architecture uses twenty butterfly units, one of which is idle. This computational resource configuration is the same as in the literature. As can be seen from the table, most hardware resources are idle during small-scale FFT operations. In contrast, the pipelined architecture proposed in this work increases parallelism and activates idle hardware resources, ultimately improving utilization by 2 to 4 times within the same number of processing points, achieving a high-performance hardware design.

[0171] Table 3

[0172]

[0173] References:

[0174] [1]A Generalized Conflict-Free Memory Addressing Scheme for Continuous-Flow Parallel-Processing FFT Processors With Rescheduling, Pei-YunTsai, Chung-Yi Lin, et al. "IEEE Trans.Very Large Scale Integr.Syst.", Volume 19, Issue 12, Pages 2290-2302, 2011.

[0175] [2] Memory-Based FFT Architecture With Optimized Number of Multiplexers and Memory Usage, Z. Kaya et al., IEEE Trans.Circuits Syst. II, Exp. Briefs, Vol. 70, No. 8, pp. 3084-3088, August 2023.

[0176] [3]Scheduling of data access for the radix-2k FFT processor using single-port memory, J. Wang et al., IEEE Trans. Very Large Scale Integration (VLSI) Syst., Vol. 28, No. 7, pp. 1676-1689, July 2020.

Claims

1. An adaptive FFT processing processor module for processing large amounts of data, characterized in that, It includes an address generation module, a data rearrangement unit, a twitch factor storage module, an FFT calculation module, and a control module; The FFT computation module includes m row basis rows arranged side by side. MDC module; The data rearrangement unit includes a read / write data storage module and a data preprocessing module; The read / write data storage module consists of multiple memory units, each with a base- The MDC module corresponds to a specific memory, which is used to store data for input to the MDC module according to the settings; The data preprocessing module consists of multiple parallel branch switching circuits and multiple shuffling units of different depths. Each shuffling unit contains two multiplexers and two buffer units of the same depth, which are used to receive intermediate computation data from the read and write data storage module and further adjust the arrangement of the data to conform to the input data layout of the MDC module in the next FFT computation stage. The rotation factor storage module is used to store fixed constant rotation factors and to reuse the constant rotation factors according to the number of calculation points. The address generation module is used to generate address sequences for data reading / writing using the program counter; The control module is used to control the above modules / units to perform FFT calculations according to the following strategy: In the pipelined architecture mode, based on the number of FFT points to be processed and the parallelism P < m, multiple groups are cascaded through data rearrangement units, each group consisting of P rows of MDC modules, by writing the input data or the calculation output of the previous P-row MDC module into the memory corresponding to the next P-row MDC module. In the storage-based architecture mode, based on the number of FFT points to be processed and the parallelism P < m, the data calculated by the P rows of MDC modules in this stage is processed by the data rearrangement unit and then input back into the same group of P rows of MDC modules for the FFT calculation in the next stage. In the data rearrangement unit, the following strategy is used to adjust the arrangement of data: Let N = Let P be the number of points to be processed in the FFT and P be the parallelism. For any cardinality k, the index of each sample in a sample sequence is calculated using the following formula: ,in Indicates the first Units dimension Bit dimension change It is defined as changing the position of each bit dimension of the original by applying the same transformation rule. The detailed mathematical formula is as follows: in Indicates the transformed The bit value at each bit; One MDC module corresponds to a maximum cardinality of In the FFT algorithm computation stage, Calculate N-point FFTs within each stage, where This indicates a rounding up operation, where the actual base for each stage is... , The definition is as follows: In the s-th stage, a row of MDC modules will calculate sequentially. There are 1 data block, and each data block contains 1 data block. There are 1 set of input sample data to be processed, arranged as follows: matrix ,symbol This represents the u-th input block in the s-th stage, where u is the index number of the data block, as shown in the following formula: element subscript Let these represent the row and column indices of the data to be processed, respectively. Then it requires The other elements in the matrix and the index u must satisfy the following conditions: The constraints are set to ensure that the correct sample pairs are operated on in MDC. The expression for variable d is as follows: The range of values ​​for u in different stages s is as follows: And the increment symbol Defined as: in This represents a sequence starting from an integer a and increasing in step size i up to b; symbol In stage s, the process described above that changes in the data rearrangement unit is defined as follows: ,and It can be composed of three consecutive bit-dimensional changes, and its mathematical definition formula is as follows: in, This indicates the transformation of the bits in the later segment of the address when reading data from memory. This represents the parallel branch transformation in the data preprocessing module. This represents a series of shuffling unit transformations in the data preprocessing module; In the rotation factor storage module, based on the configured parameters k and N, a base of - is pre-stored. The constant rotation factor, the trivial rotation -j, and the nontrivial rotation factor related to the required partial base and the number of computational bits N are used to supply the various bases in the FFT computation. The MDC module can be called repeatedly as needed; The rotation factor storage module includes a multiplexed rotation factor memory, and the algorithm for generating the read address of the multiplexed rotation factor memory is as follows: make To read the address, if s=3, then let ,otherwise ; initialization It is an empty set, and it is enabled. arrive A loop with a step size of 1, each time... Within the loop, perform the following operation: Open arrive A loop with a step size of 1, each time... Within the loop, perform the following operation: Open arrive A loop with a step size of 1, each time... Within the loop, perform the following operation: Will the current Assign to Then put the current Save to ; After completing all the loops, the final result is obtained. .

2. The FFT operation processor module according to claim 1, characterized in that, In the strategy, the sequence is initially stored in In the memory location, the sampled data is placed in natural order, that is, in the first memory location... In memory, according to the data index Arrange in sequence; First, regarding the read / write transformation of memory addresses. The position of each indexed point can be represented as: in Parallel sequences This represents the memory identifier number, while the serial sequence determines the specific location of the data in memory, enabling read / write operations. The specific expression is as follows: Where the function This indicates concatenating two bit sequences, one ranging from u to v and the other from c to d. The operation... This indicates a bit reversal operation; These are variable parameters that indicate the positions to be reversed, such as:

3. The FFT operation processor module according to claim 2, characterized in that, The control module is configured to control the memory to perform read / write operations using the following strategy: If the memory is full of intermediate data, it needs to be loaded into the next row of MDC cells. The read address pointer RD loads data from the memory according to the position pointed to by the value of the reversed specified bit at the end of each address; at the same time, the write address pointer WT stores new data at the same position until the original data in the memory is completely replaced by the new data. In the next round of data updates, the read / write operations at the same address location must be performed in a progressively increasing manner according to the original address. In subsequent rounds of data reading / writing, read / write operations are performed alternately at the same address location based on either the address after bit reversal or the original address.

4. The FFT operation processor module according to claim 3, characterized in that, Parallel branch switching circuits are used to implement the second bit dimension transformation. The parallel dimension undergoes a complete bit reversal; after the data is read from memory, the parallel branch of the circuit is changed to redirect the data stream to different shuffling unit ports. The corresponding transformation is described by the formula:

5. The FFT operation processor module according to claim 4, characterized in that, Dimensional transformation This is accomplished through the shuffling unit, which operates simultaneously on both the parallel and serial dimensions.

6. The FFT operation processor module according to claim 1, characterized in that, The specific configuration of the nontrivial rotation factor includes letting It is the rotation factor, and the superscript n is the time index. ; First, let's consider n and... Perform k+1 dimensional linear mapping decomposition: Assuming the calculation of N points requires the simultaneous use of mixed basis points... and base- algorithm, but: In the first stage of computing an N-point FFT, the last multiplication unit requires a nontrivial twitch factor with a base of N. Pre-stored; In the second stage of computing the N-point FFT, the last multiplication unit only needs to be multiplied by the base. rotation factor It is pre-stored; The rotation factor that needs to be pre-stored during the third stage of calculation is: This process continues until the final stage, where the required pre-stored rotation factor is... It belongs to the constant rotation factor.

7. The FFT operation processor module according to claim 3, characterized in that, The data rearrangement unit also includes a read / write address bit reversal module, which is used to reverse a specified number of bits in the latter part of the read / write address given by the address generation module for the memory, according to a setting.

8. The FFT operation processor module according to claim 1, characterized in that, It also includes an output data buffer module, which is used to output the results generated by the FFT calculation module to an external buffer unit.

Images