Multi-substrate fixed floating point FFT (Fast Fourier Transform) processor with configurable length

Abstract

The invention provides a multi-substrate length-configurable fixed-floating-point FFT (Fast Fourier Transform) processor. The multi-substrate length-configurable fixed-floating-point FFT processor comprises a first RAM (Random Access Memory), a second RAM, a third RAM, a primary rearrangement unit, an FFT controller, a clock configuration unit, a fixed-floating-point multiplier / summator and a twiddle factor ROM (Read Only Memory) table, the first RAM is used for receiving external input serial data; the primary rearrangement unit is used for rearrangement; the clock configuration unit is used for outputting a plurality of multiple frequency clocks to the FFT controller; the FFT controller is used for controlling the data to be arranged, read and written; the fixed-point and floating-point multiplier / adder is used for carrying out fixed-point or floating-point FFT operation; the twiddle factor ROM table is used for pre-storing a plurality of twiddle factors required for calculating FFT (Fast Fourier Transform); and the third RAM and the second RAM are used for temporarily storing data in the base 2, base 4 or base 8 butterfly operation. The processor is simple in structure, adapts to processing in different length ranges and various application scenes, and is high in processing efficiency.

Description

Technical Field

[0001] This invention belongs to the field of digital signal processing, and specifically relates to a fixed-floating-point FFT processor with configurable lengths across multiple bases. Background Technology

[0002] The Fast Fourier Transform (FFT) is a powerful algorithm that converts time-domain data into a frequency-domain representation, enabling us to analyze the frequency components of signals or datasets. The FFT is widely used in signal processing, data analysis, and image processing, revealing hidden frequencies within signals—crucial for accurate signal analysis in various engineering applications.

[0003] Existing FFT processors are efficient at processing single-packet data within a certain length range, but they cannot handle different length ranges, different implementation methods (single-packet processing and pipelined processing), and different data processing methods (fixed-point arithmetic and floating-point budgeting) simultaneously.

[0004] How to design an FFT processor that can handle different length ranges and adapt to various application scenarios is a problem that urgently needs to be solved. Summary of the Invention

[0005] In view of this, the present invention provides a multi-base configurable length fixed-floating-point FFT processor to address the shortcomings of the prior art.

[0006] To achieve the above objectives, the present invention adopts the following technical solution:

[0007] This invention provides a multi-base configurable length fixed-float FFT processor, including: a first RAM, a second RAM, a third RAM, an initial rearrangement unit, an FFT controller, a clock configuration unit, a fixed-float multiplier / adder, and a rotation factor ROM table;

[0008] The first RAM is used to store the received external input serial data sequentially according to the external low-frequency clock signal. After the data is full, the FFT controller is triggered to start the FFT calculation.

[0009] The initial rearrangement unit is used to read the data stored in the first RAM, rearrange it according to a preset time, and then store it in the second RAM;

[0010] The third RAM and the second RAM together form a ping-pong storage for temporarily storing data in the FFT butterfly operation;

[0011] The clock configuration unit uses a phase-locked loop to multiply the input low-frequency clock signal and outputs multiple multiplied frequency clocks to the FFT controller.

[0012] The fixed-point / floating-point multiplier / adder is used to perform fixed-point or floating-point FFT operations on the input data and then output the results to the FFT controller.

[0013] The rotation factor ROM table is used to pre-store the complex rotation factors required for calculating the FFT and provides high-speed lookup access during the calculation process;

[0014] The third RAM and the second RAM together form a ping-pong storage for temporarily storing data in radix-2, radix-4 or radix-8 butterfly operations;

[0015] The FFT controller inputs the received data, complex twitch factor, and clock signal to the fixed-floating-point multiplier / adder, and completes the FFT operation on the input signal by controlling the data arrangement, reading, writing, and temporary storage.

[0016] Furthermore, the FFT controller includes: a state machine, a radix-2 kernel processing unit, a radix-4 kernel processing unit, and a radix-8 kernel processing unit; the state machine calls different kernel processing units to process the data according to the control signal and the data length, when the data length is 8... N1 When N1 is an integer greater than 2, it is processed using a radix-8 core processing unit; when the data length is 4... N2 When N2 is an integer greater than 1, it is processed using a radix-4 kernel processing unit; when the data length is 2... N3 When N3 is an integer greater than 1, it is processed using a radix-2 kernel processing unit; when the data length is suitable for multiple kernel processing units, the kernel processing unit with the larger value is used first.

[0017] Furthermore, it also includes a pipelined cache RAM; the processor supports single-packet data processing and pipelined processing. When pipelined processing is performed, the pipelined cache RAM is used for data caching during pipelined processing; and the clock configuration unit generates different clock frequencies, with a high-frequency clock used for butterfly operation processing and multiplication / addition processing, and a low-frequency clock used for serial data input.

[0018] Furthermore, the clock configuration unit generates different clock frequencies, including configuring a high-frequency clock and a low-frequency clock, satisfying the following condition: the time for serial input of a data packet under the low-frequency clock is the same as the time for completing data processing under the control of the high-frequency clock.

[0019] Furthermore, the fixed-point / floating-point multiplier / adder controls whether to perform fixed-point or floating-point operations via a single data bit at the port. The multiplication / addition modules required for fixed-point and floating-point operations are independent of each other. The data operation process is as follows: a valid pulse signal and two data points arrive at the fixed-point / floating-point multiplier / adder at the same time. The valid pulse signal is ANDed with the fixed-point / floating-point control signal to make the fixed-point or floating-point operation module valid. After the calculation is completed, the fixed-point / floating-point operation module provides a valid end pulse signal, and the FFT controller receives the signal and continues to work.

[0020] Furthermore, the initial rearrangement unit, which reads the data stored in the first RAM, rearranges it according to a preset order, and then stores it in the second RAM, specifically includes:

[0021] If the first RAM cache data uses a width of M bits and a depth of N;

[0022] In radix-2 and radix-8 operations, both the second RAM and the third RAM are divided into 2 or 8 storage blocks of length M and depth N / 2 or N / 8. The data in the first RAM is sequentially divided into 2 or 8 parts and stored into 2 or 8 storage blocks in sequence. That is, data is preferentially written to the RAM block with the lowest bit number first, and the writing is done from the low address to the high address. After the highest address is written, the data is written to the next RAM block with the highest bit number.

[0023] In the radix-4 operation, both the second RAM and the third RAM are divided into four storage blocks of length M and depth N / 4. The first four data are stored in the lowest address of the storage block, and the address of the subsequent data is stored in the next higher address. That is, data is first written to multiple RAM blocks at lower addresses in sequence, and after multiple RAM blocks at the same address are written, the next RAM block at a higher address is written.

[0024] Furthermore, the third RAM and the second RAM constitute ping-pong storage for temporarily storing data in the FFT butterfly operation. Specifically, this includes: retrieving data stored in the second RAM, performing the FFT operation, and then storing it in the third RAM according to a preset read / write rule to complete the first layer of operation; then retrieving data stored in the third RAM, performing the FFT operation, and then storing it in the second RAM according to the preset read / write rule to complete the second layer of operation, and so on, until all processing is completed after K layers; wherein in the radix-2 operation, the data length is 2. K In radix-4 operations, the data length is 4. K In radix-8 operations, the data length is 8. K And so on.

[0025] Furthermore, the radix-2 operation reads the data from the second RAM or the third RAM, performs an FFT operation, and then writes it back to the address corresponding to the third RAM or the second RAM, meaning the read and write addresses remain unchanged.

[0026] Furthermore, the radix-4 operation read / write rules are as follows:

[0027] The reading rule for radix-4 is as follows: each time data is read, it is read in blocks of RAM at the same address, sequentially from low address to high address;

[0028] The radix-4 write rules are as follows: When writing the first four data entries from the first layer, the block number remains unchanged, only the address changes. The write address offsets for the first to fourth entries are 0, 1, 2, and 3, respectively. When writing the second four data entries from the first layer, they immediately follow the block number after the first data entry, i.e., the data is shifted one position higher in the block number. This process continues until the fourth read completes one cycle of writing 16 data entries. Then, the above operation is repeated to complete the operation of the next 16 data entries, and so on.

[0029] In the nth layer (n>1), the first four data entries read have the same block number but different addresses during writing. The write address offset for the first to fourth data entries is 0 and 1*4, respectively. n-1 2*4 n-1 3*4 n-1 The second read of the four data items in the second layer retains the same block number but changes the address during writing. The write address offset for the first to fourth data items is the previous offset of 0 and 1*4. n-1 2*4 n-1 3*4 n-1 Moving one bit to the right corresponds to a write address offset of 3*4. n-1 0, 1*4 n-1 2*4 n-1 The address offset and data shift operations are both overflow-free cyclic shifts, the 4th... n-1 When writing the 4 data reads in the +1st read, the block number of the data is shifted one bit to the higher position of the block number;

[0030] The smallest unit of data processing in the nth layer is 4 blocks, and each 4 blocks... n The second layer of data processing consists of 4 consecutive addresses; the smallest unit of data processing is 4 blocks and 16 consecutive addresses; and so on until all data is read and written.

[0031] Furthermore, the radix-8 operation read / write rules are as follows:

[0032] The read rules for radix-8 are as follows: During the first level of operation, data is read sequentially from the same address in different RAM blocks, and then the next same address in different RAM blocks is read, sequentially from low address to high address; subsequent level operations follow the same write rules as the previous level; the offset shift rules for data reading and writing are the same to ensure that the data read in the next level is in the same order as the data written in the previous level.

[0033] The rules for writing radix-8 are as follows:

[0034] S1: Permutation operation: Arrange all data in ascending order, represented by the number idx;

[0035] S2.1: Move operation: Move the data that was just arranged in order backward in a loop without overflow. The data corresponding to the last data number idx is moved to the position of the data corresponding to the first data number idx, and the remaining data numbers idx are moved backward in sequence.

[0036] S2.2: Re-shift operation: The number of writes cycles in cycles of 8. In the first cycle, S2.1 shifts forward once, in the second cycle, S2.1 shifts forward twice, and so on.

[0037] S3: Write operation: Divide the data number idx by 8 to get the actual address, fill the first data into the address space of idx / 8 of the first block of RAM, and write the remaining data into the subsequent blocks according to this rule;

[0038] In the above read and write operations, the difference between the first-level idx is 8. N1 / 8, the difference in IDX at the second level is 8. N1 / 64, the third-level IDX is 8 N1 / 512, and so on, until the difference in idx at the last level is 1; after all the level operations are completed, the binary bit reversal address conversion is finally performed.

[0039] The multi-base configurable length fixed-point FFT processor provided in this application has a simple structure and can effectively improve processing efficiency. The original radix-2 calculation can meet the FFT calculation requirements. This application adds radix-4 and radix-8 processing, which can effectively improve the calculation speed. At the same time, it adopts a reasonable arrangement, especially optimizing the FFT length range of 8 to 32768 used in navigation audio. Different bases are used for different lengths, which not only improves the calculation speed, but also does not significantly increase the hardware area, thus saving hardware resources.

[0040] This application supports both fixed-point and floating-point computation. Specifically, the multiplication and addition modules required for both fixed-point and floating-point operations are separated, and the data bit width is fixed. This allows 32-bit data to represent both fixed-point numbers and IEEE single-precision floating-point numbers without increasing area or computational resources, while simultaneously enabling both fixed-point and floating-point computations. Furthermore, this patent can meet the requirements of single-packet or pipelined computations. By setting different internal and external clock frequencies, the next packet of data can be written while the current data is being computed, completing pipelined computation. When single-packet FFT computation is required, simply adjusting the internal and external clock frequencies to ensure they are at the same frequency allows the system to compute the single-packet FFT. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 This is a schematic diagram of the device in the system according to the patent.

[0043] Figure 2 This is a schematic diagram of the FFT controller.

[0044] Figure 3 This is a diagram illustrating data operations for radix-2 operations.

[0045] Figure 4 A diagram illustrating data operations for radix-4. Detailed Implementation

[0046] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0047] To make the technical solutions and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this invention, not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this invention.

[0048] like Figure 1As shown, this embodiment of the invention provides a multi-base configurable length fixed-floating-point FFT processor, which includes: a first RAM (RAM0), a second RAM (RAM1), a third RAM (RAM2), an initial rearrangement unit, an FFT controller, a clock configuration unit, a fixed-floating-point multiplier / adder, and a rotation factor ROM table.

[0049] The first RAM (RAM0) is used to sequentially store the received external input serial data according to the external low-frequency clock signal. After the data is full, the FFT controller is triggered to start the FFT calculation. The initial rearrangement unit is used to read the data stored in the first RAM, rearrange it according to a preset time, and then store it in the second RAM. The third RAM and the second RAM form a ping-pong storage for temporarily storing data in the FFT butterfly operation. The clock configuration unit is used to multiply the input low-frequency clock signal using a phase-locked loop and output multiple multiplied frequency clocks to the FFT controller. The FFT controller is used to control the data arrangement, reading, and writing operations. The fixed-point and floating-point multipliers / adders are used to perform fixed-point or floating-point FFT operations on the input data and output them to the FFT controller. The rotation factor ROM table is used to pre-store the complex rotation factors required for FFT calculation and provide high-speed lookup access during the calculation process. The third RAM and the second RAM form a ping-pong storage for temporarily storing data in radix-2, radix-4, or radix-8 butterfly operations. The FFT controller receives data, complex twitch factors, and clock signals, which are then input to the fixed-point multiplier / adder. By controlling the arrangement, reading, writing, and temporary storage of the data, it completes the FFT operation on the input signal.

[0050] like Figure 2 As shown, the FFT controller includes a state machine, a radix-2 kernel processing unit, a radix-4 kernel processing unit, and a radix-8 kernel processing unit. The state machine calls different kernel processing units to process the data according to the control signal and the data length. When the data length is 512, 4096, or 32768, the radix-8 kernel processing unit is used for processing; when the data length is 16, 64, 256, 1024, or 16384, the radix-4 kernel processing unit is used for processing; and when the data length is 8, 32, 128, 2048, or 8192, the radix-2 kernel processing unit is used for processing.

[0051] The third RAM (RAM2) and the second RAM (RAM1) constitute ping-pong storage. Ping-pong storage is a high-efficiency hardware storage technology that utilizes alternating operation of two buffers to achieve seamless data flow, specifically designed to solve the bottleneck of processing high-speed continuous data streams. By switching roles between the two storage areas, data write and read operations are completely isolated in time or space, thereby eliminating access conflicts and maximizing throughput. Ping-pong storage, through a hardware-level dual-buffering alternation mechanism, completely solves the storage access conflict problem in high-speed data stream scenarios, while also providing increased throughput and real-time performance guarantees.

[0052] The twiddle factor ROM table is used to pre-store the complex twiddle factors required for FFT computation and provides high-speed lookup access during computation, thereby avoiding real-time calculation of trigonometric functions and greatly improving the efficiency and speed of hardware implementation. By pre-calculating, quantizing, and storing the twiddle factors, the required complex multipliers can be obtained through simple address lookup during FFT computation, thus avoiding time-consuming real-time trigonometric calculations and significantly improving computation speed and hardware resource utilization.

[0053] The processor supports single-packet data processing and pipelined processing. For pipelined processing, an additional pipelined cache RAM is required. During pipelined processing, the pipelined cache RAM serves as a data buffer. The clock configuration unit generates different clock frequencies to create time differences: a high-frequency clock is used for butterfly operations and multiplication / addition, while a low-frequency clock is used for serial data input. When performing continuous FFTs, the time taken to perform a butterfly FFT on the previous packet is less than or equal to the time taken to serially write the next packet to RAM0. This ensures that the computation of a single packet is completed within a specific time window.

[0054] Because the required clock cycles differ depending on the computation length, different clock frequencies are needed to compute different lengths. For example, for a radix-8 operation with a length of 4096, a reasonable internal-to-external clock ratio is 1:2.5, meaning the internal clock frequency needs to be at least 2.5 times that of the external clock to complete the computation of one data packet within the time it takes to write one data packet. For a radix-8 operation with a length of 32768, the internal clock frequency needs to be 5.5 times that of the external clock frequency to complete the computation. Therefore, this is addressed by adding a pipelined cache RAM and using different operating frequencies to achieve system versatility.

[0055] The fixed-point / floating-point multiplier / adder controls whether to perform fixed-point or floating-point operations via a single data bit at its port. The multiplication / addition modules required for fixed-point and floating-point operations are independent of each other, and the data bit width is fixed at 32 bits or 64 bits. The data operation process is as follows: a valid pulse signal and two data bits arrive at the fixed-point / floating-point multiplier / adder simultaneously. The valid pulse signal is ANDed with the fixed-point / floating-point control signal to activate either the fixed-point or floating-point operation module. After the calculation is complete, the fixed-point / floating-point operation module provides a valid end pulse signal, which the FFT controller receives and continues operation. The fixed-point multiplier / adder can use existing Designware IP or a custom-designed fixed-point multiplier / adder. The floating-point multiplier / adder is designed according to the IEEE single-precision floating-point standard.

[0056] The following description covers both clock flow and data flow.

[0057] 1. Clock Flow

[0058] This application can perform both single-packet and pipelined modes, thus requiring clock groups and related control signals to adjust the system. For example, in a radix-8 4096FFT calculation, the clock entering the PLL is 50MHz, while the clock exiting the PLL must be at least twice the frequency of the entering clock. This ensures that the time to write data to RAM0 is slightly longer than the time for the FFT core to perform the calculation, achieving a suitable clock ratio for pipelined operation. In the single-packet calculation mode of the 4096FFT, the calculation clock of the FFT core and the input clock frequency are synchronized.

[0059] The current design uses a 50MHz input clock, which, after passing through the PLL, outputs five frequencies: 50MHz, 100MHz, 150MHz, 200MHz, and 300MHz. The output clock frequencies are 1-6 times the input clock frequency. Once the FFT calculation length is determined, a selector selects the corresponding clock input to the FFT controller.

[0060] 2. Data Flow

[0061] Part 1: This application employs multiple RAMs for data transmission. RAM0 serves as the data receiving RAM, receiving an external low-frequency clock and writing data into RAM0. The following example illustrates this using data with a length of 64 bits and a depth of 32768. Data is written sequentially in ascending order. Once all data is written to RAM0, the state machine starts the FFT controller. The FFT controller uses a high-frequency clock or the same frequency clock (depending on whether it's single-packet or pipelined computation) to begin reading data from RAM0 for the next processing step.

[0062] After the data is read from RAM0, it will be initially rearranged and then written to RAM1 (RAM1 / RAM2 uses 8 RAM storage blocks with a length of 64*4096, which are labeled [63:0], [127:64], [191:128], [255:192], [319:256], [383:320], [447:384], [511:448] in the following text to replace the branch block numbers ram0,1,2,3,4,5,6,7 in RAM1 / 2).

[0063] Radix-2 operations do not require rearrangement; data can be directly written to RAM1 in sequence. In the radix-2 calculation, the first data is written to address 0 of RAM[63:0], the second data is written to address 1 of RAM[63:0], the third data is written to address 2 of RAM[63:0], and so on. The 4096th data is written to address 4095 of RAM[63:0], the 4097th data is written to address 0 of RAM[127:64], and so on. The 8193rd data is written to address 0 of RAM[191:128].

[0064] The radix-4 calculation requires rearrangement (regardless of length). The writing rules are shown in Table 1 below. The 1st, 2nd, 3rd, and 4th data (represented by the label idx starting from 0 in the table, the same below) are written to the 0th address of ram[63:0],[127:64],[191:128],[255:192] in sequence. The 5th, 6th, 7th, and 8th data are written to the 1st address of ram[63:0],[127:64],[191:128],[255:192] in sequence, and so on. The addresses of ram[319:256],[383:320],[447:384], and[511:448] can be appended to the preceding ram as concatenated addresses.

[0065] Table 1. Initial rearrangement of base 4

[0066] [63:0] [127:64] [191:128] [255:192] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

[0067] The radix-8 also needs to be rearranged, and the writing rules are as follows: When the length is 8n, the first data is written to address 0 of ram[63:0], the (n+1)th data is written to address 0 of ram[127:64], and so on until the (7n+1)th data is written to address 0 of ram[511:448], the second data is written to address 1 of ram[63:0], the (n+2)th data is written to address 1 of ram[127:64], and so on until the (7n+2)th data is written to address 1 of ram[511:448], and so on.

[0068] The radix-8 reordering with a length of 4096 is written according to the following rules (Table 2): The first data is written to address 0 of RAM[63:0], the 513th data is written to address 0 of RAM[127:64], the 1025th data is written to address 0 of RAM[191:128], and so on until the 3585th data is written to address 0 of RAM[511:448]. The second data is written to address 1 of RAM[63:0], the 514th data is written to address 1 of RAM[127:64], and so on until the 3586th data is written to address 1 of RAM[511:448], and so on. All data is written to RAM1.

[0069] Table 2 shows the initial rearrangement of a radix-8 FFT with a length of 4096.

[0070]

[0071]

[0072] The write rules for a radix-8 reordered array with a length of 32768 are shown in Table 3 below: The first data is written to address 0 of RAM[63:0], the 4097th data is written to address 0 of RAM[127:64], the 8193rd data is written to address 0 of RAM[191:128], and so on until the 28673rd data is written to address 0 of RAM[511:448]. The second data is written to address 1 of RAM[63:0], the 4098th data is written to address 1 of RAM[127:64], and so on until the 28674th data is written to address 1 of RAM[511:448]. This process continues until all data is written to RAM1.

[0073] Table 3 shows the initial rearrangement of a radix-8 FFT with a length of 32768.

[0074] [63:0] [127:64] [191:128] [255:192] [319:256] [383:320] [447:384] [511:448] 0 4096 8192 12288 16384 20480 24576 28672 1 4097 8193 12289 16385 20481 24577 28673 2 4098 8194 12290 16386 20482 24578 28674

[0075] Part Two: After all data is written according to the initial arrangement rules, the first-level calculation begins. Because of the rearrangement, each time only the same address of each small RAM block needs to be extracted, and the retrieved data is calculated according to the calculation rules. (The radix-2 kernel does not perform rearrangement because it only needs to retrieve the data twice).

[0076] The general formula for calculating radix-2 is as follows: x m (p) represents the upper node value of the input for the m-th stage butterfly operation, x m (q) represents the next node value of the m-th level butterfly operation input. x is the rotation factor. m+1(p) represents the value of the upper node output by the (m+1)th level butterfly operation. A schematic diagram of the radix-2 operation is shown below. Figure 3 As shown.

[0077] Level: The N-point units are first divided into two N / 2-point DFTs, then four N / 4-point DFTs, then eight N / 8-point DFTs, and so on, up to N / 2 two-point DFTs. Each division is called a "level" operation. Group Level: The N / 2 butterfly units in each level can be divided into several groups, each group having the same structure and twiddle factor distribution. For example, level m=0 is divided into four groups, level m=1 into two groups, and level m=2 into one group.

[0078] Radix 2 and radix 4 are calculated according to a general formula. The difference between radix 2 and radix 4 is that radix 4 adds rearrangement, which allows the hardware to read data at the same address at one time when reading and write data at multiple addresses at one time when writing data.

[0079] The general formula for calculating radix-4 is as follows:

[0080]

[0081] x(n), X(4r), X(4r+2), X(4r+1), and X(4r+3) are the upper node values ​​of the nth stage butterfly operation input, respectively. is the rotation factor.

[0082] A diagram illustrating radix-4 operation is shown below. Figure 4 As shown.

[0083] The subsequent read / write rules for radix-4 are as follows: When writing the first four data entries read in the first layer, the block number remains unchanged, only the address changes. The write address offsets for the first to fourth data entries are 0, 1, 2, and 3, respectively. When writing the second four data entries read in the first layer, the data immediately follows the block after the first data entry, i.e., the data is shifted one position to the right. This process continues until the fourth data entry read in the first layer is written.

[0084] The read / write order of the first layer of radix 4 is shown in Table 4 below. The data read in the first layer are 0, 1, 2, 3 (idx). When writing, the address of the second number is increased by 1, the address of the third number is increased by 2, and the address of the fourth number is increased by 3. The data read in the first layer are 4, 5, 6, 7 (idx). When writing, idx 4 is written to the 0th address of [127:64], idx 5 is written to the 1st address of [191:128], idx 6 is written to the 2nd address of [255:192], and idx 7 is written to the 3rd address of [63:0]. The data is written to RAM in this order.

[0085] Table 4 shows the first layer read / write order of Base 4.

[0086] [63:0] [127:64] [191:128] [255:192] 0 4 8 12 13 1 5 9 10 14 2 6 7 11 15 3 16 20 24 28 29 17 21 25 26 30 18 22 23 27 31 19

[0087] The read / write order of the second layer of radix 4 is shown in Table 5 below. The idx values ​​read in the first layer of the second layer are 0, 4, 8, 12, and after calculation, they are written to the RAM at addresses 0 of [63:0], 4 of [127:64], 8 of [191:128], and 12 of [255:192], respectively. The idx values ​​read in the second layer are 1, 5, 9, 13, and after calculation, they are written to the RAM at addresses 1 of [127:64], 5 of [191:128], 9 of [255:192], and 13 of [63:0], respectively.

[0088] Table 5. Second Layer Read / Write Sequence of Base 4

[0089] [63:0] [127:64] [191:128] [255:192] 0 16 32 48 49 1 17 33 34 50 2 18 19 35 51 3 52 4 20 36 37 53 5 21 22 38 54 6 7 23 39 55 40 56 8 24 25 41 57 9 10 26 42 58 59 11 27 43 28 44 60 12 13 29 45 61 62 14 30 46 47 63 15 31

[0090] The formula for calculating radix-8:

[0091] The group-level calculation of radix-8 reads 8 numbers at once and performs the following calculations, which are divided into 4 steps in total.

[0092] p0[0].Re=x[0].Re+x[4].Re; p0[0].Im=x[0].Im+x[4].Im

[0093] p0[1].Re=x[1].Re+x[5].Re; p0[1].Im=x[1].Im+x[5].Im;

[0094] p0[2].Re=x[2].Re+x[6].Re; p0[2].Im=x[2].Im+x[6].Im;

[0095] p0[3].Re=x[3].Re+x[7].Re; p0[3].Im=x[3].Im+x[7].Im;

[0096] p0[4].Re=x[0].Re-x[4].Re; p0[4].Im=x[0].Im-x[4].Im;

[0097] p0[5].Re=x[1].Re-x[5].Re; p0[5].Im=x[1].Im-x[5].Im;

[0098] p0[6].Re=(x[2].Im-x[6].Im)*inv_val;

[0099] p0[6].Im=(x[6].Re-x[2].Re)*inv_val;

[0100] p0[7].Re=(x[3].Im-x[7].Im)*inv_val;

[0101] p0[7].Im=(x[7].Re-x[3].Re)*inv_val;

[0102] x represents the eight input values, RE is the real part, Im is the imaginary part, inv_val equals -1, and p0 is the result of the first layer computation.

[0103] p1[0].Re=p0[0].Re+p0[2].Re; p1[0].Im=p0[0].Im+p0[2].Im;

[0104] p1[1].Re=p0[1].Re+p0[3].Re; p1[1].Im=p0[1].Im+p0[3].Im;

[0105] p1[2].Re=p0[0].Re-p0[2].Re; p1[2].Im=p0[0].Im-p0[2].Im;

[0106] p1[3].Re=(p0[1].Im-p0[3].Im)*inv_val;

[0107] p1[3].Im=(p0[3].Re-p0[1].Re)*inv_val;

[0108] p1[4].Re=p0[4].Re+p0[6].Re; p1[4].Im=p0[4].Im+p0[6].Im;

[0109] p1[6].Re=p0[4].Re-p0[6].Re; p1[6].Im=p0[4].Im-p0[6].Im;

[0110] p1_t0.Re=(p0[5].Re+p0[7].Re)*181+(p0[5].Im+p0[7].Im)*inv_val*181;

[0111] p1_t0.Im=(p0[5].Im+p0[7].Im)*181-(p0[5].Re+p0[7].Re)*inv_val*181;

[0112] p1_t1.Re=(p0[5].Re-p0[7].Re)*(-181)+(p0[5].Im-p0[7].Im)*inv_val*181;

[0113] p1_t1.Im=(p0[5].Im-p0[7].Im)*(-181)-(p0[5].Re-p0[7].Re)*inv_val*181;

[0114] p0 is the result of the previous layer, which is used as the input of the second layer. There are a total of 8 values: RE is the real part, Im is the imaginary part, inv_val is equal to -1, 181 is a fixed parameter, and p1 is the result of the first layer calculation.

[0115] p2[0].Re=p1[0].Re+p1[1].Re; p2[0].Im=p1[0].Im+p1[1].Im;

[0116] p2[1].Re=p1[0].Re-p1[1].Re; p2[1].Im=p1[0].Im-p1[1].Im;

[0117] p2[2].Re=p1[2].Re+p1[3].Re; p2[2].Im=p1[2].Im+p1[3].Im;

[0118] p2[3].Re=p1[2].Re-p1[3].Re; p2[3].Im=p1[2].Im-p1[3].Im;

[0119] p2[4].Re=p1[4].Re+p1[5].Re; p2[4].Im=p1[4].Im+p1[5].Im;

[0120] p2[5].Re=p1[4].Re-p1[5].Re; p2[5].Im=p1[4].Im-p1[5].Im;

[0121] p2[6].Re=p1[6].Re+p1[7].Re; p2[6].Im=p1[6].Im+p1[7].Im;

[0122] p2[7].Re=p1[6].Re-p1[7].Re; p2[7].Im=p1[6].Im-p1[7].Im;

[0123] P1 is the result of the previous layer, which serves as the input for the third layer. It has a total of 8 values: RE is the real part, Im is the imaginary part, and p2 is the result of the first layer calculation.

[0124] Finally, multiply each p2 value by its corresponding FFT_COSSIN value.

[0125] X.Re=p2.Re*FFT_COSSIN.Re-p2.Im*FFT_COSSIN.Im;

[0126] X.Im=p2.Im*FFT_COSSIN.Re+p2.Re*FFT_COSSIN.Im;

[0127] Hierarchical data flow:

[0128] Taking a length of 4096 as an example, after the first layer of FFT calculation, the obtained values ​​0, 512, 1024, 1536, 2048, 2560, 3072, and 3584 will be written into the third RAM (ram2) according to the following rules. Because the length is 4096, it is divided into 8 parts and stored in ram, meaning that only 512 addresses are used in the ram. Therefore, when writing to ram, the addresses need to be rearranged (1. Shift: move the data to the right each time it is stored. 2. Divide idx by 8 to get the actual address).

[0129] As shown in Table 6 below, idx0 is written to address 0 of [63:0], idx512 is written to address 64 of [127:64], idx1024 is written to address 128 of [191:128], idx1536 is written to address 192 of [255:192], idx2048 is written to address 256 of [319:256], idx2560 is written to address 320 of [383:320], idx3072 is written to address 384 of [447:384], and idx3584 is written to address 448 of [511:448]. idx1 is written to address 0 of [127:64], idx513 is written to address 64 of [191:128], idx1025 is written to address 128 of [255:192], idx1537 is written to address 192 of [319:256], idx2049 is written to address 256 of [383:320], idx2561 is written to address 320 of [447:384], idx3073 is written to address 384 of [511:448], and idx3585 is written to address 448 of [63:0], and so on. Similarly, idx8 is written to address 1 of [127:64], idx520 is written to address 65 of [191:128], idx1032 is written to address 129 of [255:192], idx1544 is written to address 193 of [319:256], idx2056 is written to address 257 of [383:320], idx2568 is written to address 321 of [447:384], idx3080 is written to address 385 of [511:448], and idx3592 is written to address 449 of [63:0].

[0130] Table 6-1 First Layer IDX Table for 4096-Point Base-8 FFT

[0131] [63:0] [127:64] [191:128] [255:192] [319:256] [383:320] [447:384] [511:448] 0 512 1024 1536 2048 2560 3072 3584 3585 1 513 1025 1537 2049 2561 3073 3074 3586 2 514 1026 1538 2050 2562 2563 3075 3587 3 515 1027 1539 2051 2052 2564 3076 3588 4 516 1028 1540 1541 2053 2565 3077 3589 5 517 1029 1030 1542 2054 2566 3078 3590 6 518 519 1031 1543 2055 2567 3079 3591 7 3592 8 520 1032 1544 2056 2568 3080 3081 3593 9 521 1033 1545 2057 2569 2570 3082 3594 10 522 1034 1546 2058

[0132] Table 6-2 Actual Storage Addresses of the First Layer of a 4096-Point Base-8 FFT

[0133]

[0134]

[0135] Tables 6-2 and 6-1 are reference tables, where idx and the actual storage address correspond one-to-one.

[0136] The idx difference for the first-level group data is 512; the idx difference for the second-level group data is 64; the idx difference for the third-level group data is 8; and the idx difference for the fourth-level group data is 1.

[0137] As shown in Table 7 below, idx0 is written to address 0 of [63:0], idx64 is written to address 8 of [127:64], idx128 is written to address 16 of [191:128], idx192 is written to address 24 of [255:192], idx256 is written to address 32 of [319:256], idx320 is written to address 40 of [383:320], idx384 is written to address 48 of [447:384], and idx448 is written to address 56 of [511:448].

[0138] Table 7-1 Second-layer IDX table for 4096-point basal 8FFT

[0139] [63:0] [127:64] [191:128] [255:192] [319:256] [383:320] [447:384] [511:448] 0 64 128 192 256 320 384 448 449 1 65 129 193 257 321 385 386 450 2 66 130 194 258 322 323 387 451 3 67 131 195 259 260 324 388 452 4 68 132 196 197 261 325 389 453 5 69 133 134 198 262 326 390 454 6 70 71 135 199 263 327 391 455 7 456 8 72 136 200 264 328 392 393 457 9 73 137 201 265 329 330 394 458 10 74 138 201 266

[0140] Table 7-2 Actual Storage Addresses of the Second Layer of a 4096-Point Base-8 FFT

[0141]

[0142]

[0143] Tables 7-2 and 7-1 are reference tables, where idx and the actual storage address correspond one-to-one.

[0144] As shown in Table 8 below, idx0 is written to address 0 of [63:0], idx8 is written to address 1 of [127:64], idx16 is written to address 2 of [191:128], idx24 is written to address 3 of [255:192], idx32 is written to address 4 of [319:256], idx40 is written to address 5 of [383:320], idx48 is written to address 6 of [447:384], and idx56 is written to address 7 of [511:448].

[0145] Table 8. Comparison of the third-layer idx and actual storage address of a 4096-point radix-8 FFT.

[0146] [63:0] [127:64] [191:128] [255:192] [319:256] [383:320] [447:384] [511:448] 0 8 16 24 32 40 48 56 0 1 2 3 4 5 6 7 57 1 9 17 25 33 41 49 7 0 1 2 3 4 5 6 6 7 0 1 2 3 4 5 5 6 7 0 1 2 3 4 4 5 6 7 0 1 2 3 3 4 5 6 7 0 1 2 2 3 4 5 6 7 0 1 1 2 3 4 5 6 7 0 15 8 9 10 11 12 13 14 14 15 8 9 10 11 12 13 13 14 15 8 9 10 11 12

[0147] Table 8 shows the idx values ​​for the first and third layers, and the remaining values ​​are the actual storage address values.

[0148] As shown in Table 9 below, idx0 is written to address 0 of [63:0], idx1 is written to address 0 of [127:64], idx2 is written to address 0 of [191:128], idx3 is written to address 0 of [255:192], idx4 is written to address 0 of [319:256], idx5 is written to address 0 of [383:320], idx6 is written to address 0 of [447:384], and idx7 is written to address 0 of [511:448].

[0149] Table 9. Actual storage address table for the fourth layer of a 4096-point radix-8 FFT.

[0150] [63:0] [127:64] [191:128] [255:192] [319:256] [383:320] [447:384] [511:448] 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 7 7 7 7 7 7 7 7 8 8 8 8 8 8 8 8 9 9 9 9 9 9 9 9 10 10 10 10 10 10 10 10

[0151] After all the level operations are completed, the final step is to perform a bitwise address reversal. For example, with an FFT length of 4096 bits and a 9-bit address width, the 4th bit remains unchanged as the middle value. The remaining bits are swapped: the 8th bit and the 0th bit, the 7th bit and the 1st bit, the 6th bit and the 2nd bit, and the 5th bit and the 3rd bit. In a practical example, with an FFT length of 4096, 1 ​​becomes 256, 2 becomes 128, and 3 becomes 384.

[0152] Because the last level of storage stores idx0, 1, 2, 3, 4, 5, 6, 7 at the beginning of the RAM address, and 8, 9, 10, 11, 12, 13, 14, 15 at the second address, after performing the bit reversal, only the data is shifted to the starting position; adjacent data is unaffected. Therefore, it does not affect the final result.

[0153] The radix-8 read rules are as follows: In the first level of operation, data is read in blocks from different RAM addresses at the same address, sequentially from low to high addresses. Subsequent levels of operation follow the same write rules as the previous level. The radix-8 read / write rules are as follows: S1: Arrangement operation; Arrange all data numbers idx in ascending order, and move the corresponding data accordingly. S2.1: Shift operation; Shift the previously arranged data sequentially backward in a loop without overflow. The last data number idx becomes the first data number idx, and the remaining data numbers idx are shifted sequentially, with the corresponding data shifted accordingly. S2.2: Re-shift operation; The number of write operations cycles in increments of 8 (calculating 1-8 is the first cycle, calculating 9-16 is the second calculation). In the first cycle, S2.1 shifts forward once, in the second cycle, S2.1 shifts forward twice, and so on. No shift is performed when retrieving 8 data points for the first time at each level; when retrieving 8 data points next time, the data shifts forward one position each time. Every 8 data retrievals constitute one cycle, and data needs to be shifted again when retrieving 8 data points after each cycle. S3: Read / Write operation; The data number idx is divided by 8 to obtain the actual address. The first data point is filled into the address space of idx / 8 of the first segment of RAM. The remaining data is filled into or read from subsequent blocks according to this rule. The difference in idx between the first level and the second level is 8. N1 / 8, the difference in IDX at the second level is 8. N1 / 64, the third-level IDX is 8 N1 / 512, and so on, until the difference in idx at the last level is 1; after all the level operations are completed, the final step is to perform binary bit reversal address conversion.

[0154] With 4096(8 N1 Taking 4096 (where N1 = 4, requiring 4 levels of computation) as an example, we'll consider four levels of computation. The first level reads 8 data points from the same address in RAM. The first data read is encoded as 0, 8... N1 / 8,8 N1 / 8*2,8 N1 / 8*3,8 N1 / 8*4,8 N1 / 8*5,8 N1 / 8*6,8 N1 / 8*7, the RAM offset address is 0; the address read the second time is...

[0155] 1,8 N1 / 8+1,8 N1 / 8*2+1,8 N1 / 8*3+1,8 N1 / 8*4+1,8 N1 / 8*5+1,8 N1 / 8*6+1,8 N1 / 8*7+1, the RAM offset address is 1; the second layer read needs to follow the S1, S2 rules mentioned above, and the data encoding of the first read is...

[0156] 0,8 N1 / 8 / 8,8 N1 / 8 / 8*2,8 N1 / 8 / 8*3,8 N1 / 8 / 8*4,8 N1 / 8 / 8*5,8 N1 / 8 / 8*6,8 N1 / 8 / 8*7, corresponding to the RAM offset address is

[0157] 0,8 N1 / 8 / 8 / 8,8 N1 / 8 / 8 / 8*2,8 N1 / 8 / 8 / 8*3,8 N1 / 8 / 8 / 8*4,8 N1 / 8 / 8 / 8*5,8 N1 / 8 / 8 / 8*6,8 N1 / 8 / 8 / 8*7; The data encoding read the second time is 1,8 N1 / 8 / 8+1,8 N1 / 8 / 8*2+1,8 N1 / 8 / 8*3+1,8 N1 / 8 / 8*4+1,8 N1 / 8 / 8*5+1,8 N1 / 8 / 8*6+1,8 N1 / 8 / 8*7+1 corresponds to an offset address of 8 in RAM. N1 / 8 / 8 / 8*7,0,8 N1 / 8 / 8 / 8,8 N1 / 8 / 8 / 8*2,8 N1 / 8 / 8 / 8*3,8 N1 / 8 / 8 / 8*4,8 N1 / 8 / 8 / 8*5,8 N1 / 8 / 8 / 8*6; The data encoding for the ninth read is 8,8 N1 / 8 / 8+8,8 N1 / 8 / 8*2+8,8 N1 / 8 / 8*3+8,8 N1 / 8 / 8*4+8,8 N1 / 8 / 8*5+8,8 N1 / 8 / 8*6+8,8 N1 / 8 / 8*7+8 corresponds to an offset address of 8 in RAM. N1 / 8 / 8 / 8*7+1,1,8N1 / 8 / 8 / 8+1,8 N1 / 8 / 8 / 8*2+1,8 N1 / 8 / 8 / 8*3+1,8 N1 / 8 / 8 / 8*4+1,8 N1 / 8 / 8 / 8*5+1,8 N1 / 8 / 8 / 8*6+1; The third-level read also needs to follow the S1 and S2 rules mentioned above. The data encoding for the first read is 0,8. N1 / 8 / 8 / 8,8 N1 / 8 / 8 / 8*2,8 N1 / 8 / 8 / 8*3,8 N1 / 8 / 8 / 8*4,8 N1 / 8 / 8 / 8*5,8 N1 / 8 / 8 / 8*6,8 N1 / 8 / 8 / 8*7, corresponding to an offset address of 0, 8 in RAM. N1 / 8 / 8 / 8 / 8,8 N1 / 8 / 8 / 8 / 8+1,8 N1 / 8 / 8 / 8 / 8+2,8 N1 / 8 / 8 / 8 / 8+3,8 N1 / 8 / 8 / 8 / 8+4,8 N1 / 8 / 8 / 8 / 8+5,8 N1 / 8 / 8 / 8 / 8+6; The second data read is encoded as 1,8 N1 / 8 / 8 / 8+1,8 N1 / 8 / 8 / 8*2+1,8 N1 / 8 / 8 / 8*3+1,8 N1 / 8 / 8 / 8*4+1,8 N1 / 8 / 8 / 8*5+1,8 N1 / 8 / 8 / 8*6+1,8 N1 / 8 / 8 / 8*7+1 corresponds to an offset address of 8 in RAM. N1 / 8 / 8 / 8 / 8+6,0,0,8 N1 / 8 / 8 / 8 / 8+1,8 N1 / 8 / 8 / 8 / 8+2,8 N1 / 8 / 8 / 8 / 8+3,8 N1 / 8 / 8 / 8 / 8+4,8 N1 / 8 / 8 / 8 / 8+5; The data encoding for the ninth read is 8. N1 / 8 / 8,8 N1 / 8 / 8+8,8 N1 / 8 / 8+8*2,8 N1 / 8 / 8+8*3,8 N1 / 8 / 8+8*4,8N1 / 8 / 8+8*5,8 N1 / 8 / 8+8*6,8 N1 / 8 / 8+8*7 corresponds to an offset address of 8 in RAM. N1 / 8 / 8 / 8+7,8 N1 / 8 / 8 / 8,8 N1 / 8 / 8 / 8+1,8 N1 / 8 / 8 / 8+2,8 N1 / 8 / 8 / 8+3,8 N1 / 8 / 8 / 8+4,8 N1 / 8 / 8 / 8+5,8 N1 / 8 / 8 / 8+6; The fourth layer read also needs to follow the S1 and S2 rules mentioned above. The data code for the first read is 0,1,2,3,4,5,6,7, corresponding to the RAM offset address 0,0,0,0,0,0,0,0; the data code for the second read is 8,9,10,11,12,13,14,15, corresponding to the RAM offset address 1,1,1,1,1,1,1,1; the data code for the ninth read is 64,65,66,67,68,69,70,71, corresponding to the RAM offset address 8,8,8,8,8,8,8,8; (taking 4096 as an example, calculating four layers) The first layer write needs to follow the S1 and S2 rules mentioned above. The data code for the first write is 0,8 N1 / 8,8 N1 / 8*2,8 N1 / 8*3,8 N1 / 8*4,8 N1 / 8*5,8 N1 / 8*6,8 N1 / 8*7 corresponds to the RAM offset address.

[0158] 0,8 N1 / 8 / 8,8 N1 / 8 / 8*2,8 N1 / 8 / 8*3,8 N1 / 8 / 8*4,8 N1 / 8 / 8*5,8 N1 / 8 / 8*6,8 N1 / 8 / 8*7; The data encoding written the second time is...

[0159] 1,8 N1 / 8+1,8 N1 / 8*2+1,8 N1 / 8*3+1,8 N1 / 8*4+1,8 N1 / 8*5+1,8 N1 / 8*6+1,8 N1 / 8*7+1 corresponds to an offset address of 8 in RAM. N1 / 8 / 8*7,

[0160] 0,8 N1 / 8 / 8,8 N1 / 8 / 8*2,8 N1 / 8 / 8*3,8 N1 / 8 / 8*4,8 N1 / 8 / 8*5,8 N1 / 8 / 8*6; The data encoding for the ninth write is...

[0161] 8,8 N1 / 8+8,8 N1 / 8*2+8,8 N1 / 8*3+8,8 N1 / 8*4+8,8 N1 / 8*5+8,8 N1 / 8*6+8,8 N1 / 8*7+8 corresponds to an offset address of 8 in RAM. N1 / 8 / 8*7+1,1,8 N1 / 8 / 8+1,8 N1 / 8 / 8*2+1,8 N1 / 8 / 8*3+1,8 N1 / 8 / 8*4+1,8 N1 / 8 / 8*5+1,8 N1 / 8 / 8*6+1; The second layer write also needs to follow the S1 and S2 rules mentioned above. The data encoding for the first write is 0,8. N1 / 8 / 8,8 N1 / 8 / 8*2,8 N1 / 8 / 8*3,8 N1 / 8 / 8*4,8 N1 / 8 / 8*5,8 N1 / 8 / 8*6,8 N1 / 8 / 8*7 corresponds to an offset address of 0 in RAM.

[0162] 8 N1 / 8 / 8 / 8,8 N1 / 8 / 8 / 8*2,8 N1 / 8 / 8 / 8*3,8 N1 / 8 / 8 / 8*4,8 N1 / 8 / 8 / 8*5,8 N1 / 8 / 8 / 8*6,8 N1 / 8 / 8 / 8*7; The second data written is encoded as follows:

[0163] 1,8 N1 / 8 / 8+1,8 N1 / 8 / 8*2+1,8 N1 / 8 / 8*3+1,8 N1 / 8 / 8*4+1,8 N1 / 8 / 8*5+1,8 N1 / 8 / 8*6+1,8 N1 / 8 / 8*7+1 corresponds to an offset address of 8 in RAM. N1 / 8 / 8 / 8 / *7,0,8 N1 / 8 / 8 / 8*1,8 N1 / 8 / 8 / 8*2,8 N1 / 8 / 8 / 8*3,8 N1 / 8 / 8 / 8*4,8 N1 / 8 / 8 / 8*5,8 N1 / 8 / 8 / 8*6; The data encoding for the ninth write is 8,8 N1 / 8 / 8+8,8 N1 / 8 / 8*2+8,8 N1 / 8 / 8*3+8,8 N1 / 8 / 8*4+8,8 N1 / 8 / 8*5+8,8 N1 / 8 / 8*6+8,8 N1 / 8 / 8*7+8 corresponds to an offset address of 8 in RAM. N1 / 8 / 8 / 8*7+1,1,8 N1 / 8 / 8 / 8+1,8 N1 / 8 / 8 / 8*2+1,8 N1 / 8 / 8 / 8*3+1,8 N1 / 8 / 8 / 8*4+1,8 N1 / 8 / 8 / 8*5+1,8 N1 / 8 / 8 / 8*6+1; The third layer write also needs to follow the S1 and S2 rules mentioned above. The data encoding for the first write is 0,8. N1 / 8 / 8 / 8,8 N1 / 8 / 8 / 8*2,8 N1 / 8 / 8 / 8*3,8 N1 / 8 / 8 / 8*4,8 N1 / 8 / 8 / 8*5,8 N1 / 8 / 8 / 8*6,8 N1 / 8 / 8 / 8*7 corresponds to an offset address of 0,8 in RAM. N1 / 8 / 8 / 8 / 8+1, 8 N1 / 8 / 8 / 8 / 8+2,8 N1 / 8 / 8 / 8 / 8+3,8 N1 / 8 / 8 / 8 / 8+4,8 N1 / 8 / 8 / 8 / 8+5,8N1 / 8 / 8 / 8 / 8+6,8 N1 / 8 / 8 / 8 / 8+7; The second data written is encoded as 1,8 N1 / 8 / 8 / 8+1,8 N1 / 8 / 8 / 8+2,8 N1 / 8 / 8 / 8+3,8 N1 / 8 / 8 / 8+4,8 N1 / 8 / 8 / 8+5,8 N1 / 8 / 8 / 8+6,8 N1 / 8 / 8 / 8+7 corresponds to an offset address of 8 in RAM. N1 / 8 / 8 / 8 / 8+7,0,8 N1 / 8 / 8 / 8 / 8, 8 N1 / 8 / 8 / 8 / 8+2,8 N1 / 8 / 8 / 8 / 8+3,8 N1 / 8 / 8 / 8 / 8+4,8 N1 / 8 / 8 / 8 / 8+5,8 N1 / 8 / 8 / 8 / 8+6; The data encoding for the ninth write is 8. N1 / 8 / 8,8 N1 / 8 / 8+8,8 N1 / 8 / 8+8*2,8 N1 / 8 / 8+8*3,8 N1 / 8 / 8+8*4,8 N1 / 8 / 8+8*5,8 N1 / 8 / 8+8*6,8 N1 The RAM offset address corresponding to / 8 / 8+8*7 is 8. N1 / 8 / 8 / 8+7,8 N1 / 8 / 8 / 8, 8 N1 / 8 / 8 / 8+1, 8 N1 / 8 / 8 / 8+2,8 N1 / 8 / 8 / 8++3,8 N1 / 8 / 8 / 8+4,8 N1 / 8 / 8 / 8+5, 8 N1 / 8 / 8 / 8+6; The fourth layer write also needs to follow the S1 and S2 rules mentioned above. The data code for the first write is 0,1,2,3,4,5,6,7, and the corresponding RAM offset address is 0,0,0,0,0,0,0,0; the data code for the second write is 8,9,10,11,12,13,14,15, and the corresponding RAM offset address is 1,1,1,1,1,1,1,1; the data code for the ninth write is 64,65,66,67,68,69,70,71, and the corresponding RAM offset address is 8,8,8,8,8,8,8,8.

[0164] Data can be output in two ways: 1. Send data directly through the port. 2. Store data in the data buffer RAM and read it when an external signal is valid.

[0165] Data format conversion: This patent uses a separate computing module, so only 32 bits of data are transmitted in the entire FFT kernel. The meaning of each data bit is that it is effective through the combined action of the multiplier / adder and the flag bit.

[0166] When the system selects floating-point operations, the flag bit is set to 1, and the FFT kernel state machine only performs data arrangement, reading, and writing. When computation is required, the FFT kernel sends 32-bit data to the multiplier / adder. After receiving the data and the flag bit, the multiplier / adder sends the data to the corresponding fixed-point or floating-point computation module. After obtaining the result, the data is sent back to the FFT kernel processor.

[0167] Figure 2 This indicates the structure of the FFT controller.

[0168] Lengths of 512,4096,32768 can be processed using a radix-8 core; lengths of 16,64,256,1024,16384 can be processed using a radix-4 core; and lengths of 8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768 can be processed using a radix-2 core. Since radix-4 and radix-8 are faster than radix-2, they will be prioritized for computation. Furthermore, the reason for prioritizing radix-8 cores over radix-4 cores is that 512 = 8^3; therefore, radix-8 cores are preferred for processing lengths of 512. This also saves hardware resources, preventing the overall circuit area from becoming excessively large due to the presence of radix-8 and radix-4 cores, while significantly improving computational speed. For example, FFT radix-2 requires 26,848 cycles to calculate a length of 2048, while FFT radix-8 only requires 22,774 cycles to calculate a length of 4096.

[0169] The user writes data to RAM0. After all the data is written, the parameters of length, FFT, single-packet / pipeline are configured, and then the FFT calculation is started, and the data is written to RAM1. The calculation process of radix-2 is simple, divided into two loops: hierarchical loop and group loop. The hierarchical loop is the large loop, and the group loop is the small loop. The system reads two data and a rotation factor from RAM1 according to the idx information provided by the group loop. There are two ways to process the rotation factor: 1. Make a parameter table and call different rotation factors according to different lengths. 2. Write the rotation factor into the ROM every time, generate it outside the system according to the length every time, and then write it into the ROM. The FFT directly reads from the ROM. After the calculation of these two data is completed, the result is written to RAM2. Until the current group loop is completed. When running to the next level, the system reads data from RAM2 and writes the result to RAM1. The system uses the ping / pong principle to complete the data reading and writing.

[0170] Calculate the rotation factor using Euler's formula. The real part and imaginary part of the rotation factor are calculated as W[i].realPart = cos(2π / size_x*i) and W[i].imaginaryPart = -sin(2π / size_x*i) respectively; where i is the value of each loop, 0 < i < size_x; size_x is the data length.

[0171] The calculation process of radix-4 is similar to that of radix-2. After the data is read from RAM0, it is stored in RAM1 after changing positions. At this time, the state machine starts and enters the first-level calculation. The system reads in 4 data and 3 rotation factors W N Perform multiplication and addition calculations, as shown in Formula 2. After the calculation is completed, the result is written to RAM2, and the loop continues until all the data in the first level is calculated. Then enter the second level. The system reads data from RAM2, calculates and writes it to RAM1. The subsequent data is read and written between these two RAMs until the butterfly calculation is completed.

[0172] The radix-8 calculation process is as follows: After reading data from RAM0, it is written to RAM1 according to certain rules. Taking the 4096 as an example, the first 512 numbers are written to the lower 63 bits of RAM sequentially (from address 0 to address 511, the next 512 numbers are written to the middle of RAM [127:64], the next 512 numbers are written to the middle of RAM [191:128], and so on, until the last 512 numbers are written to [511:448]). Then, the radix-8 kernel is started. The first layer retrieves 8 numbers, namely the 0th, 512th, 1024th, 1536th, 2048th, 2560th, 3072nd, and 3584th numbers. These 8 numbers are sent to the arithmetic control. First, a preliminary radix-8 butterfly calculation is performed. Then, the resulting numbers are multiplied sequentially by the cos / sin values ​​obtained from the external lookup table. The cos / sin value is also part of the twitch factor, and due to algorithmic reasons, it is divided into two parts for multiplication and addition. After the calculation is complete, the result is written to RAM2 according to certain rules. At this time, the address mapping starts working, writing the idx-th number to different positions in RAM2 according to the address rules. For example, the 512th number is written to the [127:64]th bit of the 64th position in RAM, and the next time the 513th number will be written to the 0th position, which contains a certain position rotation mechanism. After all levels of calculation are completed, the storage location of the output data will be adjusted once, that is, binary bit inversion address conversion. In the FFT algorithm, the data is usually arranged in a certain order, such as time order. However, in order to optimize the calculation, the data needs to be rearranged so that adjacent data points can be processed in the best way at each stage of the FFT calculation. This is the purpose of binary bit inversion address conversion. After obtaining the new address, the data is buffered or directly output, and a completion signal is issued.

[0173] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A fixed-floating-point FFT processor with multi-base configurable length, characterized in that, include: First RAM, second RAM, third RAM, initial rearrangement unit, FFT controller, clock configuration unit, fixed-floating-point multiplier / adder, and rotation factor ROM table; The first RAM is used to store the received external input serial data sequentially according to the external low-frequency clock signal. After the data is full, the FFT controller is triggered to start the FFT calculation. The initial rearrangement unit is used to read the data stored in the first RAM, rearrange it according to a preset time, and then store it in the second RAM; The third RAM and the second RAM together form a ping-pong storage for temporarily storing data in the FFT butterfly operation; The clock configuration unit uses a phase-locked loop to multiply the input low-frequency clock signal and outputs multiple multiplied frequency clocks to the FFT controller. The fixed-point / floating-point multiplier / adder is used to perform fixed-point or floating-point FFT operations on the input data and then output the results to the FFT controller. The rotation factor ROM table is used to pre-store the complex rotation factors required for calculating the FFT and provides high-speed lookup access during the calculation process; The third RAM and the second RAM together form a ping-pong storage for temporarily storing data in radix-2, radix-4 or radix-8 butterfly operations; The FFT controller inputs the received data, complex twitch factor, and clock signal to the fixed-floating-point multiplier / adder, and completes the FFT operation on the input signal by controlling the data arrangement, reading, writing, and temporary storage.

2. The processor according to claim 1, characterized in that, The FFT controller includes a state machine, a radix-2 kernel processing unit, a radix-4 kernel processing unit, and a radix-8 kernel processing unit. The state machine calls different kernel processing units to process the data based on control signals and the data length. When the data length is 8... N1 When N1 is an integer greater than 2, it is processed using a radix-8 core processing unit; when the data length is 4... N2 When N2 is an integer greater than 1, it is processed using a radix-4 kernel processing unit; when the data length is 2... N3 When N3 is an integer greater than 1, it is processed using a radix-2 kernel processing unit; when the data length is suitable for multiple kernel processing units, the kernel processing unit with the larger value is used first.

3. The processor according to claim 1, characterized in that, It also includes a pipelined cache RAM; the processor supports single-packet data processing and pipelined processing, and when pipelined processing is performed, the pipelined cache RAM is used for data caching during pipelined processing; Furthermore, the clock configuration unit generates different clock frequencies: a high-frequency clock is used for butterfly operation processing and multiplication / addition processing, and a low-frequency clock is used for serial data input.

4. The processor according to claim 3, characterized in that, The clock configuration unit generates different clock frequencies, including configuring a high-frequency clock and a low-frequency clock, satisfying the following condition: the time for serial input of a packet of data under the low-frequency clock is the same as the time for processing a packet of data under the control of the high-frequency clock.

5. The processor according to claim 1, characterized in that, The fixed-point / floating-point multiplier / adder controls whether to perform fixed-point or floating-point operations via a single data bit at its port. The multiplication / addition modules required for fixed-point and floating-point operations are independent of each other. The data operation process is as follows: a valid pulse signal and two data points arrive at the fixed-point / floating-point multiplier / adder at the same time. The valid pulse signal is ANDed with the fixed-point / floating-point control signal to make the fixed-point or floating-point operation module valid. After the calculation is completed, the fixed-point / floating-point operation module provides a valid end pulse signal, and the FFT controller receives the signal and continues to work.

6. The processor according to claim 1, characterized in that, The initial rearrangement unit is used to read the data stored in the first RAM, rearrange it according to a preset procedure, and then store it in the second RAM. Specifically, it includes: If the first RAM cache data uses a width of M bits and a depth of N; In radix-2 and radix-8 operations, both the second RAM and the third RAM are divided into 2 or 8 storage blocks of length M and depth N / 2 or N / 8. The data in the first RAM is sequentially divided into 2 or 8 parts and stored into 2 or 8 storage blocks in sequence. That is, data is preferentially written to the RAM block with the lowest bit number first, and the writing is done from the low address to the high address. After the highest address is written, the data is written to the next RAM block with the highest bit number. In the radix-4 operation, both the second RAM and the third RAM are divided into four storage blocks of length M and depth N / 4. The first four data are stored in the lowest address of the storage block, and the address of the subsequent data is stored in the next higher address. That is, data is first written to multiple RAM blocks at lower addresses in sequence, and after multiple RAM blocks at the same address are written, the next RAM block at a higher address is written.

7. The processor according to claim 6, characterized in that, The third RAM and the second RAM together form a ping-pong storage system for temporarily storing data in the FFT butterfly operation. Specifically, this includes: retrieving data from the second RAM, performing the FFT operation, and then storing it in the third RAM according to a preset read / write rule, completing the first layer of operation; then retrieving data from the third RAM, performing the FFT operation, and then storing it in the second RAM according to the preset read / write rule, completing the second layer of operation, and so on, until all processing is complete after K layers; where the data length in the radix-2 operation is 2. K In radix-4 operations, the data length is 4. K In radix-8 operations, the data length is 8. K And so on.

8. The processor according to claim 7, characterized in that, The radix-2 operation reads the data from the second RAM or the third RAM, performs an FFT operation, and then writes it back to the address corresponding to the third RAM or the second RAM, meaning the read and write addresses remain unchanged.

9. The processor according to claim 7, characterized in that, The radix-4 operation read / write rules are as follows: The reading rule for radix-4 is as follows: each time data is read, it is read in blocks of RAM at the same address, sequentially from low address to high address; The write rules for radix-4 are as follows: When writing the first four data reads at the first level, the block number of the data remains unchanged, only the address changes. The write address offset for the first to the fourth data is 0, 1, 2, and 3, respectively. The four data entries read in the second reading of the first layer are written immediately after the block of data written in the first layer, that is, the data is shifted one position to the higher number of the block. This process continues until the fourth read of data has been completed and written, completing one cycle of 16 data entries. Then, the above operation is repeated to complete the operation of the next 16 data entries, and so on. In the nth layer (n>1), the first four data entries read have the same block number but different addresses during writing. The write address offset for the first to fourth data entries is 0 and 1*4, respectively. n-1 2*4 n-1 3*4 n-1 The second read of the four data items in the second layer retains the same block number but changes the address during writing. The write address offset for the first to fourth data items is the previous offset of 0 and 1*4. n-1 2*4 n-1 3*4 n-1 Moving one bit to the right corresponds to a write address offset of 3*4. n-1 0, 1*4 n -1 2*4 n-1 The address offset and data shift operations are both overflow-free cyclic shifts, the 4th... n-1 When writing the 4 data reads in the +1st read, the block number of the data is shifted one bit to the higher position of the block number; The smallest unit of data processing in the nth layer is 4 blocks, and each 4 blocks... n The second layer of data processing consists of 4 consecutive addresses; the smallest unit of data processing is 4 blocks and 16 consecutive addresses; and so on until all data is read and written.

10. The processor according to claim 8, characterized in that, The radix-8 operation read / write rules are as follows: The read rules for radix-8 are as follows: During the first level of operation, data is read sequentially from the same address in different RAM blocks, and then the next same address in different RAM blocks is read, and so on from low address to high address; subsequent level operations follow the same write rules as the previous level. The rules for writing radix-8 are as follows: S1: Permutation operation: Arrange all data in ascending order, represented by the number idx; S2.1: Move operation: Move the data that was just arranged in order backward in a loop without overflow. The data corresponding to the last data number idx is moved to the position of the data corresponding to the first data number idx, and the remaining data numbers idx are moved backward in sequence. S2.2: Re-shift operation: The number of writes cycles in cycles of 8. In the first cycle, S2.1 shifts forward once, in the second cycle, S2.1 shifts forward twice, and so on. S3: Write operation: Divide the data number idx by 8 to get the actual address, fill the first data into the address space of idx / 8 of the first block of RAM, and write the remaining data into the subsequent blocks according to this rule; In the above read and write operations, the difference between the first-level idx is 8. N1 / 8, the difference in IDX at the second level is 8. N1 / 64, the third-level IDX is 8 N1 / 512, and so on, until the difference in idx at the last level is 1; after all the level operations are completed, the binary bit reversal address conversion is finally performed.

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