Package with optical integrated devices

Abstract

A package comprising: a package substrate; a first integrated device bonded to the package substrate through a plurality of first solder interconnects; a sealing layer that at least partially seals the first integrated device; a plurality of post interconnects located within the sealing layer; a metallization portion bonded to the plurality of post interconnects; a second integrated device bonded to the metallization portion through a plurality of second solder interconnects; an optical integrated device bonded to the package substrate; and an optical fiber bonded to the optical integrated device.

Description

Technical Field

[0001] (Cross - reference to Related Applications)

[0001] This application claims priority and benefit to (i) U.S. Non - Provisional Application No. 18 / 607,170, filed with the United States Patent and Trademark Office on March 15, 2024, and (ii) U.S. Provisional Application No. 63 / 491,982, filed with the United States Patent and Trademark Office on March 24, 2023. U.S. Non - Provisional Application No. 18 / 607,170 claims priority and benefit to U.S. Provisional Application No. 63 / 491,982. The entire contents of both applications are incorporated herein by reference as if fully set forth below and for all applicable purposes.

[0002]

[0002] Various features relate to packages that include integrated devices.

Background Art

[0003]

[0003] A package can include a substrate and an integrated device. These components, when joined together, can provide a package that can perform various functions. The performance of the package and its components can depend on many factors. There is a continuing need to provide packages that offer improved performance. There is a continuing need to include packages with a more compact form factor so that the package can be implemented in a smaller device.

Summary of the Invention

[0004]

[0004] Various features relate to packages that include integrated devices.

[0005]

[0005] One example is a package comprising: a package substrate; a first integrated device bonded to the package substrate through a first plurality of solder interconnects; a sealing layer that at least partially seals the first integrated device; a plurality of post interconnects located within the sealing layer; a metallization portion bonded to the plurality of post interconnects; a second integrated device bonded to the metallization portion through a second plurality of solder interconnects; an optical integrated device bonded to the package substrate; and an optical fiber bonded to the optical integrated device.

[0006]

[0006] Another example is a package comprising: a metallization portion; a first integrated device coupled to the metallization portion through a first plurality of solder interconnects, wherein the front surface of the first integrated device is oriented toward the metallization portion; a sealing layer that at least partially seals the first integrated device; a plurality of post interconnects located within the sealing layer; a second integrated device coupled to the metallization portion through a second plurality of solder interconnects; an optical integrated device coupled to the metallization portion through a third plurality of solder interconnects; an optical fiber coupled to the optical integrated device; and a package substrate coupled to the plurality of post interconnects through a fourth plurality of solder interconnects. [Brief explanation of the drawing]

[0007]

[0007] Various features, properties, and advantages can be revealed by reading the "Modes for Carrying Out the Invention" described below in conjunction with the drawings, in which similar reference numerals throughout the text identify corresponding elements. [Figure 1]

[0008] A cross-sectional view of an exemplary package containing an optical integrated device is shown. [Figure 2]

[0009] A cross-sectional view of an exemplary package containing an optical integrated device is shown. [Figure 3]

[0010] A cross-sectional view of an exemplary package containing an optical integrated device is shown. [Figure 4]

[0011] A cross-sectional view of an exemplary package containing an optical integrated device is shown. [Figure 5]

[0012] A cross-sectional view of an exemplary package containing an optical integrated device is shown. [Figure 6]

[0013] A cross-sectional view of an exemplary package containing an optical integrated device is shown. [Figure 7]

[0014] An exemplary cross-sectional view of an optically integrated device is shown. [Figure 8]

[0015] An exemplary cross-sectional view of an optically integrated device is shown. [Figure 9A]

[0016] This shows an exemplary sequence for manufacturing a package containing an optically integrated device. [Figure 9B] This shows an exemplary sequence for manufacturing a package containing an optically integrated device. [Figure 9C] This shows an exemplary sequence for manufacturing a package containing an optically integrated device. [Figure 9D] This shows an exemplary sequence for manufacturing a package containing an optically integrated device. [Figure 10]

[0017] This diagram illustrates an exemplary flow chart of a method for manufacturing a package containing an optically integrated device. [Figure 11]

[0018] This describes various electronic devices that can integrate dies, integrated devices, integrated passive devices (IPDs), passive components, packages, and / or device packages as described herein. [Modes for carrying out the invention]

[0008]

[0019] The following description includes specific details to provide a complete understanding of the various aspects of this disclosure. However, those skilled in the art will understand that these aspects can be practiced without these specific details. For example, circuits may be shown in block diagrams to avoid obscuring the aspects with unnecessary details. In other cases, well-known circuits, structures, and techniques may not be shown in detail so as not to obscure the aspects of this disclosure.

[0009]

[0020] This disclosure describes a package comprising: a package substrate; a first integrated device bonded to the package substrate through a plurality of first solder interconnects; a sealing layer at least partially sealing the first integrated device; a plurality of post interconnects located within the sealing layer; a metallization portion bonded to the plurality of post interconnects; a second integrated device bonded to the metallization portion through a plurality of second solder interconnects; an optical integrated device bonded to the package substrate; and an optical fiber bonded to the optical integrated device. The bonding of the optical integrated device to the package substrate provides a short distance for at least one electrical path of the package to various integrated devices. Furthermore, the proximity of the optical integrated device to the integrated devices reduces IR drop, which helps improve the performance of the integrated devices and / or the package.

[0010] Exemplary package with optical integrated device

[0021] Figure 1 shows a cross-sectional view of a package 100 including an optical integrated device. The package 100 includes an optical integrated device 101, a package substrate 102, an integrated device 103, a metallization portion 104, an integrated device 105, an integrated device 109, a connector socket 107, a passive device 111, an integrated device 130, an integrated device 132, an integrated device 134, a plurality of post interconnection portions 160, and a sealing layer 106.

[0011]

[0022] The package substrate 102 includes at least one dielectric layer 120 and a plurality of interconnection parts 122 (e.g., substrate interconnection parts). The optical integrated device 101 is coupled to the package substrate 102. For example, the optical integrated device 101 may be embedded within the package substrate 102. In some mounting configurations, the optical integrated device 101 may be located within a cavity in the package substrate 102. The optical integrated device 101 may be coupled to the package substrate 102 via an adhesive (not shown). The optical fiber 110 is coupled to the optical integrated device 101. The optical fiber 110 may be considered part of the package 100. The optical fiber 110 may be coupled to another optical integrated device (not shown). Other optical integrated devices may be coupled to another package or board. An example of the optical integrated device 101 is shown and illustrated in Figure 7 below. The optical integrated device may include (i) the ability to convert optical signals / energy into electrical signals / energy, and / or (ii) the ability to convert electrical signals / energy into optical signals / energy. For example, a signal may be received as an optical signal and converted to an electrical signal. Similarly, a signal may be received as an electrical signal and converted to an optical signal. An optical integrated device can transmit a signal as an optical signal and / or an electrical signal. More detailed examples of optical integrated devices are shown and described below, at least in Figures 7 and 8. In some implementations, the optical integrated device 101 may be implemented as the optical integrated device 700 and / or the optical integrated device 800.

[0012]

[0023] The sealing layer 106 can at least partially seal the integrated device 103, the integrated device 105, and the plurality of post interconnects 160. The integrated device 103 is coupled to the package substrate 102 through solder interconnects from the plurality of solder interconnects 123. The front surface of the integrated device 103 faces the package substrate 102. For example, the surface of the front surface of the integrated device 103 can be directed in a direction toward the package substrate 102. The integrated device 105 is coupled to the package substrate 102 through another solder interconnect from the plurality of solder interconnects 123. The front surface of the integrated device 105 faces the package substrate 102. For example, the surface of the front surface of the integrated device 105 can be directed in a direction toward the package substrate 102. The plurality of post interconnects 160 are coupled to the package substrate 102 through other solder interconnects from the plurality of solder interconnects 123. There is an underfill 125 between the package substrate 102 and the sealing layer 106. The underfill 125 can surround the plurality of solder interconnects 123 laterally. The underfill 125 can be coupled to and in contact with the package substrate 102, the plurality of solder interconnects 123, the sealing layer 106, the integrated device 103, and the integrated device 105.

[0013]

[0024] The metallization portion 104 is coupled to the encapsulation layer 106 and the plurality of post interconnects 160. The metallization portion 104 includes at least one dielectric layer 140 and a plurality of metallization interconnects 142. The metallization portion 104 can be a redistribution portion. The plurality of metallization interconnects 142 can include redistribution interconnects. The plurality of post interconnects 160 can be coupled to the metallization interconnects from the plurality of metallization interconnects 142 of the metallization portion 104. The back surface of the integrated device 103 can face the metallization portion 104. For example, the surface of the back surface of the integrated device 103 can be oriented in a direction towards the metallization portion 104. The back surface of the integrated device 105 can face the metallization portion 104. For example, the surface of the back surface of the integrated device 105 can be oriented in a direction towards the metallization portion 104. The bottom surface of the metallization portion 104 can be coupled to the encapsulation layer 106.

[0014]

[0025] The passive device 111 can be coupled to the upper surface of the metallization portion 104 through the plurality of solder interconnects 112. For example, the passive device 111 can be coupled to the metallization interconnects from the plurality of metallization interconnects 142 through the plurality of solder interconnects 112.

[0015]

[0026] The integrated device 109 can be coupled to the upper surface of the metallization portion 104 through the plurality of solder interconnects 190. For example, the integrated device 109 can be coupled to the metallization interconnects from the plurality of metallization interconnects 142 through the plurality of solder interconnects 190. The integrated device 130 can be coupled to the upper surface of the metallization portion 104 through the plurality of solder interconnects 131. For example, the integrated device 130 can be coupled to the metallization interconnects from the plurality of metallization interconnects 142 through the plurality of solder interconnects 131.

[0016]

[0027] The integrated device 132 may be coupled to the integrated device 130 through a plurality of solder interconnects 133. The integrated device 134 may be coupled to the integrated device 132 through a plurality of solder interconnects 135. The integrated devices 130, 132, and 134 may be stacked integrated devices.

[0017]

[0028] The connector socket 107 is coupled to the upper surface of the metallization portion 104 through a plurality of solder interconnects 170. The connector socket 107 is configured to be electrically coupled to the connector socket 113. The connector socket 107 is configured to provide an electrical path for power. The connector socket 107 is configured to provide an electrical path for grounding. The connector socket 107 may be coupled to the connector socket 113 through one or more wires.

[0018]

[0029] Package 100 is coupled to board 108 through a plurality of solder interconnects 183. Board 108 includes at least one board dielectric layer 180 and a plurality of board interconnects 182. Connector socket 113 is coupled to board 108 through a plurality of solder interconnects 114. Connector sockets (e.g., 107, 113) may include a plurality of connector interconnects. Connector sockets may include connector housings, and the plurality of connector interconnects may be at least partially located within the connector housing. One or more wires coupled to a connector socket may include wire interconnects and a dielectric layer surrounding one or more wires.

[0019]

[0030] The optical fiber 110 is coupled to the optical integrated device 101. The optical fiber 110 may extend through the package substrate 102. The optical fiber 110 may extend through cavities within the package substrate 102. In some implementations, the optical fiber 110 may extend within the board 108. In some implementations, the optical fiber 110 may extend between the package substrate 102 and the board 108. One or more optical signals may propagate through the optical fiber 110 to and / or from the optical integrated device 101.

[0020]

[0031] The integrated device 103 may be configured to be electrically coupled to the optical integrated device 101 through an electrical path 151 including solder interconnects from a plurality of solder interconnects 123. The integrated device 105 may be configured to be electrically coupled to the optical integrated device 101 through an electrical path 153 including solder interconnects from a plurality of solder interconnects 123. The integrated device 103 may be configured to be electrically coupled to the optical integrated device 101 through an electrical path including solder interconnects from a plurality of solder interconnects 123, the optical integrated device 101, and other solder interconnects from a plurality of solder interconnects. The integrated device 130 may be configured to be electrically coupled to the optical integrated device 101 through an electrical path 155 including solder interconnects from a plurality of solder interconnects 131, metallization interconnects from a metallization portion 104, post interconnects from a plurality of post interconnects 160, and solder interconnects from a plurality of solder interconnects 123. The electrical path 155 may include the electrical path between the integrated device 130 and the integrated device 134. The electrical path between the integrated device 130 and the integrated device 134 may include die interconnects from the integrated device 130, through-substrate vias from the integrated device 130, solder interconnects from a plurality of solder interconnects 133, die interconnects from the integrated device 132, through-substrate vias from the integrated device 132, solder interconnects from a plurality of solder interconnects 135, and die interconnects from the integrated device 134. In some mounting configurations, there may be pillar interconnects between (i) the integrated device 130 and the integrated device 132, and / or (ii) the integrated device 132 and the integrated device 134. In such cases, the electrical path between the integrated device 130 and the integrated device 134 may also include the pillar interconnects described above.

[0021]

[0032] The integrated device 130 may be configured to be electrically coupled to the integrated device 103 through an electrical path 157 which includes solder interconnects from a plurality of solder interconnects 131, metallization interconnects from a metallization portion 104, post interconnects from a plurality of post interconnects 160, solder interconnects from a plurality of solder interconnects 123, interconnects from a package substrate 102, and other solder interconnects from a plurality of solder interconnects 123. The electrical path 157 may include an electrical path between the integrated device 130 and the integrated device 134. The electrical path between integrated device 130 and integrated device 134 may include die interconnects from integrated device 130, through-substrate vias from integrated device 130, solder interconnects from a plurality of solder interconnects 133, die interconnects from integrated device 132, through-substrate vias from integrated device 132, solder interconnects from a plurality of solder interconnects 135, and die interconnects from integrated device 134. In some mounting configurations, there may be pillar interconnects between (i) integrated device 130 and integrated device 132 and / or (ii) integrated device 132 and integrated device 134. In such cases, the electrical path between integrated device 130 and integrated device 134 may also include the pillar interconnects described above.

[0022]

[0033] The integrated device 130 may be configured to be electrically coupled to the integrated device 105 through an electrical path 159 that includes solder interconnects from a plurality of solder interconnects 131, metallization interconnects from a metallization portion 104, post interconnects from a plurality of post interconnects 160, solder interconnects from a plurality of solder interconnects 123, interconnects from a package substrate 102, and other solder interconnects from a plurality of solder interconnects 123. The electrical path 159 may include an electrical path between the integrated device 130 and the integrated device 134. The electrical path between integrated device 130 and integrated device 134 may include die interconnects from integrated device 130, through-substrate vias from integrated device 130, solder interconnects from a plurality of solder interconnects 133, die interconnects from integrated device 132, through-substrate vias from integrated device 132, solder interconnects from a plurality of solder interconnects 135, and die interconnects from integrated device 134. In some mounting configurations, there may be pillar interconnects between (i) integrated device 130 and integrated device 132 and / or (ii) integrated device 132 and integrated device 134. In such cases, the electrical path between integrated device 130 and integrated device 134 may also include the pillar interconnects described above.

[0023]

[0034] In some implementations, the optical signal may be received by the optical integrator 101 through the optical fiber 110. The optical signal may be converted into an electrical signal by the optical integrator 101, and the electrical signal may be sent to the integrator 103, integrator 105, and / or integrator 130 using one or more of the electrical paths described above.

[0024]

[0035] In some implementations, electrical signals may be received by the optical integrated device 101 through one or more of the electrical paths described above. The electrical signals may be converted into optical signals by the optical integrated device 101, and the optical signals may be transmitted through the optical fiber 110.

[0025]

[0036] The integrated device 103 may be a system on a chip (SoC). The integrated device 109 may include a power management integrated circuit (PMIC). The passive device 111 may include a capacitor. The integrated devices 130, 132, and / or 134 may include memory. The electrical path between the integrated device 109 and the integrated device 130 may include solder interconnects from a plurality of solder interconnects 190, metallization interconnects from a plurality of metallization interconnects 142, and solder interconnects from a plurality of solder interconnects 131. The electrical path between the integrated device 109 and the integrated device 134 may include the electrical path between the integrated device 130 and the integrated device 134, as described above.

[0026]

[0037] In some implementations, the optical integrated device 101 may be configured to operate as a bridge. The integrated device 103 may be configured to be electrically coupled to the integrated device 105 through the optical integrated device 101. For example, the electrical path between the integrated device 103 and the integrated device 105 may include the optical integrated device 101. The electrical path between the integrated device 103 and the integrated device 105 may include the electrical path 151 (as described above), the interconnect from the optical integrated device 101, and the electrical path 153 (as described above).

[0027]

[0038] Figure 2 shows a cross-sectional view of a package 200 including an optical integrated device. The package 200 includes an optical integrated device 101, a package substrate 102, an integrated device 103, a metallization portion 104, an integrated device 105, an integrated device 109, a connector socket 107, a passive device 111, an integrated device 130, an integrated device 132, an integrated device 134, a plurality of post interconnects 160, a sealing layer 106, at least one back-side power rail interconnect 203, and at least one back-side power rail interconnect 205.

[0028]

[0039] At least one back-side power rail interconnect 203 can be considered part of the integrated device 103. For example, at least one back-side power rail interconnect 203 may be located within the die substrate of the integrated device 103. The back-side power rail interconnect 203 may include trace interconnects and / or through-substrate vias. The back-side power rail interconnect 203 can be considered part of the back surface of the integrated device 103. At least one back-side power rail interconnect 205 can be considered part of the integrated device 105. For example, at least one back-side power rail interconnect 205 may be located within the die substrate of the integrated device 105. The back-side power rail interconnect 205 may include trace interconnects and / or through-substrate vias. The back-side power rail interconnect 205 can be considered part of the back surface of the integrated device 105.

[0029]

[0040] Package 200 is similar to package 100. However, some of the components of package 200 are positioned and / or combined differently from some of the components in package 100.

[0030]

[0041] The integrated device 103 is coupled to the bottom surface of the metallization portion 104 through a plurality of solder interconnects 223. The front surface of the integrated device 103 may face the metallization portion 104. For example, the front surface of the integrated device 103 may be oriented toward the metallization portion 104. The integrated device 105 is coupled to the bottom surface of the metallization portion 104 through a plurality of solder interconnects 225. The front surface of the integrated device 105 may face the metallization portion 104. For example, the front surface of the integrated device 105 may be oriented toward the metallization portion 104. The integrated device 109 is coupled to the bottom surface of the metallization portion 104 through a plurality of solder interconnects 190. The passive device 111 is coupled to the bottom surface of the metallization portion 104 through a plurality of solder interconnects 112. The sealing layer 106 can at least partially seal the integrated device 103, integrated device 105, integrated device 109, passive device 111, rear power rail interconnect 203, rear power rail interconnect 205, and a plurality of post interconnects 160. The sealing layer 106 may include molded material, resin, and / or epoxy. Compression molding, transfer molding, or liquid molding processes may be used to form the sealing layer 106.

[0031]

[0042] The package 200 is coupled to the board 108 through multiple solder interconnects 183. The connector socket 113 is coupled to the board 108 through multiple solder interconnects 114.

[0032]

[0043] The integrated device 130 may be configured to be electrically coupled to the integrated device 103 through an electrical path 257 that includes solder interconnects from a plurality of solder interconnects 131, metallization interconnects from a metallization portion 104, and solder interconnects from a plurality of solder interconnects 223. The integrated device 130 may be configured to be electrically coupled to the integrated device 105 through an electrical path 259 that includes solder interconnects from a plurality of solder interconnects 131, metallization interconnects from a metallization portion 104, and solder interconnects from a plurality of solder interconnects 225. The electrical path 257 may include an electrical path between the integrated device 130 and the integrated device 134. The electrical path between integrated device 130 and integrated device 134 may include die interconnects from integrated device 130, through-substrate vias from integrated device 130, solder interconnects from a plurality of solder interconnects 133, die interconnects from integrated device 132, through-substrate vias from integrated device 132, solder interconnects from a plurality of solder interconnects 135, and die interconnects from integrated device 134. In some mounting configurations, there may be pillar interconnects between (i) integrated device 130 and integrated device 132 and / or (ii) integrated device 132 and integrated device 134. In such cases, the electrical path between integrated device 130 and integrated device 134 may also include the pillar interconnects described above. The electrical path 259 may include the electrical path between integrated device 130 and integrated device 134. The electrical path between integrated device 130 and integrated device 134 may include die interconnects from integrated device 130, through-substrate vias from integrated device 130, solder interconnects from a plurality of solder interconnects 133, die interconnects from integrated device 132, through-substrate vias from integrated device 132, solder interconnects from a plurality of solder interconnects 135, and die interconnects from integrated device 134. In some mounting configurations, pillar interconnects may be present between (i) integrated device 130 and integrated device 132 and / or between integrated device 132 and integrated device 134.In such cases, the electrical path between the integrated device 130 and the integrated device 134 may also include the pillar interconnect described above.

[0033]

[0044] The integrated device 130 may be configured to be electrically coupled to the optical integrated device 101 through an electrical path 255 which includes solder interconnects from a plurality of solder interconnects 131, metallization interconnects from a metallization portion 104, post interconnects from a plurality of post interconnects 160, and solder interconnects from a plurality of solder interconnects 123. The electrical path 255 may include an electrical path between the integrated device 130 and the integrated device 134. The electrical path between the integrated device 130 and the integrated device 134 may include die interconnects from the integrated device 130, through-substrate vias from the integrated device 130, solder interconnects from a plurality of solder interconnects 133, die interconnects from the integrated device 132, through-substrate vias from the integrated device 132, solder interconnects from a plurality of solder interconnects 135, and die interconnects from the integrated device 134. In some implementations, pillar interconnects may exist between (i) integrated device 130 and integrated device 132, and / or between integrated device 132 and integrated device 134. In such cases, the electrical path between integrated device 130 and integrated device 134 may also include the aforementioned pillar interconnects.

[0034]

[0045] In some implementation configurations, the integrated device 103 may be configured to be electrically coupled to the integrated device 105 through a plurality of solder interconnects 223, metallization interconnects from a plurality of metallization interconnects 142, and a plurality of solder interconnects 225.

[0035]

[0046] In some implementations, the integrated device 103 may be configured to be electrically coupled to the integrated device 105 through solder interconnects from a plurality of solder interconnects 123, the optical integrated device 101, and other solder interconnects from the plurality of solder interconnects 123. In some implementations, the optical integrated device 101 may be configured as a bridge. In some implementations, the optical integrated device 101, the integrated device 103, and / or the integrated device 105 may be one or more chiplets. In some implementations, the integrated device 103 may be manufactured using a first technology node, and the integrated device 105 may be manufactured using a second technology node that is less advanced than the first technology node. The optical integrated device 101 may be manufactured using a third technology node different from the first and / or second technology nodes.

[0036]

[0047] In some implementations, the optical signal may be received by the optical integrator 101 through the optical fiber 110. The optical signal may be converted into an electrical signal by the optical integrator 101, and the electrical signal may be sent to the integrator 103, integrator 105, and / or integrator 130 using one or more of the electrical paths described above.

[0037]

[0048] In some implementations, electrical signals may be received by the optical integrated device 101 through one or more of the electrical paths described above. The electrical signals may be converted into optical signals by the optical integrated device 101, and the optical signals may be transmitted through the optical fiber 110.

[0038]

[0049] The optical integrated device 101 is coupled to the package substrate 102. For example, the optical integrated device 101 may be embedded within the package substrate 102. In some mounting configurations, the optical integrated device 101 may be located within a cavity in the package substrate 102. The optical integrated device 101 may be coupled to the package substrate 102 via an adhesive (not shown). The optical fiber 110 is coupled to the optical integrated device 101. The optical fiber 110 may be considered part of the package 200.

[0039]

[0050] Power may be supplied to the integrated device 103 through its back surface. For example, an electrical path for power to the integrated device 103 may include interconnects from a plurality of interconnects 122, at least one solder interconnect from a plurality of solder interconnects 123, and at least one back surface power rail interconnect 203. Similarly, power may be supplied to the integrated device 105 through its back surface. For example, an electrical path for power to the integrated device 105 may include interconnects from a plurality of interconnects 122, at least one solder interconnect from a plurality of solder interconnects 123, and at least one back surface power rail interconnect 205.

[0040]

[0051] Figure 3 shows a cross-sectional view of a package 300 including an optical integrated device. The package 300 includes an optical integrated device 101, a package substrate 102, an integrated device 103, a metallization portion 104, an integrated device 105, an integrated device 109, a connector socket 107, a passive device 111, an integrated device 130, an integrated device 132, an integrated device 134, a plurality of post interconnects 160, a sealing layer 106, at least one back-side power rail interconnect 203, and at least one back-side power rail interconnect 205.

[0041]

[0052] Package 300 is similar to package 200. However, some of the components of package 300 are positioned and / or combined differently from some of the components in package 200.

[0042]

[0053] For example, the optical integrated device 101 is coupled to the upper surface of the metallization portion 104 through a plurality of solder interconnects 310. An example of the optical integrated device 101 is shown and explained in Figure 8 below. The optical integrated device 101 is coupled to the optical integrated device 301 through an optical fiber 110. The optical integrated device 301 is coupled to the board 108. The optical integrated device 301 may be coupled to the board 108 through a plurality of solder interconnects.

[0043]

[0054] The integrated device 130 may be configured to be electrically coupled to the integrated device 103 through an electrical path 257 that includes solder interconnects from a plurality of solder interconnects 131, metallization interconnects from a metallization portion 104, and solder interconnects from a plurality of solder interconnects 223. The integrated device 130 may be configured to be electrically coupled to the integrated device 105 through an electrical path that includes solder interconnects from a plurality of solder interconnects 131, metallization interconnects from a metallization portion 104, and solder interconnects from a plurality of solder interconnects 225.

[0044]

[0055] The integrated device 130 may be configured to be electrically coupled to the optical integrated device 101 through an electrical path 355 that includes solder interconnects from a plurality of solder interconnects 131, metallization interconnects from a metallization portion 104, and solder interconnects from a plurality of solder interconnects 310. The electrical path 355 may include an electrical path between the integrated device 130 and the integrated device 134. The electrical path between the integrated device 130 and the integrated device 134 may include die interconnects from the integrated device 130, through-substrate vias from the integrated device 130, solder interconnects from a plurality of solder interconnects 133, die interconnects from the integrated device 132, through-substrate vias from the integrated device 132, solder interconnects from a plurality of solder interconnects 135, and die interconnects from the integrated device 134. In some implementations, pillar interconnects may exist between (i) integrated device 130 and integrated device 132, and / or between integrated device 132 and integrated device 134. In such cases, the electrical path between integrated device 130 and integrated device 134 may also include the aforementioned pillar interconnects.

[0045]

[0056] The integrated device 103 may be configured to be electrically coupled to the optical integrated device 101 through an electrical path 353 that includes solder interconnects from a plurality of solder interconnects 223, metallization interconnects from a metallization portion 104, and solder interconnects from a plurality of solder interconnects 310.

[0046]

[0057] The integrated device 105 may be configured to be electrically coupled to the optical integrated device 101 through an electrical path 357 that includes solder interconnects from a plurality of solder interconnects 225, metallization interconnects from a metallization portion 104, and solder interconnects from a plurality of solder interconnects 310.

[0047]

[0058] In some implementations, the optical signal may be received by the optical integrator 101 through the optical fiber 110. The optical signal may be converted into an electrical signal by the optical integrator 101, and the electrical signal may be sent to the integrator 103, integrator 105, and / or integrator 130 using one or more of the electrical paths described above.

[0048]

[0059] In some implementations, electrical signals may be received by the optical integrated device 101 through one or more of the electrical paths described above. The electrical signals may be converted into optical signals by the optical integrated device 101, and the optical signals may be transmitted through the optical fiber 110.

[0049]

[0060] Figure 4 shows a cross-sectional view of a package 400 including an optical integrated device. The package 400 includes an optical integrated device 101, a package substrate 102, an integrated device 103, a metallization portion 104, an integrated device 105, an integrated device 109, a connector socket 107, a passive device 111, an integrated device 130, an integrated device 132, an integrated device 134, a plurality of post interconnects 160, a sealing layer 106, at least one back-side power rail interconnect 203, and at least one back-side power rail interconnect 205.

[0050]

[0061] Package 400 is similar to package 300. However, some of the components of package 400 are positioned and / or coupled differently from some of the components in package 300. For example, package substrate 102 includes interconnects 122a and 122b. Interconnects 122a and 122b are configured as heat spreaders on package substrate 102. Board 108 includes board interconnects 182a and 182b. A heat sink 403 is coupled to board 108. A thermal interface material may be used to couple the heat sink 403 to board 108. A heat sink 405 is coupled to board 108. A thermal interface material may be used to couple the heat sink 405 to board 108. The heat generated by the integrated device 103 and / or the back-side power rail interconnect 203 can be dissipated through the solder interconnects from the multiple solder interconnects 123, interconnect 122a, the solder interconnects from the multiple solder interconnects 183, the board interconnect 182a, and the heat sink 403. The heat generated by the integrated device 105 and / or the back-side power rail interconnect 205 can be dissipated through the solder interconnects from the multiple solder interconnects 123, interconnect 122b, the solder interconnects from the multiple solder interconnects 183, the board interconnect 182b, and the heat sink 405.

[0051]

[0062] In some implementations, the integrated device 103 may be a first chiplet, and the integrated device 105 may be a second chiplet. The integrated device 103 may be configured to perform a first set of functions and / or operations. The integrated device 105 may be configured to perform a second set of functions and / or operations. The second set of functions and / or operations includes at least one function and / or operation that is different from the first set of functions and / or operations. In some implementations, the integrated device 103 may be manufactured using a first technology node, and the integrated device 105 may be manufactured using a second technology node that is less advanced than the first technology node.

[0052]

[0063] Figure 5 shows a cross-sectional view of a package 500 including an optical integrated device. The package 500 includes an optical integrated device 101, a package substrate 102, an integrated device 103, a metallization portion 104, an integrated device 105, an integrated device 109, a connector socket 107, a passive device 111, an integrated device 130, an integrated device 132, an integrated device 134, a plurality of post interconnects 160, a sealing layer 106, at least one back-side power rail interconnect 203, and at least one back-side power rail interconnect 205.

[0053]

[0064] Package 500 is similar to package 300 and / or package 400. However, some of the components of package 500 are positioned and / or combined differently from some of the components in package 300 and / or package 400.

[0054]

[0065] As shown in Figure 5, the optical integrated device 101 is coupled to the upper surface of the metallization portion 104 (for example, the second integrated device) through a plurality of solder interconnects 310. The integrated device 109 is coupled to the upper surface of the metallization portion 104 through a plurality of solder interconnects 190. The passive device 111 is coupled to the upper surface of the metallization portion 104 through a plurality of solder interconnects 112.

[0055]

[0066] In some implementations, the optical signal may be received by the optical integrator 101 through the optical fiber 110. The optical signal may be converted into an electrical signal by the optical integrator 101, and the electrical signal may be sent to the integrator 103, integrator 105, and / or integrator 130 using at least one or more of the electrical paths described above in Figure 3.

[0056]

[0067] In some implementations, electrical signals can be received by the optical integrated device 101 through at least one or more of the electrical paths described in Figure 3. The electrical signals can be converted into optical signals by the optical integrated device 101, and the optical signals can be transmitted through the optical fiber 110.

[0057]

[0068] Figure 6 shows a cross-sectional view of a package 600 including an optical integrated device. The package 600 includes an optical integrated device 101, a package substrate 102, an integrated device 103, a metallization portion 104, an integrated device 105, an integrated device 109, a connector socket 107, a passive device 111, an integrated device 130, an integrated device 132, an integrated device 134, a plurality of post interconnects 160, a sealing layer 106, at least one back-side power rail interconnect 203, and at least one back-side power rail interconnect 205.

[0058]

[0069] Package 600 is similar to package 300 and / or package 400. However, some of the components of package 600 are positioned and / or combined differently from some of the components in package 300 and / or package 400.

[0059]

[0070] The package substrate 102 includes interconnection sections 122a and 122b. The interconnection sections 122a and 122b are configured as heat spreaders on the package substrate 102. The board 108 includes board interconnection sections 182a and 182b. A heat sink 403 is bonded to the board 108. A thermal interface material may be used to bond the heat sink 403 to the board 108. A heat sink 405 is bonded to the board 108. A thermal interface material may be used to bond the heat sink 405 to the board 108. Heat generated by the integrated device 103 and / or the back-side power rail interconnection section 203 can be dissipated through the solder interconnection sections from the multiple solder interconnection sections 123, interconnection section 122a, the solder interconnection sections from the multiple solder interconnection sections 183, board interconnection section 182a, and heat sink 403. The heat generated by the integrated device 105 and / or the back-side power rail interconnect 205 can be dissipated through the solder interconnects from the multiple solder interconnects 123, the interconnect 122b, the solder interconnects from the multiple solder interconnects 183, the board interconnect 182b, and the heat sink 405.

[0060]

[0071] In some implementations, the optical signal may be received by the optical integrator 101 through the optical fiber 110. The optical signal may be converted into an electrical signal by the optical integrator 101, and the electrical signal may be sent to the integrator 103, integrator 105, and / or integrator 130 using at least one or more of the electrical paths described above in Figure 3.

[0061]

[0072] In some implementations, electrical signals can be received by the optical integrated device 101 through at least one or more of the electrical paths described in Figure 3. The electrical signals can be converted into optical signals by the optical integrated device 101, and the optical signals can be transmitted through the optical fiber 110.

[0062]

[0073] Note that any package may include additional and / or other components. For example, an integrated device may be replaced by a stack of integrated devices. For example, integrated device 103 and / or integrated device 105 may each be replaced by a stack of integrated devices (similar to integrated devices 130, 132, and 134). A stack of integrated devices may include integrated devices facing each other front to front, integrated devices facing each other front to back, and / or integrated devices facing each other back to back. In another example, a substrate and / or interposer may be located between the package substrate 102 and integrated devices 103 and / or integrated devices 105.

[0063]

[0074] It should be noted that any of the multiple solder interconnects described herein may be implemented as multiple bump interconnects. Bump interconnects may include pillar interconnects and solder interconnects. In some implementations, multiple bump interconnects may include multiple microbump interconnects. Microbump interconnects may be similar to bump interconnects. However, microbump interconnects may have smaller dimensions than bump interconnects to accommodate finer interconnect pitches. For example, in some implementations, multiple solder interconnects 123 may be implemented as multiple microbump interconnects, and multiple solder interconnects 183 may be implemented as multiple bump interconnects. In some implementations, one or more bump interconnects may have a pitch in the range of about 80 to 120 micrometers (e.g., minimum pitch). In some implementations, one or more microbump interconnects may have a pitch in the range of about 25 to 50 micrometers (e.g., minimum pitch).

[0064] Exemplary optical integrated device

[0075] Figure 7 shows an exemplary optical integrated device 700. The optical integrated device 700 may be the optical integrated device 101 described in Figures 1 to 6. The optical integrated device 700 includes a substrate 702 (e.g., a silicon substrate), an optical device 704, waveguides 706, 708, 709, an oxide layer 710, a plurality of interconnects 730, and a fiber ferrule 720. The optical fiber 110 is coupled to waveguides 706 and fiber ferrule 720. Optical signals from the optical fiber 110 can propagate through waveguides 706, 709, and 708. The optical signals can be processed by optical device 704 and converted into electrical signals. The electrical signals can be transmitted through the plurality of interconnects 730. The oxide layer 710 may surround waveguides 709 and 708. Waveguide 709 may contain silicon(S) or silicon nitride. Waveguide 709 may extend through the thickness of substrate 702, such as through silicon via (TSV). Waveguide 708 may contain silicon(S), germanium(Ge), or silicon nitride.

[0065]

[0076] Figure 8 shows an exemplary optical integrated device 800. The optical integrated device 800 may be the optical integrated device 101 described in Figures 1 to 6. The optical integrated device 800 includes a substrate 702 (e.g., a silicon substrate), an optical device 704, a waveguide 706, a plurality of interconnectors 830, a plurality of interconnectors 840, and a fiber ferrule 720. The optical fiber 110 is coupled to the waveguide 706 and the fiber ferrule 720. Optical signals from the optical fiber 110 can propagate through the waveguide 706. The optical signals can be processed by the optical device 704, and the optical signals can be converted into electrical signals. The electrical signals can be transmitted through the plurality of interconnectors 830 and / or the plurality of interconnectors 840.

[0066]

[0077] Although not shown, the fiber ferrule 720 may be coupled to a carrier (e.g., a silicon carrier), which is used to help couple the fiber ferrule 720 to the waveguide 706. In some implementations, there may be two or more optical fibers.

[0067]

[0078] Different implementations may use different waveguide designs. In some implementations, the waveguide may include silicon ridge waveguides, silicon rib waveguides, silicon slot waveguides, and / or silicon nitride ridge waveguides. However, other implementations may use other waveguide designs. For example, some implementations may use germanium in combination with silicon.

[0068]

[0079] An integrated device (e.g., 103) may include a die (e.g., a bare semiconductor die). An integrated device may include a power management integrated circuit (PMIC). An integrated device may include an application processor. An integrated device may include a modem. An integrated device may include radio frequency (RF) devices, passive devices, filters, capacitors, inductors, antennas, transmitters, receivers, gallium arsenide (GaAs) based integrated devices, surface acoustic wave (SAW) filters, bulk acoustic wave (BAW) filters, light-emitting diode (LED) integrated devices, silicon (Si) based integrated devices, silicon carbide (SiC) based integrated devices, memory, power management processors, and / or combinations thereof. An integrated device (e.g., 103, 105) may include at least one electronic circuit (e.g., a first electronic circuit, a second electronic circuit, etc.). An integrated device may include a transistor. An integrated device may be an example of an electrical component and / or electrical device. In some implementations, integrated devices may be in the form of chiplets. In some implementations, optical integrated devices (e.g., 101) can be chiplets. Chiplets may be manufactured using processes that yield better results compared to other processes used to manufacture other types of integrated devices, thereby reducing the overall cost of manufacturing chiplets. Different chiplets may have different sizes and / or shapes. Different chiplets may be configured to provide different functions. Different chiplets may have different interconnect density (e.g., interconnects with different widths and / or spacing). In some implementations, several chiplets may be used to perform the functions of one or more chips (e.g., one or more integrated devices). Therefore, for example, a single integrated device may be divided into several chiplets.As described above, using several chiplets that perform several functions can reduce the overall cost of the package compared to using a single chip to perform all the functions of the package. In some implementations, one or more of the chiplets described herein and / or one or more of the integrated devices (e.g., 103) may be manufactured using the same technology node or two or more different technology nodes. For example, an integrated device may be manufactured using a first technology node, and a chiplet may be manufactured using a second technology node that is less advanced than the first technology node. In such an example, an integrated device may include components having a first minimum size (e.g., interconnects, transistors), and a chiplet may include components having a second minimum size (e.g., interconnects, transistors), where the second minimum size is larger than the first minimum size. In some implementations, one integrated device and another integrated device in the package may be manufactured using the same technology node or different technology nodes. In some implementations, one chiplet and another chiplet in the package may be manufactured using the same technology node or different technology nodes.

[0069]

[0080] A technology node can refer to a specific manufacturing process and / or technology used to manufacture integrated devices and / or chiplets. A technology node can specify the minimum possible size that can be manufactured (e.g., minimum size) (e.g., transistor size, trace width, gap between two transistors). Different technology nodes may have different yield losses. Different technology nodes may have different costs. A technology node that produces components with finer details (e.g., traces, transistors) may be more expensive and have higher yield losses than a technology node that produces components with less fine details (e.g., traces, transistors). Therefore, more advanced technology nodes may be more expensive and have higher yield losses than less advanced technology nodes. If all the functionality of a package is implemented within a single integrated device, the entire integrated device will be manufactured using the same technology node, even if some of the functionality of the integrated device does not need to be manufactured using that particular technology node. Thus, an integrated device is locked into one technology node. To optimize package costs, some functions can be implemented in different integrated devices and / or chiplets, and these different integrated devices and / or chiplets can be manufactured using different technology nodes to reduce overall costs. For example, functions requiring the use of the most advanced technology node can be implemented in an integrated device, while functions that can be implemented using less advanced technology nodes can be implemented in a different integrated device and / or one or more chiplets. One example is an integrated device manufactured using a first technology node (e.g., a state-of-the-art technology node) configured to provide a computing application, and at least one chiplet manufactured using a second technology node configured to provide other functions, where the second technology node is not as expensive as the first technology node, and the second technology node manufactures components having a minimum size greater than the minimum size of components manufactured using the first technology node.Examples of computing applications may include high-performance computing and / or high-performance processing, which can be achieved by manufacturing and packing as many transistors as possible in an integrated device. Therefore, integrated devices configured for computing applications may be manufactured using the most advanced technology nodes available, while other chiplets may be manufactured using less advanced technology nodes because these chiplets may not require as many transistors to be manufactured in the chiplet. Thus, the combination of using different technology nodes (which may have different associated yield losses) for different integrated devices and / or chiplets can reduce the overall cost of the package compared to using a single integrated device to perform all the functions of the package.

[0070]

[0081] Another advantage of splitting functionality into several integrated devices and / or chiplets is that it allows for improvements in package performance without the need to redesign any single integrated device and / or chiplet. For example, if a package configuration uses a first integrated device and a first chiplet, it may be possible to improve package performance by changing the design of the first integrated device while keeping the design of the first chiplet the same. Thus, the first chiplet can be reused with an improved and / or differently configured first integrated device. This saves costs by eliminating the need to redesign the first chiplet when a package with an improved integrated device is manufactured.

[0071] Exemplary sequence for manufacturing a package with an optically integrated device

[0082] In some implementations, manufacturing a package involves several processes. Figures 9A–9D show exemplary sequences for providing or manufacturing a package. In some implementations, the sequences in Figures 9A–9D may be used to provide or manufacture package 300 in Figure 3. However, the processes in Figures 9A–9D may be used to manufacture any of the packages described in this disclosure (e.g., 100, 200, 400, 500, 600).

[0072]

[0083] It should be noted that the sequences in Figures 9A to 9D may be combinations of one or more steps to simplify and / or clarify the sequence for providing or manufacturing a package. In some implementations, the order of the process may be changed or modified. In some implementations, one or more of the processes may be replaced or substituted without departing from the spirit of this disclosure.

[0073]

[0084] Stage 1 shows the state after the metallization portion 104 has been provided on the carrier 900, as shown in Figure 9A. The metallization portion 104 includes at least one dielectric layer 140 and a plurality of metallization interconnects 142. The metallization portion 104 can be formed on the carrier 900. A deposition process, masking process, exposure process, etching process, plating process, and / or stripping process may be used to form the metallization portion 104. A deposition, lamination, exposure, development, and / or etching process may be used to form and pattern at least one dielectric layer. A plating process and / or patterning process may be used to form the metallization interconnects.

[0074]

[0085] Stage 2 shows the state after multiple post interconnects 160 have been formed on the metallization portion 104 and coupled thereto. The multiple post interconnects 160 are coupled to the multiple metallization interconnects 142. A plating process may be used to form the multiple post interconnects 160.

[0075]

[0086] Step 3 shows the subsequent state of multiple integrated devices and / or at least one passive device coupled to the surface of the metallization portion 104. For example, integrated device 103 is coupled to the surface of the metallization portion 104 through multiple solder interconnects 223. For example, the front surface of integrated device 103 is coupled to the surface of the metallization portion 104. Integrated device 103 may include a back-side power rail interconnect 203. Integrated device 105 is coupled to the surface of the metallization portion 104 through multiple solder interconnects 225. For example, the front surface of integrated device 105 is coupled to the surface of the metallization portion 104. Integrated device 105 may include a back-side power rail interconnect 205. Integrated device 109 is coupled to the surface of the metallization portion 104 through multiple solder interconnects 190. Passive device 111 is coupled to the surface of the metallization portion 104 through multiple solder interconnects 112. One or more solder reflow processes may be used to couple multiple integrated devices and / or passive devices to the metallization portion 104.

[0076]

[0087] Stage 4 shows the state after the sealing layer 106 has been formed on and bonded to the metallization portion 104, as shown in Figure 9B. The sealing layer 106 may include molded material, resin, and / or epoxy. Compression molding, transfer molding, or liquid molding processes may be used to form the sealing layer 106. The sealing may seal (e.g., partially seal) the integrated device 103 / backside power rail interconnect 203, the integrated device 105 / backside power rail interconnect 205, the integrated device 109, the passive device 111, and a plurality of post interconnects 160.

[0077]

[0088] Stage 5 shows the state after the carrier 900 has been uncoupled from the metallization portion 104.

[0078]

[0089] Step 6 shows the state after the package substrate 102 has been coupled to the back-side power rail interconnects (e.g., 203, 205) and the post interconnects 160 of the integrated devices (e.g., 103, 105) through a plurality of solder interconnects 123. A solder reflow process may be used to couple the power rail interconnects and the post interconnects 160 through the plurality of solder interconnects 123. The package substrate 102 may be coupled to the back-side of the integrated device 103 and the back-side of the integrated device 105. The package substrate 102 includes at least one dielectric layer 120 and a plurality of interconnects 122. In some mounting configurations, the package substrate 102 may include an optical integrated device 101 and / or the optical integrated device 101 may be coupled to the package substrate 102. As illustrated and described in Figures 1 and 2, in some mounting configurations, the optical integrated device 101 may be part of the package substrate 102. The optical integrated device 101 may be located within a cavity in the package substrate 102. The optical integrated device 101 may be bonded to the package substrate 102 via an adhesive.

[0079]

[0090] Step 7 shows the state after an underfill 125 has been provided between the package substrate 102 and the sealing layer 106. The underfill 125 may be formed so as to laterally surround a plurality of solder interconnects 123. The underfill 125 may be coupled to and in contact with the package substrate 102, the plurality of solder interconnects 123, the sealing layer 106, the integrated device 103, and / or the integrated device 105.

[0080]

[0091] Step 8 shows the state after one or more integrated devices have been bonded to the surface of the metallization portion 104, as shown in Figure 9C. For example, a stack of integrated devices may be bonded to the metallization portion 104. In one example, a stack of integrated devices comprising integrated device 130, integrated device 132, and integrated device 134 may be bonded to the metallization portion 104 via a solder reflow process.

[0081]

[0092] Stage 9 shows the state after the package substrate 102 has been bonded to the board 108 through a plurality of solder interconnects 183. A solder reflow process may be used to bond the package substrate 102 to the board 108.

[0082]

[0093] Step 10 shows the state after the optical integrated device 101 is coupled to the metallization portion 104 through a plurality of solder interconnects 310, as shown in Figure 9D. The optical integrated device 301 is coupled to the board 108. The optical integrated device 301 may be similar to the optical integrated device 101. The optical integrated device 301 may be coupled to the board 108 through a plurality of solder interconnects. The optical fiber 110 may be coupled to the optical integrated device 101 and the optical integrated device 301.

[0083]

[0094] Stage 10 also shows the state after the connector socket 107 is coupled to the metallization portion 104 through a plurality of solder interconnects 170 and the connector socket 113 is coupled to the board 108 through a plurality of solder interconnects 114. A solder reflow process may be used for the connector socket 107 to the metallization portion 104 and for the connector socket 113 to the board 108. The connector socket 107 may be coupled to the connector socket 113 through one or more wires.

[0084] Exemplary flowchart of a method for manufacturing a package containing an optically integrated device.

[0095] In some implementations, manufacturing a package involves several processes. Figure 10 shows an exemplary flowchart of method 1000 for providing or manufacturing a package. In some implementations, method 1000 in Figure 10 may be used to provide or manufacture at least the packages shown in Figures 1 to 6.

[0085]

[0096] It should be noted that Method 1000 in Figure 10 may combine one or more processes to simplify and / or clarify the method for providing or manufacturing a package. In some implementations, the order of the processes may be changed or modified.

[0086]

[0097] The method involves providing a metallization portion and a plurality of post interconnects (in 1005). The metallization portion may be provided on a carrier. In some implementations, providing the metallization portion and the plurality of post interconnects includes manufacturing the metallization portion and the plurality of post interconnects. Steps 1 and 2 of Figure 9A illustrate and describe an example of providing a metallization portion 104 and a plurality of post interconnects 160. Step 1 of Figure 9A illustrates and describes an example of providing a metallization portion. The metallization portion 104 includes at least one dielectric layer 140 and a plurality of metallization interconnects 142. The metallization portion 104 may be formed on a carrier 900. Deposition, lamination, exposure, development, and / or etching processes may be used to form and pattern the at least one dielectric layer. Plating processes and / or patterning processes may be used to form the metallization interconnects.

[0087]

[0098] Step 2 in Figure 9A illustrates and describes an example of multiple post interconnects 160 formed on and coupled to the metallization portion 104. The multiple post interconnects 160 are coupled to the multiple metallization interconnects 142. A plating process may be used to form the multiple post interconnects 160.

[0088]

[0099] This method (in 1010) connects one or more integrated devices and / or at least one passive device to the metallization portion. Step 3 in Figure 9A illustrates and describes an example of multiple integrated devices and / or at least one passive device connected to the surface of the metallization portion 104. For example, integrated device 103 is connected to the surface of the metallization portion 104 through multiple solder interconnects 223. Integrated device 105 is connected to the surface of the metallization portion 104 through multiple solder interconnects 225. Integrated device 109 is connected to the surface of the metallization portion 104 through multiple solder interconnects 190. Passive device 111 is connected to the surface of the metallization portion 104 through multiple solder interconnects 112. One or more solder reflow processes may be used to connect multiple integrated devices and / or passive devices to the metallization portion 104.

[0089]

[0100] This method forms a sealing layer (at 1015). The sealing layer can at least partially seal multiple post interconnects, integrated devices, and / or passive devices. Step 4 in Figure 9B illustrates and describes an example of a sealing layer 106 formed on and bonded to the metallization portion 104. The sealing layer 106 may include molded material, resin, and / or epoxy. Compression molding, transfer molding, or liquid molding processes may be used to form the sealing layer 106. The sealing can seal integrated device 103 / backside power rail interconnect 203, integrated device 105 / backside power rail interconnect 205, integrated device 109, passive device 111, and multiple post interconnects 160.

[0090]

[0101] This method can also remove carriers bound to the metallization portion (at 1015). Step 5 in Figure 9B illustrates and describes an example of carriers 900 debonded from the metallization portion 104.

[0091]

[0102] This method allows a package substrate to be coupled to multiple post interconnects through multiple solder interconnects (in 1020). Step 6 in Figure 9B illustrates and describes an example of a package substrate 102 coupled to power rail interconnects (e.g., 203, 205) of an integrated device (e.g., 103, 105) and multiple post interconnects 160 through multiple solder interconnects 123. A solder reflow process may be used to couple the power rail interconnects and the multiple post interconnects 160 through the multiple solder interconnects 123. The package substrate 102 includes at least one dielectric layer 120 and multiple interconnects 122.

[0092]

[0103] In some implementations, the package substrate 102 may include an optical integrated device 101, and / or the optical integrated device 101 may be bonded to the package substrate 102. As illustrated and described in Figures 1 and 2, in some implementations, the optical integrated device 101 may be part of the package substrate 102. The optical integrated device 101 may be located within a cavity in the package substrate 102. The optical integrated device 101 may be bonded to the package substrate 102 via an adhesive.

[0093]

[0104] In some implementation configurations, once the package substrate 102 is coupled to multiple post interconnects through multiple solder interconnects, an underfill 125 may be provided between the package substrate 102 and the encapsulation layer 106. Step 7 in Figure 9B illustrates and describes an example of providing an underfill. The underfill 125 may be formed so as to laterally surround the multiple solder interconnects 123. The underfill 125 may be coupled to and in contact with the package substrate 102, the multiple solder interconnects 123, the encapsulation layer 106, the integrated device 103, and / or the integrated device 105.

[0094]

[0105] The method may also (in 1020) combine integrated devices and / or passive devices into a package. For example, the method may combine integrated devices and / or passive devices into the surface of the metallization portion. Step 8 in Figure 9C illustrates and describes an example of one or more integrated devices combined into the surface of the metallization portion 104. For example, a stack of integrated devices may be combined into the metallization portion 104. In one example, a stack of integrated devices comprising integrated device 130, integrated device 132, and integrated device 134 may be combined into the metallization portion 104 via a solder reflow process.

[0095]

[0106] This method allows the package substrate to be bonded to the board through multiple solder interconnects (in 1025). Step 9 in Figure 9C illustrates and describes an example of a package substrate 102 bonded to the board 108 through multiple solder interconnects 183. A solder reflow process may be used to bond the package substrate 102 to the board 108 through multiple solder interconnects 183.

[0096]

[0107] This method allows (in 1030) to couple connector sockets to a package and a board. This method also allows (in 1030) to couple an optical integrated device to a package and another optical integrated device to a board. Step 10 in Figure 9D illustrates and describes an example of an optical integrated device 101 coupled to a metallization portion 104 through a plurality of solder interconnects 310. An optical integrated device 301 is coupled to a board 108. An optical integrated device 301 may be similar to an optical integrated device 101. An optical integrated device 301 may be coupled to a board 108 through a plurality of solder interconnects. An optical fiber 110 may be coupled to the optical integrated device 101 and the optical integrated device 301.

[0097]

[0108] Step 10 in Figure 9D also illustrates and describes an example of a connector socket 107 coupled to a metallization portion 104 through a plurality of solder interconnects 170, and a connector socket 113 coupled to a board 108 through a plurality of solder interconnects 114. A solder reflow process may be used for the connector socket 107 to the metallization portion 104 and for the connector socket 113 to the board 108. The connector socket 107 may be coupled to the connector socket 113 through one or more wires.

[0098] Exemplary electronic devices

[0109] Figure 11 shows various electronic devices that can be integrated with any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, package-on-package (PoP), system-in-package (SiP), or system-on-chip (SoC). For example, a mobile phone device 1102, a laptop computer device 1104, a fixed-location terminal device 1106, a wearable device 1108, or an automatic vehicle 1110 may include a device 1100 as described herein. Device 1100 may be, for example, any of the devices and / or integrated circuit (IC) packages described herein. The devices 1102, 1104, 1106, and 1108 and the vehicle 1110 shown in Figure 11 are merely examples. Other electronic devices may also characterize device 1100, and such electronic devices include, but are not limited to, a group of devices (e.g., electronic devices) including mobile devices, hand-held personal communication system (PCS) units, portable data units such as personal information terminals, global positioning system (GPS) devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed-position data units such as meter reading devices, communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in automated vehicles (e.g., autonomous vehicles), or any other devices that store or retrieve data or computer instructions, or any combination thereof.

[0099]

[0110] One or more of the components, processes, features, and / or functions shown in Figures 1-8, 9A-9D, and / or Figures 10-11 may be reconfigured and / or combined into a single component, process, feature, or function, or may be embodied as several components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from this disclosure. It should also be noted that Figures 1-8, 9A-9D, and / or Figures 10-11, and their corresponding descriptions in this disclosure, are not limited to dies and / or ICs. In some implementations, Figures 1-8, 9A-9D, and / or Figures 10-11, and their corresponding descriptions in this disclosure may be used to manufacture, build, provide, and / or produce devices and / or integrated devices. In some implementations, a device may include a die, an integrated device, an integrated passive device (IPD), a die package, an integrated circuit (IC) device, a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a package-on-package (PoP) device, a heat dissipation device, and / or an interposer.

[0100]

[0111] Note that the figures in this disclosure may represent actual and / or conceptual representations of various components, elements, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some cases, the figures may not be to exact scale. In some cases, not all elements and / or components may be shown for clarity. In some cases, the location, position, size, and / or shape of various components and / or elements in the figures may be illustrative. In some implementations, various components and / or elements in the figures may be optional.

[0101]

[0112] The term “exemplary” is used herein to mean “serving as an example, case, or illustration.” Any implementation or aspect described herein as “exemplary” should not necessarily be construed as being preferable or advantageous to other aspects of the Disclosure. Similarly, the term “aspect” does not require that all aspects of the Disclosure include the features, advantages, or modes of operation described herein. The term “coupled” is used herein to mean a direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A is in physical contact with object B, and object B is in contact with object C, then objects A and C may still be considered coupled to each other, even if they are not in direct physical contact with each other. The term “electrically coupled” may mean that two objects are directly or indirectly coupled together so that an electric current (e.g., signal, power, ground) can propagate between them. Two electrically coupled objects may or may not propagate an electric current between them. The use of the terms “first,” “second,” “third,” and “fourth” (and / or any of the fourth) is arbitrary. Any of the components described may be the first, second, third, or fourth component. For example, a component referred to as the second component may be the first, second, third, or fourth component. The term “encapsulating” means that one object can partially or completely encapsulate another object. A first component “located” within a second component may mean that the first component is “partially located” within the second component or “completely located” within the second component. A first component “embedded” within a second component may mean that the first component is “partially embedded” within the second component or “completely embedded” within the second component.The terms “top” and “bottom” are arbitrary. A component located at the top may be located above a component located at the bottom. A component at the top may be considered a component at the bottom, and vice versa. As described in this disclosure, a first component located “over” a second component may mean that the first component is located above or below the second component, depending on how the bottom or top is arbitrarily defined. In another example, a first component may be located above (e.g., above) a first surface of a second component, and a third component may be located above (e.g., below) a second surface of a second component, in which case the second surface is on the opposite side of the first surface. It should be further noted that, in the context of one component being located above another, the term “on” as used in this application may be used to mean a component that is on and / or within another component (e.g., on the surface of a component or embedded within a component). Therefore, for example, a first component on a second component may mean (1) the first component is on the second component but does not directly contact the second component, (2) the first component is on the second component (e.g., on the surface of the second component), and / or (3) the first component is inside the second component (e.g., embedded within the second component). A value of about X to XX may mean a value between X and XX, including X and XX. The values ​​(singular or plural) between X and XX may be discrete or continuous. As used in this disclosure, the terms “about ‘value X’” or “approximately value X” mean a range of 10 percent of “value X.” For example, a value of about 1 or approximately 1 means a value in the range of 0.9 to 1.1. “Multiple” components may include all possible components, or only some components from all possible components.For example, if a device contains 10 components, the term "multiple components" could refer to all 10 components or only some of the 10 components.

[0102]

[0113] In some implementations, an interconnect is an element or component of a device or package that enables or facilitates an electrical connection between two points, elements, and / or components. In some implementations, an interconnect may include traces, vias, pads, pillars, redistribution metal layers, and / or underbump metallization (UBM) layers. An interconnect may include one or more metal components (e.g., seed layer + metal layer). In some implementations, an interconnect may be a conductive material configured to provide an electrical path for current (e.g., data signal, ground, or power). An interconnect may be part of a circuit. An interconnect may include two or more elements or components. An interconnect may be defined by one or more interconnects. Different implementations may use similar or different processes to form interconnects. In some implementations, chemical vapor deposition (CVD) and / or physical vapor deposition (PVD) processes are used to form interconnects. For example, sputtering, spray coating, and / or electroplating or electroless plating processes may be used to form interconnections.

[0103]

[0114] Furthermore, note that various disclosures contained herein may be described as processes shown as flowcharts, flow diagrams, structural diagrams, or block diagrams. While flowcharts can describe operations as sequential processes, many operations can also be performed in parallel or simultaneously. Moreover, the order of operations may be rearranged. A process terminates when its operations are completed.

[0104]

[0115] Further examples are described below to facilitate understanding of the present invention.

[0105]

[0116] Embodiment 1: A package comprising: a package substrate; a first integrated device coupled to the package substrate through a first plurality of solder interconnects; a sealing layer that at least partially seals the first integrated device; a plurality of post interconnects located within the sealing layer; a metallization portion coupled to the plurality of post interconnects; a second integrated device coupled to the metallization portion through a second plurality of solder interconnects; an optical integrated device coupled to the package substrate; and an optical fiber coupled to the optical integrated device.

[0106]

[0117] Embodiment 2: The package according to Embodiment 1, wherein the front surface of the first integrated device is oriented toward the package substrate.

[0107]

[0118] Embodiment 3: The package according to Embodiment 1 or 2, wherein the second integrated device is configured to be electrically coupled to an optical integrated device through an electrical path including solder interconnects from a second plurality of solder interconnects, metallization interconnects from a metallization portion, post interconnects from a plurality of post interconnects, and solder interconnects from a first plurality of solder interconnects.

[0108]

[0119] Embodiment 4: The package according to embodiments 1 to 3, wherein the first integrated device is configured to be electrically coupled to an optical integrated device through an electrical path including solder interconnects from a first plurality of solder interconnects.

[0109]

[0120] Embodiment 5: The package according to embodiments 1 to 4, wherein the second integrated device is configured to be electrically coupled to the first integrated device through an electrical path including solder interconnects from a second plurality of solder interconnects, metallization interconnects from a metallization portion, post interconnects from a plurality of post interconnects, and solder interconnects from a first plurality of solder interconnects, interconnects from a package substrate, and other solder interconnects from the first plurality of solder interconnects.

[0110]

[0121] Embodiment 6: The package according to embodiments 1 to 5, wherein the second integrated device is configured to be electrically coupled to the first integrated device through an electrical path including solder interconnects from a second plurality of solder interconnects, metallization interconnects from a metallization portion, post interconnects from a plurality of post interconnects, and solder interconnects from a first plurality of solder interconnects, an optical integrated device, and another solder interconnect from the first plurality of solder interconnects.

[0111]

[0122] Embodiment 7: The package according to embodiments 1 to 6, further comprising a connector socket coupled to the metallization portion, wherein the connector socket is configured to provide an electrical path for power.

[0112]

[0123] Embodiment 8: The package according to Embodiments 1 to 7, wherein the optical integrated device includes a waveguide and a circuit for processing optical and / or electrical signals.

[0113]

[0124] Embodiment 9: The package according to Embodiments 1 to 8, wherein the optical fiber extends through the package substrate.

[0114]

[0125] Embodiment 10: The package according to Embodiments 1 to 9, wherein the second integrated device includes memory.

[0115]

[0126] Embodiment 11: A package comprising: a metallization portion; a first integrated device coupled to the metallization portion through a first plurality of solder interconnects, wherein the front surface of the first integrated device is oriented toward the metallization portion; a sealing layer for sealing the first integrated device; a plurality of post interconnects located within the sealing layer; a second integrated device coupled to the metallization portion through a second plurality of solder interconnects; an optical integrated device coupled to the metallization portion through a third plurality of solder interconnects; an optical fiber coupled to the optical integrated device; and a package substrate coupled to a plurality of post interconnects through a fourth plurality of solder interconnects.

[0116]

[0127] Embodiment 12: The package according to Embodiment 11, wherein the second integrated device is coupled to an optical integrated device through an electrical path including solder interconnects from a second plurality of solder interconnects, metallization interconnects from a metallization portion, and solder interconnects from a third plurality of solder interconnects.

[0117]

[0128] Embodiment 13: The package according to Embodiment 11 or 12, wherein the first integrated device is coupled to an optical integrated device through an electrical path including solder interconnects from a first plurality of solder interconnects, metallization interconnects from a metallization portion, and solder interconnects from a third plurality of solder interconnects.

[0118]

[0129] Embodiment 14: The package according to embodiments 11 to 13, wherein the second integrated device is coupled to the first integrated device through an electrical path including solder interconnects from a second plurality of solder interconnects, metallization interconnects from a metallization portion, and solder interconnects from a first plurality of solder interconnects.

[0119]

[0130] Embodiment 15: The package according to embodiments 11 to 14, further comprising a passive device coupled to the metallization portion.

[0120]

[0131] Embodiment 16: The package according to Embodiment 15, wherein the passive device is at least partially sealed by a sealing layer.

[0121]

[0132] Embodiment 17: The package according to embodiments 11 to 16, further comprising a plurality of power rail interconnections located within the sealing layer.

[0122]

[0133] Embodiment 18: The package according to Embodiment 17, wherein a plurality of power rail interconnects are located between the back surface of the first integrated device and the package substrate.

[0123]

[0134] Embodiment 19: The package according to Embodiments 11 to 18, wherein the second integrated device includes memory.

[0124]

[0135] Embodiment 20: The package according to embodiments 11 to 19, further comprising a connector socket coupled to the metallization portion, wherein the connector socket is configured to provide an electrical path for power.

[0125]

[0136] Embodiment 21: The package according to Embodiments 11 to 20, wherein the package is implemented in a device selected from the group consisting of music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, stationary terminals, tablet computers, computers, wearable devices, laptop computers, servers, Internet of Things (IoT) devices, and devices in automated vehicles.

[0126]

[0137] Embodiment 22: The package according to Embodiments 1 to 10, wherein the package is implemented in a device selected from the group consisting of music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, stationary terminals, tablet computers, computers, wearable devices, laptop computers, servers, Internet of Things (IoT) devices, and devices in automated vehicles.

[0127]

[0138] Various features of the Disclosure described herein can be implemented in various systems without departing from the Disclosure. It should be noted that the above-described embodiments of the Disclosure are merely examples and should not be construed as limiting the Disclosure. The descriptions of embodiments of the Disclosure are intended to be illustrative and not to limit the scope of embodiments. Therefore, these teachings can be readily applied to other types of devices, and many alternative, modified, and variant forms will be apparent to those skilled in the art.

Claims

1. It is a package, Package substrate and A first integrated device coupled to the package substrate through a first plurality of solder interconnections, A sealing layer that at least partially seals the first integrated device, A plurality of post interconnection parts located within the sealing layer, A metallization portion coupled to the plurality of post interconnection parts, A second integrated device coupled to the metallization portion through a second plurality of solder interconnections, The optical integrated device coupled to the aforementioned package substrate, A package comprising an optical fiber coupled to the aforementioned optical integrated device.

2. The package according to claim 1, wherein the front surface of the first integrated device is oriented toward the package substrate.

3. The package according to claim 1, wherein the second integrated device is configured to be electrically coupled to the optical integrated device through an electrical path including solder interconnects from the second plurality of solder interconnects, metallization interconnects from the metallization portion, post interconnects from the plurality of post interconnects, and solder interconnects from the first plurality of solder interconnects.

4. The package according to claim 1, wherein the first integrated device is configured to be electrically coupled to the optical integrated device through an electrical path including solder interconnections from the first plurality of solder interconnections.

5. The package according to claim 1, wherein the second integrated device is configured to be electrically coupled to the first integrated device through an electrical path including solder interconnects from the second plurality of solder interconnects, metallization interconnects from the metallization portion, post interconnects from the plurality of post interconnects, solder interconnects from the first plurality of solder interconnects, interconnects from the package substrate, and other solder interconnects from the first plurality of solder interconnects.

6. The package according to claim 1, wherein the second integrated device is configured to be electrically coupled to the first integrated device through an electrical path including solder interconnects from the second plurality of solder interconnects, metallization interconnects from the metallization portion, post interconnects from the plurality of post interconnects, solder interconnects from the first plurality of solder interconnects, the optical integrated device, and another solder interconnect from the first plurality of solder interconnects.

7. The package according to claim 1, further comprising a connector socket coupled to the metallization portion, wherein the connector socket is configured to provide an electrical path for power.

8. The package according to claim 1, wherein the optical integrated device includes a waveguide and a circuit for processing optical and / or electrical signals.

9. The package according to claim 1, wherein the optical fiber extends through the package substrate.

10. The package according to claim 1, wherein the second integrated device includes a memory.

11. It is a package, The metallization part, A first integrated device coupled to the metallization portion through a first plurality of solder interconnections, wherein the front surface of the first integrated device is oriented toward the metallization portion, A sealing layer that at least partially seals the first integrated device, A plurality of post interconnection parts located within the sealing layer, A second integrated device coupled to the metallization portion through a second plurality of solder interconnections, An optical integrated device coupled to the metallization portion through a third plurality of solder interconnections, An optical fiber coupled to the aforementioned optical integration device, A package comprising a package substrate coupled to the plurality of post interconnections through a fourth plurality of solder interconnections.

12. The package according to claim 11, wherein the second integrated device is coupled to the optical integrated device through an electrical path including solder interconnects from the second plurality of solder interconnects, metallization interconnects from the metallization portion, and solder interconnects from the third plurality of solder interconnects.

13. The package according to claim 11, wherein the first integrated device is coupled to the optical integrated device through an electrical path including solder interconnects from the first plurality of solder interconnects, metallization interconnects from the metallization portion, and solder interconnects from the third plurality of solder interconnects.

14. The package according to claim 11, wherein the second integrated device is coupled to the first integrated device through an electrical path including solder interconnects from the second plurality of solder interconnects, metallization interconnects from the metallization portion, and solder interconnects from the first plurality of solder interconnects.

15. The package according to claim 11, further comprising a passive device coupled to the metallization portion.

16. The package according to claim 15, wherein the passive device is at least partially sealed by the sealing layer.

17. The package according to claim 11, further comprising a plurality of power rail interconnection parts located within the sealing layer.

18. The package according to claim 17, wherein the plurality of power rail interconnection portions are located between the back surface of the first integrated device and the package substrate.

19. The package according to claim 11, wherein the second integrated device includes a memory.

20. The package according to claim 11, further comprising a connector socket coupled to the metallization portion, wherein the connector socket is configured to provide an electrical path for power.

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