Lateral partitioned digit line memory architecture

Abstract

Methods, systems, and devices for a laterally divided digit line memory architecture are described. A memory array may include a first set of word line plates separated from a second set of word line plates by pillars (e.g., pillars configured as digit lines), the pillars interacting with the first and second sets of word line plates. Furthermore, the memory array may include a set of dielectric piers positioned between the pillars, each dielectric pier contacting the first and second pillars. Furthermore, the memory array may include a set of memory elements and a set of digit lines, which are coupled to the word line plates, pillars, and dielectric material positioned between the first and second pillars of each pair of pillars.

Description

Technical Field

[0001] Cross-reference This patent application claims priority and benefit to U.S. Patent Application No. 18 / 440,460, by Fratin et al., titled "LATERAL SPLIT DIGIT LINE MEMORY ARCHITECTURES," filed on February 13, 2024, and U.S. Provisional Patent Application No. 63 / 447,546, by Fratin et al., titled "LATERAL SPLIT DIGIT LINE MEMORY ARCHITECTURES," filed on February 22, 2023, each of which has been assigned to the assignee of this specification, and each of which is hereby expressly incorporated by reference in its entirety.

[0002] The following relates to one or more systems for memory, including a lateral split digit line memory architecture.

Background Art

[0003] Memory devices are widely used in devices such as computers, user devices, wireless communication devices, cameras, and digital displays to store information. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed into one of two supported states, often one of the states represented by logic 1 or logic 0. In some embodiments, a single memory cell can support two or more states, and any one of these can be stored. To access the stored information, the memory device can read out (e.g., sense, detect, acquire, identify) the state from the memory cell. To store information, the memory device can write (e.g., program, set, assign) a state to the memory cell.

[0004] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive random-access RAM (RRAM), flash memory, phase-change memory (PCM), self-selecting memory, chalcogenide memory technology, negative OR (NOR) memory devices, and negative AND (NAND) memory devices. Memory cells can be described in terms of volatile or non-volatile configurations. Non-volatile memory cells can maintain their stored logical state for a long time even without an external power supply. Volatile memory cells can lose their stored state when disconnected from an external power supply. [Brief explanation of the drawing]

[0005] [Figure 1] Examples of memory arrays supporting a lateral partitioned digit-line memory architecture are shown according to embodiments disclosed herein. [Figure 2A] A side view of an example of a memory array supporting a lateral partitioned digit-line memory architecture according to the embodiments disclosed herein is shown. [Figure 2B] A side view of an example of a memory array supporting a lateral partitioned digit-line memory architecture according to the embodiments disclosed herein is shown. [Figure 3] Examples of material arrangements supporting a lateral split digit line memory architecture are shown according to the embodiments disclosed herein. [Figure 4] Examples of material arrangements supporting a lateral split digit line memory architecture are shown according to the embodiments disclosed herein. [Figure 5] Examples of material arrangements supporting a lateral split digit line memory architecture are shown according to the embodiments disclosed herein. [Figure 6]Examples of material arrangements supporting a lateral split digit line memory architecture are shown according to the embodiments disclosed herein. [Figure 7] Examples of material arrangements supporting a lateral split digit line memory architecture are shown according to the embodiments disclosed herein. [Figure 8] Examples of material arrangements supporting a lateral split digit line memory architecture are shown according to the embodiments disclosed herein. [Figure 9] Examples of material arrangements supporting a lateral split digit line memory architecture are shown according to the embodiments disclosed herein. [Figure 10] Examples of material arrangements supporting a lateral split digit line memory architecture are shown according to the embodiments disclosed herein. [Figure 11] Examples of material arrangements supporting a lateral split digit line memory architecture are shown according to the embodiments disclosed herein. [Figure 12] Examples of material arrangements supporting a lateral split digit line memory architecture are shown according to the embodiments disclosed herein. [Figure 13] Examples of material arrangements supporting a lateral split digit line memory architecture are shown according to the embodiments disclosed herein. [Figure 14] Examples of material arrangements supporting a lateral split digit line memory architecture are shown according to the embodiments disclosed herein. [Figure 15] Examples of material arrangements supporting a lateral split digit line memory architecture are shown according to the embodiments disclosed herein. [Figure 16] A flowchart illustrating one or more methods for supporting a lateral partitioned digit-line memory architecture according to the embodiments disclosed herein is shown. [Figure 17] A flowchart illustrating one or more methods for supporting a lateral partitioned digit-line memory architecture according to the embodiments disclosed herein is shown. [Modes for carrying out the invention]

[0006] This disclosure relates to a memory device having a divided digit line architecture and a method for processing the same. The memory device may include an arrangement of conductive contacts and openings through alternating layers of conductive and insulating materials, thereby reducing the spacing between memory cells while maintaining the dielectric thickness that sustains the voltage applied to the memory array of the memory device.

[0007] In some embodiments, the memory device may include a substrate on which a set of contacts is arranged in a pattern (e.g., a geometric pattern). During the manufacturing of the memory device, a stack of layers may be formed on the substrate. For example, a stack of layers may be formed by depositing alternating layers of nitride material (or another type of material which may be a sacrificial material) and a first dielectric material on the substrate. In the first example (e.g., a trench and pier architecture), a trench may be formed through the stack of layers to expose the substrate. For example, the trench may be formed to divide the stack into two sections or two sets of plates. After the trench is formed, a set of dielectric piers (e.g., including a second dielectric material) may be formed along the trench. In the second example (e.g., a pillar and pier architecture), a set of dielectric piers may be formed without first forming a trench through the stack. For example, a set of cavities extending through the stack of layers may be formed, and a set of dielectric piers may be formed by depositing the second dielectric material in each cavity of the set of cavities. Next, a second set of cavities is formed through the stack of layers, each cavity extending through the stack of layers and exposing the substrate. In this example, the second set of cavities may functionally divide the stack into two sections or two plate sets (similar to the trenches in the first example, for example).

[0008] In each case, after forming a set of dielectric piers, a wordline plate may be formed by replacing the layer of nitride material with a conductive material. The wordline plate may include a set of even wordline plates separated from a set of odd wordline plates (e.g., by trenches or any other set of cavities). Next, a set of dielectric pillars extending through the stack of material and in contact with the substrate may be formed between the sets of dielectric piers, each dielectric pillar including a third dielectric material (e.g., an insulating pillar sheath) surrounding a fourth dielectric material (e.g., a core dielectric material). By removing portions of the dielectric piers and pillar sheaths, a third set of cavities may be formed, and each dielectric pillar may have a first remaining portion and a second remaining portion of the pillar sheath. In some cases, the first portion of each remaining pillar sheath may mechanically bond each dielectric pillar to a first sidewall of the material stack, and the second portion of each remaining pillar sheath may mechanically bond each dielectric pillar to a second sidewall of the material stack. After forming a third cavity, a set of conductive pillars (e.g., configured as digit lines or bit lines) can be formed by depositing a second conductive material within the set of third cavities. In some cases, each conductive pillar may be in contact with a portion of the sidewall of a dielectric pillar sheath (e.g., related to the core of a dielectric pillar) and the sidewall of a fourth dielectric material. Memory cells can then be formed by depositing memory material, with each memory cell being coupled to one conductive pillar and one word line plate.

[0009] Such memory device configurations and manufacturing methods may enable higher density memory cells compared to conventional solutions. For example, the digit line and memory cell configurations described herein may enable higher density digit lines and memory cells with respect to some conventional solutions. Similarly, as described herein, the dielectric pier configuration and the portion of the dielectric pillar sheath that connects the dielectric pillars to the sidewalls of the material stack may improve stability or tolerance, which may result in reduced variability or improved consistency, among other advantages, when forming subsequent mechanisms (e.g., circuit structures, access lines, memory cells). That is, the dielectric piers and the remaining portion of the dielectric pillar sheath may be formed in contact with the cross-sectional pattern, so that when other materials in the stack (e.g., nitride materials in a replacement gate process, dielectric piers, etc.) are removed, the dielectric piers or the remaining portion of the dielectric pillar sheath provide mechanical support for the cross-sectional pattern of the remaining material.

[0010] First, the features of the memory devices and arrays of this disclosure will be described with reference to Figures 1, 2A, and 2B. The features of the material arrangement of this disclosure will be described with reference to Figures 3 through 15. These and other features of this disclosure will be further illustrated and described with reference to flowcharts relating to the lateral split digit line memory architecture, which will be described with reference to Figures 16 and 17.

[0011] Figures 1, 2A, and 2B show examples of memory arrays 100 supporting a laterally divided digit line memory architecture according to embodiments disclosed herein. Figure 1 shows a top cross-sectional view (e.g., section A-A) of the memory array 100 with respect to the cross-section A-A shown in Figures 2A and 2B. Figure 2A shows a side cross-sectional view (e.g., section B-B) of the memory array 100 with respect to the cross-section B-B shown in Figure 1. Figure 2B shows a side cross-sectional view (e.g., section C-C) of the memory array 100 with respect to the cross-section C-C shown in Figure 1. The cross-sectional views may be examples of cross-sectional views of the memory array 100 with some aspects (e.g., dielectric structure) removed for clarity. As shown in Figures 1, 2A, and 2B respectively, the elements of the memory array 100 can be described with respect to the x, y, and z directions. To enhance the visibility and clarity of the depicted mechanisms, some elements included in Figures 1, 2A, and 2B are labeled with numerical markers, while other corresponding elements are not labeled, although it will be understood that they are identical or similar. Furthermore, while the example of memory array 100 shown includes several quantities of repeating elements, the techniques of the embodiments described herein may be applicable to any quantity of such elements, or to any ratio of repeating elements of one repeating element to another.

[0012] In the example of the memory array 100, the memory cells 102 and word lines 105 may be distributed along the z-direction according to levels 130 (e.g., decks, layers, planes, tiers shown in Figures 2A and 2B). In some embodiments, the z-direction may be orthogonal to the substrate (not shown) of the memory array 100, and the substrate may be located beneath the shown structure along the z-direction. The example of the memory array 100 shown includes four levels 130, but the memory array 100 according to the embodiments disclosed herein may include any number of one or more levels 130 along the z-direction (e.g., 64 levels, 128 levels).

[0013] Each word line 105 may be an example of a portion of an access line formed of one or more conductive materials (e.g., one or more metal portions, one or more metal alloy portions). As shown, a word line 105 may be formed of a comb structure including portions (e.g., projections, forks) that extend along the y-direction through the gaps between pillars 120 (e.g., alternating gaps). For example, as shown, a memory array 100 may include two word lines 105 for each level 130 (e.g., by an odd word line 105-a-n1 and an even word line 105-a-n2 of a given level n), and such word lines 105 of the same level 130 may be described as being arranged alternately (e.g., the portion of the odd word line 105-a-n1 protrudes along the y-direction between the portion of the even word line 105-a-n2, and vice versa). In some embodiments, an odd word line 105 (e.g., one at level 130) may be associated with a first memory cell 102 located on a first side of a given pillar 120 (e.g., along the x-direction), and an even word line (e.g., one at the same level 130) may be associated with a second memory cell 102 located on a second side of a given pillar 120 (e.g., on the opposite side of the first memory cell 102 along the x-direction). Thus, in some embodiments, a given memory cell 102 at level 130 may be addressed (e.g., selected, activated) by an even word line 105 or an odd word line 105.

[0014] Each pillar 120 can be an example of a portion of an access line (e.g., a conductive pillar portion) formed of one or more conductive materials (e.g., one or more metal parts, one or more metal alloys). As shown, the pillars 120 can be arranged in a two-dimensional array (e.g., the xy plane) having a first number of pillars 120 (e.g., eight pillars along the x direction, eight rows of pillars) along a first direction and a second number of pillars 120 (e.g., five pillars along the y direction, five columns of pillars) along a second direction. The example of the memory array 100 shown includes a two-dimensional array of eight pillars 120 along the x direction and five pillars 120 along the y direction, but the memory array 100 according to the embodiments disclosed herein may include any number of pillars 120 along the x direction and any number of pillars 120 along the y direction. Further, as shown, each pillar 120 can be coupled to a respective set of memory cells 102 (e.g., one or more memory cells 102 of each level 130 along the z direction). The pillar 120 can have a cross-sectional area in the xy plane, which extends along the z direction. The pillar 120 is shown as having a circular cross-sectional area in the xy plane, but may be formed in different shapes such as having an elliptical, square, rectangular, polygonal, or other cross-sectional area in the xy plane.

[0015] Each memory cell 102 can include a chalcogenide material. In some embodiments, the memory cell 102 can be an example of a threshold processing memory cell. Each memory cell 102 can be accessed (e.g., addressed, selected) according to an intersection between a word line 105 (e.g., a level selection that can include an even or odd selection within level 130) and a pillar 120. For example, as shown, the selected memory cell 102-a at level 130-a-3 can be accessed according to an intersection between pillar 120-a-43 and word line 105-a-32.

[0016] By applying an access bias (e.g., an access voltage Vaccess that can be a positive voltage or a negative voltage) across the memory cell 102, an access (e.g., write, read) regarding the memory cell 102 can be performed. In some embodiments, by biasing the select word line 105 with a first voltage (e.g., Vaccess / 2), and by biasing the select pillar 120 with a second voltage (e.g., -Vaccess / 2) that can have a sign opposite to that of the first voltage, the access bias can be applied. Regarding the selected memory cell 102-a, a corresponding access bias (e.g., the first voltage) can be applied to the word line 105-a-32, while the other non-selected word lines 105 can be grounded (e.g., biased to 0V). In some embodiments, the word line bias can be provided by a word line driver (not shown) coupled to one or more of the word lines 105.

[0017] To apply a corresponding access bias (e.g., the second voltage) to the pillar 120, the pillar 120 can be configured to be selectively coupled to the sense line 115 (e.g., a digit line, column line, access line extending along the y direction), and this coupling is performed via respective transistors 125 coupled (e.g., physically, electrically) between the pillar 120 and the sense line 115. In some embodiments, the transistor 125 can be a vertical transistor (e.g., a transistor having a channel along the z direction, a transistor having a semiconductor junction along the z direction), and the vertical transistor can be formed above the substrate of the memory array 100 using various techniques (e.g., thin film techniques).

[0018] Transistor 125 (e.g., the channel portion of transistor 125) can be activated by gate lines 110 (e.g., activation lines, selection lines, row lines, access lines extending along the x-direction) coupled to the gates of each of the sets of transistors 125 (e.g., sets along the x-direction). In other words, each of the pillars 120 may have a first end (e.g., a bottom end facing the negative z-direction) configured to be coupled to an access line (e.g., a sense line 115). In some embodiments, the gate lines 110, transistors 125, or both may be considered components of a row decoder (e.g., pillar decoder components). In some embodiments, a selection of pillars 120, or sense lines 115, or various combinations thereof (e.g., bias application) may be supported by a row decoder, a sense component, or both.

[0019] To apply the corresponding access bias (e.g., -Vaccess / 2) to pillar 120-a-43, sense line 115-a-4 may be biased with the access bias, gate line 110-a-3 may be grounded (e.g., biased to 0V), or biased with an activation voltage. In embodiments where transistor 125 is an n-type transistor, gate line 110-a-3, which is biased with a voltage relatively higher than that of sense line 115-a-4, may activate transistor 125-a (e.g., operate transistor 125-a in a conductive state), thereby coupling pillar 120-a-43 with sense line 115-a-4, and pillar 120-a-43 may be biased with the associated access bias. However, transistor 125 may include different channel types or operate according to different bias schemes to support various access operations.

[0020] In some embodiments, the unselected pillar 120 of the memory array 100 may be electrically floating when transistor 125-a is activated, or may be coupled to another voltage source to avoid voltage drift in pillar 120 (e.g., via a high-resistance path, via a leakage path, or grounded). For example, even if a ground voltage is applied to gate line 110-a-3, the ground voltage of gate line 110-a-3 may be less than or equal to the voltage of other sense lines 115 (e.g., other sense lines 115 may be biased with the ground voltage or may be floating), so other transistors coupled to gate line 110-a-3 will not be activated. Furthermore, other unselected gate lines 110, including gate line 110-a-5 shown in Figure 2A, may be biased with a voltage equal to or similar to the access bias (e.g., -Vaccess / 2, or some other negative bias or bias relatively close to the access bias voltage), so transistors 125 along the unselected gate lines 110 will not be activated. Therefore, transistor 125-b coupled to gate line 110-a-5 can be deactivated (for example, it can operate in a non-conductive state), thereby isolating the voltage of sense line 115-a-4 from pillar 120-a-45 among the many pillars 120.

[0021] In some embodiments, a memory device (e.g., including one or more memory arrays 100) may include a substrate on which a set of contacts is arranged in a pattern (e.g., a geometric pattern). During the manufacture of the memory device, a stack of layers may be formed on the substrate. For example, a stack of layers may be formed by depositing alternating layers of nitride material (or another type of material which may be a sacrificial material) and a first dielectric material on the substrate. In the first case, a trench may be formed through the stack of layers to expose the substrate. For example, a trench may be formed to divide the stack into two sections or two sets of plates. After the trench is formed, a set of dielectric piers (e.g., including a second dielectric material) may be formed along the trench. In the second case, a set of dielectric piers may be formed without first forming a trench through the stack. For example, a set of cavities extending through the stack of layers may be formed, and a set of dielectric piers may be formed by depositing the second dielectric material in each cavity of the set of cavities. Then, a second set of cavities is formed through the stack of layers, each cavity extending through the stack of layers and exposing the substrate. In this example, the second set of cavities could functionally divide the stack into two sections or two plate sets (similar to the trench in the first example, for example).

[0022] In each case, after forming a set of dielectric piers, a wordline plate may be formed by replacing the nitride material layer with a conductive material. The wordline plate may include a set of even wordline plates separated from a set of odd wordline plates (e.g., by trenches or other sets of cavities). Next, a set of conductive pillars 120 that contact the substrate may be formed between the sets of dielectric piers. For example, a second conductive material may be conformally deposited on the sidewalls of cavities extending between the dielectric piers, and a third dielectric material may be deposited within the cavities. An insulating pillar sheath may be formed by depositing an insulating material on the sidewalls of the cavities (e.g., on the third dielectric material, on the dielectric piers). A conductive pillar 120 may be formed by depositing a fourth dielectric within the cavities (e.g., each conductive pillar 120 is surrounded by a pillar sheath). By removing portions of the dielectric piers and pillar sheaths, a third set of cavities may be formed, and a fourth dielectric material may be deposited within portions of the third cavities. The fourth dielectric material may be partially removed, and thus a conductive material (e.g., similar to the second conductive material) may be deposited within the third cavity to form digit lines (e.g., each digit line may be partially surrounded by the fourth dielectric material). By removing portions of the third dielectric material, voids may be formed, and memory cells may be formed within sets of voids, each void being defined by a pillar 120, a word line plate, and one of the adjacent layers of the third dielectric material. Thus, the material associated with each pillar 120 may, for each pillar 120, include two divided digit lines (e.g., a total of four digit lines) and four memory cells.

[0023] Figures 3 to 15 illustrate examples of manufacturing operations that may support a laterally divided digit line memory architecture according to embodiments disclosed herein. For example, Figures 3 to 15 may illustrate operations for manufacturing an aspect of material arrangement 300 that may be part of a memory device (e.g., part of a memory array 100, part of a memory die). Each of Figures 3 to 15 may illustrate an aspect of material arrangement 300 after a different subset or alternative of manufacturing operations for forming the material arrangement 300 (e.g., material arrangement 300-a after a first set of one or more manufacturing operations, material arrangement 300-b after a second set of one or more manufacturing operations, and so on). Each of the figures in Figures 3 to 15 may be described with reference to the indicated x, y, and z directions, which may correspond to the respective directions described with reference to the memory array 100.

[0024] Each of Figures 3 to 15 includes a cross-sectional view showing an exemplary cross-section of the material arrangement 300. For example, in Figures 3 to 15, the "section E-E'" may be associated with a cross-section in the xy plane (e.g., by the cutting plane E-E') passing through the portion of the material arrangement 300 related to the word line 105 and the memory cell 102 (e.g., activation level, level 130), the "section F-F'" may be associated with a cross-section in the xy plane (e.g., by the cutting plane F-F') passing through the portion of the material arrangement 300 related to the word line 105 and the memory cell 102 (e.g., activation level, level 130), and the "section D1-D1'" may be associated with a conductive pyramidal A section of the material arrangement 300 may be associated with a portion of the material arrangement 300 related to a pillar (e.g., pillar 120) in the xz plane (e.g., by cross-sections D1-D1'), a section of "section D2-D2'" may be associated with a portion of the material arrangement 300 related to a pier (e.g., structural pier, dielectric pier) in the xz plane (e.g., by cross-sections D2-D2'), and a section of "section D3-D3'" may be associated with a portion of the material arrangement 300 related to a conductive pillar (e.g., pillar 120) in the xz plane (e.g., by cross-sections D3-D3'). While the material arrangement 300 illustrates an example of specific relative dimensions and quantities for various mechanisms, embodiments of the material arrangement 300 may be implemented with other relative dimensions or quantities for such mechanisms according to the embodiments disclosed herein.

[0025] The operations shown in and described with reference to Figures 3 to 15 may be performed by a manufacturing system, such as a semiconductor fabrication system, configured to perform additional operations such as deposition or bonding, removal operations such as etching, trenching, planarization, or polishing, and supporting operations such as masking, patterning, photolithography, or aligning, among many operations that support the techniques described. In some embodiments, the operations performed by such a manufacturing system may be supported by a process controller or its components as described herein.

[0026] Figure 3 shows an example of a material placement 300 after a first set of one or more manufacturing operations supporting a lateral split digit line memory architecture according to embodiments disclosed herein (e.g., as material placement 300-a). The first set of operations may include depositing a stack of layers 310 on a substrate 305. The substrate 305 may be a semiconductor wafer or other substrate on which the stack of layers 310 is deposited. The substrate 305 may include one or more conductive contacts 325 within the same cavity. The conductive contacts 325 may be in direct contact with the substrate 305 and may be used as interconnections between various elements of the material placement 300 (e.g., the substrate 305, various access lines, various pillars, access circuits). The stack of layers 310 is shown as a deposit in direct contact with the substrate 305 and associated conductive contacts 325, but in some other embodiments, the material arrangement 300 may include other materials or components between the stack of layers 310 and the substrate 305 (e.g., conductive contacts 325), such as interconnect or routing circuits (e.g., access lines, sense lines, gate lines), control circuits (e.g., transistors, local memory controllers, decoders, multiplexers), or another stack of layers 310 (e.g., another stack of layers 310 processed according to embodiments disclosed herein), and various conductors, semiconductors, or dielectric materials may be included between the stack of layers 310 and the substrate 305. For example, the material arrangement 300 may include a layer containing thin-film transistors (TFTs) between the substrate 305 and the stack of layers 310, among many others, such as transistors. In some embodiments, the substrate 305 itself may include such interconnect or routing circuits.

[0027] The stack of layers 310 may comprise alternating layers of material 315 (e.g., a first material) and material 320 (e.g., a second material), which can be formed using at least partially alternating material deposition operations. In some embodiments, material 315 may comprise a dielectric material (e.g., a first dielectric material) such as an oxide (e.g., tear oxide, silicon oxide), which can provide electrical insulation between levels. Material 320 may comprise a variety of materials different from material 315, which can support differential processing (e.g., differential etching, high selectivity). For example, the layer of material 320 may be a sacrificial layer (e.g., a material that cannot be present in the completed portion of material arrangement 300). In some embodiments, material 320 may be a nitride material (e.g., tear nitride, silicon nitride). The layer stack 310 is shown to have 9 layers (for example, 5 layers of material 315 and 4 layers of material 320), but the layer stack 310 according to the embodiments disclosed herein may include any number of layers (for example, tens of layers, hundreds of layers, etc.) in which each layer consists of two or more materials, such that either material 315 or material 320 is relatively close to the substrate 305.

[0028] Figure 4 shows an example of a material placement 300 after a first alternative, including a second set of one or more manufacturing operations supporting a lateral split digit line memory architecture, according to embodiments disclosed herein (e.g., as material placement 300-b). In some embodiments, these second sets of manufacturing operations are performed on material placement 300-a to form material placement 300-b. The second set of operations may include operations (e.g., trench etching operations) that support the formation of trenches 405 through the stack of layers 310 (e.g., by removing portions of material 315 and material 320 along the z-direction to the substrate 305 and associated conductive contacts 325, or to the intervening material between the stack of layers 310 and the substrate 305). In some embodiments, forming trenches 405 may include patterning by depositing a masking material (e.g., performed on the stack of layers 310, but not shown), followed by etching operations (e.g., dry etching operations such as reactive ion etching (RIE) that support material removal in a preferred direction along the z-direction). The trenches 405 may extend along the y-direction and may correspond to isolated regions of the memory array located between access lines (e.g., between word lines or between protrusions of word lines along the y-direction). In some embodiments, the trenches 405 may be aligned along the direction of the pillars. For example, the sidewalls of the trenches 405 may coincide with the sidewalls of the pillars formed in later operations, so that the sidewalls of the trenches 405 can provide pillar alignment, among many other mechanisms of the material arrangement 300, and support the operation as a memory array (e.g., it may improve array density and reduce the possibility of misalignment of the mechanism).

[0029] A second set of operations may also include operations (e.g., trench filling operations) that involve depositing material 410 (e.g., one or more third materials) into the trench 405. Material 410 may be a nitride material and may be referred to as a sacrificial material. In some embodiments, material 410 may be the same as material 320 (e.g., sacrificial material, nitride material). In some other embodiments, material 410 may be different from materials 315 and 320, thereby supporting a manner of material removal distinction (e.g., selectivity) between materials 315, 320, and 410. In some embodiments, a second set of operations may include a planaring operation (e.g., polishing operation, chemical mechanical planaring (CMP) operation) that planarizes the upper surface of material arrangement 300-b, thereby supporting a manner of subsequent operations.

[0030] Figure 5 shows an example of a material placement 300 after a third set of one or more manufacturing operations supporting a lateral split digit line memory architecture, as included in the first alternative according to embodiments disclosed herein (e.g., as material placement 300-c). The third set of manufacturing operations may be performed on material placement 300-b to form material placement 300-c. The third set of operations may include operations (e.g., pier etching operations) that support the formation of a set of piers 505 (e.g., dielectric piers). The third set of operations may include forming cavities (e.g., cavities that will be later filled to create dielectric piers 505) based on removing portions of material 410 (e.g., along the z-direction, up to the substrate 305, conductive contacts 325, or intervening material between the stack of layers 310 and the substrate 305) to form the piers 505. In some embodiments, by forming each cavity, the first sidewall of each of the stacks 310 of layers may be exposed on the first side of each cavity (e.g., along the x-direction), and the second sidewall of each of the stacks 310 of layers may be exposed on the second side of the cavity (e.g., along the x-direction). In some embodiments, when the cavity is formed wider than the trench 405, for example, along the x-direction, forming the cavity may also include removing portions of material 315 and material 320 (e.g., along the z-direction, up to the substrate 305, or to the intervening material between the stacks 310 of layers and the substrate 305). In various embodiments, the cavity may be wider than the trench 405, which may be for several reasons, including to support a degree of misalignment between the patterning of the cavity and the patterning of the trench 405 (e.g., along the x-direction), or to support the formation of protrusions of material 315 and material 320 between the cavities (e.g., along the x-direction, for the formation of memory cells), or for both. In some embodiments, forming a cavity may involve depositing and patterning a masking material (e.g., on a stack of layers 310 and material 410, but not shown), followed by an etching operation (e.g., a dry etching operation such as RIE that supports material removal in a preferred direction along the z-direction).

[0031] A third set of operations may also include operations (e.g., pier filling operations) that support the formation of a set of piers 505 (e.g., dielectric piers) (e.g., in sets along each trench 405, along the z-direction). For example, a third set of operations may include depositing material 510 in the cavity to form the piers 505 (e.g., the deposits are in contact with the exposed sidewalls of the stack of layers 310 and in contact with the substrate 305). In some embodiments, material 510 may be a dielectric material or an oxide material. In some embodiments, material 510 of piers 505 may be selected to have relatively high strength, high rigidity, bonding strength with material 315, bonding strength with the substrate 305, or any combination thereof. In some embodiments, such as those in which material 320 is removed in subsequent operations, material 510 of piers 505 may be selected to have greater selectivity for differential processing of material 320. In some embodiments, multiple materials 510 may be deposited in the cavity to form piers 505, for example, when piers 505 are formed by first depositing a liner material (e.g., a dielectric liner) in the cavity and then filling it with liner material (e.g., together with a material that may be a conductor, semiconductor, or dielectric). In some embodiments, a third set of operations may include a planarization operation (e.g., a polishing operation, a CMP operation) that flattens the upper surface of the material arrangement 300-c, thereby supporting a subsequent set of operations.

[0032] Figure 6 shows an example of a material arrangement 300 after a second alternative, which includes a second set of one or more manufacturing operations supporting a lateral split digit line memory architecture, according to embodiments disclosed herein (e.g., as material arrangement 300-d). These second sets of manufacturing operations included in the second alternative may be performed on material arrangement 300-a to form material arrangement 300-d (e.g., as an alternative to the second set of manufacturing operations performed on material arrangement 300-a to form material arrangement 300-b). In some embodiments, the second set of operations of the alternative may include forming a set of piers 505. As previously stated, the piers 505 may be an example of a support structure, such as pillars or rows of dielectric material that adhere to or provide support for the stack of layers 310, the substrate 305, the conductive contacts 325, or a combination thereof. In some embodiments, the piers 505 may provide mechanical support to the stack of materials during subsequent steps of the manufacturing process. For example, Pier 505 can restrict the movement of the material stack to the x, y, z directions, or any combination thereof.

[0033] To form the piers 505 shown in material arrangement 300-d, a set of cavities may be formed by performing vertical etching through a stack of material using a first etching mask. In some cases, the etching may be completed above the substrate 305 and the conductive contacts 325; that is, the substrate 305 and the conductive contacts 325 are not etched during the etching process. In some cases, the formation of the cavities may expose the substrate 305. Next, a second set of alternative operations may involve depositing a pier material 510, such as a dielectric material, into each cavity of the set of cavities. The dielectric material 510 may fill the set of cavities and may contact each layer of the stack of layers 310 (e.g., each layer of material 315, each layer of material 320). Additionally or alternatively, the piers 505 may include a dielectric liner material such as an oxide or nitride and a filler material such as aluminum oxide (AlOx), oxide, or polysilicon. Therefore, the set of piers 505 can provide mechanical support to the stack of layers 310 during subsequent steps of the manufacturing process. In some embodiments, the dielectric material 510 of the piers 505 may be the same as the dielectric material of the material 315. Alternatively, the material 510 of the piers 505 may be a different material or a combination of materials (for example, with respect to material 315). In some embodiments, forming the set of piers 505 may include a polishing step. For example, after depositing the pier material 510, the stack of layers 310 may be polished or planarized using, for example, a CMP procedure.

[0034] Figure 7 shows an example of a material placement 300 after a third set of one or more manufacturing operations supporting a lateral partitioned digit line memory architecture, as included in a second alternative according to embodiments disclosed herein (e.g., as material placement 300-e). These third sets of manufacturing operations may be performed on material placement 300-d to form material placement 300-e (e.g., as an alternative to a third set of manufacturing operations performed on material placement 300-b to form material placement 300-c). The third set of operations in the alternative may include forming a set of cavities 705 in material placement 300-e. The set of cavities 705 may be formed by etching or removing material from a stack of layers 310 (e.g., a layer of material 315, a layer of material 320). In some cases, forming the set of cavities 705 may expose portions of the sidewalls of piers 505 and portions of the stack of layers 310. Furthermore, by forming a set of cavities 705, portions of the substrate 305 and portions of the conductive contacts 325 may be exposed. For example, by forming each cavity 705, the first sidewall of each of the layer stacks 310 may be exposed on the first side of the cavity 705 (e.g., along the x-direction), and the second sidewall of each of the layer stacks 310 may be exposed on the second side of the cavity 705 (e.g., along the x-direction). In some embodiments, by forming each cavity 705, the sidewall of each of the first piers 505 (e.g., made of material 510) may be exposed on the first side of the cavity 705 (e.g., along the y-direction), and the sidewall of each of the second piers 505 may be exposed on the second side of the cavity 705 (e.g., along the y-direction).

[0035] In some embodiments, the etching process for forming the set of cavities 705 may be selective with respect to the material of the set of piers 505 and the stack of layers 310. That is, the etching process may selectively remove materials such as material 315 and material 320 while preserving the material of the set of piers 505 or the stack of layers 310. Thus, a set of isolated holes (e.g., corresponding to each position of the cavity 705) may be etched with the pattern used to etch the set of cavities 705. In such cases, the etching process may be directional (e.g., etching along the z-direction).

[0036] Figure 8 shows an example of a material placement 300 after a fourth set of one or more manufacturing operations supporting a lateral split digit line memory architecture according to embodiments disclosed herein (e.g., as material placement 300-f). The fourth set of operations may include operations that support the formation of a set of access lines 805 (e.g., pillar etching operations). There may be two alternative fourth sets of operations for forming material placement 300-f, namely a first alternative fourth set of operations performed on material placement 300-c to form material placement 300-f, and a second alternative fourth set of operations performed on material placement 300-e to form material placement 300-f.

[0037] In the first alternative of the fourth set of operations (e.g., when forming material arrangement 300-c using a trench and pier fabrication method), the fourth set of operations may include operations that support forming the cavity 705 based on removing portions of material 410 (e.g., along the z-direction, according to the operations of Figure 5, up to the substrate 305, up to the conductive contact 325, or up to the intervening material between the stack of layers 310 and the substrate 305). In some embodiments, forming each cavity 705 may expose the first sidewall of each of the stack of layers 310 on the first side of the cavity 705 (e.g., along the x-direction) and the second sidewall of each of the stack of layers 310 on the second side of the cavity 705 (e.g., along the x-direction). In some embodiments, by forming each cavity 705, the sidewalls of the first pier 505 (e.g., made of material 510) may be exposed on the first side of the cavity 705 (e.g., along the y-direction), and the sidewalls of the second pier 505 may be exposed on the second side of the cavity 705 (e.g., along the y-direction). In some embodiments, forming the cavity 705 may involve depositing and patterning a masking material (e.g., on a material arrangement 300-c including a stack of layers 310, material 510, and material 410, but not shown), followed by an etching operation (e.g., a dry etching operation such as RIE that supports material removal in a preferred direction along the z-direction). In some other embodiments, forming the cavity 705 may omit the patterning, and instead, another material removal operation may be used, such as a wet etching operation that preferentially removes the rest of material 410. In some embodiments (for example, when material 410 is the same as material 320), such etching operations may also involve removing the remaining portion of material 320. In some cases, a material stack similar to material arrangement 300-e shown in Figure 7 can be formed by performing an operation to form a cavity 705 with respect to material arrangement 300-c.

[0038] Next, in both the first and second alternatives, an operation is performed to replace a layer of nitride material 320 in the stack of layers 310 with a layer of conductive material 810 (for example, for a material arrangement that is or is similar to material arrangement 300-e). For example, a fourth set of operations may include operations that support the formation of voids between the layers of material 315 (e.g., mining operations, nitride mining). For example, a fourth set of operations may include removing material 320 (e.g., etching, mining), thereby allowing voids to be formed between the remaining layers of material 315. A fourth set of operations may also expose the sidewalls or sidewall portions of pier 505 (e.g., sidewalls in the xz plane, sidewall portions in the yz plane between the layers of material 315, consisting of material 510). In the first alternative embodiment, a single wet etching operation may be performed to remove both material 410 (e.g., from trench 405) and the layer of material 320 from the stack of layers 310.

[0039] The pier 505 may remain in contact with the layers of material 315 and the substrate 305, thereby providing mechanical support to the rest of material 315 (e.g., reduced displacement of the rest of material 315 along the z-direction, reduced displacement of the rest of material 315 along the x-direction, reduced bending of the rest of material 315, and reduced unsupported height or cantilever of the rest of material 315). Thus, by mounting the pier 505 of material 510, the cavity 705 and void may be formed with improved stability or resistance, thereby allowing the formation of mechanisms within the cavity 705 and void (e.g., pillars, word lines, memory cells between the rest of material 315 along the z-direction) with lower variability or improved consistency.

[0040] A fourth set of operations may also include operations (e.g., one or more conductive deposition operations) that support the formation of access lines 805 (e.g., word lines) based on the deposition of material 810 (e.g., conductive material) within the void. In some embodiments, the fourth set of operations may include deposition of a first conductive material 810 on the exposed surface of the material arrangement 300, which may include deposition of the first conductive material 810 such that it contacts a layer of material 315, contacts the substrate 305, and contacts the exposed sidewall or portion of the exposed sidewall of the pier 505.

[0041] Figure 9 shows an example of a material arrangement 300 after a fifth set of one or more manufacturing operations supporting a lateral split digit line memory architecture according to embodiments disclosed herein (e.g., as material arrangement 300-g). The fifth set of manufacturing operations is performed on material arrangement 300-f to form material arrangement 300-g. The fifth set of operations may include further operations (e.g., metal recess etching) to support the formation of voids 905 between layers of material 315. For example, the fifth set of operations may include removing (e.g., etching) exposed portions of one or more pieces of material 810, thereby forming recesses in the material 810 and thus forming voids 905. The top and bottom surfaces of the voids 905 may be defined by different layers of material 315, respectively, and the sidewalls of the voids 905 may be defined by material 810 (e.g., forming access lines 805).

[0042] Figure 10 shows an example of material placement 300 after a sixth set of one or more manufacturing operations supporting a lateral split digit line memory architecture according to embodiments disclosed herein (e.g., as material placement 300-h). The sixth set of operations may include operations that support the formation of electrodes coupled to the access lines 805. For example, the sixth set of operations may include depositing conductive material 1005 within a set of voids 905 so as to be in contact with conductive material 810 (e.g., forming the access lines 805). In some cases, the sixth set of operations may further include subsequent recess operations that retract material 1005 to form a set present within the voids 905. For example, a lateral etching process may be performed to etch a portion of material 1005, forming another set of voids smaller than the voids 905 between layers of material 315 (e.g., based on depositing material 1005 within the voids 905). In some embodiments, a sixth set of operations may also include depositing material 1010 (e.g., a dielectric material) so as to contact the exposed portion of material 1005, which may also include a subsequent recess operation that causes material 1010 to recede so as to reside within the void 905. In some embodiments, a sixth set of operations may further include a subsequent recess operation that causes material 1010 to recede so as to reside within the void 905 (e.g., material 1010 does not extend beyond the void 905 to contact the sidewall of material 315).

[0043] After depositing material 1010, the material arrangement 300-h may include a set of cavities 1015 that extend through the stack of layers 310 and expose the substrate 305. The sidewalls of each cavity 1015 may include alternating layers of material 1010 and material 315, and the sidewalls of piers 505.

[0044] Figure 11 shows an example of material placement 300 after a seventh set of one or more manufacturing operations supporting a lateral split digit line memory architecture according to embodiments disclosed herein (e.g., as material placement 300-i). The seventh set of operations may include operations supporting the formation of dielectric pillars 1115 within the cavity 1015. In some embodiments, the seventh set of operations may include conformally depositing material 1105 (e.g., doped polysilicon material, aluminum oxide material) within the cavity 1015 to form a sheath. After conformally depositing material 1105, layers of material 1105 of substantially the same thickness may be in contact with the sidewalls of the layer of material 315, the sidewalls of material 1010, the substrate 305, and the sidewalls of the piers 505. In various embodiments, material 1105 may be a dielectric material associated with different selectivity to other materials already present in material placement 300 (e.g., metals, carbides, titanium nitride, titanium silicon nitride, tungsten silicon nitride, etc.). In some cases, a second set of cavities smaller than cavity 1015 can be formed by conformally depositing material 1105.

[0045] A seventh set of operations may also include depositing material 1110 (e.g., a dielectric material) in a second set of smaller cavities and bringing it into contact with the exposed surfaces of material 1105 (e.g., as well as the exposed surfaces of the substrate 305 and the conductive contact 325). Thus, material 1110 may be surrounded by material 1105 and in contact with material 1105 (e.g., in the xy plane). In some embodiments, material 1110 may include a dielectric material such as aluminum oxide.

[0046] Therefore, the material arrangement 300-i may include a set of dielectric pillars 1115, at least partially formed from material 1105 and material 1110, which in various embodiments may be in contact with material 1010. Each dielectric pillar 1115 extends through a stack of layers 310 and may be in contact with one or more contactors 325, each contactor may be coupled to a single dielectric pillar 1115 and associated with a single digit line. The sidewalls of the dielectric pillars 1115 may be in contact with alternating layers of material 315, alternating layers of material 1010, and the sidewalls of piers 505.

[0047] Figure 12 shows an example of material placement 300 after an eighth set of one or more manufacturing operations supporting a lateral split digit line memory architecture according to embodiments disclosed herein (e.g., as material placement 300-j). The eighth set of operations may include operations (e.g., etching operations) that support the formation of a cavity 1205 based on removing material 510 (e.g., pier 505) and portions of material 1105 (e.g., along the z-direction, up to the substrate 305, up to the conductive contact 325, or up to the intervening material between the layer stack 310 and the conductive contact 325). For example, the eighth set of operations may include removing a first portion of material 1105 and a second portion of material 1105 from each dielectric pillar 1115. After the eighth set of operations, each dielectric pillar 1115 may contain two remaining portions 1210 of dielectric material 1105. Each remaining portion 1210 of the dielectric material 1105 can bond the dielectric pillar 1115 to one of the sidewalls of the stack of layers 310. In some cases, the remaining portions 1210 of the dielectric material 1105 can enhance the stability of the dielectric pillar 1115 in the material arrangement 300-j (e.g., compared to a similar material arrangement 300-j in which the dielectric pillar 1115 is not bonded to the sidewall of the stack of layers 310 via the remaining portions 1210 of the dielectric material 1105). Such etching can create cavities, and conductive pillars (e.g., digit lines) can be formed within these cavities.

[0048] In some embodiments, by forming each cavity 1205, the first sidewalls of each stack of layers 310 may be exposed on the first side of the cavity 1205 (e.g., along the x-direction), and the second sidewalls of each stack of layers 310 may be exposed on the second side of the cavity 1205 (e.g., along the x-direction). Furthermore, by forming each cavity 1205, the sidewalls of the materials 1005, 1010, 1105, and 1110 within each cavity 1205 may be exposed, thereby allowing each cavity of the cavity 1205 to contain a first quantity of materials 1005, 1010, 1105, and 1110, as well as a second quantity of materials 1005, 1010, 1105, and 1110.

[0049] Figure 13 shows an example of a material placement 300 after a ninth set of one or more manufacturing operations supporting a lateral split digit line memory architecture according to embodiments disclosed herein (e.g., as material placement 300-k). The ninth set of operations may include operations supporting the formation of conductive pillars 1320 (e.g., configured as digit lines) based on the deposition of conductive materials 1310 (e.g., electrode material, lower electrode) and 1315 within the cavity 1205. For example, the ninth set of operations may include conformally depositing material 1310 to line the exposed surface of the cavity 1205. The ninth set of operations may then include depositing material 1315 (e.g., another conductive material 1315) within the remainder of the cavity 1205. After these deposition operations, material placement 300-k may not include the cavity 1305. For example, the sidewalls of cavity 1305 may be conformally lined with material 1310, and the rest of cavity 1305 may be filled with material 1315. Conductive materials 1310 and 1315 (e.g., electrode material, lower electrode) may be examples of conductive pillars that function as digit lines.

[0050] To form material arrangement 300-k, a ninth set of operations may include operations (e.g., excavation operations, nitride excavation) that support the formation of cavity 1305. For example, a ninth set of operations may include performing a dry etching process to remove a portion of material 1315 from material arrangement 300-k. After the dry etching process, material arrangement 300-k may include a portion of material 1315 within the conductive pillar 1320. A ninth set of operations may further include a selective wet etching process to selectively remove a portion of material 1310 from the sidewall of material arrangement 300 to form cavity 1305. In some cases, the selective wet etching process may not be able to remove the portion of material 1310 surrounding material 1315, so a portion of material 1310 within the conductive pillar 1320 may remain in material arrangement 300-k. Therefore, after the selective wet etching process, the material arrangement 300-k may include a set of conductive pillars 1320, each conductive pillar 1320 in contact with the sidewall of the remaining portion 1210 of the material 1105 and the sidewall of the dielectric pillar 1115.

[0051] In some cases, the remaining portion 1210 of material 1105 (e.g., pillar sheath) enables the formation of the “split” digit lines described herein, while simultaneously avoiding challenges that may arise with other processes that do not include pillar sheaths. Thus, the digit lines formed by the conductive pillars 1320 may have the same or higher density than digit lines and pillars that do not use the lateral split digit line process (e.g., an architecture with two digit lines for each pillar).

[0052] Figure 14 shows an example of material placement 300 after a 10th set of one or more manufacturing operations supporting a lateral split digit line memory architecture according to embodiments disclosed herein (e.g., as material placement 300-l). The 10th set of operations may include operations (e.g., etching operations) that support the formation of voids 1405 based on removing portions of material 1010 (e.g., between layers of material 315, along the z-direction, up to adjacent layers of material 315). In some embodiments, by forming each void 1405, the first sidewall of each of the stacks of layers 310 may be exposed on the first side of the void 1405 (e.g., along the x-direction), and the second sidewall of each of the stacks of layers 310 may be exposed on the second side of the void 1405 (e.g., along the x-direction). In some embodiments, exposing the sidewalls of the layer stack 310 may include exposing a single layer of material 810 (for example, layers of material 315 may remain above and below the void 1405 so that the void 1405 does not expose the substrate 305). Furthermore, by forming each void 1405, the sidewalls of material 1310, the remainder of material 1010, and material 1005 may be exposed within each void 1405. Cavities formed adjacent to materials 1310 and 1315 may be configured to receive memory material 1510, as described with reference to Figure 15.

[0053] Figure 15 shows an example of material placement 300 following an eleventh set of one or more manufacturing operations supporting a lateral division digit line memory architecture according to embodiments disclosed herein (e.g., as material placement 300-m). The eleventh set of operations may include operations that support the formation of memory cells electrically coupled to the access line 805 (e.g., coupled with material 810 along the x-direction) based on depositing memory material 1510 into portions of void 1405. For example, the eleventh set of operations may include depositing material 1510 (e.g., memory material, storage material, chalcogenide) in voids defined by adjacent layers of material 1005, material 1010, and material 1310 (e.g., sidewalls of digit lines). The eleventh set of operations may also include subsequent recess operations that recede the material 1510 so that it is present within the void. In some embodiments, the 11th set of operations may also include depositing a sealing layer on the material 1510, or performing the deposition by applying a plasma treatment using ammonia (NH3), etc.

[0054] An eleventh set of operations may include depositing material 1505 (e.g., dielectric material) onto the remaining portion of the void 1405. For example, after forming a memory cell in a void defined by adjacent layers of material 315, material 1005, material 1010, and material 1310 (e.g., the sidewalls of the digit line), material 1505 is deposited in the void 1405 so that material 1505 can come into contact with the substrate 305.

[0055] Accordingly, the described techniques for a laterally divided digit line memory architecture can support various embodiments for forming a device including an embodiment of a memory array. For example, the memory array may include a material arrangement 300-m in which conductive pillars 1320 (including, for example, conductive materials 1310 and 1315) are configured as digit lines, layers of conductive material 810 are configured as access lines 805 (e.g., word line plates), materials 1310 and 1005 are configured as electrodes, and each portion of material 1510 is configured as a memory cell. In this embodiment, each memory cell may be in contact with adjacent layers of material 315 (e.g., dielectric material), material 1505 (e.g., another dielectric material), portions of material 1005 (e.g., conductive material forming electrodes), and material 1310 (e.g., another conductive material forming another electrode). Thus, each memory element may be electrically coupled to the word line plate (e.g., via electrodes including material 1005) and to the digit lines (e.g., via electrodes including material 1105).

[0056] In embodiments of a memory array including a material arrangement 300-m, the memory array may include a set of dielectric pillars 1115 (e.g., dielectric pillars 1115 formed from material 1110 and the remaining portion 1210 of material 1105) which extend through a stack of layers 310 and contact the substrate 305. In some cases, there may be four conductive pillars 1320 (e.g., conductive pillars 1320 each configured as a single digit line) isolated from each other by a single dielectric pillar 1115. Each of the conductive pillars 1320 may correspond to a single digit line and extend through a stack of layers 310 to contact a contactor 325. The dielectric material 1505 also extends between the dielectric pillar 1115 and the associated conductive pillar 1320, electrically insulating each conductive pillar 1320 in contact with the first dielectric pillar 1115 from the conductive pillar 1320 in contact with the second dielectric pillar 1115. Furthermore, in each layer of the stack of layers 310, each dielectric pillar 1115 may be in contact with four memory cells (e.g., including material 1510). In some embodiments, each of the four memory cells (e.g., four memory cells associated with one of the dielectric pillars 1115) may be coupled to a word line plate associated with a first word line driver. In some other embodiments, there may be two conductive pillars 1320 isolated from each other by a single dielectric pillar 1115. In the case of two conductive pillars 1320, each of the two conductive pillars 1320 may be coupled (for example, with any associated memory cell) to an even word line plate and an odd word line plate, the even word line plate and the odd word line plate being separated from each other and associated with a word line driver.

[0057] Figure 16 illustrates a flowchart showing Method 1600 supporting a lateral partitioned digit line memory architecture according to embodiments disclosed herein. The operation of Method 1600 may be carried out by a manufacturing system or its components as described herein. For example, the operation of Method 1600 may be carried out by a manufacturing system as described with reference to Figures 1 to 15. In some embodiments, the manufacturing system may execute a set of instructions that control the functional elements of the device in order to perform the described functions. Additionally or alternatively, the manufacturing system may use dedicated hardware to perform aspects of the described functions.

[0058] In 1605, the method may include forming a trench through a stack of layers on a substrate to expose the substrate, the stack of layers including a layer of a first dielectric material and a layer of a nitride material. The operation of 1605 may be carried out according to the embodiments disclosed herein.

[0059] Procedure 1610 may include forming a plurality of dielectric piers along the trench, each containing a second dielectric material, at least partially based on depositing each second dielectric material portion within the trench. The operation of 1610 may be carried out according to the embodiments disclosed herein.

[0060] In 1615, the method may include forming multiple access lines, at least partially based on removing nitride material from a stack of layers and depositing a first conductive material in multiple voids between layers of a first dielectric material. The operation of 1615 may be carried out according to the embodiments disclosed herein.

[0061] In 1620, the method may include forming a plurality of dielectric pillars along a trench, each containing a third dielectric material surrounding a fourth dielectric material, at least in part on the basis of depositing a third dielectric material and a fourth dielectric material in a plurality of first cavities positioned between each of a plurality of dielectric piers. The operation of 1620 may be carried out according to the embodiments disclosed herein.

[0062] In 1625, the method may include removing a plurality of dielectric piers, a first portion of the third dielectric material, and a second portion of the third dielectric material opposite the first portion to form a third portion of the third dielectric material and a fourth portion of the third dielectric material located opposite the third portion, the third portion of the third dielectric material, the fourth portion of the third dielectric material, and the fourth dielectric material forming a plurality of second cavities that expose the substrate. The operation of 1625 may be carried out according to the embodiments disclosed herein.

[0063] In 1630, the method may include forming a plurality of conductive pillars along a trench by depositing a second conductive material in a plurality of second cavities, each of which conductive pillars is in contact with the sidewalls of a third dielectric material and a fourth dielectric material. The operation of 1630 may be carried out according to the embodiments disclosed herein.

[0064] In 1635, the method may include forming a plurality of memory cells, at least in part, by forming a plurality of conductive pillars and then depositing a memory material, each of the plurality of memory cells being electrically coupled to one of the plurality of conductive pillars and to one of the plurality of access lines. The operation of 1635 may be carried out according to the embodiments disclosed herein.

[0065] In some embodiments, the apparatus described herein may perform methods such as method 1600. The apparatus may include mechanisms, circuits, logic, means, or instructions (e.g., a non-temporary computer-readable medium storing instructions executable by a processor), or any combination thereof, for performing the following embodiments of the disclosure.

[0066] Embodiment 1: Forming a trench through a stack of layers on the substrate so as to expose the substrate, wherein the stack of layers comprises a layer of a first dielectric material and a layer of a nitride material; forming a plurality of dielectric piers along the trench, each containing a second dielectric material, at least partially based on forming the trench and depositing each second dielectric material portion within the trench; forming a plurality of access lines, at least partially based on removing the nitride material from the stack of layers and depositing a first conductive material in a plurality of voids between the layers of the first dielectric material; forming a plurality of dielectric pillars along the trench, each containing the third dielectric material surrounding the fourth dielectric material, at least partially based on depositing a third dielectric material and a fourth dielectric material in a plurality of first cavities positioned between each of the plurality of dielectric piers; and removing the plurality of dielectric piers, a first portion of the third dielectric material, and a second portion of the third dielectric material on the opposite side of the first portion to the third dielectric material A method, apparatus, or non-temporary computer-readable medium comprising an operation, mechanism, circuit, logic, means, or instruction, or any combination thereof, for performing the forming of a third portion of a material and a fourth portion of the third dielectric material disposed opposite to the third portion, wherein the third portion of the third dielectric material, the fourth portion of the third dielectric material, and the fourth dielectric material form a plurality of second cavities exposing the substrate; forming a plurality of conductive pillars along the trench by depositing a second conductive material within the plurality of second cavities, wherein each of the plurality of conductive pillars is in contact with the sidewalls of the third dielectric material and the fourth dielectric material; and forming a plurality of memory cells, at least in part, based on the forming of the plurality of conductive pillars and depositing a memory material after the plurality of conductive pillars have been formed.

[0067] Embodiment 2: The method, apparatus, or non-transient computer-readable medium according to Embodiment 1, wherein, after forming the plurality of second cavities, the fourth dielectric material and the sidewall of the trench are mechanically coupled by the third portion of the third dielectric material and the fourth portion of the third dielectric material.

[0068] Embodiment 3: The method, apparatus, or non-temporary computer-readable medium of any embodiment 1 to 2, further comprising operations, mechanisms, circuits, logic, means, or instructions, or any combination thereof, for forming the plurality of dielectric pillars, conformally depositing the third dielectric material on the side walls of the plurality of first cavities to form a plurality of third cavities smaller than each of the plurality of first cavities, and for depositing the fourth dielectric material within the plurality of third cavities.

[0069] Embodiment 4: The method, apparatus, or non-temporary computer-readable medium of any embodiment 1 to 3, further comprising operations, mechanisms, circuits, logic, means, or instructions, or any combination thereof, for forming the plurality of conductive pillars, which further include a first conductive pillar and a second conductive pillar electrically coupled to a first digit line driver, and a third conductive pillar and a fourth conductive pillar electrically coupled to a second digit line driver.

[0070] Embodiment 5: Forming the plurality of conductive pillars further comprises conformally depositing a third conductive material in the plurality of second cavities; depositing the second conductive material in the plurality of second cavities after conformally depositing the third conductive material; performing a dry etching process to remove portions of the second conductive material; and performing a selective wet etching process to selectively remove portions of the third conductive material from the sidewalls of the plurality of second cavities, wherein each conductive material includes a remainder of the third conductive material that at least partially surrounds the remainder of the second conductive material, and includes operations, mechanisms, circuits, logic, means, or instructions, or any combination thereof, for performing the actions and actions described herein. The method, apparatus, or non-temporary computer-readable medium is described herein.

[0071] Embodiment 6: The method, apparatus, or non-temporary computer-readable medium of any embodiment 1 to 5, further comprising actions, mechanisms, circuits, logic, means, or instructions, or any combination thereof, for performing a first excavation process to remove the plurality of dielectric piers, and, after performing the first excavation process, a second excavation process to remove the first portion of the third dielectric material and the second portion of the third dielectric material.

[0072] Embodiment 7: Forming the plurality of voids between the layers of the first dielectric material, at least partially based on removing the layers of the nitride material from the trench after forming the plurality of dielectric piers, to form the plurality of voids between the layers of the first dielectric material, to deposit the first conductive material in the plurality of voids between the layers of the first dielectric material to form alternating layers of the first dielectric material and the first conductive material, and forming the plurality of second voids between the layers of the first dielectric material, at least partially based on removing portions of the first conductive material from each layer of the first conductive material, wherein each of the plurality of second voids is defined by different layers of the first dielectric material and the sidewalls of the first conductive material, and the plurality of access lines include the first conductive material and are formed at least partially based on forming the plurality of second voids, further comprising operations, mechanisms, circuits, logic, means, or instructions, or any combination thereof, for performing the forming and the apparatus, apparatus, or non-temporary computer-readable medium, according to any embodiment 1 to 6.

[0073] Embodiment 8: The method, apparatus, or non-transient computer-readable medium of Embodiment 7, further comprising operations, mechanisms, circuits, logic, means, or instructions, or any combination thereof, for performing the deposition, which involves depositing a fourth conductive material in each of the plurality of second voids, wherein the fourth conductive material is in contact with the plurality of access lines, and performing a lateral etching process to etch portions of the fourth conductive material so as to form a plurality of third voids between the layers of the first dielectric material, and depositing a fifth dielectric material in each of the plurality of third voids, wherein the fifth dielectric material is electrically coupled to the plurality of access lines via the fourth conductive material, and the formation of the plurality of conductive pillars is performed after the deposition of the fifth dielectric material.

[0074] Embodiment 9: The method, apparatus, or non-temporary computer-readable medium of Embodiment 8, further comprising: performing a second lateral etching process to etch portions of the fifth dielectric material so as to form a plurality of fourth voids between the layers of the first dielectric material, each of the plurality of fourth voids being defined by different layers of the first dielectric material, the sidewalls of the fifth dielectric material, and the sidewalls of one of the plurality of conductive pillars, and further comprising an operation, mechanism, circuit, logic, means, or instruction for performing the operation, or any combination thereof.

[0075] Embodiment 10: The method, apparatus, or non-temporary computer-readable medium according to Embodiment 9, further comprising operations, mechanisms, circuits, logic, means, or instructions, or any combination thereof, for depositing the memory material within the plurality of fourth voids in order to form the plurality of memory cells.

[0076] Embodiment 11: The method, apparatus, or non-temporary computer-readable medium of any embodiment 7 to 10, further comprising actions, mechanisms, circuits, logic, means, or instructions, or any combination thereof, for performing a wet etching process to selectively remove the nitride material and the second nitride material, wherein the formation of the plurality of voids further includes actions, mechanisms, circuits, logic, means, or instructions for performing a wet etching process to selectively remove the nitride material and the second nitride material.

[0077] Embodiment 12: A method, apparatus, or non-temporary computer-readable medium by any embodiment 1 to 11, further comprising an operation, mechanism, circuit, logic, means, or instruction for depositing a sixth dielectric material in a plurality of fourth cavities after the plurality of memory cells have been formed, wherein each of the plurality of fourth cavities extends between two of the plurality of dielectric pillars and is formed at least in part on the basis of depositing the second conductive material in the plurality of second cavities.

[0078] Embodiment 13: The method, apparatus, or non-temporary computer-readable medium according to any embodiment 1 to 12, wherein forming the trenches comprises dividing each layer of the nitride material into a first portion associated with a first word line driver and a second portion associated with a second word line driver, and forming the plurality of access lines further comprises forming a plurality of first access lines electrically coupled to the first word line driver, at least partially based on depositing the first conductive material in voids associated with the first portion of the nitride material, and forming a plurality of second access lines electrically coupled to the second word line driver, at least partially based on depositing the first conductive material in voids associated with the second portion of the nitride material.

[0079] Embodiment 14: The method, apparatus, or non-transient computer-readable medium according to any of Embodiments 1 to 13, wherein the side walls of the plurality of first cavities include alternating layers of the first dielectric material and the fifth dielectric material.

[0080] Embodiment 15: A method, apparatus, or non-temporary computer-readable medium by any embodiment 1 to 14, further comprising operations, mechanisms, circuits, logic, means, or instructions for forming the plurality of dielectric piers, or any combination thereof, comprising depositing the respective second dielectric material portions within the plurality of fifth cavities, thereby depositing the second dielectric material portions within the plurality of fifth cavities, wherein the plurality of dielectric piers comprises depositing the respective second dielectric material portions within the plurality of fifth cavities.

[0081] Embodiment 16: The method, apparatus, or non-transient computer-readable medium of Embodiment 15, wherein forming each of the plurality of fifth cavities involves exposing each first sidewall of the layer stack on the first side of each fifth cavity and each second sidewall of the layer stack on the second side of each fifth cavity, and forming the plurality of dielectric piers involves depositing each second dielectric material portion within each fifth cavity in contact with each first sidewall and each second sidewall.

[0082] Figure 17 illustrates a flowchart showing Method 1700 supporting a lateral partitioned digit line memory architecture according to embodiments disclosed herein. The operation of Method 1700 may be carried out by a manufacturing system or its components as described herein. For example, the operation of Method 1700 may be carried out by a manufacturing system as described with reference to Figures 1 to 15. In some embodiments, the manufacturing system may execute a set of instructions that control the functional elements of the device in order to perform the described functions. Additionally or alternatively, the manufacturing system may use dedicated hardware to perform aspects of the described functions.

[0083] In 1705, the method may include forming a plurality of dielectric piers, each comprising a second dielectric material, through a stack of layers comprising a first dielectric material layer and a nitride material layer on a substrate, which is at least partially based on depositing each second dielectric material portion in a plurality of first cavities, each extending through the stack of layers and exposing the substrate. The operation of 1705 may be carried out according to the embodiments disclosed herein.

[0084] In 1710, the method may include forming a plurality of access lines, at least in part, based on removing nitride material from a stack of layers and depositing a first conductive material in a plurality of voids between layers of a first dielectric material. The operation of 1710 may be carried out according to the embodiments disclosed herein.

[0085] In 1715, the method may include forming a plurality of dielectric pillars, each containing a third dielectric material surrounding a fourth dielectric material, based at least in part on depositing a third dielectric material and a fourth dielectric material in a plurality of second cavities positioned between each of a plurality of dielectric piers. The operation of 1715 may be carried out according to the embodiments disclosed herein.

[0086] In 1720, the method may include removing a plurality of dielectric piers, a first portion of the third dielectric material, and a second portion of the third dielectric material opposite the first portion to form a third portion of the third dielectric material and a fourth portion of the third dielectric material located opposite the third portion, the third portion of the third dielectric material, the fourth portion of the third dielectric material, and the fourth dielectric material forming a plurality of third cavities that expose the substrate. The operation of 1720 may be performed according to the embodiments disclosed herein.

[0087] In 1725, the method may include forming a plurality of conductive pillars by depositing a second conductive material in a plurality of third cavities, each of which conductive pillars is in contact with the sidewalls of the third dielectric material and the fourth dielectric material. The operation of 1725 may be carried out according to the embodiments disclosed herein.

[0088] In 1730, the method may include forming a plurality of memory cells, at least in part, by forming a plurality of conductive pillars and then depositing a memory material, each of the plurality of memory cells being electrically coupled to one of the plurality of conductive pillars and to one of the plurality of access lines. Operation of 1730 may be carried out according to the embodiments disclosed herein.

[0089] In some embodiments, the apparatus described herein may perform methods such as Method 1700. The apparatus may include mechanisms, circuits, logic, means, or instructions (e.g., non-temporary computer-readable media for storing instructions executable by a processor), or any combination thereof, for performing the following embodiments of the disclosure.

[0090] Embodiment 17: Forming a plurality of dielectric piers, each containing a second dielectric material, through a stack of layers on a substrate, each containing a first dielectric material and a nitride material, and at least partially based on depositing each second dielectric material portion in a plurality of first cavities, each extending through the stack of layers and exposing the substrate; forming a plurality of access lines, at least partially based on removing the nitride material from the stack of layers and depositing a first conductive material in a plurality of voids between the layers of the first dielectric material; forming a plurality of dielectric pillars, each containing the third dielectric material surrounding the fourth dielectric material, and at least partially based on depositing the third dielectric material and the fourth dielectric material in a plurality of second cavities located between each of the plurality of dielectric piers; and removing the plurality of dielectric piers, the first portion of the third dielectric material, and the second portion of the third dielectric material on the opposite side of the first portion, to obtain the third dielectric material A method, apparatus, or non-temporary computer-readable medium comprising an operation, mechanism, circuit, logic, means, or instruction, or any combination thereof, for performing the operation, mechanism, circuit, logic, means, or instruction of the operation, mechanism, circuit, logic, means, or instruction of the operation, mechanism, circuit, instruction

[0091] Embodiment 18: The method, apparatus, or non-transient computer-readable medium according to Embodiment 17, wherein, after forming the plurality of third cavities, the third portion of the third dielectric material and the fourth portion of the third dielectric material mechanically bond the fourth dielectric material to the sidewall of the layer stack.

[0092] Embodiment 19: The method, apparatus, or non-temporary computer-readable medium of any embodiment 17 to 18, further comprising operations, mechanisms, circuits, logic, means, or instructions, or any combination thereof, for forming the plurality of dielectric pillars, conformally depositing the third dielectric material on the side walls of the plurality of second cavities to form a plurality of fourth cavities smaller than each of the plurality of second cavities, and for depositing the fourth dielectric material within the plurality of fourth cavities.

[0093] Embodiment 20: The method, apparatus, or non-temporary computer-readable medium of any embodiment 17 to 19, further comprising operations, mechanisms, circuits, logic, means, or instructions, or any combination thereof, for forming the plurality of conductive pillars, which further include a first conductive pillar and a second conductive pillar electrically coupled to a first digit line driver, and a third conductive pillar and a fourth conductive pillar electrically coupled to a second digit line driver.

[0094] Embodiment 21: Forming the plurality of conductive pillars further comprises conformally depositing a third conductive material in the plurality of third cavities; depositing the second conductive material in the plurality of third cavities after conformally depositing the third conductive material; performing a dry etching process to remove portions of the second conductive material; and performing a selective wet etching process to selectively remove portions of the third conductive material from the sidewalls of the plurality of third cavities, wherein each conductive material comprises a remainder of the third conductive material at least partially surrounding the remainder of the second conductive material, and includes operations, mechanisms, circuits, logic, means, or instructions, or any combination thereof, of the method, apparatus, or non-temporary computer-readable medium of any of Embodiments 17 to 20.

[0095] Embodiment 22: The method, apparatus, or non-temporary computer-readable medium of any embodiment 17 to 21, further comprising actions, mechanisms, circuits, logic, means, or instructions, or any combination thereof, for performing a first excavation process to remove the plurality of dielectric piers, and, after performing the first excavation process, a second excavation process to remove the first portion of the third dielectric material and the second portion of the third dielectric material.

[0096] Embodiment 23: A method, apparatus, or non-temporary computer-readable medium according to any of Embodiments 17 to 22, further comprising an operation, mechanism, circuit, logic, means, or instruction, or any combination thereof, for forming the dielectric piers, wherein each of the plurality of second cavities is positioned between each of the plurality of dielectric piers, the operation, mechanism, circuit, logic, means, or instruction for forming the substrate, further comprising an operation, mechanism, circuit, logic, means, or instruction for forming the substrate, or any combination thereof.

[0097] Embodiment 24: The method, apparatus, or non-temporary computer-readable medium of Embodiment 23, further comprising operations, mechanisms, circuits, logic, means, or instructions, or any combination thereof, for performing the actions of forming and removing the layers of the nitride material to form the plurality of second cavities; depositing the first conductive material in the plurality of voids between the layers of the first dielectric material to form alternating layers of the first dielectric material and the first conductive material; and forming a plurality of second voids between the layers of the first dielectric material to form a plurality of second voids, each of which is defined by a different layer of the first dielectric material and a sidewall of the first conductive material, and the plurality of access lines comprising the first conductive material and formed at least in part based on forming the plurality of second voids.

[0098] Embodiment 25: The method, apparatus, or non-temporary computer-readable medium of Embodiment 24, further comprising operations, mechanisms, circuits, logic, means, or instructions, or any combination thereof, for performing the deposition, which involves depositing a fourth conductive material in each of the plurality of second voids, wherein the fourth conductive material is in contact with the plurality of access lines, and performing a lateral etching process to etch portions of the fourth conductive material so as to form a plurality of third voids between the layers of the first dielectric material, and depositing a fifth dielectric material in each of the plurality of third voids, wherein the fifth dielectric material is electrically coupled to the plurality of access lines via the fourth conductive material, and the formation of the plurality of conductive pillars is performed after the deposition of the fifth dielectric material.

[0099] Embodiment 26: The method, apparatus, or non-temporary computer-readable medium of Embodiment 25, further comprising: performing a second lateral etching process to etch portions of the fifth dielectric material so as to form a plurality of fourth voids between the layers of the first dielectric material, each of the plurality of fourth voids being defined by a different layer of the first dielectric material, a sidewall of the fifth dielectric material, and a sidewall of one of the plurality of conductive pillars; and further comprising an operation, mechanism, circuit, logic, means, or instruction for performing the operation, or any combination thereof.

[0100] Embodiment 27: The method, apparatus, or non-temporary computer-readable medium of Embodiment 26, further comprising operations, mechanisms, circuits, logic, means, or instructions, or any combination thereof, for depositing the memory material within the plurality of fourth voids in order to form the plurality of memory cells.

[0101] Embodiment 28: The method, apparatus, or non-temporary computer-readable medium of any embodiment 24 to 27, further comprising actions, mechanisms, circuits, logic, means, or instructions, or any combination thereof, for performing a wet etching process to selectively remove the nitride material, wherein the formation of the plurality of voids further includes actions, mechanisms, circuits, logic, means, or instructions for performing a wet etching process to selectively remove the nitride material.

[0102] Embodiment 29: A method, apparatus, or non-temporary computer-readable medium by any embodiment 17 to 28, further comprising an operation, mechanism, circuit, logic, means, or instruction for depositing a sixth dielectric material in a plurality of fifth cavities after the plurality of memory cells have been formed, wherein each of the plurality of fifth cavities extends between two of the plurality of dielectric pillars and is formed at least in part on the basis of depositing the second conductive material in the plurality of third cavities.

[0103] Embodiment 30: The method, apparatus, or non-temporary computer-readable medium of any embodiment 17 to 29, further comprising operations, mechanisms, circuits, logic, means, or instructions, or any combination thereof, for performing the following: forming the plurality of access lines further, at least in part, based on depositing the first conductive material in voids associated with a first portion of the nitride material, forming a plurality of first access lines electrically coupled to a first word line driver; and forming a plurality of second access lines electrically coupled to a second word line driver, at least in part, based on depositing the first conductive material in voids associated with a second portion of the nitride material.

[0104] Embodiment 31: The method, apparatus, or non-transient computer-readable medium according to any of Embodiments 17 to 30, wherein the side walls of the plurality of second cavities include alternating layers of the first dielectric material and the fifth dielectric material.

[0105] It should be noted that the methods described herein describe possible embodiments, and that the operations and steps may be rearranged or otherwise modified, and that other embodiments are also possible. Furthermore, two or more parts of the methods may be combined.

[0106] The apparatus is described. Below, an overview of the embodiments of the apparatus described herein is provided.

[0107] Embodiment 32: A plurality of contacts extending through a substrate, each associated with a plurality of digit lines, a plurality of first word line plates separated from a plurality of second word line plates by trenches, and a plurality of sets of pillars, each set of pillars comprising a first pillar and a second pillar electrically coupled to the first plurality of word line plates, and a third pillar and a fourth pillar electrically coupled to the second plurality of word line plates, each of the first pillar and the third pillar electrically coupled to one of the plurality of digit lines, and each of the second pillar and the fourth pillar The apparatus comprises a plurality of sets of pillars, each electrically coupled to another digit line among the plurality of digit lines; a dielectric material disposed between each set of the plurality of sets of pillars, wherein the dielectric material is in contact with the second and fourth pillars of the first set of pillars and the first and third pillars of the second set of pillars; and a plurality of memory elements comprising a memory material, each comprising a word line plate among the first plurality of word line plates and the second plurality of word line plates, and the plurality of memory elements electrically coupled to the pillars of the plurality of sets of pillars.

[0108] Embodiment 33: The apparatus according to Embodiment 32, further comprising a plurality of dielectric pillars positioned between each of the first, second, third, and fourth pillars of a plurality of sets of pillars.

[0109] Embodiment 34: The apparatus according to any one of Embodiments 32 to 33, wherein the plurality of memory elements further include a plurality of first memory elements that contact the first pillar of each set of the plurality of sets of pillars, a plurality of second memory elements that contact the second pillar of each set of the plurality of sets of pillars, a plurality of third memory elements that contact the third pillar of each set of the plurality of sets of pillars, and a plurality of fourth memory elements that contact the fourth pillar of each set of the plurality of sets of pillars.

[0110] The apparatus is described. Below, an overview of the embodiments of the apparatus described herein is provided.

[0111] Embodiment 35: Apparatus having a memory array, wherein the memory array is formed by forming a trench through a stack of layers on the substrate so as to expose the substrate, the stack of layers comprising a layer of a first dielectric material and a layer of a nitride material, forming a plurality of dielectric piers along the trench, each comprising a second dielectric material, at least partially based on forming the trench and depositing each second dielectric material portion within the trench, forming a plurality of access lines, at least partially based on removing the nitride material from the stack of layers and depositing a first conductive material in a plurality of voids between the layers of the first dielectric material, forming a plurality of dielectric pillars along the trench, each comprising the third dielectric material surrounding the fourth dielectric material, at least partially based on depositing a third dielectric material and a fourth dielectric material in a plurality of first cavities positioned between each of the plurality of dielectric piers, the plurality of dielectric piers, the first portion of the third dielectric material, and the The apparatus is formed by a process comprising: removing a second portion of the third dielectric material on the opposite side of a first portion to form a third portion of the third dielectric material and a fourth portion of the third dielectric material located on the opposite side of the third portion, wherein the third portion of the third dielectric material, the fourth portion of the third dielectric material, and the fourth dielectric material form a plurality of second cavities that expose the substrate; forming a plurality of conductive pillars along the trench by depositing a second conductive material in the plurality of second cavities, wherein each of the plurality of conductive pillars is in contact with the sidewalls of the third dielectric material and the fourth dielectric material; and forming a plurality of memory cells, at least partially based on depositing a memory material after forming the plurality of conductive pillars, wherein each of the plurality of memory cells is electrically coupled to one of the plurality of conductive pillars and to one of the plurality of access lines.

[0112] It should be noted that the methods described herein describe possible embodiments, and that the operations and steps may be rearranged or otherwise modified, and that other embodiments are also possible. Furthermore, two or more parts of the methods may be combined.

[0113] The information and signals described herein may be represented using any of a variety of different techniques and methods. For example, signaling data, instructions, commands, information, signals, bits, or symbols that may be referred to throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. In some drawings, signals may be shown as a single signal, but a signal may represent a bus of signals, and a bus may have a variety of bit widths.

[0114] The terms “electronic communication,” “conductive contact,” “connected,” and “coupled” may refer to relationships between components that support the flow of signals between them. Components are considered to be in an electronic communication state (or conductive contact state, or connected state, or coupled state) with respect to each other if there is any conductive path between them that can support the flow of signals between them at any time. Conductive paths between components that are in an electronic communication state (or conductive contact state, or connected state, or coupled state) with respect to each other can be open or closed at any time, based on the operation of the device containing the connected components. Conductive paths between connected components may be direct conductive paths between components, or they may be indirect conductive paths that may include intermediate components such as switches, transistors, or other components. In some embodiments, the flow of signals between connected components may be temporarily interrupted by using one or more intermediate components, such as switches or transistors.

[0115] The term "coupling" (for example, "electrically coupled") can refer to a transition from an open-circuit relationship between components, where it is not currently possible for them to communicate signals through conductive paths, to a closed-circuit relationship between components, where it is possible for them to communicate signals through conductive paths. When a component, such as a controller, couples other components together, that component causes a change that allows signals to flow between the other components through conductive paths that previously did not permit signal flow.

[0116] The term "isolated" refers to a relationship between components where signals cannot currently flow between them. Components are isolated from each other if an open circuit exists between them. For example, two components separated by a switch placed between them are isolated from each other when the switch is open. When a controller isolates two components, the controller makes a change that prevents signals from flowing between the components using conductive paths that previously allowed signals to flow.

[0117] As used herein, the terms “layer” or “level” refer to a layer or sheet of geometric structure (for example, on a substrate). Each layer or level may have three dimensions (e.g., height, width, and depth) and may cover at least a portion of the surface. For example, a layer or level may be a three-dimensional structure, such as a thin film, where two dimensions are greater than the third. Layers or levels may contain different elements, components, or materials. In some embodiments, a single layer or level may consist of two or more sublayers or sublevels.

[0118] As used herein, the term “electrode” may refer to a conductor, which in some embodiments may be used as an electrical contact to a memory cell or other component of a memory array. Electrodes may include traces, wires, conductive lines, or conductive layers that provide conductive paths between elements or components of a memory array.

[0119] Devices described herein, including memory arrays, may be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, and gallium nitride. In some embodiments, the substrate is a semiconductor wafer. In other embodiments, the substrate may be a silicon-on-insulator (SOI) substrate such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate may be controlled through doping with various chemical species, including but not limited to phosphorus, boron, or arsenide. Doping may be performed by ion implantation or by any other doping means during the initial formation or growth of the substrate.

[0120] The switching components or transistors discussed herein represent field-effect transistors (FETs) and may include three-terminal devices comprising a source, drain, and gate. The terminals may be connected to other electronic elements via a conductive material, such as a metal. The source and drain may be conductive and may include highly doped, e.g., degenerate, semiconductor regions. The source and drain may be separated by a less doped semiconductor region or channel. If the channel is n-type (i.e., the majority carriers are electrons), the FET may be called an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET may be called a p-type FET. The channel may be covered with an insulating gate oxide. The conductivity of the channel can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type or p-type FET may result in a conductive channel. When a voltage above the transistor's threshold voltage is applied to the transistor gate, the transistor may enter an "on" or "activated" state. When a voltage lower than the transistor's threshold voltage is applied to the transistor gate, the transistor can enter an "off" or "deactivated" state.

[0121] The descriptions provided herein in relation to the accompanying drawings describe exemplary configurations and do not represent all embodiments that may be practiced or that fall within the claims. The term “exemplary” as used herein means “serving as an example, case, or illustration,” and not “preferred” or “advantageous over other examples.” Embodiments for carrying out the invention include specific details to facilitate understanding of the techniques described. However, these techniques may be practiced without these specific details. In some cases, well-known structures and devices are shown in block diagram form to avoid ambiguity of the concepts of the embodiments described.

[0122] In the attached diagram, similar components or mechanisms may have the same reference label. Furthermore, various components of the same type may be distinguished by adding a second label after the reference label, followed by a dash, to differentiate similar components. If only the first reference label is used in the specification, the description may apply to any component of similar components having the same first reference label, regardless of the second reference label.

[0123] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If a function is implemented in software executed by a processor, the function may be stored or transmitted as one or more instructions or codes on a computer-readable medium. Other embodiments and representations are also within the scope of this disclosure and the accompanying claims. For example, due to the nature of the software, the functions described herein may be implemented using software executed by a processor, hardware, firmware, hardwiring, or any combination thereof. The mechanism for implementing the function may also be physically located in various locations, including being distributed so that parts of the function are implemented in different physical locations.

[0124] For example, various exemplary blocks and modules described in connection with the disclosure herein may be implemented or run in general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but alternatively, a processor may be any processor, controller, microcontroller, or state machine. A processor may also be implemented in a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors working in conjunction with a DSP core, or any other such configuration).

[0125] Where used herein, including in the claims, “or” in a list of items (e.g., a list of items ending with a phrase such as “at least one of the following” or “one or more of the following”) indicates an inclusive list, for example, the list “at least one of A, B, or C” means A, or B, or C, or AB, or AC, or BC, or ABC (i.e., A and B and C). Also, where used herein, the phrase “based on” should not be interpreted as a reference to a closed set of conditions. For example, an exemplary step described as “based on condition A” may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, where used herein, the phrase “based on” should be interpreted in the same way as the phrase “based at least partially on.”

[0126] Computer-readable media include both non-temporary computer storage media and communication media, and these include any media that facilitate the transfer of computer programs from one location to another. Non-temporary storage media can be any available media that can be accessed by a general-purpose or dedicated computer. Examples, but not limited to, of non-temporary computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disk (CD)ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-temporary media that can be used to transport or store desired program code means in the form of instructions or data structures, and that can be accessed by a general-purpose or dedicated computer, or a general-purpose or dedicated processor. Any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used herein, discs (Disk and Disc) include CDs, laser discs, optical discs, digital multipurpose discs (DVDs), floppy disks, and Blu-ray discs, where a disc typically reproduces data magnetically, while a disc reproduces data optically using a laser. Any combination of the above is also included in the scope of computer-readable media.

[0127] The descriptions herein are provided to enable those skilled in the art to create or use this disclosure. Various modifications to this disclosure will be obvious to those skilled in the art, and the general principles defined herein can be applied to other modifications without departing from the scope of this disclosure. Thus, this disclosure should be recognized as having the broadest scope consistent with the principles and new features disclosed herein, and not limited to the examples and designs described herein.

Claims

1. The process involves forming a trench through a stack of layers on the substrate so as to expose the substrate, wherein the stack of layers includes a layer of a first dielectric material and a layer of a nitride material. Forming a plurality of dielectric piers, each containing a second dielectric material, along the trench, at least partially based on depositing each second dielectric material portion within the trench, Forming a plurality of access lines, at least partially based on removing the nitride material from the stack of the layers and depositing the first conductive material in a plurality of voids between the layers of the first dielectric material, Forming a plurality of dielectric pillars along the trench, each containing the third dielectric material surrounding the fourth dielectric material, based at least partially on depositing the third dielectric material and the fourth dielectric material in a plurality of first cavities positioned between each of the plurality of dielectric piers, The process involves removing the plurality of dielectric piers, the first portion of the third dielectric material, and the second portion of the third dielectric material opposite to the first portion to form a third portion of the third dielectric material and a fourth portion of the third dielectric material located opposite to the third portion, wherein the third portion of the third dielectric material, the fourth portion of the third dielectric material, and the fourth dielectric material form a plurality of second cavities that expose the substrate. The process involves depositing a second conductive material in the plurality of second cavities to form a plurality of conductive pillars along the trench, wherein each of the plurality of conductive pillars is in contact with the side walls of the third dielectric material and the fourth dielectric material. Forming a plurality of memory cells, at least in part, by depositing a memory material after forming the plurality of conductive pillars, wherein each of the plurality of memory cells is electrically coupled to one of the plurality of conductive pillars and to one of the plurality of access lines, Methods that include...

2. The method according to claim 1, wherein, after forming the plurality of second cavities, the fourth dielectric material and the side wall of the trench are mechanically coupled by the third portion of the third dielectric material and the fourth portion of the third dielectric material.

3. Forming the aforementioned plurality of dielectric pillars further, The third dielectric material is conformally deposited on the side walls of the plurality of first cavities to form a plurality of third cavities, each smaller than the plurality of first cavities. The fourth dielectric material is deposited in the plurality of third cavities, The method according to claim 1, including the method described in claim 1.

4. Forming the aforementioned plurality of conductive pillars further, To form a plurality of conductive pillars, including a first conductive pillar and a second conductive pillar electrically coupled to a first digit line driver, and a third conductive pillar and a fourth conductive pillar electrically coupled to a second digit line driver, The method according to claim 1, including the method described in claim 1.

5. Forming the aforementioned plurality of conductive pillars further, Conformally depositing a third conductive material within the plurality of second cavities, After conformally depositing the third conductive material, the second conductive material is deposited in the plurality of second cavities, Performing a dry etching process to remove the portion of the second conductive material, Performing a selective wet etching process to selectively remove portions of the third conductive material from the sidewalls of the plurality of second cavities, wherein each conductive material includes a remainder of the third conductive material that at least partially surrounds the remainder of the second conductive material. The method according to claim 1, including the method described in claim 1.

6. Forming the aforementioned plurality of second cavities further, Performing a first excavation process to remove the plurality of dielectric piers, After performing the first excavation process, a second excavation process is performed to remove the first portion of the third dielectric material and the second portion of the third dielectric material. The method according to claim 1, including the method described in claim 1.

7. After forming the plurality of dielectric piers, the plurality of voids are formed between the layers of the first dielectric material, at least partially based on removing the layers of the nitride material from the trench and removing the second nitride material. The first conductive material is deposited in the plurality of voids between the layers of the first dielectric material to form alternating layers of the first dielectric material and the first conductive material. Forming a plurality of second voids between the layers of the first dielectric material, at least partially based on removing a portion of the first conductive material from each layer of the first conductive material, wherein each of the plurality of second voids is defined by a different layer of the first dielectric material and the sidewall of the first conductive material, and the plurality of access lines include the first conductive material and are formed at least partially based on forming the plurality of second voids, The method according to claim 1, further comprising:

8. The method involves depositing a fourth conductive material within each of the plurality of second voids, wherein the fourth conductive material is in contact with the plurality of access lines, and the deposition is carried out accordingly. Performing a lateral etching process to etch a portion of the fourth conductive material so as to form a plurality of third voids between the layers of the first dielectric material, The process involves depositing a fifth dielectric material within each of the plurality of third voids, wherein the fifth dielectric material is electrically coupled to the plurality of access lines via the fourth conductive material, and the formation of the plurality of conductive pillars is performed after the deposition of the fifth dielectric material. The method according to claim 7, further comprising:

9. After forming the plurality of conductive pillars, a second lateral etching process is performed to etch a portion of the fifth dielectric material so as to form a plurality of fourth voids between the layers of the first dielectric material, wherein each of the plurality of fourth voids is defined by a different layer of the first dielectric material, a sidewall of the fifth dielectric material, and a sidewall of one of the plurality of conductive pillars. The method according to claim 8, further comprising:

10. Forming the aforementioned plurality of memory cells further involves Depositing the memory material within the plurality of fourth voids, The method according to claim 9, including the method described in claim 9.

11. Forming the aforementioned multiple voids further, Perform a wet etching process to selectively remove the nitride material and the second nitride material. The method according to claim 7, including the method described in claim 7.

12. After forming the plurality of memory cells, deposit a sixth dielectric material in a plurality of fourth cavities, wherein each of the plurality of fourth cavities extends between two of the plurality of dielectric pillars and is formed at least partially based on depositing the second conductive material in the plurality of second cavities. The method according to claim 1, further comprising:

13. Forming the trench divides each layer of the nitride material into a first portion associated with a first word line driver and a second portion associated with a second word line driver. Forming the aforementioned multiple access lines further means Forming a plurality of first access lines electrically coupled to the first word line driver, at least partially based on depositing the first conductive material in voids associated with the first portion of the nitride material, Forming a plurality of second access lines electrically coupled to the second word line driver, at least partially based on depositing the first conductive material in voids associated with the second portion of the nitride material, The method according to claim 1, including the method described in claim 1.

14. The method according to claim 1, wherein the side walls of the plurality of first cavities include alternating layers of the first dielectric material and the fifth dielectric material.

15. Depositing a second nitride material in the trench, The formation of a plurality of fifth cavities extending through the second nitride material, the portion of the first dielectric material, and the portion of the nitride material, respectively, so as to expose the substrate, wherein the formation of the plurality of dielectric piers includes depositing the respective second dielectric material portions within the plurality of fifth cavities, The method according to claim 1, further comprising:

16. Forming each of the plurality of fifth cavities involves exposing the first side wall of the layer stack on the first side of each fifth cavity, and the second side wall of the layer stack on the second side of each fifth cavity. Forming the plurality of dielectric piers involves depositing each of the second dielectric material portions in each fifth cavity so as to be in contact with each of the first and second side walls. The method according to claim 15.

17. Multiple contacts extending through the substrate, each associated with multiple digit lines, A first set of ward line plates separated from a second set of ward line plates by a trench, A plurality of sets of pillars, each set of pillars comprising a first pillar and a second pillar electrically coupled to the first plurality of wordline plates, and a third pillar and a fourth pillar electrically coupled to the second plurality of wordline plates, wherein each of the first pillar and the third pillar is electrically coupled to one of the plurality of digit lines, and each of the second pillar and the fourth pillar is electrically coupled to another of the plurality of digit lines, A dielectric material disposed between each set of the plurality of sets of pillars, wherein the dielectric material is in contact with the second and fourth pillars of the first set of pillars and with the first and third pillars of the second set of pillars, A plurality of memory elements comprising a memory material, wherein the plurality of memory elements are electrically coupled to a word line plate among the first plurality of word line plates and the second plurality of word line plates, and to a pillar among the plurality of sets of pillars, A device equipped with the following features.

18. The apparatus according to claim 17, further comprising a plurality of dielectric pillars positioned between the first pillar, second pillar, third pillar, and fourth pillar of each of the plurality of sets of pillars.

19. The aforementioned plurality of memory elements further include, A plurality of first memory elements that contact the first pillar of each of the plurality of sets of pillars, A plurality of second memory elements that contact the second pillar of each set of the plurality of sets of the pillars, A plurality of third memory elements that contact the third pillar of each of the plurality of sets of the pillars, A plurality of fourth memory elements that contact the fourth pillar of each of the plurality of sets of the pillars, The apparatus according to claim 17, comprising:

20. A device having a memory array, wherein the memory array is The process involves forming a trench through a stack of layers on the substrate so as to expose the substrate, wherein the stack of layers includes a layer of a first dielectric material and a layer of a nitride material. Forming a plurality of dielectric piers, each containing a second dielectric material, along the trench, at least partially based on depositing each second dielectric material portion within the trench, Forming a plurality of access lines, at least partially based on removing the nitride material from the stack of the layers and depositing the first conductive material in a plurality of voids between the layers of the first dielectric material, Forming a plurality of dielectric pillars along the trench, each containing the third dielectric material surrounding the fourth dielectric material, based at least partially on depositing the third dielectric material and the fourth dielectric material in a plurality of first cavities positioned between each of the plurality of dielectric piers, The process involves removing the plurality of dielectric piers, the first portion of the third dielectric material, and the second portion of the third dielectric material opposite to the first portion to form a third portion of the third dielectric material and a fourth portion of the third dielectric material located opposite to the third portion, wherein the third portion of the third dielectric material, the fourth portion of the third dielectric material, and the fourth dielectric material form a plurality of second cavities that expose the substrate. The process involves depositing a second conductive material in the plurality of second cavities to form a plurality of conductive pillars along the trench, wherein each of the plurality of conductive pillars is in contact with the side walls of the third dielectric material and the fourth dielectric material. Forming a plurality of memory cells, at least in part, by depositing a memory material after forming the plurality of conductive pillars, wherein each of the plurality of memory cells is electrically coupled to one of the plurality of conductive pillars and to one of the plurality of access lines, The apparatus, formed by a process including the following.

Images