Semiconductor package assembly

Abstract

A semiconductor package assembly is provided, comprising a semiconductor structure (e.g., an IC chip) and a package substrate electrically connected to the semiconductor structure. The assembly also includes a ceramic capacitor comprising alternating dielectric layers and internal electrode layers, the internal electrode layers comprising a first internal electrode layer and a second internal electrode layer. The capacitor further includes external terminals disposed on a first surface of the capacitor and electrically connected to the semiconductor structure, and external terminals disposed on a second surface of the capacitor and electrically connected to the package substrate.

Description

[Technical Field]

[0001] Related applications This application is based on U.S. Provisional Patent Application No. 63 / 420,761, filed on 31 October 2022, which claims priority, and the literature is incorporated herein by reference. [Background technology]

[0002] The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has resulted from repeated reductions in minimum feature size, which allows more components to be integrated into a given area. As the demand for miniaturization of electronic devices increases, the need for smaller and more ingenious packaging techniques for semiconductor chips has emerged. Interposers formed from organic, inorganic (e.g., glass), or silicon materials are often used to help implement high-density mounting of semiconductor chips. Such assemblies are often referred to as chip-on-interposers or chip-on-wafer (CoW) structures when the interposer is formed from a semiconductor material (e.g., silicon). The CoW structure can then be mounted on a build-up packaging substrate to form a CoWoS structure, and the resulting package assembly can finally be connected to a printed circuit board. As part of the power delivery system to the chip, one or more ceramic capacitors are also typically used so that any sudden demands for current can be supplied to the chip while the voltage is kept constant or nearly constant. Unfortunately, however, the increasing switching speed in the chip has resulted in an increase in parasitic inductance. Therefore, there is now a need for improved semiconductor package assemblies that utilize ceramic capacitors. [Overview of the project] [Means for solving the problem]

[0003] According to one embodiment of the present invention, a semiconductor package assembly is disclosed that includes a semiconductor structure and a package substrate electrically connected to the semiconductor structure. The assembly also includes a ceramic capacitor having a first surface and a second surface on the opposite side, the ceramic capacitor including alternating dielectric layers and internal electrode layers. The internal electrode layers include a first internal electrode layer and a second internal electrode layer. The capacitor further includes a first external terminal, a second external terminal, a third external terminal, and a fourth external terminal, the first external terminal being electrically connected to the first internal electrode layer and disposed on the first surface of the capacitor, the second external terminal being electrically connected to the first internal electrode layer and disposed on the second surface of the capacitor, the third external terminal being electrically connected to the second internal electrode layer and disposed on the first surface of the capacitor, and the fourth external terminal being electrically connected to the second internal electrode layer and disposed on the second surface of the capacitor. The first and third external terminals are electrically connected to the semiconductor structure (for example, optionally via an interposer), and the second and fourth external terminals of the ceramic capacitor are electrically connected to the package substrate.

[0004] Other features and embodiments of the present invention are described in more detail below.

[0005] A complete and implementable disclosure of the present invention (including its best mode for those skilled in the art) is described more specifically in the remainder of the specification (including by reference to the accompanying drawings). [Brief explanation of the drawing]

[0006] [Figure 1] This is a cross-sectional view of one embodiment of the semiconductor package assembly of the present invention, mounted on a circuit board. [Figure 2] This is a cross-sectional view of another embodiment of the semiconductor package assembly of the present invention. [Figure 3A] This is a perspective view of one embodiment of a ceramic capacitor that may be used in the present invention. [Figure 3B] Figure 3A is a side view of the internal electrode layer of the capacitor. [Figure 4A] This is a perspective view of another embodiment of a ceramic capacitor that may be used in the present invention. [Figure 4B] Figure 4A is an end view of the capacitor. [Figure 4C] Figure 4A is a side view of the capacitor. [Figure 5A] This is a perspective view of another embodiment of a ceramic capacitor that may be used in the present invention. [Figure 5B] Figure 5A is a side view of the internal electrode layer of the capacitor. [Figure 6A] This is a perspective view of another embodiment of a ceramic capacitor that may be used in the present invention. [Figure 6B] Figure 6A is a side view of the internal electrode layer of the capacitor. [Figure 6C] Figure 6A is a perspective view of the internal electrode layer of the capacitor. [Figure 6D] Figure 6A is a cross-sectional perspective view of the capacitor. [Figure 7A] This is a perspective view of another embodiment of a ceramic capacitor that may be used in the present invention. [Figure 7B] Figure 7A is a side view of the internal electrode layer of the capacitor. [Figure 7C] Figure 7A is a perspective view of the internal electrode layer of the capacitor. [Figure 7D] Figure 7A is a cross-sectional perspective view of the capacitor. [Figure 8A] This is a perspective view of another embodiment of a ceramic capacitor that may be used in the present invention. [Figure 8B] Figure 8A is a cross-sectional perspective view of the capacitor. [Figure 9A]A perspective view of yet another embodiment of a ceramic capacitor that can be used in the present invention. [Figure 9B] A side perspective view of one configuration of the internal electrode layer of the capacitor of FIG. 9A. [Figure 9C] A side perspective view of another configuration of the internal electrode layer of the capacitor of FIG. 9A.

Best Mode for Carrying Out the Invention

[0007] Repeated reference to characters in this specification and the figures is intended to represent the same or similar features or elements of the present invention.

[0008] Those skilled in the art should understand that this discussion is merely an illustration of exemplary embodiments and is not intended to limit the broader aspects of the present invention.

[0009] Generally speaking, the present invention is directed toward a semiconductor package assembly, which comprises a semiconductor structure, a package substrate electrically connected to the semiconductor structure, and optionally an interposer, which is positioned between the semiconductor structure and the package substrate and electrically connected to the semiconductor structure and the package substrate. The assembly further comprises a ceramic capacitor having a first surface and a second surface on the opposite side. The ceramic capacitor comprises alternating dielectric layers and internal electrode layers, the internal electrode layers comprising a first internal electrode layer and a second internal electrode layer. A first external terminal is electrically connected to the first internal electrode layer and disposed on the first surface of the capacitor, and a second external terminal is electrically connected to the first internal electrode layer and disposed on the second surface of the capacitor. Similarly, a third external terminal is electrically connected to the second internal electrode layer and disposed on the first surface of the capacitor, and a fourth external terminal is electrically connected to the second internal electrode layer and disposed on the second surface of the capacitor. Typically, the first and second external terminals have the same polarity (e.g., positive), and the third and fourth external terminals have the same polarity (e.g., negative). Nevertheless, the first and third external terminals of the ceramic capacitor are electrically connected to the semiconductor structure, and the second and fourth external terminals of the ceramic capacitor are electrically connected to the package substrate.

[0010] Herein, various embodiments of the present invention will be described in more detail below.

[0011] I. Semiconductor Structures One or more semiconductor structures (e.g., dies, wafers, integrated circuit devices, etc.) can generally be used in semiconductor package assemblies. Generally speaking, a semiconductor structure can include an insulating material (e.g., a dielectric material formed in multiple layers, as is known in the art) and multiple conductive paths formed through the insulating material. The insulating material can include dielectric materials such as silicon dioxide, silicon nitride, oxynitrides, polyimide materials, glass-reinforced epoxy matrix materials, or low-k or ultra-low-k dielectrics (e.g., carbon-doped dielectrics, fluorine-doped dielectrics, porous dielectrics, organic polymer dielectrics, photo-imageable dielectrics, and / or benzocyclobutene-based polymers). The insulating material can also include a semiconductor material such as silicon, germanium, or a III-V material (e.g., gallium nitride) and one or more additional materials. For example, the insulating material can include silicon dioxide or silicon nitride. The conductive paths of the die may include conductive traces and / or conductive vias, and any of the conductive contacts in the die may be connected in any suitable manner. The semiconductor structure may include mixed-pitch dies (meaning the die has sets of conductive contacts with different pitches), for example, the die may have "coarser" conductive contacts for connecting to an interposer in a semiconductor package assembly. The structure may also include single-sided dies (having conductive contacts on only one surface) and / or double-sided dies (conductive contacts on a first surface and on a second surface on the opposite side). The conductive paths in the die may be bordered by liner material (e.g., adhesive liners and / or barrier liners, etc.) as appropriate. The semiconductor structure may also include a wafer.In some embodiments, the semiconductor structure includes monolithic silicon, fan-out or fan-in package dies, or die stacks (e.g., wafer stacks, die stacks, or multilayer die stacks).

[0012] Furthermore, the semiconductor structure may have an integrated circuit ("IC") structure, which may take the form of a discrete IC device or "chip." Such an IC device may include one or more device layers disposed on a die substrate. The die substrate may be a semiconductor substrate composed of a semiconductor material system including, for example, an n-type or p-type material system (or a combination thereof). The die substrate may include, for example, a crystalline substrate formed using bulk silicon or a silicon-on-insulator (SOI) substructure. In some embodiments, the die substrate may be formed using alternative materials, which may or may not be combined with silicon, and which include, but are not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. In addition, materials classified as Group II-VI, Group III-V, or Group IV may also be used to form the die substrate. The device layer may include one or more transistors (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs)), supporting circuits for routing electrical signals to the transistors, passive components (e.g., signal traces, resistors, capacitors, or inductors), and / or any other IC components. The device layer may include, for example, one or more source and / or drain (S / D) regions, a gate for controlling the current flow in the transistor between the S / D regions, and one or more S / D contacts for routing electrical signals to and from the S / D regions. Each transistor may include a gate formed from at least two layers, a gate dielectric, and a gate electrode. The gate dielectric may include one layer or a stack of layers. One or more layers may include silicon oxide, silicon dioxide, silicon carbide, and / or high-k dielectric materials.High-k dielectric materials can include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that can be used in gate dielectrics include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, aluminum lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, when high-k materials are used, an annealing process can be carried out to improve their quality for gate dielectrics.

[0013] The gate electrode can be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor is a PMOS or NMOS transistor. In some implementations, the gate electrode may consist of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a filler metal layer. Furthermore, metal layers may be included for other purposes (e.g., barrier layers). With respect to PMOS transistors, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to NMOS transistors (e.g., for work function tuning). With respect to NMOS transistors, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to PMOS transistors (e.g., for work function tuning). Electrical signals (e.g., power and / or input / output (I / O) signals) can be routed to and / or from devices in the device layer (e.g., transistors) through one or more interconnect layers disposed above the device layer. For example, conductive features of the device layer (e.g., gate and S / D contacts) can be electrically coupled to interconnect structures that can optionally form a metallization stack (also referred to as an "ILD stack") of the IC device. The interconnect structures can include lines and / or vias filled with conductive material (e.g., metal).Lines can be arranged to route electrical signals in a plane substantially parallel to the surface of the die substrate on which the device layer is formed. Vias can be arranged to route electrical signals in a plane substantially perpendicular to the surface of the die substrate on which the device layer is formed.

[0014] IC devices can include, for example, memory devices (e.g., random access memory (RAM) devices, e.g., static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM) devices, conductive bridging RAM (CBRAM) devices, erasable programmable read-only memory (EPROM) chips, non-volatile memory (e.g., 3D XPoint), volatile memory (e.g., high-bandwidth memory), stacked memory, etc.); logic devices (e.g., AND, OR, NAND, or NOR gates, programmable logic devices, etc.); processor devices (e.g., central processing units (CPUs), graphics processing units (GPUs), etc.); application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), and platform controller hubs (PCHs), as well as any other suitable memory, logic, and / or processor devices. Multiple devices can be combined on a single structure. For example, a memory array formed by multiple memory devices can be formed on the same die as processing devices or other logic configured to store information in the memory devices or to execute instructions stored in the memory array.

[0015] Furthermore, the semiconductor structure can be a “chiplet,” which is a small integrated circuit (IC) containing a clearly defined subset of functionality that is one part of a processing module that makes up a larger integrated circuit, such as a computer processor. In some embodiments, one or more chiplets are coupled in various ways to a host chip, and each of the one or more chiplets contains its own cache (e.g., including a last-level cache (LLC)) that is accessible to one or more cores of the host chip. The host chip can contain one or more processor cores, each capable of acting as a consumer of memory resources, and the chiplets can contain one or more memory arrays coupled to each of the processor cores of the host chip, each accessible by each of the processor cores. In this particular context, the terms “memory,” “memory array,” “memory resource,” and related terms generally refer to either cached memory or non-cache memory (e.g., system memory). Similarly, the term “memory controller” generally refers to a controller circuit that provides access to either cached memory or non-cache memory. The host chip can contain processor cores that will act as consumers of memory resources. For example, a host chip can run an operating system, a binary input / output system (BIOS), and / or various other software processes. To facilitate the execution of such software, a chiplet may include one or more memory arrays that are linked to the processor core via a hardware interface. In one embodiment, the memory array includes static random access memory (SRAM) cells or dynamic random access memory (DRAM) cells.Additionally or alternatively, processor cores can be coupled to cache data in a memory array; for example, a processor core may be coupled to access the last-level cache (LLC) of the memory array. In various other embodiments, the memory array may include non-volatile memory (NVM) cells. The chiplet may also include a memory controller coupled between the hardware interface and the memory array to control memory access on behalf of the process run by the core. By providing the memory array within a chiplet disposed between the hardware interface and the host chip, data locality can be improved for use by one or more cores in a packaged device. This improved data locality enables access to memory resources that are relatively more space-efficient, time-efficient, and / or power-efficient.

[0016] Semiconductor structures can be arranged in a two-dimensional configuration or array (e.g., 2D, 2.1D, 2.3D, or 2.5D heterogeneous integration) as known in the art, or they can be stacked to form a three-dimensional configuration. When using a stacked configuration, the semiconductor structure can include two or more semiconductor substrates (e.g., chips, interposers, etc.) mounted on a circuit board. When implemented as a semiconductor chip, the substrate can be any of the countless different types of circuit devices used in electronic devices, such as microprocessors, graphics processors, combined microprocessor / graphics processors, application-specific integrated circuits, or memory devices, and can be single-core or multi-core. The substrate can be constructed from bulk semiconductors (e.g., silicon or germanium, etc.) or semiconductor-on-insulator materials (e.g., silicon-on-insulator materials, etc.). The circuit board can be a semiconductor chip package substrate, a circuit card, or virtually any other type of printed circuit board. While monolithic structures can be used for circuit boards, a more typical configuration would involve utilizing a build-up design. In this regard, the circuit board may consist of a central core, with one or more build-up layers formed on top of the central core, and one or more additional build-up layers formed below the central core. The core itself may consist of a stack of one or more layers. Electrical paths between substrates and circuit boards, and between any two substrates, may be provided by interconnection structures.

[0017] II. Package substrates In addition to semiconductor structures, semiconductor package assemblies also include a package substrate that helps bridge high-density interconnects and functionality. Generally speaking, a package substrate includes an insulating material and one or more conductive paths through the insulating material (e.g., including conductive traces and / or conductive vias, as shown). The insulating material can include, for example, organic materials, such as bismaleimidotriazine ("BT") resin materials (e.g., BT, BT-epoxy resin, etc.), epoxy resin materials (e.g., glass fiber reinforced epoxy resin (e.g., FR4)), polyimide materials, and low-k and ultra-low-k dielectrics (e.g., carbon-doped dielectrics, fluorine-doped dielectrics, porous dielectrics, and organic polymer dielectrics). The insulating material can also be formed from inorganic materials, such as ceramic materials (e.g., glass), as well as semiconductor materials (e.g., silicon, germanium, and other Group III-V materials (e.g., gallium nitride) and Group IV materials, etc.).

[0018] Depending on the specific configuration of the semiconductor package assembly, conductive paths in the package substrate can serve a variety of different purposes. For example, in embodiments where the package substrate is directly connected to the semiconductor structure, the conductive paths can help connect the semiconductor structure to the circuit board. In embodiments where an interposer is used, the conductive paths can help connect the interposer to the circuit board. Any suitable arrangement of conductive paths through any suitable number of insulating layers can be commonly used. Conductive paths can be fabricated from any suitable conductive material (e.g., copper). Conductive paths can be bordered by liner material (e.g., adhesive liners and / or barrier liners) as appropriate. In certain embodiments, the package substrate can be a lower-density medium, and the semiconductor structure and / or optional interposer can be a higher-density medium. As used herein, the terms “lower density” and “higher density” are relative terms indicating that conductive paths in a lower-density medium (e.g., including conductive lines and conductive vias) have a larger and / or larger pitch than conductive paths in a higher-density medium. For example, higher-density media can be manufactured using a modified semi-additive or semi-additive build-up process with advanced lithography (featuring small vertical interconnection features formed by an advanced laser or lithography process), while lower-density media can be PCBs manufactured using standard PCB processes (e.g., a standard subtractive process using etching chemistry to remove unwanted copper areas, and featuring coarse vertical interconnection features formed by a standard laser process).

[0019] As described above, a semiconductor structure can optionally be electrically connected to one or more interposers, and the resulting semiconductor package assembly is considered a “chip-on-interposer” structure. In particular, the interposer can provide an intervening substrate to help spread the connections to a wider pitch or reroute the connections to different connections. In such embodiments, the semiconductor structure can be electrically connected to the interposer by one or more coupling components. The coupling components can electrically and mechanically connect the chip-on-interposer structure to the package substrate and can include, for example, solder bumps, solder balls, male and female parts of sockets, adhesives, underfill materials, and / or any other suitable electrical and / or mechanical coupling structures. The underfill material can be an insulating material such as a suitable epoxy material. When used, the underfill material can include capillary underfill, non-conductive film (NCF), or molded underfill. In some embodiments, the underfill material may include epoxy flux, which assists in soldering the semiconductor structure and then polymerizes and encapsulates the interconnects in the interposer. The interposer generally includes an insulating material (e.g., those described above) and one or more conductive paths through the insulating material (e.g., including conductive traces and / or conductive vias, as shown). Such paths may include one or more metal interconnects and vias, as known in the art. In one embodiment, for example, the interposer may be formed from silicon, and vias may be formed therein, which are referred to as “through-silicon vias” (“TSVs”).

[0020] When used, an interposer can be passive or active, depending on the particular embodiment. “Passive” generally means that the interposer generally does not have embedded electronic components. On the other hand, an “active” interposer generally includes one or more electronic components embedded in an insulating material. Examples of such electronic components may include, for example, capacitors (e.g., ceramic capacitors as described herein), resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices, such as radio frequency devices, power amplifiers, power management devices, antennas, and microelectromechanical systems (MEMS) devices, can also be formed within the interposer. For example, an active interposer may include an active layer and a bulk semiconductor layer. The front surface of the active layer may be referred to herein as the “active side,” and the opposite surface of the bulk semiconductor layer may be referred to as the “rear side.” In one embodiment, the active layer may include one or more electronic components formed on the active side, such as a Level 1 (L1) memory element used as a memory cache for storing a configuration bitstream for configuring logical sectors within the coprocessor. The active layer may optionally include decryption / decryption circuits for processing encrypted and / or decrypted configuration bitstreams. The semiconductor layer may include a TSV connecting the electronic components in the active layer (e.g., the L1 memory element) to a linking element (e.g., a solder ball). For example, the L1 cache may receive the configuration bitstream from the host processor through the solder ball and the TSV. In this way, the energy efficiency of transferring signals and power between the interposer's active layer and the package substrate can be improved.

[0021] III. Ceramic Capacitors As described above, at least one ceramic capacitor is electrically connected to the semiconductor structure and the package substrate so that the assembly can achieve “package-level decoupling”. In one embodiment, for example, the ceramic capacitor can be directly connected to the semiconductor structure and the package substrate. However, in other embodiments, an interposer can be used between the semiconductor structure and the package substrate. In such embodiments, the ceramic capacitor can be positioned between the semiconductor structure and the interposer so that the capacitor is electrically connected to the package substrate via the interposer. In another embodiment, the ceramic capacitor can be positioned between the interposer and the package substrate so that the capacitor is electrically connected to the semiconductor structure via the interposer.

[0022] Regardless of the specific configuration of the assembly, a ceramic capacitor includes a main body comprising alternating dielectric layers and internal electrode layers. The internal electrode layers include at least a first internal electrode layer and a second internal electrode layer. The capacitor may include, for example, at least two sets of internal electrode layers, and for example, at least three sets, and for example, at least four sets of internal electrode layers. Naturally, it should be understood that the capacitor may and is not necessarily limited to any number of sets of alternating dielectric layers and internal electrode layers. Typically, the capacitor includes an upper surface (e.g., a first surface) and a lower surface opposite the upper surface (e.g., a second surface). The capacitor also includes at least one side surface, in particular at least two side surfaces, extending between the upper and lower surfaces. The capacitor may also include at least one end surface, in particular at least two end surfaces, extending between the upper and lower surfaces. The side surfaces can extend in the length (L) direction and can generally have longer dimensions than the end surfaces, while the end surfaces extend in the width (W) direction and generally have shorter dimensions. In one embodiment, the capacitor can have a parallelepiped shape, such as a rectangular parallelepiped shape. The overall dimensions of the capacitor can depend on the specific application. However, typically, the height or thickness of the capacitor is about 10 μm to about 5,000 μm, in some embodiments about 20 μm to about 2,500 μm, in some embodiments about 50 μm to about 1,500 μm, and in some embodiments about 100 μm to about 1,000 μm. When surrounded by a ball grid array, the height of the capacitor can be within 10% of the height (or diameter) of the balls in the ball grid array, for example, within 7%, for example, within 5%, for example, within 3%, for example, within 2%, for example, within 1%, etc. For example, such a height could be the original height before any reflow.Similarly, the length of the capacitor in the "L" direction can range from approximately 50 μm to approximately 10,000 μm, and in some embodiments, from approximately 100 μm to approximately 7,500 μm, and in some embodiments, from approximately 1,000 μm to approximately 5,000 μm. The width of the capacitor in the "W" direction can range from approximately 25 μm to approximately 5,000 μm, and in some embodiments, from approximately 50 μm to approximately 3,500 μm, and in some embodiments, from approximately 500 μm to approximately 2,500 μm.

[0023] The first and second internal electrode layers can be interleaved in a manner in which the dielectric layers are positioned opposite each other and spaced apart, with the dielectric layers located between them. Each set of alternating dielectric layers and internal electrode layers can be separated from adjacent sets by a certain distance. For example, the distance can be greater than the thickness of the individual dielectric layers in the set, for example, at least twice, in some embodiments at least three times, in some embodiments at least five times, and in some embodiments at least ten times the thickness of the dielectric layers in the set. Each set of internal electrode layers, and / or the entire capacitor, can contain about 10 to about 4,000 internal electrode layers, in some embodiments about 50 to about 2,000, and in some embodiments about 100 to about 1,000 internal electrode layers. The thickness of the dielectric layers and / or internal electrode layers is not limited and can be any thickness as desired depending on the performance characteristics. For example, the thickness of the internal electrode layer and / or individual dielectric layers can be in the range of about 100 nm to about 10 μm, in some embodiments it can be in the range of about 500 nm to about 8 μm, and in some embodiments it can be in the range of about 1 μm to about 5 μm. In certain embodiments, if the capacitor includes a second set of alternating dielectric layers and internal electrode layers, the distance between the first internal electrode layer of one set and the last internal electrode layer of another set can be greater than the distance between adjacent internal electrode layers in a given set. For example, the distance between the first internal electrode layer of the first set and the last internal electrode layer of the second set can be greater than the distance between the first internal electrode layer of the first set and the second internal electrode layer.

[0024] While not always necessary, the dielectric region of a ceramic capacitor may contain one or more voids. In this regard, the dielectric region may be a region containing dielectric material but not internal electrode material. Thus, the dielectric region may constitute a region that does not contain alternating dielectric layers and internal electrode layers. Therefore, the dielectric region may contain dielectric material between each set of alternating dielectric layers and internal electrode layers in the "W" direction. In addition, the dielectric region may contain dielectric material between the lateral edges of the electrodes in a given set of alternating dielectric layers and internal electrode layers and adjacent end surfaces in the longitudinal direction, for example, in the extent that such internal electrode layers do not extend to the end surfaces and are offset from the end surfaces. Such a dielectric region may be formed from a ceramic green sheet of alternating dielectric layers and internal electrode layers, but it should be understood that such a region does not contain any internal electrode material or corresponding layers. As a result, air voids may be provided within such a region. In addition, the dielectric region may contain dielectric material present between the first internal electrode layer of each set and adjacent side surfaces of the capacitor. Furthermore, the dielectric region may also include dielectric material present between the last internal electrode layer of each set and the adjacent side surface of the capacitor. Alternatively, the dielectric region may include dielectric material between the lateral edges of adjacent lead tabs extending from the main body of the internal electrode layer. In one particular embodiment, the dielectric region may include a region within the capacitor present between two external terminals. In addition, it should be understood that the dielectric region may include any combination of the regions described above.

[0025] As shown above, the dielectric region includes a region that contains dielectric material but does not contain internal electrode material. Therefore, when air voids are not considered, the dielectric region can contain 90 volume% or more of dielectric material, for example, 93 volume% or more, for example, 95 volume% or more, for example, 97 volume% or more, for example, 98 volume% or more, for example, 99 volume% or more, for example, 100 volume% or more, etc. Such air voids can be free of any material, in particular any dielectric material or internal electrode material. In one embodiment, the air void can be enclosed by enclosure material (for example, partially or completely). In one embodiment, the air void can be partially enclosed by enclosure material. By partially enclosing, the enclosure material is only partially present around the interior of the air void, and is partially separated from the dielectric material. In this regard, at least certain peripheral portions of the air void can be in direct contact with the dielectric material of the dielectric region. In another embodiment, the air void can be completely or entirely enclosed by enclosure material. By being completely enclosed, the enclosure material is present around the interior of the air void, so that it is entirely separated from the dielectric material. Nevertheless, the enclosure material can be used to act as a barrier between the interior of the air void and the dielectric material in the dielectric region. In one embodiment, the enclosure material can be a non-conductive material. However, it should be understood that in one embodiment, the air void may not be enclosed (even partially) by enclosure material.

[0026] Voids can be provided without a barrier between the air void and the dielectric material of the dielectric region. Air voids can and are not necessarily limited to any shape. For example, the shape can be a sphere, a cylinder, etc. In one embodiment, the shape can be a sphere. Air voids can have maximum dimensions (e.g., length, width, diameter, etc.) from about 5 μm to about 5,000 μm, and in some embodiments, they can have maximum dimensions from about 50 μm to about 2,500 μm, and in some embodiments, from about 100 μm to about 1,000 μm. Voids can be formed using any known technique, for example, by printing a specific pattern on a ceramic green sheet, and then laminating and firing the stacked laminates. Alternatively, voids can be formed using various drilling techniques to provide any desired shape within the dielectric material of the dielectric region. Voids can also be provided using one or more vias (e.g., through-hole vias). The vias do not necessarily have to be filled with material (e.g., any conductive or nonconductive material), and air may be present inside. In addition, in one embodiment, vias can be provided so that they exist only within the dielectric region. In this regard, vias can be provided so that they do not contact any of the internal electrode layers. In one embodiment, vias can extend from the upper surface of the capacitor to the lower surface of the capacitor. In this regard, vias can be columnar, extending through the thickness of the capacitor. Thus, vias can be through-hole conductive vias. In another embodiment, vias can extend only partially through the thickness of the capacitor. For example, vias can extend only partially through the thickness of the capacitor, for example, from about 10% to about 90% of the capacitor thickness, and in some embodiments, from about 20% to about 80%.

[0027] In addition to alternating internal electrode layers and dielectric layers, the ceramic capacitor also includes a first external terminal and a second external terminal, the first external terminal being electrically connected to the first internal electrode layer and located on a first surface (e.g., the upper surface) of the capacitor, and the second external terminal being electrically connected to the first internal electrode layer and located on a second surface (e.g., the lower surface) of the capacitor. Similarly, a third external terminal being electrically connected to the second internal electrode layer and located on the first surface of the capacitor, and a fourth external terminal being electrically connected to the second internal electrode layer and located on the second surface of the capacitor. Typically, the first and second external terminals have the same polarity (e.g., positive), and the third and fourth external terminals have the same polarity (e.g., negative). Nevertheless, the first and third external terminals of the ceramic capacitor can be electrically connected to a semiconductor structure, and the second and fourth external terminals of the ceramic capacitor can be electrically connected to a package substrate.

[0028] Furthermore, the capacitor may include external terminals on the opposite end surfaces. For example, one or more of the external terminals may extend from a first surface (e.g., the upper surface) and / or a second surface (e.g., the lower surface) to the end surface. When present on the end surface, the external terminals may be present only partially on the end surface and not cover the entire end surface. In another embodiment, the capacitor may not include external terminals on the opposite end surfaces. In one particular embodiment, the external terminals may not be present on the side surfaces of the capacitor. Nevertheless, the external terminals generally include at least one first polarity terminal and at least one second and opposite polarity terminal. The capacitor may include at least one, for example, at least two, for example, at least four, for example, at least six, for example, at least eight, etc., of first polarity terminals and / or second and opposite polarity terminals on the upper surface of the capacitor. Additionally, the capacitor may include the aforementioned number of terminals on the lower surface of the capacitor.

[0029] A capacitor may have an equal number of first polarity terminals and / or second polarity terminals on its upper and lower surfaces. The number of first polarity terminals may be equal to the number of second and opposite polarity terminals on the upper surface of the capacitor. The number of first polarity terminals may be equal to the number of second and opposite polarity terminals on the lower surface of the capacitor. The total number of terminals present on the upper surface of the capacitor may be equal to the total number of terminals present on the lower surface of the capacitor. The total number of first polarity terminals present on the upper and lower surfaces of the capacitor may be equal to the total number of second and opposite polarity terminals present on the upper and lower surfaces of the capacitor. Typically, similar polarity terminals on the lower surface of the capacitor corresponding to a particular set of alternating dielectric layers and internal electrode layers are electrically connected to similar polarity terminals on the upper surface of the capacitor. Similar polarity terminals located on the upper and lower surfaces of the capacitor do not necessarily have to be interlocked with each other. In this regard, corresponding similar polarity terminals on the upper and lower surfaces may not be offset by terminal position, but instead may be positioned directly above or directly below another similar polarity terminal on the opposite upper or lower surface. In other words, corresponding similar polarity terminals corresponding to a particular set of alternating dielectric layers and internal electrode layers, and, among other things, the corresponding lead tabs of such sets, may be substantially aligned. Being substantially aligned means that the offset of one lateral edge of a polarity terminal on the upper surface from its side edge is within + / -10% of the offset of the corresponding polarity terminal on the lower surface from its side edge, for example, within + / -5%, for example, within + / -4%, for example, within + / -3%, for example, within + / -2%, for example, within + / -1%, for example, within + / -0.5%, etc.

[0030] The pitch of the external terminals (i.e., the nominal distance between centers, also referred to as the center-to-center spacing) can be determined by a particular package substrate configuration. The pitch between external terminals in one direction (i.e., the x-direction or the y-direction) can be the same as the pitch between adjacent external terminals in the other direction (i.e., the y-direction or the x-direction, respectively). That is, the pitch between any two adjacent external terminals can be substantially the same as the pitch between any other two adjacent external terminals. The pitch can be, for example, in the range of about 0.1 mm to about 2 mm, in some embodiments in the range of about 0.2 mm to about 1.5 mm, and in some embodiments in the range of about 0.4 mm to about 1.4 mm.

[0031] If desired, external terminals can be positioned similarly to the configuration of a ball grid array. For example, external terminals can be provided to make contact as typically used by a ball grid array (particularly a surrounding ball grid array). In this regard, the pitch of the external terminals can be the same as the pitch of the surrounding ball grid array. That is, the pitch can be within 10% of the pitch of the surrounding ball grid array, for example, within 5%, within 2%, within 1%, within 0.5%, within 0.1%, etc. In addition, like a ball grid array, external terminals can be provided in rows and columns. That is, external terminals can be provided such that they exist in at least one row and at least two columns. For example, external terminals can be provided in at least two rows, for example, at least three rows, etc., for example, at least four rows, etc. The number of rows can be determined by the number of different sets of alternating dielectric layers and internal electrode layers. In addition, the external terminals can be provided in at least two columns, for example, at least three columns, for example, at least four columns, and so on. The number of columns can be determined by the number of different columnar tabs of the internal electrodes.

[0032] The length of an external terminal extending along the upper surface (i.e., extending longitudinally from one end surface to another) can be the same as the length of the corresponding external terminal extending along the lower surface. For example, the length of an external terminal can be approximately 0.3 mm to approximately 1.1 mm, in some embodiments approximately 0.4 mm to approximately 1 mm, and in some embodiments approximately 0.5 mm to approximately 0.9 mm. The length of an external terminal can also be less than the length of the capacitor, for example, 50% or less, 40% or less, 30% or less, 25% or less, 20% or less, 15% or less, etc. If desired, each external terminal can have a different length. For example, an external terminal adjacent to an end surface can have a longer length than an external terminal offset from the end surface. In this regard, the ratio of the length of the external terminal adjacent to the end surface to the length of the external terminal offset from the end surface can be about 0.3 to about 5, in some embodiments about 0.5 to about 4, and in some embodiments about 0.7 to about 3. The width of the external terminal extending from one side surface to the opposite side surface can be the same on the upper and lower surfaces. For example, the width can be in the range of about 0.3 mm to about 1.1 mm, in some embodiments about 0.4 mm to about 1 mm, and in some embodiments about 0.5 mm to about 0.9 mm.

[0033] Referring to Figures 3A and 3B, one particular embodiment of a ceramic capacitor 10 that may be used in a semiconductor package assembly of the present invention is shown in more detail. The capacitor 10 generally has a thickness "T", width "W", and length "L", such as those described above. Furthermore, as shown, the capacitor 10 has a 1×2 configuration in that it includes two external terminals along one dimension of the upper and lower surfaces. That is, the capacitor 10 includes a first external terminal 12 and a second external terminal 14 on the upper surface and two corresponding third and fourth external terminals (not shown) on the lower surface. The first external terminal 12 and the third external terminal (not shown) can have the same polarity (i.e., positive), and the second external terminal 14 and the fourth external terminal (not shown) can also have the same polarity (i.e., negative). The width "BW" and length "BL" of the external terminals 12 and / or 14 can be within the range discussed above. Although not always necessary, a void 1350 can also be formed within the capacitor 10 between terminals 12 and 14, as described above.

[0034] Furthermore, the capacitor 10 includes a dielectric layer (not shown) and an internal electrode layer 110, as illustrated in Figure 3B. Specifically, the internal electrode layer 110 includes a first internal electrode layer 105 and a second set of internal electrode layers 115. In the particular embodiment shown, the internal electrode layers 105, 115 include at least one lead tab 120, 130, 140, 150 extending from the upper and lower edges of the main body of the internal electrode layer. The lead tabs 120, 130, 140, 150 of the internal electrode layers 105, 115 can extend to the upper and lower surfaces of the capacitor and assist in forming external terminals. In this regard, the lead tabs 120, 130, 140, 150 are exposed on the upper and lower surfaces of the capacitor and can enable connections between the main body of the internal electrode layer and the external terminals. For example, lead tabs 120, 130, 140, and 150 may include leading edges 123, 133, 143, and 153, which extend to the edge of the dielectric layer, enabling the formation of external terminals. The lengths of the lead tabs 120, 130, 140, and 150 can vary as desired, but are typically about 0.3 mm to about 1.2 mm, in some embodiments about 0.4 mm to about 1.1 mm, and in some embodiments about 0.5 mm to about 1 mm. When more than one lead tab is present along the edge, each lead tab may have the same length. In another embodiment, each lead tab may have different lengths. For example, a lead tab substantially aligned with the side edge of the internal electrode layer may have a longer length than a lead tab offset from the side edge of the internal electrode layer. In this regard, the ratio of the length of the lead tab aligned with the side edge of the internal electrode layer to the length of the lead tab offset from the side edge of the internal electrode layer can be about 0.3 to about 5, in some embodiments about 0.5 to about 4, and in some embodiments about 0.7 to about 3.Being substantially aligned generally means that the offset of one lateral edge of the first lead tab and / or second lead tab at the upper edge from the lateral edge is within + / -10%, for example, within + / -5%, for example, within + / -4%, for example, within + / -3%, for example, within + / -2%, for example, within + / -1%, for example, within + / -0.5%, etc., of the offset of the corresponding lateral edge of the first lead tab and / or second lead tab at the bottom edge from the lateral edge.

[0035] As illustrated in Figure 3B, the first internal electrode layer 105 includes one lead tab 120, 130 extending from the main body 135 along the upper edge 105c and the bottom edge 105d. The second internal electrode layer 115 includes one lead tab 140, 150 extending from the main body 145 along the upper edge and the bottom edge. The lead tabs 120, 130 at the upper and bottom edges of the first internal electrode layer 105 can be aligned vertically. That is, the lateral edges 121, 122 of the first lead tab 120 along the upper edge 105c can be aligned with the lateral edges 131, 132 of the first lead tab 130 along the bottom edge 105d opposite the upper edge 105c. In addition, such lateral edges 121 and 131 can be aligned with the side edge 105a of the internal electrode layer 105. However, it should be understood that both lateral edges 121 and 122 of the first lead tab 120 along the upper edge 105c can be aligned with the lateral edges 131 and 132 of the first lead tab 130 along the bottom edge 105d opposite the upper edge 105c. In other words, both lateral edges 122 and 132 can be aligned and offset by the same distance from the side edges 105a and 105b along the bottom edge 105d and the upper edge 105c. Similarly, the lead tabs 140 and 150 on the upper and bottom edges of the second internal electrode layer 115 can be aligned vertically. In other words, the lateral edges 141, 142 of the first lead tab 140 along the upper edge can be aligned with the lateral edges 151, 152 of the first lead tab 150 along the bottom edge opposite the upper edge. In one embodiment, both lateral edges 141, 142 of the first lead tab 140 along the upper edge can be aligned with the lateral edges 151, 152 of the first lead tab 150 along the bottom edge opposite the upper edge. The relationship between the lateral edges of the first lead tab at the upper edge and the lateral edges of the first lead tab at the bottom edge, as described with respect to the internal electrode layer 105, can also be applied to the internal electrode layer 115.Such an arrangement allows a gap to be formed between the lead tab 120 of the first internal electrode layer 105 and the lead tab 140 of the second internal electrode layer 115. Similarly, a gap can be formed between the lead tab 130 of the first internal electrode layer 105 and the lead tab 150 of the second internal electrode layer 115. The size of each gap can be substantially the same.

[0036] The lead tabs 120 and 140 can be arranged in parallel with the lead tabs 130 and 150 extending from the internal electrode layers 105 and 115, respectively, so that the lead tabs extending from the alternating electrode layers 105 and 115 can be aligned in their respective rows. For example, the lead tabs 120 and 130 of the internal electrode layer 105 can be arranged in their respective stacked configurations, while the lead tabs 140 and 150 of the internal electrode layer 115 can be arranged in their respective stacked configurations.

[0037] It is understood that lead tab 120 is connected to external terminal 12, while lead tab 140 is connected to external terminal 14. Therefore, each lead tab 120 interlocks with each other with each other with the respective lead tab 140 in the same manner as external terminals 12 and 14. The interlocked lead tabs can provide multiple adjacent current injection points on the associated main electrode portion.

[0038] The distance between adjacent exposed lead tabs of the internal electrode layer in a given column can be specifically designed to help ensure guided formation of the terminations. The distance between exposed lead tabs of the internal electrode layer in a given column can be, for example, in the range of about 0.25 μm to about 10 μm, in some embodiments in the range of about 0.5 μm to about 5 μm, and in some embodiments in the range of about 1 μm to about 4 μm. Additionally, the distance between adjacent columnar stacks of electrode tabs can be, but is not limited to, at least twice as large as the distance between adjacent lead tabs in a given column to ensure that individual terminations do not mix. In some embodiments, the distance between adjacent columnar stacks of exposed metallization can be about four times the distance between adjacent exposed electrode tabs in a particular stack. However, such distances can vary depending on the desired capacitance performance and package substrate configuration. For example, the distance can be approximately 0.1 mm to approximately 1.5 mm, in some embodiments approximately 0.2 mm to approximately 1.3 mm, and in some embodiments approximately 0.3 mm to approximately 1 mm, when determined based on the center point of each lead tab or the distance between adjacent lateral edges of the lead tabs. In addition, such distances can correspond to the separation distance of balls on a ball grid array.

[0039] In the embodiments illustrated in Figures 3A and 3B, the capacitor includes two external terminals that extend to the ends of the capacitor. However, this is not always necessary. Referring to Figures 4A and 4C, one embodiment of the capacitor 10 is shown, in which a first external terminal 12, a second external terminal 14, and third and fourth external terminals (not shown) do not extend to the ends of the capacitor. To help achieve such a configuration in this particular embodiment, the capacitor 10 includes an internal electrode layer 110 comprising a first internal electrode layer 105 and a second internal electrode layer 115. The first internal electrode layer 105 can extend to the upper surface of the capacitor 10, and the second internal electrode layer 115 extends to the lower surface of the capacitor. This extension assists in the formation of the external terminals. In this regard, the internal electrode layers can be exposed on the upper and lower surfaces of the capacitor, allowing for connections between the main body of the internal electrode layer and the external terminals. For example, the internal electrode layers 105 and 115 extend to the edges of the dielectric layer, enabling the formation of external terminals. The lateral or side edges of the internal electrode layers 105 and 115 can be aligned vertically. That is, the lateral edge of the first internal electrode layer 105 can be aligned with the lateral edge of the second internal electrode layer 115. In one embodiment, both lateral edges can be aligned. In another embodiment, the point of contact between the first internal electrode layer 105 and the external terminal can be aligned with the point of contact between the second internal electrode layer 115 and the external terminal. Additionally, the capacitor 10 in Figure 4A includes at least one first polarity terminal and at least one second and opposite polarity terminal on the upper surface. Although not shown, the lower surface includes at least one first polarity terminal and the second and opposite terminal.

[0040] In the embodiments illustrated in Figures 3A-3B and 4A-4C, the capacitor includes two external terminals on each surface. However, as shown above, the present invention is not limited by the number of external terminals, and / or the number of lead tabs extending from the upper and / or bottom edges. For example, referring to Figures 5A and 5B, a capacitor 20 is shown, which has a 1×4 array configuration and therefore includes four external terminals on each surface. That is, the capacitor includes four terminals along two dimensions: the upper surface and the lower surface. In this regard, the capacitor includes a total of four external terminals on the upper surface (i.e., first external terminals 22a and 22b and second external terminals 24a and 24b), and a corresponding set of third and fourth external terminals (not shown) on the lower surface. The first external terminals 22a, 22b and the third external terminal (not shown) generally have the same polarity (i.e., positive), and the second external terminals 24a, 24b and the fourth external terminal (not shown) generally have the same polarity (i.e., negative). The capacitor 20 generally has a thickness "T", width "W", and length "L", such as those described above, and the width "BW" and lengths "BLA" and "BLB" of the external terminals 22a, 22b and / or 24a, 24b can be within the range discussed above. Also, although not required, a void 1350 can be formed in the capacitor 20 between the external terminals 22a, 24b, 22b, and / or 24a, as described above.

[0041] Furthermore, the capacitor 20 includes an internal electrode layer 210 comprising a first internal electrode layer 205 and a second internal electrode layer 215 in an alternating arrangement. The internal electrode layers 205 and 215 include at least one lead tab 220a~b, 230a~b, 240a~b, 250a~b extending from the upper and lower edges of the main body of the internal electrode layer. The lead tabs 220a~b, 230a~b, 240a~b, 250a~b of the internal electrode layers 205 and 215 extend to the upper and lower surfaces of the capacitor and assist in forming external terminals. In this regard, the lead tabs 220a~b, 230a~b, 240a~b, 250a~b are exposed on the upper and lower surfaces of the capacitor and can enable connections between the main body of the internal electrode layer and the external terminals. For example, lead tabs 220a~b, 230a~b, 240a~b, 250a~b may include leading edges 223a~b, 233a~b, 243a~b, 253a~b, and these leading edges extend to the edge of the dielectric layer, enabling the formation of external terminals. Internal electrode layers 205, 215 include at least two lead tabs 220a~b, 230a~b, 240a~b, 250a~b along their upper and bottom edges. The first internal electrode layer 205 includes two lead tabs 220a~b, 230a~b extending from the main body 235 along their respective upper and bottom edges 205c and 205d. The second internal electrode layer 215 includes two lead tabs 240a-b and 250a-b that extend from the main body 245 along their respective upper and bottom edges.

[0042] The lead tabs 220a-b and 230a-b located at the upper edge 205c and bottom edge 205d of the first internal electrode layer 205 can be aligned vertically. That is, the lateral edges 221a and 222a of the first lead tab 220 along the upper edge 205c can be aligned with the lateral edges 231a and 232a of the first lead tab 230 along the bottom edge 205d opposite the upper edge 205c. In addition, such lateral edges 221a and 231a can be aligned with the lateral edge 205a of the internal electrode layer 205. However, it should be understood that both lateral edges 221a, 222a of the first lead tab 220a along the upper edge 205c can be aligned with the lateral edges 231a, 232a of the first lead tab 230a along the bottom edge 205d opposite the upper edge 205c. In other words, both lateral edges 222a, 232a can be offset by the same distance from the lateral edges 205a-b along the bottom edge 205d and the upper edge 205c. When the upper edge 205c and the bottom edge 205d contain at least two lead tabs 220a-b, 230a-b, at least one lateral edge of each lead tab on the upper edge 205c can be aligned with the corresponding lateral edge of the lead tab on the bottom edge 205d. Furthermore, the lateral edges of each lead tab located at the upper edge 205c can be aligned with the corresponding lateral edges of the lead tabs located at the bottom edge 205d. Similarly, the lead tabs 240a-b and 250a-b located at the upper and bottom edges of the second internal electrode layer 215 can be aligned vertically. That is, the lateral edges 241a and 242a of the first lead tab 240 along the upper edge can be aligned with the lateral edges 251a and 252a of the first lead tab 250 along the bottom edge opposite the upper edge.

[0043] The lateral edges 241a, 242a of the first lead tab 240 along the upper edge can be aligned with the lateral edges 251a, 252a of the first lead tab 250 along the bottom edge opposite the upper edge. The relationship between the lateral edge of the first lead tab at the upper edge and the lateral edge of the first lead tab at the bottom edge, as described with respect to the internal electrode layer 205, can also be applied to the internal electrode layer 215. Such an arrangement would form a gap between any of the lead tabs along the upper edge 205c of the first internal electrode layer 205, the second internal electrode layer 215, or both. For example, the gap can be formed between any of the lead tabs 220a-b, 240a-b extending from the upper edge of each internal electrode layer. Additionally, the gap can be formed between any of the lead tabs along the bottom edge 205d of the first internal electrode layer 205, the second internal electrode layer 215, or both. For example, a gap can be formed between any of the lead tabs 230a-b and 250a-b extending from the bottom edge of each internal electrode layer. Furthermore, the size of the gap between two tabs extending from the top edge, whether from the same internal electrode layer or from adjacent internal electrode layers, can be substantially the same as the size of the gap between the corresponding two tabs extending from the bottom edge. For example, the gap between lead tab 220a and lead tab 220b can be substantially the same as the gap between lead tab 230a and lead tab 230b. Similarly, the gap between lead tab 220a and lead tab 240a can be substantially the same as the gap between lead tab 230a and lead tab 250a.

[0044] One or all of the lead tabs 220a-b and 240a-b can be arranged in parallel with the lead tabs 230a-b and 250a-b extending from the alternating electrode layers 205 and 215, respectively, so that the lead tabs extending from the alternating electrode layers 205 and 215 can be aligned in their respective rows. For example, the lead tabs 220a-b and 230a-b of the internal electrode layer 205 can be arranged in their respective stacked configurations, while the lead tabs 240a-b and 250a-b of the internal electrode layer 215 can be arranged in their respective stacked configurations. It will be recognized that the lead tabs 220a-b are connected to the external terminals 22a-b, respectively, while the lead tabs 240a-b are connected to the external terminals 24a-b, respectively. Therefore, each lead tab 220a-b will interlock with each other with each lead tab 240a-b in the same manner as the external terminals 22a-b and 24a-b. The interlocked lead tabs can provide multiple adjacent current injection points on the associated main electrode portion.

[0045] In the embodiments discussed above, the external terminals are arranged in a linear manner in a single dimension (e.g., a 1×2 or 1×4 configuration). Naturally, it should be understood that multidimensional arrays of external terminals are also possible. For example, referring to Figures 6A to 6D, one particular embodiment of a capacitor 10 having a 2×2 array configuration is shown. In such a configuration, the capacitor includes a total of four external terminals (first external terminal 12 and second external terminal 14) on the upper surface and a corresponding number of external terminals (third and fourth external terminals, not shown) on the lower surface. The first external terminal 12 and the third external terminal (not shown) generally have the same polarity (i.e., positive), and the second external terminal 14 and the fourth external terminal (not shown) also generally have the same polarity (i.e., negative). Although not always required, a void 1350 can also be formed in the capacitor 10 between external terminals 12 and 14, as described above.

[0046] The capacitor 10 includes alternating dielectric layers and internal electrode layers 110, the internal electrode layers 110 including a first internal electrode layer 105 and a second internal electrode layer 115 in an alternating arrangement. Similar to the embodiments discussed above in Figures 3A to 3B, the internal electrode layers 105, 115 also include at least one lead tab 120, 130, 140, 150 extending from the upper and bottom edges of the main body of the internal electrode layers. However, in contrast to the internal electrodes in Figures 3A to 3B, the lateral edges 121, 122 of the first lead tab 120 along the upper edge 105c can be aligned with the lateral edges 131, 132 of the first lead tab 130 along the bottom edge 105d opposite the upper edge 105c. In other words, the lateral edges 121 and 122 of the first lead tab 120 along the upper edge 105c can be offset from the lateral edges 105a and 132 of the first lead tab 130 along the bottom edge 105d opposite the upper edge 105c by the same distance (indicated by "O"). However, it should be understood that both lateral edges 121 and 122 of the first lead tab 120 along the upper edge 105c can be aligned with the lateral edges 131 and 132 of the first lead tab 130 along the bottom edge 105d opposite the upper edge 105c. In other words, both lateral edges 121 and 122 of the first lead tab 120 along the upper edge 105c can be offset from the lateral edges 105a and 132 of the first lead tab 130 along the bottom edge 105d opposite the upper edge 105c by the same distance.

[0047] Similarly, the lead tabs 140 and 150 at the upper and lower edges of the second internal electrode layer 115 can be aligned vertically. That is, the lateral edges 141 and 142 of the first lead tab 140 along the upper edge can be aligned with the lateral edges 151 and 152 of the first lead tab 150 along the lower edge opposite the upper edge. In one embodiment, both lateral edges 141 and 142 of the first lead tab 140 along the upper edge can be aligned with the lateral edges 151 and 152 of the first lead tab 150 along the lower edge opposite the upper edge. The relationship between the lateral edges of the first lead tab at the upper edge and the lateral edges of the first lead tab at the lower edge, as described with respect to the internal electrode layer 105, can also be applied to the internal electrode layer 115. Such an arrangement allows for the formation of a gap between the lead tab 120 of the first internal electrode layer 105 and the lead tab 140 of the second internal electrode layer 115. A gap can also be formed between the lead tab 130 of the first internal electrode layer 105 and the lead tab 150 of the second internal electrode layer 115. The size of each gap can be substantially the same.

[0048] The lead tabs 120 and 140 can be arranged in parallel with the lead tabs 130 and 150 extending from the internal electrode layers 105 and 115, respectively, so that the lead tabs extending from the alternating electrode layers 105 and 115 can be aligned in their respective rows. For example, the lead tabs 120 and 130 of the internal electrode layer 105 can be arranged in their respective stacked configurations, while the lead tabs 140 and 150 of the internal electrode layer 115 can be arranged in their respective stacked configurations. It will be recognized that the lead tab 120 connects to the external terminal 12, and the lead tab 140 connects to the external terminal 14. Thus, each lead tab 120 will interlock with each other with the respective lead tab 140 in a similar manner to the external terminals 12 and 14. The interlocked lead tabs can provide multiple adjacent current injection points on the associated main electrode portion.

[0049] As shown in Figure 6D, multiple sets 110a and 110b of the internal electrode layer 110 can be used to form an array of external terminals shown in Figure 6A. Typically, the distance "t" between sets 110a and 110b is about 0.2 μm to about 10 μm, in some embodiments about 0.5 μm to about 8 μm, and in some embodiments about 1 μm to about 5 μm. Additionally, the distance "t" can be at least twice as large as the distance between adjacent lead tabs in a given column, in some embodiments at least about three times, and in some embodiments about four times to about eight times, in order to ensure that individual terminals do not mix.

[0050] Referring to Figures 7A to 7D, one embodiment of a capacitor 20 having a 2x4 array configuration is shown. In such a configuration, the capacitor includes a total of eight external terminals (first external terminals 22a, 22b and second external terminals 24a, 24b) on its upper surface and a corresponding number of external terminals (third and fourth external terminals, not shown) on its lower surface. The first external terminals 22a, 22b and the third external terminal (not shown) generally have the same polarity (i.e., positive), and the second external terminals 24a, 24b and the fourth external terminal (not shown) also generally have the same polarity (i.e., negative). Although not always required, voids 1350 can also be formed in the capacitor 20 between the external terminals 22a, 22b, 24a, and / or 24b, as described above.

[0051] Furthermore, the capacitor 20 includes two sets 210a and 210b of alternating internal electrode layers 210, as illustrated in Figure 7D. As illustrated in Figures 7B and 7C, each set of alternating dielectric layers and internal electrode layers 210 includes a first internal electrode layer 205 and a second internal electrode layer 215 in an alternating arrangement. The internal electrode layers 205 and 215 include at least one lead tab 220a~b, 230a~b, 240a~b, and 250a~b extending from the upper and lower edges of the main body of the internal electrode layer. The lead tabs 220a~b, 230a~b, 240a~b, and 250a~b of the internal electrode layers 205 and 215 extend to the upper and lower surfaces of the capacitor and help form external terminals. In this regard, the lead tabs 220a~b, 230a~b, 240a~b, and 250a~b are exposed on the upper and lower surfaces of the capacitor, enabling connection between the main body of the internal electrode layer and the external terminals. For example, the lead tabs 220a~b, 230a~b, 240a~b, and 250a~b may include leading edges 223a~b, 233a~b, 243a~b, and 253a~b, which extend to the edge of the dielectric layer, enabling the formation of external terminals. The internal electrode layers 205 and 215 include at least two lead tabs 220a~b, 230a~b, 240a~b, and 250a~b along their upper and bottom edges. The first internal electrode layer 205 includes two lead tabs 220a-b and 230a-b extending from the main body 235 along their respective upper edges 205c and bottom edges 205d. The second internal electrode layer 215 includes two lead tabs 240a-b and 250a-b extending from the main body 245 along their respective upper and bottom edges.

[0052] The lead tabs 220a-b and 230a-b located at the upper edge 205c and bottom edge 205d of the first internal electrode layer 205 can be aligned vertically. That is, the lateral edges 221a and 222a of the first lead tab 220 along the upper edge 205c can be aligned with the lateral edges 231a and 232a of the first lead tab 230 along the bottom edge 205d opposite the upper edge 205c. In other words, the lateral edges 221a and 222a of the first lead tab 220 along the upper edge 205c can be offset from the lateral edges 205a-b by the same distance as the lateral edges 231a and 232a of the first lead tab 230 along the bottom edge 205d opposite the upper edge 205c (indicated by "O"). Furthermore, both lateral edges 221a and 222a of the first lead tab 220 along the upper edge 205c can be aligned with the lateral edges 231a and 232a of the first lead tab 230 along the bottom edge 205d opposite the upper edge 205c. That is, both lateral edges can be offset by the same distance from the side edges 205a and 205b. When the upper edge 205c and the bottom edge 205d contain at least two lead tabs 220a and 220b, 230a and 230b, at least one lateral edge of each lead tab on the upper edge 205c can be aligned with the corresponding lateral edge of the lead tab on the bottom edge 205d. Also, both lateral edges of each lead tab on the upper edge 205c can be aligned with the corresponding lateral edges of the lead tab on the bottom edge 205d.

[0053] Similarly, the lead tabs 240a-b and 250a-b at the upper and lower edges of the second internal electrode layer 215 can be aligned vertically. That is, the lateral edges 241a and 242a of the first lead tab 240 along the upper edge can be aligned with the lateral edges 251a and 252a of the first lead tab 250 along the lower edge opposite the upper edge. Both lateral edges 241a and 242a of the first lead tab 240 along the upper edge can be aligned with the lateral edges 251a and 252a of the first lead tab 250 along the lower edge opposite the upper edge. The relationship between the lateral edges of the first lead tab at the upper edge and the lateral edges of the first lead tab at the lower edge, as described for the internal electrode layer 205, can also be applied to the internal electrode layer 215. Such arrangements allow gaps to be formed between any of the lead tabs along the upper edge 205c of the first internal electrode layer 205, the second internal electrode layer 215, or both. For example, gaps can be formed between any of the lead tabs 220a-b, 240a-b extending from the upper edge of each internal electrode layer. Additionally, gaps can be formed between any of the lead tabs along the bottom edge 205d of the first internal electrode layer 205, the second internal electrode layer 215, or both. For example, gaps can be formed between any of the lead tabs 230a-b, 250a-b extending from the bottom edge of each internal electrode layer. Furthermore, the size of the gap between each pair of tabs extending from the upper edge, whether from the same internal electrode layer or from adjacent internal electrode layers, can be substantially the same as the size of the gap between each of the corresponding tabs extending from the bottom edge. For example, the gap between lead tab 220a and lead tab 220b can be substantially the same as the gap between lead tab 230a and lead tab 230b. Similarly, the gap between lead tab 220a and lead tab 240a can be substantially the same as the gap between lead tab 230a and lead tab 250a.

[0054] One or all of the lead tabs 220a-b and 240a-b can be arranged in parallel with the lead tabs 230a-b and 250a-b extending from the alternating electrode layers 205 and 215, respectively, so that the lead tabs extending from the alternating electrode layers 205 and 215 can be aligned in their respective rows. For example, the lead tabs 220a-b and 230a-b of the internal electrode layer 205 can be arranged in their respective stacked configurations, while the lead tabs 240a-b and 250a-b of the internal electrode layer 215 can be arranged in their respective stacked configurations. It will be recognized that the lead tabs 220a-b are connected to the external terminals 22a-b, respectively, while the lead tabs 240a-b are connected to the external terminals 24a-b, respectively. Therefore, each lead tab 220a-b will interlock with each other with each lead tab 240a-b in the same manner as the external terminals 22a-b and 24a-b. The interlocked lead tabs can provide multiple adjacent current injection points on the associated main electrode portion.

[0055] As shown in Figure 7D, multiple sets 210a and 210b of the internal electrode layer 110 can be used to form an array of external terminals shown in Figure 7A. Typically, the distance "t" between sets 110a and 110b is about 0.2 μm to about 10 μm, in some embodiments about 0.5 μm to about 8 μm, and in some embodiments about 1 μm to about 5 μm. Additionally, the distance "t" can be at least twice as large as the distance between adjacent lead tabs in a given column, in some embodiments at least about three times, and in some embodiments about four times to about eight times, in order to ensure that individual terminals do not mix.

[0056] Referring to Figures 8A and 8B, one embodiment of a capacitor 20 having a 4x4 array configuration is shown. In such a configuration, the capacitor includes a total of 16 external terminals (first external terminals 32a, 32b and second external terminals 34a, 34b) on its upper surface and a corresponding number of external terminals (third and fourth external terminals, not shown) on its lower surface. The first external terminals 32a, 32b and the third external terminal (not shown) generally have the same polarity (i.e., positive), and the second external terminals 34a, 34b and the fourth external terminal (not shown) also generally have the same polarity (i.e., negative). Although not always required, voids 1350 can also be formed in the capacitor 20 between the external terminals 32a, 32b, 34a, and / or 34b, as described above. Furthermore, the capacitor 30 includes an internal electrode layer 210 arranged in four sets 210a, 210b, 210c, and 210d, as illustrated in Figure 8B. Similar to the embodiments discussed above, the distances between sets "t1", "t2", and / or "t3" can be from about 0.2 μm to about 10 μm, from about 0.5 μm to about 8 μm in some embodiments, and from about 1 μm to about 5 μm in some embodiments. In addition, the distances "t1", "t2", and / or "t3" can be at least twice as large as the distance between adjacent lead tabs in a given column, from about four times to about eight times in some embodiments, but not limited to, to ensure that individual terminations do not mix.

[0057] In the embodiments referenced above, the internal electrode layers are generally oriented in a vertical configuration. Naturally, this is not always necessary, and other geometric configurations (e.g., a horizontal configuration) are equally appropriate. For example, referring to Figures 9A-9C, a capacitor 20 is shown, which has a 4x4 configuration of external terminals 32 and 34 similar to Figures 8A-8B, but uses a horizontal internal electrode configuration. That is, as shown in Figures 9B-9C, the capacitor 20 includes multiple internal electrode layers 205 and 215 and multiple dielectric layers in an alternating arrangement, and the electrode layers are interleaved in a relationship where the dielectric layers are positioned opposite each other and spaced apart, with the dielectric layers positioned between each adjacent electrode layer. The internal electrode layers are electrically connected to the external terminals through conductive vias (e.g., a first conductive via 225 and a second conductive via 285). The conductive vias extend to the upper surface 235 and the lower surface 245 of the capacitor. In this regard, conductive vias can be exposed on the upper surface 235 and the lower surface 245 of the capacitor. This exposure can facilitate the formation of external terminals on the upper surface 235 and the lower surface 245 of the capacitor. Furthermore, the internal electrode layers 205 and 215 have a rectangular configuration and are provided so as not to extend to the side surfaces of the capacitor.

[0058] If desired, the capacitor 20 may also include a first shielding region 255 and a second shielding region 265, each of which may include one or more shielding electrode layers 275. As shown, the shielding regions are provided above and below the active electrode region and active electrode layers 205, 215. Figure 9C similarly illustrates the use of a first anchor electrode 305 and a second anchor electrode 295. The first anchor electrode 305 is provided in the first active electrode layer 205 together with the first active electrode. In this regard, the first active electrode is electrically connected to a first conductive via 225, while the first anchor electrode is connected to a second conductive via 285. Similarly, the second anchor electrode 295 is provided in the second active electrode layer 215 together with the second active electrode. In this regard, the second active electrode is electrically connected to the second conductive via 285, while the second anchor electrode is connected to the first conductive via 225.

[0059] The first conductive via 225 extends through the first plurality of internal electrode layers 205 and is in electrical contact with the first plurality of internal electrode layers 205. However, the first conductive via 225 extends through a non-contact hole 105, and a gap 105 is formed between the first conductive via 225 and the electrodes of the second plurality of internal electrode layers 215. Such a gap 105 allows for insulation of the second plurality of internal electrode layers 215 from the first conductive via 225. Similarly, the second conductive via 285 extends through the second plurality of internal electrode layers 215 and is in electrical contact with the second plurality of internal electrode layers 215. However, the second conductive via 285 extends through a non-contact hole 115, and a gap 115 is formed between the second conductive via 285 and the electrodes of the first plurality of internal electrode layers 205. Such gap 115 allows for the isolation of the first plurality of internal electrode layers 205 from the second conductive via 285. When an anchor (or dummy) electrode is present, as illustrated in Figure 10C, such layers also include gaps 125 and 135. The first conductive via 225 extends through the first plurality of internal electrode layers 205 and is in electrical contact with it and in contact with the second anchor tab 295. However, the second anchor tab 295 is isolated from the active electrode of the second plurality of internal electrode layers 215 through a gap 125 formed between the anchor tab 295 and the active electrode 215. Such gap 125 allows for the isolation of the second plurality of internal electrode layers 215 from the second anchor tab 295 and the first conductive via 225.

[0060] The dielectric layers of ceramic capacitors described herein are typically formed from ceramic materials. Ceramic materials can have relatively high dielectric constants. For example, the dielectric constant can be 3 or greater, and in some embodiments it can be about 10 to about 20,000, in some embodiments it can be about 50 to about 10,000, in some embodiments it can be about 60 to about 9,000, and in some embodiments it can be about 80 to about 8,000. Particularly suitable examples of ceramic materials with high dielectric constants are those designated as NPO(COG) (up to about 100), X7R (about 3,000 to about 7,000), X7S, Z5U, and / or Y5V, based on the standard classification established by the Electronic Industries Alliance (EIA). Such materials may include perovskites, for example, barium titanate ceramic materials (e.g., barium titanate, barium strontium titanate, barium calcium titanate, barium zirconate titanate, barium strontium zirconate titanate, barium calcium zirconate, etc.), lead titanate ceramic materials (e.g., lead zirconate titanate, lead lanthanum zirconate titanate), and sodium bismuth titanate. In one particular embodiment, for example, the chemical formula Ba x Sr 1-x Barium strontium titanate ("BSTO") of TiO3 can be used, where x is from 0 to 1, and in some embodiments from about 0.15 to about 0.65, and in some embodiments from about 0.25 to about 0.6. Other suitable barium titanate ceramic materials include, for example, Ba x Ca 1-x TiO3 (where x is about 0.2 to about 0.8, and in some embodiments about 0.4 to about 0.6); and barium calcium zirconium titanate (BaCaZrTiO3); A[B1 1 / 3 B2 2 / 3 ]O3 material (where A is Ba x Sr 1-xwhere x can be a value from 0 to 1, and B1 is Mg y Zn 1-y where y can be a value from 0 to 1, and B2 is Ta z Nb 1-z and so on can be included. Other suitable ceramic materials can include, for example, Pb x Zr 1-x TiO3 ("PZT") (where x is in the range of about 0.05 to about 0.4); lead lanthanum zirconium titanate ("PLZT"); and lead titanate (PbTiO3) and so on can be included.

[0061] The internal electrode layer can be formed from any of a variety of different metals as known in the art. The internal electrode layer can be made from a metal such as a conductive metal. The materials can include noble metals (such as silver, gold, palladium, platinum, etc.), base metals (such as copper, tin, nickel, chromium, titanium, tungsten, etc.), and various combinations thereof. Sputtered titanium / tungsten (Ti / W) alloys, as well as sputtered layers of chromium, nickel, and gold respectively, may also be suitable. In one particular embodiment, the internal electrode layer can include nickel or an alloy thereof. Similarly, the external terminal can be formed from any of a variety of different metals as known in the art. The external terminal can be made from a metal such as a conductive metal. The materials can include noble metals (such as silver, gold, palladium, platinum, etc.), base metals (such as copper, tin, nickel, chromium, titanium, tungsten, etc.), and various combinations thereof. In one particular embodiment, the external terminal can include copper or an alloy thereof. The external terminal can have an average thickness of about 100 μm or less, in some embodiments about 1 μm to about 70 μm, and in some embodiments about 5 μm to about 50 μm.

[0062] External terminals can be formed using any method commonly known in the art. External terminals can be formed using techniques such as sputtering, painting, printing, electroless plating or fine copper termination (FCT), electroplating, plasma deposition, propellant spray / airbrushing, etc. External terminals can be formed such that they are thin-film platings of metal. Such thin-film platings can be formed by depositing a conductive material (e.g., a conductive metal) onto an exposed portion of an internal electrode layer. For example, the leading edge of the internal electrode layer can be exposed so as to allow for the formation of a plated terminal. Plated terminals can be formed by techniques known in the art (e.g., electroless plating, electroplating, or a combination thereof). When multiple layers are used to form an external terminal, the external terminal can include electroplated and electroless plating layers. For example, electroless plating can be used first to deposit an initial layer of material. The plating technique can then be switched to an electrochemical plating system, which can allow for faster accumulation of the material. When forming terminals plated by any of the plating methods, the leading edges of the lead tabs of the internal electrode layer exposed from the main body of the capacitor are exposed to the plating solution. By exposure, in one embodiment, the capacitor can be immersed in the plating solution.

[0063] The plating solution used in the plating process may contain conductive materials (e.g., conductive metals). For example, the plating solution may be a nickel sulfamate bath solution or other nickel solution, such that the plated layer and external terminals contain nickel. Alternatively, the plating solution may be a copper acid bath or other suitable copper solution, such that the plated layer and external terminals contain copper. Additionally, it should be understood that the plating solution may contain other additives as are commonly known in the art. For example, the additives may include other organic additives and media that can assist the plating process. Additionally, additives may be used to use the plating solution at a desired pH level. In one embodiment, a resistance-reducing additive may be used in the solution to assist in complete plating, as well as in the bonding of the plating material to the exposed leading edges of the lead tabs of the capacitor and internal electrode layers. The capacitor may be exposed, submerged, or immersed in the plating solution for a predetermined amount of time. The exposure time is not necessarily limited, but can be a sufficient amount of time to allow sufficient plating material to deposit to form the plated terminals. In this regard, the time should be sufficient to allow the formation of a continuous connection between the desired exposed adjacent leading edges of the lead tabs of a given polarity in each internal electrode layer within the set of alternating dielectric and internal electrode layers.

[0064] The difference between electrolytic plating and electroless plating is that electrolytic plating uses an electrical bias (for example, by using an external power supply). Electrolytic plating solutions typically have a high current density range, e.g., 10 to 15 amp / ft. 2It may be exposed to (rated 9.4 volts). The connection can be formed by a negative connection to the capacitor, which requires the formation of plated terminals, and a positive connection to a solid material in the same plating solution (e.g., Cu in a Cu plating solution). That is, the capacitor is biased to a polarity opposite to the polarity of the plating solution. Using such a method, the conductive material of the plating solution is attracted to the metal of the exposed leading edge of the lead tab of the internal electrode layer.

[0065] Various pretreatment steps can be used before immersing or exposing the capacitor in a plating solution. Such steps can be performed for a variety of purposes, including catalytically accelerating, and / or improving the adhesion of the plating material to the leading edge of the lead tab. Additionally, an initial cleaning step can be used before plating or any other pretreatment step. This step can be used to remove any oxide accumulations that may form on the exposed lead tab of the internal electrode layer. The cleaning step may be particularly useful in assisting the removal of any nickel oxide accumulations when the internal electrodes or other conductive elements are formed from nickel. Component cleaning can be achieved by complete immersion in a pre-cleaning tank (e.g., one containing an acid cleaner). In one embodiment, the exposure can be over a predetermined time (e.g., on the order of about 10 minutes). Alternatively, cleaning can be achieved by a chemical polishing or hyper-rising step.

[0066] In addition, to promote the deposition of conductive material, a step may be performed to activate the exposed metal leading edge of the lead tab of the internal electrode layer. Activation can be achieved by immersion in a palladium salt, a photo-patterned palladium organometallic precursor (via a mask or laser), a screen-printed or inkjet-deposited palladium compound, or an electrophoretic palladium deposit. It should be recognized that the palladium-based activation is disclosed hereby merely as an example of an activation solution, which often works well for activating the exposed tab portion formed from nickel or its alloys. However, it should be understood that other activation solutions may be used and are therefore not necessarily limited. Furthermore, instead of or in addition to the activation step described above, an activation dopant may be introduced into the conductive material when forming the internal electrode layer of the capacitor. For example, when the internal electrode layer contains nickel and the activation dopant contains palladium, the palladium dopant may be introduced into the nickel ink or composition forming the internal electrode layer. Doing so makes it possible to eliminate the palladium activation step. It should be further recognized that some of the activation methods described above, such as those using organometallic precursors, are also useful for co-deposition of glass-forming agents to improve adhesion to the generally ceramic body of the capacitor. When the activation step is carried out as described above, traces of the activating material may often remain on the exposed conductive parts before and after the terminal plating. In addition, post-treatment steps after plating may be used as desired or as needed. Such steps may be performed for a variety of purposes, including strengthening and / or improving the adhesion of the materials. For example, a heating (or annealing) step may be used after the plating step has been carried out. Such heating may be carried out via baking, laser subjection, UV exposure, microwave exposure, arc welding, etc.

[0067] Therefore, as described above, the external terminals used in the capacitor may include at least one plated layer. In one embodiment, the external terminal may include only one plated layer. However, it should be understood that the external terminal may include multiple plated layers. For example, the external terminal may include a first plated layer and a second plated layer. In addition, the external terminal may include a third plated layer. Furthermore, the materials of these plated layers may be any of those described above, or any materials commonly known in the art. For example, one plated layer (e.g., the first plated layer) may include copper or an alloy thereof. Another plated layer (e.g., the second plated layer) may include nickel or an alloy thereof. Alternatively, another plated layer (e.g., the second plated layer) may include copper or an alloy thereof. Another plated layer (e.g., the third plated layer) may include tin, lead, gold, or a combination thereof (e.g., an alloy). Alternatively, the initial plating layer may contain nickel, followed by a tin or gold plating layer. In another embodiment, an initial copper plating layer may be formed, followed by a nickel layer.

[0068] In one embodiment, the initial plating layer or first plating layer can be a conductive metal (e.g., copper). This area can then be covered by a second layer containing a resistive polymer material for sealing. The area can then be polished to selectively remove the resistive polymer material and then re-plated by a third layer containing a conductive metallic material (e.g., copper). The aforementioned second layer above the initial plating layer can correspond to a solder barrier layer (e.g., a nickel-solder barrier layer). In some embodiments, the aforementioned layer can be formed by electroplating an additional layer of metal (e.g., nickel or copper) on top of an initial electroless or electroplated layer (e.g., plated copper). Other exemplary materials for the layer (the aforementioned solder barrier layer) include nickel-phosphorus, gold, and silver. The third layer above the aforementioned solder barrier layer can correspond in some embodiments to a conductive layer (e.g., plated Ni, Ni / Cr, Ag, Pd, Sn, Pb / Sn, or other suitable plated solder). In addition, a layer of metal plating may be formed, followed by an electroplating step to provide a resistant alloy or a higher-resistance metal alloy coating (e.g., electroless Ni-P alloy) on top of such metal plating. However, it should be understood that any metal coating is possible, as will be understood by those skilled in the art from the full disclosure herein. It should be recognized that any of the steps described above can occur as a bulk process, such as barrel plating, fluidized bed plating, and / or flow-through plating termination processes (all of which are commonly known in the art). Such bulk processes allow multiple components to be processed at once, providing an efficient and rapid termination process. This is a particular advantage over conventional termination methods (e.g., printing of thick film terminations, which require processing of individual components).

[0069] IV. Semiconductor Package Assembly As is known in the art, semiconductor package assemblies can be electrically connected to and / or mounted on a circuit board (e.g., a printed circuit board) to form a microelectronic assembly. Within the package assembly itself, the semiconductor structures, package substrate, and ceramic capacitors can generally be arranged in various different configurations for connection to the circuit board. Referring to Figure 1, for example, one embodiment of a semiconductor package assembly 600 is shown, which includes semiconductor structures 610, 620, and 630 electrically connected to an interposer 650, and a package substrate 680 electrically connected to the interposer 650. The semiconductor structures can be any type of structure as described above. In one embodiment, for example, structures 610 and 630 can be high-bandwidth memory structures, field-programmable gate arrays, etc. The semiconductor structures 610, 620, and 630 can be electrically connected to the interposer 650 via first-level coupling components 611, 621, and 631, respectively, as shown. In the illustrated embodiment, the connecting component 621 can be a solder ball or bump, while the connecting components 611 and 631 can be a conductive adhesive or underfill material. Although not always required, an overmolding material 760 can also be used. The overmolding material can be an insulating material, such as those described above (e.g., epoxy resin material). Similarly, the interposer 650 includes conductive paths 652 formed in an insulating dielectric material 654. The conductive paths 652 allow for the electrical connection of the interposer 650 to the package substrate 680 through a second level connecting component 656 (e.g., a solder ball or bump). The package substrate 680 then includes conductive paths 682 (e.g., vias) in an insulating dielectric material 684.The conductive path 682 allows for the electrical connection of the package assembly 600 to the circuit board 800 (e.g., a printed circuit board) (via the package substrate 680) through a third level connecting component 704 (e.g., a solder ball).

[0070] In particular, the ceramic capacitor 10 (see, for example, Figures 3A-3B) is also electrically connected to at least one of the semiconductor structures 610, 620, and / or 630, as well as to the package substrate 680. More specifically, in the illustrated embodiment, the ceramic capacitor 10 is positioned between at least a portion of the package interposer 650 and the package substrate 680. Naturally, the ceramic capacitor 10 can also be positioned at various other locations within the package, such as between the semiconductor structures 610, 620, and / or 630 and the interposer 650. Although only one capacitor is shown, it should be understood that, naturally, multiple ceramic capacitors can be used. The external terminals of the ceramic capacitor can be electrically connected to the current paths of the interposer and the package substrate, respectively, and can be electrically connected to them using any method commonly known in the art. For example, instead of a solder ball 656, the ceramic capacitor 10 may be directly electrically connected to the package substrate 680 and the interposer 650, or at least a smaller connecting component 702 (e.g., a solder bump) than the connecting component 656 may be used. The capacitor 10 can generally allow AC signals to pass through or be transmitted while blocking DC signals. That is, it can be used to block low-frequency signals and transmit high-frequency signals. In addition, by arranging the capacitor 10 in the shown manner, it is possible to eliminate certain conductive paths directly above the capacitor, thereby further improving performance. The use of ceramic capacitors in such a manner can also allow for a significant reduction in inductance. In particular, minimizing the distance or path for ground connection can help reduce inductance.For example, the use of ceramic capacitors can result in inductances of less than approximately 1 nanohenry, and in some embodiments, inductances of approximately 25 femtohenry to approximately 900 picohrenry, in some embodiments, from approximately 100 femtohenry to approximately 500 picohrenry, and in some embodiments, from approximately 250 femtohenry to approximately 100 picohrenry. Furthermore, ceramic capacitors can exhibit low equivalent series resistances, such as less than approximately 100 mOhm, in some embodiments, from approximately 0.01 mOhm to approximately 50 mOhm, in some embodiments, from approximately 0.1 mOhm to approximately 40 mOhm, and in some embodiments, from approximately 0.5 mOhm to approximately 30 mOhm. Low inductance and / or equivalent series resistance can be achieved while still exhibiting tuned capacitance values, such as approximately 1 pF to approximately 1,000 μF, in some embodiments approximately 500 pF to approximately 500 μF, and in some embodiments approximately 1 μF to approximately 100 μF.

[0071] In the embodiment shown in Figure 1, the interposer 650 is generally considered a “passive” interposer in that it does not contain any integrated electronic components. However, it should be understood that an “active” interposer can also be appropriately used in the semiconductor package assembly of the present invention. Referring to Figure 2, one embodiment of a semiconductor package assembly 800 including an active interposer 802 is shown. In this embodiment, the interposer 802 is electrically connected to the package substrate 832, and a semiconductor structure 310 (e.g., a coprocessor) is electrically connected to the interposer 802. The semiconductor structure 310 may include an active layer 392 and a bulk semiconductor layer 390 (which may be referred to herein as an inactive layer 390). The active layer 392 may include circuit elements and register files 394, which can act as a central on-die memory for the structure 310. The active interposer 802 may also include an active layer 806 and a bulk semiconductor layer 804 (which may be referred to as an inactive layer 804). The active layer 806 may include a plurality of level 1 (L1) memory elements 808 formed on the active side, which can be used as a memory cache for storing configuration bitstreams for constituting logical sectors in the structure 310. The active interposer 802 may be electrically connected to the package substrate 832 through a linking component 822 (e.g., a solder bump or ball), and the inactive layer 804 may include a through-silicon via (TSV) 810, which can connect components such as the L1 memory elements 808 in the active layer 806 to the linking component 822. The active layer 806 may face the active layer 392 of the semiconductor structure 310 and may be electrically connected to components in the active layer 392 through a linking component 820 (e.g., a solder bump).

[0072] If desired, additional semiconductor structures 812 (e.g., auxiliary chips) can be electrically connected directly to the substrate 832. Structures 812 may include an active layer 816 and a bulk semiconductor layer 814 (optionally referred to as a deactivated layer 814). The active layer 816 may include a level 2 (L2) memory element 809 formed on the active side, which can be used as a memory cache for storing configuration bitstreams. For example, a configuration bitstream stored in an L1 memory element 808 on the interposer 802 can be transferred to the L2 memory element 809 to make space on the L1 memory element 808 for a new incoming configuration bitstream (e.g., received from a host processor in the L1 memory element 808). The active layer 816 can face the package substrate 832 and be electrically connected to it through connecting components 822 and 824 (e.g., solder balls or bumps). Furthermore, the bridge 826 can be used to connect the semiconductor structure 812 to the interposer 802. The bridge 826 may include an interconnection portion 828 formed in a silicon substrate embedded in the package substrate 832. The interconnection portion 828 can electrically connect a portion of the connecting component 824 connected to the semiconductor structure 812 to a portion of the connecting component 824 connected to the interposer 802. Also, the heat sink 830 can be installed in contact with the semiconductor structures 310 and 812, as is known in the art.

[0073] As shown, the ceramic capacitor 20 (see, for example, Figures 5A-5B) is also electrically connected to the semiconductor structure 310 and the package substrate 832 via the interposer 802. More specifically, in the illustrated embodiment, the ceramic capacitor 20 is positioned between at least a portion of the interposer 802 and the package substrate 832. Vias 810 allow the ceramic capacitor 20 to be electrically connected to the semiconductor structure 310 via the coupling component 820. The ceramic capacitor 20 can also be electrically connected to the L1 memory element 808 in the active layer 806. The external terminals of the ceramic capacitor can be electrically connected to the current paths of the interposer and the package substrate, respectively, and can be electrically connected to them using any method commonly known in the art. For example, instead of solder balls 824 or 822, the ceramic capacitor 20 may be directly electrically connected to the package substrate 832 and the interposer 802, or at least a smaller connecting component 722 (e.g., a solder bump) than the connecting component 824 or 822 may be used.

[0074] These and other modifications and variations of the present invention can be practiced by those skilled in the art without departing from the spirit and scope of the invention. In addition, it should be understood that the aspects of the various embodiments can be interchanged, both in whole and in part. Furthermore, those skilled in the art will recognize that the foregoing description is merely illustrative and not intended to limit the invention, and that the invention is further described in such appended claims. [Explanation of Symbols]

[0075] 10 Ceramic Capacitors 12 First external terminal 14. Second external terminal 20 Capacitors 22a First external terminal 22b First external terminal 24a Second external terminal 24b Second external terminal 30 Capacitors 32 External terminals 32a First external terminal 32b First external terminal 34 External terminals 34a Second external terminal 34b Second external terminal 105 First internal electrode layer, alternating electrode layers, non-contact hole, gap 105a Side edge 105b Side edge 105c Upper edge 105d bottom edge 110 Internal electrode layer 110a Set of internal electrode layers 110b Set of internal electrode layers 115 Second set of internal electrode layers, second internal electrode layer, alternating electrode layers, non-contact hole, gap 120 First lead tab 121 Lateral edge 122 Lateral edge 123 Front edge 125 Gap 130 First lead tab 131 Lateral edge 132 Lateral edge 133 Front edge 135 Main body, gap 140 First lead tab 141 Lateral edge 142 Lateral edge 143 Front edge 145 Main body 150 First lead tab 151 Lateral edge 152 Lateral edge 153 Front edge 205 First internal electrode layer, first active electrode layer 205a Side edge 205b Side edge 205c Upper edge 205d bottom edge 210 Internal electrode layer 210a Set of internal electrode layers 210b Set of internal electrode layers 210c internal electrode layer set 210d Internal electrode layer set 215 Second internal electrode layer, second active electrode layer, active electrode 220 First lead tab 220a~b Lead Tabs 221a Lateral edge 222a Lateral edge 223a~b Leading edge 225 First conductive via 230 First lead tab 230a~b Lead Tabs 231a Lateral edge 232a Lateral edge 233a~b Front edge 235 Main body section, upper surface 240 First lead tab 240a~b Lead Tabs 241a Lateral edge 242a Lateral edge 243a~b Front edge 245 Main body, lower surface 250a~b Lead Tabs 250 First lead tab 251a Lateral edge 252a Lateral edge 253a~b Leading edge 255 First Shield Area 265 Second Shield Area 275 Shield electrode layer 285 Second conductive via 295 Second anchor electrode, second anchor tab 305 First anchor electrode 310 Semiconductor Structures 390 Bulk semiconductor layer, inactive layer 392 Active layer 394 Register File 600 Semiconductor Package Assemblies 610 Semiconductor Structures 611 First-level linked components 621 First-level linked components 620 Semiconductor Structures 630 Semiconductor Structures 631 First-level linked components 650 Interposer 652 Conductive Path 654 Insulating Dielectric Materials 656 Second-level linked components 680 Package Substrates 682 Conductive Path 684 Insulating Dielectric Materials 702 Linked Components 704 Third-level linked components 722 Linked Components 760 Overmolding Material 800 Circuit boards, semiconductor package assemblies 802 Active Interposer, Interposer 804 Bulk semiconductor layer, inactive layer 806 Active layer 808 Level 1 (L1) Memory Element 809 Level 2 (L2) Memory Element 810 Through-Silicon Via (TSV) 812 Semiconductor Structures 814 Bulk semiconductor layer, inactive layer 816 Active layer 820 Linked Components 822 Linking components, solder balls 824 Linking Components, Solder Balls 826 Bridge 828 Interconnection section 830 Heatsink 832 Package substrate 1350 Void BW External terminal width BL External terminal length BLA External Terminal Length BLB External terminal length L Length O Offset T thickness t Distance between sets Distance between t1 sets Distance between t2 sets Distance between t3 sets W width

Claims

1. A semiconductor package assembly, wherein the semiconductor package assembly is Semiconductor structures and A package substrate electrically connected to the aforementioned semiconductor structure, A ceramic capacitor having a first surface and a second surface on the opposite side, wherein the ceramic capacitor includes alternating dielectric layers and internal electrode layers, the internal electrode layers include a first internal electrode layer and a second internal electrode layer, the capacitor further includes a first external terminal, a second external terminal, a third external terminal and a fourth external terminal, the first external terminal being electrically connected to the first internal electrode layer and disposed on the first surface of the capacitor, the second external terminal being electrically connected to the first internal electrode layer and disposed on the second surface of the capacitor, the third external terminal being electrically connected to the second internal electrode layer and disposed on the first surface of the capacitor, the fourth external terminal being electrically connected to the second internal electrode layer and disposed on the second surface of the capacitor, the first external terminal and the third external terminal being electrically connected to the semiconductor structure, and the second external terminal and the fourth external terminal being electrically connected to the package substrate. A semiconductor package assembly, including the above.

2. The semiconductor package assembly according to claim 1, wherein the semiconductor structure is an integrated circuit device.

3. The semiconductor package assembly according to claim 2, wherein the integrated circuit device includes a memory device, a logic device, a processor device, or a combination thereof.

4. The semiconductor package assembly according to claim 1, wherein the assembly includes a plurality of semiconductor structures.

5. The semiconductor package assembly according to claim 4, wherein the semiconductor structures are arranged in an array.

6. The semiconductor package assembly according to claim 4, wherein the semiconductor structures are stacked.

7. The semiconductor package assembly according to claim 1, wherein the package substrate includes an insulating material, one or more conductive paths are formed through the insulating material, and the conductive paths are electrically connected to the second and fourth external terminals of the ceramic capacitor.

8. The semiconductor package assembly according to claim 7, wherein the insulating material includes an organic material, an inorganic material, a semiconductor material, or a combination thereof.

9. The semiconductor package assembly according to claim 1, further comprising an interposer electrically connected to the semiconductor structure and the package substrate, wherein the first external terminal and the third external terminal are electrically connected to the interposer.

10. The semiconductor package assembly according to claim 9, wherein the interposer includes an insulating material, through which one or more conductive paths are formed, and the conductive paths are electrically connected to the first and third external terminals of the ceramic capacitor.

11. The semiconductor package assembly according to claim 10, wherein the insulating material includes an organic material, an inorganic material, a semiconductor material, or a combination thereof.

12. The semiconductor package assembly according to claim 9, wherein the electronic component is embedded in the interposer.

13. The semiconductor package assembly according to claim 12, wherein the electronic components include a capacitor, resistor, inductor, fuse, diode, transformer, sensor, electrostatic discharge device, memory device, radio frequency device, power amplifier, power management device, antenna, micro electromechanical system, or a combination thereof.

14. The semiconductor package assembly according to claim 12, wherein the ceramic capacitor is embedded in the interposer.

15. The semiconductor package assembly according to claim 1, wherein the first and second external terminals have positive polarity, and the third and fourth external terminals have negative polarity.

16. The semiconductor package assembly according to claim 1, wherein at least one of the first, second, third, or fourth external terminals extends to the end surface of the capacitor.

17. The semiconductor package assembly according to claim 1, wherein the first, second, third, and fourth external terminals do not extend to the end surface of the capacitor.

18. The semiconductor package assembly according to claim 1, wherein the ceramic capacitor includes only the first external terminal and the third external terminal on the first surface, and includes only the second external terminal and the fourth external terminal on the second surface.

19. The semiconductor package assembly according to claim 1, wherein the capacitor includes at least four external terminals on the first surface and at least four external terminals on the second surface.

20. The semiconductor package assembly according to claim 19, wherein the external terminals are arranged in a linear manner on the first surface and the second surface.

21. The semiconductor package assembly according to claim 19, wherein the external terminals are arranged in a multidimensional array on the first surface and the second surface.

22. The semiconductor package assembly according to claim 1, wherein the first and second internal electrode layers are arranged vertically.

23. The semiconductor package assembly according to claim 22, wherein the first internal electrode layer includes a lead tab extending to the first surface for contact with the first external terminal and a lead tab extending to the second surface for contact with the third external terminal, and further, the second internal electrode layer includes a lead tab extending to the first surface for contact with the second external terminal and a lead tab extending to the second surface for contact with the fourth external terminal.

24. The semiconductor package assembly according to claim 1, wherein the first and second internal electrode layers are arranged horizontally.

25. The semiconductor package assembly according to claim 24, wherein the first and second internal electrode layers are connected to the first, second, third, and fourth external terminals through conductive vias.

26. The semiconductor package assembly according to claim 1, wherein the dielectric layer of the ceramic capacitor comprises a ceramic material.

27. The semiconductor package assembly according to claim 26, wherein the ceramic material is a barium titanate ceramic material.

28. The semiconductor package assembly according to claim 1, wherein the first, second, third, and fourth external terminals each include at least one plated layer.

29. The semiconductor package assembly according to claim 28, wherein the plated layer is formed by a process including electroless plating, electrolytic plating, or a combination thereof.

30. The semiconductor package assembly according to claim 1, further comprising a circuit board electrically connected to the package substrate via a connecting component.

31. The semiconductor package assembly according to claim 30, wherein the connecting component includes solder.

32. The semiconductor package assembly according to claim 1, wherein the second and fourth external terminals of the ceramic capacitor are electrically connected to the package substrate via a connecting component.

33. A microelectronic assembly comprising a semiconductor package assembly according to claim 1 and a circuit board, wherein the package board is electrically connected to the circuit board.

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