Surface modifier for improving epitaxial nucleation and wettability

Abstract

A method for forming a semiconductor device is provided. In some packaging configurations, the method comprises positioning a substrate in a processing chamber, the substrate having an exposed amorphous surface and an exposed crystalline surface. The method further comprises heating the processing chamber to a deposition temperature. The method further comprises injecting a pretreatment gas into the processing chamber. The pretreatment gas contains molecules that act to reduce the interfacial energy between the exposed amorphous surface and the exposed crystalline surface. The method further comprises injecting a deposition gas into the processing chamber to selectively grow an n-type doped epitaxial silicon layer on the exposed crystalline surface.

Description

[Technical Field]

[0001]

[0001] Embodiments of the present disclosure generally relate to methods for forming semiconductor devices. More specifically, the present application relates to an epitaxial deposition method for forming horizontal gate all-around (hGAA) device structures. [Background technology]

[0002]

[0002] In the electronics industry, there is a growing demand for smaller and faster electronic devices, while simultaneously being required to support more complex and sophisticated functions. Therefore, the semiconductor industry continues to pursue the production of low-cost, high-performance, and low-power integrated circuits (ICs). These goals have been achieved by reducing the dimensions of semiconductor ICs (e.g., minimum feature size), thereby improving production efficiency and lowering associated costs. However, such miniaturization has introduced complexity to the semiconductor manufacturing process. Thus, the continuous advancement of semiconductor ICs and devices requires similar advancements in semiconductor manufacturing processes and technologies.

[0003]

[0003] Recently, multi-gate devices have been introduced with the aim of improving gate control by increasing gate-channel coupling, reducing off-state current, and reducing short-channel effects (SCE). One such multi-gate device is the gate-all-around transistor (GAA). In a GAA device, since all sides of the channel region are surrounded by the gate electrode, the channel region is sufficiently depleted, the amplitude of the subthreshold current becomes steeper, and the drain-induced barrier drop (DIBL) becomes smaller, thus reducing short-channel effects.

[0004]

[0004] As transistor dimensions are miniaturized to smaller technology nodes, further improvements in GAA design and manufacturing are needed. [Overview of the project]

[0005]

[0005] Embodiments of the present disclosure relate in general to methods for forming semiconductor devices. More specifically, the present application relates to an epitaxial deposition method for forming horizontal gate all-around (hGAA) device structures.

[0006]

[0006] In at least one embodiment, a method for forming a semiconductor device is provided. The method comprises positioning a substrate in a processing chamber, the substrate having an exposed amorphous surface and an exposed crystalline surface. The method further comprises heating the processing chamber to a deposition temperature. The method further comprises injecting a pretreatment gas into the processing chamber. The pretreatment gas comprises molecules configured to reduce the interfacial energy between the exposed amorphous surface and the exposed crystalline surface. The method further comprises injecting a deposition gas into the processing chamber to selectively grow an n-type doped epitaxial silicon layer on the exposed crystalline surface.

[0007]

[0007] Embodiments may include one or more of the following: The molecule is a group V chloride. The molecule is selected from the group consisting of PCl3, AsCl3 and SbCl3. The injection of the pretreatment gas and the injection of the deposition gas overlap at least partially. The injection of the pretreatment gas is completed before the injection of the deposition gas. The injection of the pretreatment gas and the injection of the deposition gas are repeated sequentially multiple times. The method further includes exposing the substrate to a dry etching solution to remove contaminants from the surface of the substrate. The exposed amorphous surface includes silicon oxide, silicon nitride, silicon carbonitride, silicon oxycarbonite, silicon oxycarbonite, or a combination thereof. Dry etching includes exposing the substrate to H2, NF3, NH3 and plasma byproducts. Multiple exposed silicon layers are <110> It has a structure. The deposition temperature is 400°C or higher. Pretreatment gas injection is carried out at a pressure ranging from approximately 1 torr to approximately 760 torr.

[0008]

[0008] In another embodiment, a method for forming a semiconductor device is provided. This method includes positioning a substrate in a processing chamber. A multi-material layer is formed on the substrate, and this multi-material layer is made up of multiple Si 1-x Ge x The method comprises a plurality of exposed dielectric surfaces on a layer and a plurality of exposed silicon layers. The method further comprises heating a processing chamber to a deposition temperature. The method further comprises injecting a pretreatment gas into the processing chamber, the pretreatment gas comprising molecules configured to reduce the interfacial energy between the plurality of exposed dielectric surfaces and the plurality of exposed silicon layers. The method further comprises injecting a deposition gas into the processing chamber to selectively grow n-type doped epitaxial silicon layers on the exposed silicon layers.

[0009]

[0009] Embodiments may include one or more of the following: The exposed dielectric surface includes silicon oxide, silicon nitride, silicon carbonitride, silicon oxycarbonite, silicon oxycarbonite, or a combination thereof. The molecule is a group V chloride. The molecule is selected from the group consisting of PCl3, AsCl3, and SbCl3. The injection of the pretreatment gas and the injection of the deposition gas overlap at least partially.

[0010]

[0010] In yet another embodiment, a method for forming a semiconductor device is provided. This method includes positioning a substrate in a cleaning chamber, on which a multi-material layer is formed, the multi-material layer being made of multiple Si 1-x Ge x The silicon includes a layer and a plurality of dielectric surfaces arranged on the outer surface of a plurality of silicon layers, and a plurality of Si 1-x Ge xThe layers are arranged in a pattern of alternating silicon layers. The method further includes exposing the substrate to a dry etching solution to remove contaminants from the substrate surface. The method further includes positioning the substrate in a processing chamber. The method further includes heating the processing chamber to a deposition temperature. The method further includes injecting a pretreatment gas into the processing chamber, the pretreatment gas containing molecules configured to reduce the interfacial energy between the dielectric surface and the silicon surface. The method further includes injecting a deposition gas into the processing chamber to selectively grow an n-type doped epitaxial silicon layer on the exposed silicon surface.

[0011]

[0011] Embodiments may include one or more of the following: The molecule is a group V chloride. The injection of pretreatment gas and the injection of deposition gas are repeated sequentially multiple times. The exposed dielectric surface includes silicon oxide, silicon nitride, silicon carbonitride, silicon carbide, silicon oxycarbide, or a combination thereof.

[0012]

[0012] In another embodiment, a non-temporary computer-readable medium stores instructions which, when executed by a processor, cause the processor to perform the processing of the above-described apparatus and / or method.

[0013]

[0013] To enable a more detailed understanding of the above-described features of the Disclosure, a more detailed description of the Disclosure, which has been briefly summarized above, can be obtained by referring to embodiments, some of which are shown in the accompanying drawings. However, it should be noted that the accompanying drawings merely illustrate typical embodiments of the Disclosure and should not be considered to limit the scope of the Disclosure, as the Disclosure may also permit other equally valid embodiments. [Brief explanation of the drawing]

[0014] [Figure 1]

[0014] A schematic isometric view of a horizontal gate-all-around (hGAA) structure according to one embodiment of the present disclosure is shown. [Figure 2A-2C]

[0015] Schematic cross-sectional views of various stages of forming the hGAA structure of FIG. 1 according to one embodiment of the present disclosure are shown. [Figure 3]

[0016] A flowchart of a method for forming a semiconductor device according to one embodiment of the present disclosure is shown. [Figure 4]

[0017] A schematic side cross-sectional view of an exemplary processing chamber according to one embodiment of the present disclosure is shown. [Figure 5]

[0018] A schematic top view of a system for processing a substrate according to one embodiment of the present disclosure is shown.

DETAILED DESCRIPTION OF THE INVENTION

[0015]

[0019] Embodiments of the present disclosure generally relate to methods for forming semiconductor devices. More specifically, the present application relates to an epitaxial deposition method for forming a horizontal gate all-around (hGAA) device structure.

[0016]

[0020] As the feature size of transistor devices continues to shrink to achieve improved circuit density and high performance, it is necessary to improve the structure of transistor devices in order to improve electrostatic coupling and reduce adverse effects such as parasitic capacitance and off-state leakage. Examples of transistor device structures include planar structures, fin field-effect transistor (FinFET) structures, and horizontal gate all-around (hGAA) structures. The hGAA device structure includes several lattice-matched channels that are suspended in a stacked configuration and connected by source / drain regions.

[0017]

[0021] Epitaxial growth of epitaxial silicon layers forming source / drain materials on nanosheet-type architectures generally begins at the (110) sidewall silicon surface and must grow laterally outward, beyond adjacent silicon spacers. Under some process conditions, epitaxial layers are resistant to nucleation at the sidewall silicon surface and overgrowth of spacers. For example, process conditions containing excess HCl can act "overselectively" on spacers, leading to void formation if source / drain cavity filling continues. Current techniques improve the wettability and lateral overgrowth of epitaxial materials by optimizing process conditions or selecting specific silicon precursors. However, these current techniques require modification of the epitaxial process to affect the desired results. Modifying the process to accommodate nucleation and overgrowth can compromise other variables, such as selectivity, throughput, and layer structure.

[0018]

[0022] Furthermore, selective growth of epitaxial silicon layers presents challenges related to the jagged growth morphology and degree of growth of the epitaxial silicon layers. Therefore, methods are needed to improve the growth morphology and degree of growth of the epitaxial silicon layers.

[0019]

[0023] This specification describes a method for forming an epitaxial silicon layer within a semiconductor device structure, such as an hGAA device structure, which can be used as, for example, an n-channel metal oxide semiconductor (NMOS) or p-channel metal oxide semiconductor (PMOS) epitaxial silicon layer. The epitaxial silicon layer can grow on the hGAA device structure to a molded structure, such as a diamond-like top structure, and can form the source / drain region and source / drain extension region required for the hGAA semiconductor device on the substrate.

[0020]

[0024] The described method involves the use of surface modifiers to enhance epitaxial nucleation and wettability. Pre-adding surface modifiers to the growth surface can assist the initial stages of epitaxial layer nucleation and subsequent stages of dielectric wettability and overgrowth. Surface modifiers act to reduce the interfacial energy between the growing semiconductor and the dielectric surface, thereby promoting the overgrowth of spacers from the subsequent silicon channel region. Surface modifiers may include surfactant molecules. Surface modifiers can be pre-injected into the processing chamber before the introduction of the deposition gas. Surface modifiers can be sequentially pulsed together with the deposition gas. Surface modifiers that can activate dielectric surfaces for n-type epitaxial growth include Group V chlorides, t-butylarsine (TBAs), triethylantimony (TESb), triethylarsine (TEAs), plasma ammonia (NH3), plasma hydrogen (H), and plasma deuterium (D). Examples of Group V chlorides suitable for n-type epitaxial growth include phosphorus chloride, e.g., PCl3, arsenic chloride, e.g., AsCl3, and antimony chloride, e.g., SbCl3. Surface modifiers that can activate dielectric surfaces for p-type epitaxial growth include Group V chlorides, triethylgallium (TEGa), triethylindium (TEIn), triethylaluminum (TEAl), plasma ammonia (NH3), plasma hydrogen (H), and plasma deuterium (D). Examples of Group V chlorides suitable for p-type epitaxial growth include aluminum chloride, e.g., AlCl3, gallium chloride, e.g., GaCl3, and ainium chloride, e.g., InCl3.

[0021]

[0025] A surface modifier may be supplied as a pretreatment gas. The pretreatment gas may be injected into the treatment chamber and adsorbed onto both the exposed dielectric surface and the exposed silicon surface. The dielectric and silicon surfaces undergo chemical changes, resulting in the surfaces becoming more reactive to the deposited gas, thereby forming an epitaxial layer.

[0022]

[0026] The pretreatment gas is used to continuously etch the epitaxial layer during its formation, thereby improving the overgrowth of the epitaxial layer as it is deposited on the superlattice structure. The epitaxial layer is selectively formed only on the crystalline portion of the superlattice structure, rather than on oxide or amorphous surfaces. Under some process conditions, the epitaxial layer is resistant to nucleation and overgrowth of spacers on the crystalline layer. For example, process conditions containing excess HCl can act "overselectively" on spacers, leading to void formation as the filling of cavities in the epitaxial silicon layer continues. The pretreatment gas resulted in less jagged growth patterns and reduced voids in the epitaxial layer.

[0023]

[0027] This method, which improves the growth morphology of epitaxial layers, does not require modification of the epitaxial process. Modifying the process to address nucleation and overgrowth may impair other process variables, such as selectivity, throughput, and layer structure. Furthermore, pre-dosing or sequential dosing can decouple growth process parameters from concerns about nucleation and overgrowth.

[0024]

[0028] Figure 1 shows a schematic isometric view of an hGAA structure 100 according to one embodiment. The hGAA structure 100 includes a multi-material layer 105 having alternating first layers 106 and second layers 108 on which spacers 110 used in the hGAA structure 100 are formed. The hGAA structure 100 utilizes the multi-material layer 105 as nanowires (e.g., channels) between the source 114a, drain 114b and gate structure 112. The source / drain 114a, 114b are formed from epitaxial silicon layers 115a, 115b formed according to Method 300. As shown in the cross-sectional view of the multi-material layer 105 in Figure 1, the spacers 110 formed at the bottom (e.g., or end) of each of the second layers 108 help manage the interface between the second layers 108 and the source / drain 114a, 114b to reduce parasitic capacitance and maintain minimal device leakage.

[0025]

[0029] The hGAA structure 100 includes a multi-material layer 105 disposed on the uppermost surface 103 of the substrate 102, such as the top of any material layer 104 disposed on the substrate 102. In embodiments where no material layer 104 exists, the multi-material layer 105 may be formed directly on the substrate 102.

[0026]

[0030] The substrate 102 is made of crystalline silicon (e.g., Si <100> or Si <111> The materials may include silicon oxide, strained silicon, silicon germanium, germanium, doped or undoped polysilicon, silicon-on-insulator (SOI) of doped or undoped silicon wafers and patterned or unpatterned wafers, carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, or sapphire. The substrate 102 may have various dimensions (e.g., 200 mm, 300 mm, 450 mm, or other diameters) and may be a rectangular or square panel. Unless otherwise specified, the embodiments described are performed on substrates of 200 mm, 300 mm, or 450 mm in diameter.

[0027]

[0031] In one example, the arbitrary material layer 104 is an insulating material. Preferred examples of insulating materials may include silicon oxide materials, silicon nitride materials, silicon oxynitride materials, or any suitable insulating material. Alternatively, the arbitrary material layer 104 may be any suitable material, including conductive or nonconductive materials as needed. The multi-material layer 105 includes at least one pair of layers, each pair including a first layer 106 and a second layer 108. In the example shown in Figure 1, four pairs and caps for the first layer 106 are shown, each pair including a first layer 106 and a second layer 108 (alternating pairs, each pair including a first layer 106 and a second layer). An additional cap 106 for the first layer is placed at the top of the multi-material layer 105. The number of pairs may be varied based on the needs of different processes, such as whether extra first layers 106 or second layers 108 are needed or not. In one embodiment, the thickness of each first layer 106 may be between about 20 Å and about 200 Å, for example, about 50 Å, and the thickness of each second layer 108 may be between about 20 Å and about 200 Å, for example, about 50 Å. The multi-material layer 105 as a whole may have a thickness between about 10 Å and about 5000 Å, for example, between about 40 Å and about 4000 Å.

[0028]

[0032] The first layer 106 is a crystalline material layer (e.g., a single-crystal, polycrystalline, or single-crystal silicon layer). The first layer 106 is formed using an epitaxial deposition process. Alternatively, the first layer 106 is a doped silicon layer containing a p-type doped silicon layer or an n-type doped layer. Suitable p-type dopants include B dopant, Al dopant, Ga dopant, In dopant, etc. Suitable n-type dopants include N dopant, P dopant, As dopant, Sb dopant, etc. In yet another example, the first layer 106 is a Group III-V material such as a GaAs layer.

[0029]

[0033] The second layer 108 is an amorphous material layer. In some embodiments, the second layer 108 is a Ge-containing layer, such as a SiGe layer, a Ge layer, or another preferred layer. Alternatively, the second layer 108 is a doped silicon layer, including a p-type doped silicon layer or an n-type doped layer. In yet another example, the second layer 108 is a Group III-V material, such as a GaAs layer. In yet another example, the first layer 106 is a silicon layer, and the second layer 108 is a metallic material having a coating of a high dielectric constant material on its outer surface. Preferred examples of high dielectric constant materials include, among others, hafnium dioxide (HfO2), zirconium dioxide (ZrO2), hafnium silicate oxide (HfSiO2), hafnium aluminum oxide (HfAlO), zirconium silicate oxide (ZrSiO2), tantalum dioxide (TaO2), aluminum oxide, aluminum-doped hafnium dioxide, bismuth strontium titanium (BST), and platinum zirconium titanium (PZT). In a particular embodiment, the coating layer is a hafnium dioxide (HfO2) layer. In some embodiments, the second layer 108 is made of the same material as the gate structure 112 and forms a wrap-around gate around the first layer 106.

[0030]

[0034] Each of the spacers 110 is formed adjacent to the edge of the second layer 108 and may be considered part of the second layer 108. The spacers 110 are dielectric spacers, voids, or a combination of dielectric spacers and voids. The spacers 110 can be any known shape. In some embodiments, the spacers may be crescent-shaped, triangular, square, rectangular, irregular, etc. The spacers 110 can be formed by etching away each portion of the second layer 108 using an etching precursor to form recesses at each edge of the amorphous layer of the second layer. The spacers 110 are formed in recesses adjacent to each of the second layer 108. A liner layer (not shown) may be further deposited in the recesses before the deposition of the spacers 110. The spacers 110 are formed from a dielectric material and separate each of the nanowires or nanosheets formed as the first layer 106. In some embodiments, the spacer 110 is selected to be a silicon-containing material, such as a low dielectric constant material, that can reduce parasitic capacitance between the gate and source / drain 114a, 114b in the hGAA nanowire structure. The silicon-containing material or low dielectric constant material may be silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon nitride, doped silicon layer, or other suitable materials such as Black Diamond® material available from Applied Materials.

[0031]

[0035] In one embodiment, the spacer 110 is a low dielectric constant material (e.g., dielectric constant less than 4) or a silicon oxide / silicon nitride / silicon carbide-containing material. In yet another embodiment, the spacer 110 is a void.

[0032]

[0036] The gate structure 112 is positioned on and around the multi-material layer 105. According to one embodiment, the gate structure 112 includes a gate electrode layer and may further include a gate dielectric layer, a gate spacer, and a mask layer. The gate electrode layer of the gate structure 112 includes a polysilicon layer or a metal layer capped with a polysilicon layer. The gate electrode layer may include a metal nitride (titanium nitride (TiN), tantalum nitride (TaN), or molybdenum nitride (MoN)).x ) etc.), metal carbides (such as tantalum carbide (TaC) or hafnium carbide (HfC)), metal carbonitrides (such as TaCN), metal oxides (such as molybdenum oxide (MoO x ) etc.), metal oxynitrides (such as molybdenum oxynitride (MoO x N y ) etc.), metal silicides (such as nickel silicide), or combinations thereof may be included. The gate electrode layer is disposed on the top and around the multi-material layer 105.

[0033]

[0037] The gate dielectric layer may optionally be disposed under the gate electrode layer and under the multi-material layer 105. Any gate dielectric layer can include silicon oxide (SiO2), which can be formed by thermal oxidation of one or more of the first layer 106 and / or the second layer 108, or by any suitable deposition process. Suitable materials for forming the gate dielectric layer include silicon oxide, silicon nitride, oxynitride, metal oxides (such as hafnium oxide (HfO2), hafnium zirconium oxide (HfZrO x )、hafnium silicon oxide (HfSiO2), hafnium titanium oxide (HfTiO x )、hafnium aluminum oxide (HfAlO x ) etc.), as well as combinations thereof and multi-material layers are included. Gate spacers are formed on the sidewalls of the gate electrode layer. Each gate spacer includes a nitride portion and / or an oxide portion. A mask layer is formed on the top of the gate electrode layer, and the mask layer may include silicon nitride.

[0034]

[0038] The composition and formation of the epitaxial silicon layers 115a, 115b that form the source / drains 114a, 114b on the hGAA structure 100 will be described.

[0035]

[0039] Figures 2A-2C are cross-sectional views of a portion of a GAA structure corresponding to various stages of Method 300. Figure 3 is a flow chart of Method 300 for processing a substrate according to one embodiment. Method 300 can be used to form nanowire structures and epitaxial silicon layers for horizontal gate-all-around (hGAA) semiconductor device structures on a substrate having a desired material. Referring to Figures 2A-2C, cross-sectional views of gate-all-around structures at various stages of manufacturing are provided to illustrate the method of Figure 3. Although Figures 2A-2C are described in relation to Method 300, it will be understood that the structures disclosed in Figures 2A-2C are not limited to Method 300, but rather can stand on their own as structures independent of Method 300. Similarly, although Method 300 is described in relation to Figures 2A-2C, it will be understood that Method 300 is not limited to the structures disclosed in Figures 2A-2C, but can stand on their own as structures independent of Figures 2A-2C.

[0036]

[0040] Figures 2A-2C show schematic cross-sectional views of the formation of the hGAA structure of Figure 1 according to one embodiment. The hGAA structure 100 is formed using the method 300 of Figure 3. The described hGAA structure 100 is an n-channel metal oxide semiconductor (NMOS) device. Therefore, the dopants in the hGAA structure 100 are n-type dopants such as phosphorus, arsenic, antimony, or any combination thereof. According to one embodiment, the dopant contains phosphorus (P).

[0037]

[0041] The source / drain layers 114a and 114b are formed from epitaxial silicon layers 115a and 115b. The epitaxial silicon layers 115a and 115b may be n-type doped epitaxial silicon layers. The epitaxial silicon layers 115a and 115b may be formed from silicon-containing materials, doped silicon materials, composite silicon materials, or silicon-free materials. For example, the epitaxial silicon layers 115a and 115b may be silicon, phosphorus-doped silicon, silicon-germanium material, germanium, or other similar materials.

[0038]

[0042] The multi-material layer 105 and gate structure 112 described with respect to Figure 2A are formed on the substrate 102 and an arbitrary material layer 104. Before starting method 300, the hGAA structure 100 is similar to the structure in Figure 2A. The combination of the multi-material layer 105 and the gate structure 112 is sometimes described as a film laminate. The multi-material layer 105 is formed using multiple deposition processes to form multiple alternating first layers 106 and second layers 108. A portion of the second layer 108 is etched back to form a spacer 110.

[0039]

[0043] The gate structure 112 is formed around the multi-material layer 105. In some embodiments, the gate electrode layer of the gate structure 112 is made of a material similar to the material of each of the second layers 108 within the multi-material layer 105. The gate structure 112 and the second layers 108 form a wrap-around gate around each of the first layers 106. The first layers 106 act as nanowires or nanosheets placed within the wrap-around gate. After the formation of the epitaxial silicon layers 115a, 115b, which form the source / drain 114a, 114b, the first layers 106 act as channels between the epitaxial silicon layers.

[0040]

[0044] After the formation of the film stack, as shown in Figure 3, epitaxial silicon layers 115a and 115b, which form the source / drain 114a and 114b, are formed during method 300.

[0041]

[0045] In one embodiment, method 300 includes step 310, which includes exposing the substrate to a remote plasma dry etching process. In one embodiment, step 310 may be a remote plasma-assisted dry etching process that includes simultaneous exposure of the substrate to H2, NF3, and NH3 plasma byproducts. Remote plasma excitation of hydrogen and fluorine species enables substrate processing without plasma damage. The etching is generally conformal and selective with respect to the silicon oxide layer, but does not readily etch silicon whether it is amorphous, crystalline, or polycrystalline. In one embodiment, the remote plasma dry etching process of step 310 is a SiCoNi® etching process, which can be carried out in a SiCoNi chamber available from Applied Materials, Inc., Santa Clara, California. Step 310 may be carried out in a pre-cleaning chamber, for example, a cleaning chamber 516 as shown in Figure 5.

[0042]

[0046] In step 320, method 300 further includes loading a substrate into a processing chamber. The processing chamber may be an epitaxial deposition chamber, for example, a processing chamber 400 as shown in Figure 4. The processing chamber 400 may be positioned on a cluster tool, for example, a cluster tool 501, as at least one of a plurality of processing chambers 502, 503, 516, 518, as shown in Figure 5.

[0043]

[0047] In step 330, method 300 further includes bringing the processing chamber to a deposition temperature. In one embodiment, the deposition temperature may be in the range of 200°C to 800°C. In another embodiment, the deposition temperature may be in the range of 400°C to 800°C. In yet another embodiment, the deposition temperature may be in the range of 600°C to 700°C. In yet another embodiment, the deposition temperature is 400°C or higher. The pressure in the processing chamber may be adjusted so that the pressure in the reaction area is in the range of about 1 torr to about 760 torr, or about 1 torr to about 600 torr, or about 100 torr to about 500 torr, or about 200 torr to about 400 torr.

[0044]

[0048] In step 340, method 300 further includes injecting a pretreatment gas into a processing chamber and allowing it to adsorb onto the exposed dielectric surface (e.g., an amorphous surface) and the exposed Si surface (e.g., a crystalline surface). In another embodiment, step 340 includes injecting a pretreatment gas into a processing chamber and allowing it to adsorb onto the exposed amorphous surface and the exposed crystalline surface. The pretreatment gas can be used for either n-type epitaxial growth or p-type epitaxial growth. The pretreatment gas contains molecules or surface modifiers configured to reduce the interfacial energy between the exposed dielectric surface and the exposed silicon surface, thereby promoting overgrowth of the dielectric surface from the silicon surface during step 350. The molecules or surface modifiers may act as etching agents on the exposed surfaces. In some embodiments, for n-type epitaxial growth, the molecules may be group V chlorides, t-butylarsine (TBAs), triethylantimony (TESb), triethylarsine (TEAs), plasma ammonia (NH3), plasma hydrogen (H), and / or plasma deuterium (D). Group V chlorides suitable for n-type epitaxial growth include phosphorus chloride, arsenic chloride, and antimony chloride. In some embodiments involving n-type epitaxial growth, the molecule is PCl3, AsCl3, or SbCl3. In some embodiments, for p-type epitaxial growth, the molecule may be a Group V chloride, triethylgallium (TEGa), triethylindium (TEIn), triethylaluminum (TEAl), plasma ammonia (NH3), plasma hydrogen (H), and / or plasma deuterium (D). Group V chlorides suitable for p-type epitaxial growth include gallium chloride, aluminium chloride, and indium chloride. In some embodiments involving p-type epitaxial growth, the molecule is GaCl3, AlCl3, or InCl3.

[0045] [0049 In some embodiments, the pretreatment gas is accompanied by a carrier gas. Any suitable carrier gas may be used. The carrier gas may be an inert gas. The carrier gas may be selected from H2, N2, argon, helium or a combination thereof.

[0046]

[0050] In some embodiments, the exposed amorphous surface (e.g., dielectric surface) includes silicon oxide (SiO), silicon dioxide (SiO2), silicon nitride (SiN), silicon nitride (SiCN), silicon carbide (SiOC), silicon oxycarbonite (SiOCN), or a combination thereof.

[0047]

[0051] In one or more embodiments, the silicon carbonitride film is of the formula SiC y N z The formula has the following properties, where both y and z are greater than zero. In one or more embodiments, the silicon carbide film is of the formula SiO x C y The formula has the following properties, where both x and y are greater than zero. In one or more embodiments, silicon oxycarbonite is of the formula SiO x C y N z The formula has the following properties, where x, y, and z are all greater than zero. In one or more embodiments, the silicon oxide film is of the formula SiO x The formula has the following properties, where x is greater than zero, for example, SiO or SiO2. In one or more embodiments, the silicon nitride film is of the formula Si v N z The formula has such that v and z are greater than zero, for example, Si3N4.

[0048]

[0052] In some embodiments, step 340 is carried out over a period of time ranging from about 10 seconds to about 120 seconds, or from about 10 seconds to about 60 seconds. In other embodiments, step 340 is carried out over a period of time ranging from about 20 seconds to about 40 seconds. Step 340 may be processed at a pressure ranging from 200 torr to 400 torr. The flow rate of the pretreatment gas in step 340 may range from 1 sccm to about 1000 sccm. In other embodiments, the flow rate of the pretreatment gas in step 340 may range from 10 sccm to 100 sccm. The flow rate of the carrier gas during step 340 may range from about 5 slm to about 30 slm.

[0049]

[0053] During step 350, a deposition mixture gas is introduced into the processing chamber to grow epitaxial silicon layers 115a, 115b that form source / drain 114a, 114b. In at least one embodiment, the deposition mixture gas comprises a silicon source gas and an n-type dopant. Any suitable silicon source gas can be used. Examples of suitable silicon source gases include silanes and chlorosilanes, e.g., disilane (Si2H6), tetrasilane (Si4H10), trichlorosilane (Cl3SiH), hexachlorodisilane (Si2Cl6), tetrachlorosilane (SiCl4), pentachlorodisilane (Cl5Si2H), octachlorotricilane (Cl8Si3), or combinations thereof. Any suitable n-type dopant can be used. In at least one implementation, the n-type dopant precursor is a phosphorus-containing precursor, an antimony precursor, or a combination thereof. Examples of suitable antimony precursors include one or a combination of stivin, antimony trichloride, antimony tetrachloride, antimony pentachloride, triphenylantimony, antimony trihydrogenate, antimony trioxide, antimony pentoxide, antimony trifluoride, antimony tribromide, antimony triiodide, antimony pentafluoride, triethylantimony, and trimethylantimony. Examples of suitable phosphorus-containing precursors include phosphine, trimethylphosphine, dimethylphosphine, triethylphosphine, diethylphosphine, tert-butylphosphine, or combinations thereof. Any suitable p-type dopant may be used, e.g., GeH4, B2H6, BCl3, or combinations thereof.

[0050]

[0054] In some embodiments for n-type deposition, the deposition mixed gases include DCS / PH3, TCS / PH3, DCS / AsH3, Si2H6 / PH3, Si2H6 / PH3, and Si4H 10 This includes pH3 or a combination thereof.

[0051]

[0055] In some embodiments for p-type deposition, the deposition mixture gas includes DCS / GeH4 / B2H6, SiH4 / GeH4 / B2H6, SiH4 / GeH4 / BCl3, Si2H6 / GeH4 / B2H6, or a combination thereof.

[0052]

[0056] The epitaxial deposition process carried out in step 350 can grow epitaxial silicon layers 115a and 115b from the first layer 106 of the multi-material layer 105, as shown in Figure 2B. Since the first layer 106 in this example is manufactured from a crystalline material such as silicon, the epitaxial deposition process in step 350 can grow from the sidewall 206 of the first layer 106 rather than from the spacer 110 (e.g., the silicon dielectric layer).

[0053]

[0057] The epitaxial silicon layers 115a and 115b can then continue to grow, forming molded structures such as diamond-like top structures, which can form the source / drain and source / drain extension regions required for horizontal gate-all-around (hGAA) semiconductor devices on the substrate 102. The epitaxial growth process carried out in step 350 can provide a selective deposition process that primarily forms the epitaxial silicon layers 115a and 115b on the top of the sidewalls 206 of the first layer 106, which is made of silicon material, and on the substrate 102, which is also made of silicon material (if no material layer 104 is present), so that gaps (e.g., voids, spaces, or air gaps) can be formed near the sidewalls 210 of the spacer 110. The silicon material is inert to the dielectric material formed from the spacer 110. Therefore, since the silicon material is almost inert to the dielectric material formed from the spacer 110 during the epitaxial deposition process, a selective deposition process is achieved in which epitaxial silicon layers 115a and 115b are mainly deposited on the uppermost sidewall 206 of the first layer 106. The gap formed on the uppermost sidewall 210 of the spacer 110 can later be used to form (together with the spacer 110) as part of a nanowire spacer for a nanowire structure for a horizontal gate-all-around (hGAA) semiconductor device on a substrate.

[0054]

[0058] The epitaxial silicon layers 115a and 115b forming the source / drain 114a and 114b can grow from each of the first layer 106 deposited on the substrate 102 and from each of the first layer 106 within the multi-material layer 205, as shown in Figure 2B. The epitaxial silicon layers 115a and 115b can have thicknesses ranging from about 1 nm to about 10 nm. In the illustrated embodiment, the epitaxial silicon layers 115a and 115b are deposited on the first layer 106 and exposed portions of the substrate 102, which are made from a crystalline material such as Si, and the epitaxial silicon layers 115a and 115b are not deposited on the gate structure 112 or spacer 110, which are made from a dielectric material. The pressure in the processing chamber can be adjusted so that the pressure in the reaction area is in the range of about 1 Torr to about 760 Torr, or about 1 Torr to about 600 Torr, or about 100 Torr to about 300 Torr, or about 200 Torr to about 300 Torr. In some embodiments, a carrier gas (e.g., nitrogen) can be flowed into the processing chamber at a flow rate of about 1 to 40 SLM (standard liters / minute).

[0055]

[0059] The deposition mixture gas used in step 350 contains a silicon-containing precursor, for example, a chlorosilane precursor. Suitable chlorosilane precursors include dichlorosilane (DCS), trichlorosilane (TCS), or a combination thereof. The silicon-containing precursor may be flowed in parallel with a dopant gas, such as an n-type dopant or a p-type dopant gas.

[0056]

[0060] The deposition mixture gas used in step 350 may further contain dopant gases, such as n-type dopants or p-type dopants. In some embodiments, the n-type dopant may be phosphorus (P), arsenic (As), or antimony (Sb), and in the case of gallium arsenide (GaAs), it may be sulfur (S), selenium (Se), tin (Sn), silicon (Si), and carbon (C). The p-type dopant includes, but is not limited to, boron (B). Exemplary dopant gases may include boron-containing gases such as BH3, or phosphorus or arsenic-containing gases such as PH3 or AsH3, and the impurity concentration in the gas phase determines the concentration in the epitaxial silicon layers 115a and 115b. According to exemplary embodiments, the epitaxial silicon layers 115a, 115b are formed from in-situ doped (i.e., growing) epitaxial materials such as in-situ doped epitaxial Si, carbon-doped silicon (Si:C), and / or SiGe. The use of an in-situ doping process in step 350 is merely one example. For example, an ex-situ process may be used to introduce dopants into the epitaxial silicon layers 115a, 115b. Alternatively, other doping techniques may be utilized to incorporate dopants into the epitaxial silicon layers 115a, 115b. Dopant techniques include, but are not limited to, ion implantation, gas-phase doping, plasma doping, plasma immersion ion implantation, cluster doping, implantation doping, liquid-phase doping, solid-phase doping, in-situ epitaxy growth, or any suitable combination of these techniques.

[0057]

[0061] The deposit gas mixture may further contain a carrier gas. Any suitable carrier gas may be used. The carrier gas may be an inert gas. For example, the deposit gas may further contain H2, N2, argon, helium, or a combination thereof.

[0058]

[0062] In some embodiments, steps 340 and 350 completely overlap. In other embodiments, steps 340 and 350 partially overlap. In other embodiments, steps 340 and 350 do not overlap.

[0059]

[0063] In some embodiments, steps 340 and 350 are performed only once. In other embodiments, step 350 is performed only once, and step 340 is performed twice (once before step 350 and once after step 350). In yet another embodiment, steps 340 and 350 are performed multiple times.

[0060]

[0064] The amount of overgrowth and uniformity of the epitaxial silicon layers 115a and 115b can be controlled by changing processing conditions such as the partial pressure of the pretreatment gas, the ratio of molecules in the pretreatment gas, the processing temperature, the number of repetitions of steps 340 and 350, and / or the layer thickness.

[0061]

[0065] In some embodiments, the pretreatment of the epitaxial silicon layers 115a and 115b via step 340 is carried out in a first processing chamber, and the gas deposition on the epitaxial silicon layers 115a and 115b via step 350 is carried out in a second processing chamber. In yet another embodiment, the pretreatment of the epitaxial silicon layers 115a and 115b and the deposition of the epitaxial silicon layers 115a and 115b are carried out in a single chamber.

[0062]

[0066] Figure 4 is a schematic side cross-sectional view of an exemplary processing chamber 400 that may be used to carry out various embodiments of the deposition process discussed herein. The chamber 400 may be used to carry out chemical vapor deposition processes such as epitaxial deposition processes, but the chamber 400 may also be used for etching or other processes. The chamber 400 includes a housing structure 402 made of a process-resistant material, such as aluminum or stainless steel. The housing structure 402 surrounds a quartz chamber 404, which includes various functional elements of the processing chamber 400, such as an upper chamber 406 and a lower chamber 408 containing a processing volume 410; and a substrate support 412 made of a ceramic material or a graphite material coated with a silicon material, such as silicon carbide, which is adapted to receive the substrate 414 within the quartz chamber 404. The substrate support 412 includes a lift mechanism 472 and a rotation mechanism 474 coupled to a substrate support assembly 464. A lift mechanism 472 may be used to move the substrate support 412 along the central axis "A". A lift mechanism 474 may be used to rotate the substrate support 412 about the central axis "A". Reactants from the precursor reaction material are applied to the treated surface 416 of the substrate 414, and by-products are subsequently removed from the treated surface 416.

[0063]

[0067] Heating of the substrate 414 and / or processing volume 410 is provided by an energy source which may be a radiation source or a heat source. Radiation sources may include UV, IR, visible frequency lamps, lasers and LEDs, or a combination thereof. Heat sources may be lasers, LEDs, filament lamps, or a combination thereof. In one embodiment shown in Figure 4, the energy source is a radiation source using lamps such as an upper lamp module 418A and / or a lower lamp module 418B. In one embodiment, as shown in Figure 4, the lamp modules 418A and 418B are installed horizontally. In one example, the upper lamp module 418A and the lower lamp module 418B are infrared lamps. Radiation from lamp modules 418A and 418B passes through the upper quartz window 420 of the upper chamber 406 and through the lower quartz window 422 of the lower chamber 408. Cooling gas for the upper chamber 406 enters through an inlet 424 and exits through an outlet 426, if necessary.

[0064]

[0068] Reacting species are supplied to the quartz chamber 404 by a gas distribution assembly 428, and processing byproducts are removed from the processing volume 410 by an exhaust assembly 430, which is typically in communication with a vacuum source (not shown). Precursor reacting materials, as well as diluents, purge gases, and vent gases for the chamber 400, can enter through the gas distribution assembly 428 and exit through the exhaust assembly 430. The processing chamber 400 includes several liners 432A-432G. The liners 432A-432G shield the processing volume 410 from a metal wall 434 surrounding the processing volume 410. In one embodiment, the liners 432A-432G include a process kit that covers all metal components that are in communication with the processing volume 410 or otherwise exposed to the processing volume 410.

[0065]

[0069] A lower liner 432A is positioned in the lower chamber 408. An upper liner 432B is positioned at least partially in the lower chamber 408, adjacent to the lower liner 432A. The exhaust insert liner assembly 432C is positioned adjacent to the upper liner 432B. In Figure 4, the exhaust insert liner 432D is positioned adjacent to the exhaust insert liner assembly 432C and may replace a portion of the upper liner 432B to facilitate installation. An injector liner 432E is shown on the side of the processing volume 410 opposite the exhaust insert liner assembly 432C and the exhaust liner 432D. The injector liner 432E is configured as a manifold for supplying one or more fluids, such as a gas or a gas plasma, to the processing volume 410. One or more fluids are supplied to the injector liner 432E by the injector insert liner assembly 432F. The baffle liner 432G is coupled to the injector insert liner assembly 432F. The baffle liner 432G is coupled to the first gas source 435A and the second gas source 435B, supplying gas to the injector insert liner assembly 432F and to the gas outlets 436A and 436B formed in the injector liner 432E.

[0066]

[0070] In one embodiment, one or more gases are supplied to the processing volume 410 from a first gas source 435A, a second gas source 435B, and a third gas source 435C, through the baffle liner 432G, the injector insert liner assembly 432F, and through one or more gas outlets 436A and 436B formed in the injector liner 432E. One or more gas outlets 436A and 436B formed in the injector liner 432E are coupled to outlets configured for angled / laminar flow paths 433A or 433B. As will be described in more detail later, one or more of the gas outlets 436A are angled differently with respect to an axis A' parallel to the substrate surface in order to adjust the uniformity of the film across the substrate. The gas outlets 436A and 436B are configured to provide various parameters such as velocity, density, or composition to individual or multiple gas flows.

[0067]

[0071] In one embodiment where multiple gas outlets 436A and 436B are fitted, the gas outlets 436A and 436B may be distributed along a portion of the circumference of a gas distribution assembly 428 (e.g., injector liner 432E) in a substantially linear arrangement to provide a gas flow wide enough to substantially cover the diameter of the substrate. For example, each of the gas outlets 436A and 436B may be arranged to the extent possible in at least one linear group to provide a gas flow roughly corresponding to the diameter of the substrate. The gas exiting gas outlet 436A flows generally along a channel 433B that is angled with axis A' (substantially perpendicular to the longitudinal axis A' of the chamber 400) and mixes with the gas exiting gas outlet 436B. The gas or mixed gas flows along channels 433A, 433B that traverse the entire surface of the substrate and flows into a plenum 437 in the exhaust liner 432D along an exhaust channel 433C. The plenum 437 is coupled to an exhaust pump or vacuum pump (not shown). In one embodiment, the plenum 437 is coupled to a manifold 439 that orients the exhaust passage 433C in a direction substantially parallel to the longitudinal axis A'. At least the injection insert liner assembly 432F may be positioned through and partially supported by the injection cap 429.

[0068]

[0072] Figure 5 is a schematic diagram of a system 500 for processing substrates according to one embodiment. The system 500 may be used to carry out the steps of method 300 shown in Figure 3. The system 500 includes a cluster tool 501. The cluster tool 501 of the system 500 includes one or more processing chambers 502, 503, 516, 518 (multiple processing chambers 502, 503, 516, 518 are shown) coupled to one or more transfer chambers 504 and 510.

[0069]

[0073] A first transfer chamber 504 is coupled to one or more epitaxy chambers 502. A transfer robot 515 for transferring substrates between the epitaxy chambers 502, the etching chamber 503, and a plurality of pass stations 506 is centrally located in the first transfer chamber 504. The first transfer chamber 504 is coupled to a second transfer chamber 510 via the pass stations 506, which is coupled to a cleaning chamber 516 and an annealing chamber 518 for cleaning substrates. A transfer robot (not shown) is centrally located in the second transfer chamber 510 for transferring substrates between a set of load lock chambers 512 and the processing chamber 516. A factory interface 520 is coupled to the second transfer chamber 510 by the load lock chambers 512. The factory interface 520 is coupled to one or more pods 530 on the opposite side of the load lock chambers 512. Pod 530 is typically a forward-opening unified pod (FOUP) accessible from the washing chamber where the cluster tool 501 is located.

[0070]

[0074] In one embodiment of the process, the substrate may first be transferred to a cleaning chamber 516 in which the substrate is pre-cleaned. The substrate is then transferred to one or more etching chambers 503, in which it is exposed to atomic hydrogen radicals to etch the substrate and remove small nodules, as described in step 310. The substrate is then transferred to one or more processing chambers 502, in which an epitaxial layer is selectively grown on the substrate, as described in steps 340 and 350. The substrate is then transferred to an annealing chamber 518, in which the epitaxial layer formed on the substrate is annealed to the annealing temperature.

[0071]

[0075] The first transfer chamber 504 and the second transfer chamber 510 are kept under vacuum during the process so that transfer robots 514 and 515 transfer the substrate under vacuum between all processing chambers and between the load lock chamber and 512 and the passage stations 50 and 6. Transferring the substrate under vacuum reduces the possibility of contamination, improves the quality of the deposited epitaxial film, and facilitates the optional pre-cleaning process before repeating steps 140 and 150 of pre-treatment gas injection and deposition gas introduction. This disclosure assumes that one or more of the chambers shown in system 500 may not be clustered in the cluster tool 501. For example, either or both of the etching chamber 503 and / or annealing chamber 518 in system 500 may be separated (and not clustered) from the cluster tool 501 having the cleaning chamber 516 and epitaxy chamber 502. The use of the cleaning chamber 516 exists when the substrate is returned (from a separate etching chamber and a separate annealing chamber) for repeating the epitaxy process, unless the cluster tool 501 can receive a purged FOUP or portable vacuum station to minimize contamination when the substrate is removed from and re-imported into the cluster tool 501.

[0072]

[0076] In the embodiment shown in Figure 5, the washing chamber 516, epitaxy chamber 502, etching chamber 503, and annealing chamber 518 are different from each other. In one embodiment that can be combined with other embodiments, each of the processing chambers 502 and 503 is a single processing chamber in which steps 310, 320, 330, 340, and 350, and the repetition of step 340 and the repetition of step 350, are carried out, respectively.

[0073]

[0077] System 500 includes a non-transient computer-readable medium 550 configured to control the processing of the cluster tool 501. The non-transient computer-readable medium 550 is coupled to and controls the processing of the pod 530, factory interface 520, load lock chamber 512, second transfer chamber 510, transfer robot 514, wash chamber 516, epitaxy chamber 502, first transfer chamber 504, transfer robot 515, etching chamber 503, and annealing chamber 518. When executed, the non-transient computer-readable medium 550 includes instructions that cause the wash chamber 516, epitaxy chamber 502, etching chamber 503, and annealing chamber 518 to perform the processing of method 300. In one embodiment, which can be combined with other embodiments, the non-transient computer-readable medium 550 is a controller containing instructions.

[0074]

[0078] While the above description applies to embodiments of the present disclosure, other embodiments and further embodiments of the present disclosure may be devised without departing from the fundamental scope of the present disclosure. The scope of the present disclosure is determined by the following claims.

Claims

1. A method for forming a semiconductor device. Positioning a substrate in a processing chamber, wherein the substrate has an exposed amorphous surface and an exposed crystalline surface; Heating the processing chamber to a temperature suitable for deposition; Injecting a pretreatment gas into the processing chamber, wherein the pretreatment gas contains molecules configured to reduce the interfacial energy between the exposed amorphous surface and the exposed crystalline surface; Injecting a deposition gas into the processing chamber to selectively grow an n-type doped epitaxial silicon layer on the exposed crystal surface; Methods that include...

2. The method according to claim 1, wherein the molecule is a group V chloride.

3. The aforementioned molecule, PCL ３ AsCl ３ and SbCl ３ The method according to claim 2, selected from the group consisting of the following.

4. The method according to claim 1, wherein the injection of the pretreatment gas and the injection of the deposition gas overlap at least partially.

5. The method according to claim 1, wherein the injection of the pretreatment gas is completed before the injection of the deposition gas.

6. The method according to claim 1, wherein the injection of the pretreatment gas and the injection of the deposition gas are repeated sequentially multiple times.

7. The method according to claim 1, further comprising exposing the substrate to a dry etching solution to remove contaminants from the surface of the substrate.

8. The method according to claim 1, wherein the exposed amorphous surface comprises silicon oxide, silicon nitride, silicon carbonitride, silicon oxycarbonite, silicon oxycarbonite, or a combination thereof.

9. The dry etching of the substrate, H ２ NF ３ NH ３ The method according to claim 1, comprising exposure to plasma by-products.

10. The method according to claim 1, wherein multiple exposed silicon layers have a <110> structure.

11. The method according to claim 1, wherein the temperature for deposition is 400°C or higher.

12. The method according to claim 1, wherein the injection of the pretreatment gas is carried out at a pressure in the range of about 1 torr to about 760 torr.

13. A method for forming a semiconductor device. The process involves positioning a substrate in a processing chamber, wherein a multi-material layer is formed on the substrate, and the multi-material layer is composed of multiple Si １－ｘ Ge ｘ Positioning a substrate having multiple exposed dielectric surfaces and multiple exposed silicon layers; Heating the processing chamber to a temperature suitable for deposition; Injecting a pretreatment gas into the processing chamber, wherein the pretreatment gas contains molecules configured to reduce the interfacial energy between the plurality of exposed dielectric surfaces and the plurality of exposed silicon layers; Injecting a deposition gas into the processing chamber to selectively grow an n-type doped epitaxial silicon layer on the exposed silicon layer; Methods that include...

14. The exposed dielectric surface is SiC ｙ N ｚ The method according to claim 13, wherein y is zero or more and z is greater than zero and contains N.

15. The method according to claim 13, wherein the molecule is a group V chloride.

16. The aforementioned molecule, PCL ３ AsCl ３ and SbCl ３ The method according to claim 15, selected from the group consisting of the following.

17. A method for forming a semiconductor device. The method involves positioning a substrate in a cleaning chamber, wherein a multi-material layer is formed on the substrate, and the multi-material layer is composed of multiple Si １－ｘ Ge ｘ The plurality of silicon layers and the plurality of dielectric surfaces arranged on the outer surface of the plurality of silicon layers, １－ｘ Ge ｘ Positioning a substrate in which layers are arranged in an alternating pattern with the plurality of silicon layers; Exposing the substrate to a dry etching solution to remove contaminants from the surface of the substrate; Positioning the substrate within the processing chamber; Heating the processing chamber to a temperature suitable for deposition; Injecting a pretreatment gas into the processing chamber, wherein the pretreatment gas contains molecules configured to reduce the interfacial energy between the dielectric surface and the silicon surface; Injecting a deposition gas into the processing chamber to selectively grow an n-type doped epitaxial silicon layer on the silicon surface; Methods that include...

18. The method according to claim 17, wherein the molecule is a group V chloride.

19. The method according to claim 17, wherein the injection of the pretreatment gas and the injection of the deposition gas are repeated sequentially multiple times.

20. The method according to claim 17, wherein the exposed dielectric surface comprises silicon oxide, silicon nitride, silicon carbonitride, silicon oxycarbonite, silicon oxycarbonite, or a combination thereof.

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