Charged particle trapping device

Abstract

A charged particle trapping device is disclosed. The device includes a charged particle trap (3) (Figure 2) which includes a set of electrodes (6) for generating an electric field for manipulating charged particles. The device comprises a voltage source (44) having an output, and a demultiplexer (26) having an input and a plurality of outputs, wherein the output of the voltage source is coupled to the input of the demultiplexer, and each of the plurality of outputs of the demultiplexer is coupled to each of the electrodes of the set of electrodes. The demultiplexer is configured to sequentially charge the electrodes in a first phase, and to be disconnected from the electrodes for a given time in a second phase to provide a relatively low-noise environment in which operation can be performed on charged particles.

Description

[Technical Field]

[0001] This invention relates to a charged particle trapping device, such as a trapped charged particle quantum computer. [Background technology]

[0002] Ion-trapped qubits are one of the most promising methods for quantum computing. One of the advantages of using ion-trapped qubits is their flexible connectivity. In particular, qubit routing (i.e., changing which qubit is coupled to which other qubit) can be achieved by physically moving ions in space. This ability, coupled with excellent coherence time, allows for qubit routing with negligible error, even at large scales. Flexible qubit routing is the foundation of quantum charge-coupled device (QCCD) architectures and is one of the reasons why ion-trapped systems enable high quantum volume. For more information on the above techniques, see, for example, Non-Patent Document 1.

[0003] However, flexible connectivity comes at a cost. High-speed, low-heat ion transport requires precise dynamic control of the voltages of many electrodes.

[0004] Figure 1 illustrates, for example, the electrical wiring method for an ion-trap quantum computer described in Non-Patent Documents 2 and 3. This method uses approximately 10 electrodes per ion or qubit, with each electrode wired to a separate digital-to-analog converter (DAC) outside the vacuum system. This method is not scalable with respect to system size. For example, a 1000-qubit chip requires approximately 10,000 analog input lines. Developing a reliable DAC-to-chip interface at this scale is a significant challenge in itself.

[0005] One proposed and experimentally investigated solution is to form an integrated quantum processing unit (QPU) that combines an ion trap chip with a DAC, see, for example, Non-Patent Document 4. Integration can be monolithic or achieved by packaging multiple independently manufactured chips together, as described, for example, Non-Patent Document 5.

[0006] However, integrating DACs presents several significant challenges.

[0007] The first issue is power consumption. A compact cryogenic DAC has been developed with a power consumption of 30mW per channel or 300W for 1000 qubits. While this can be optimized, the power consumption of the DAC presents a significant challenge for the cryogenic system and thermal interface.

[0008] Secondly, DAC control requires streaming large amounts of data to the QPU. For example, in Non-Patent Document 3, each DAC requires a data input of 5 MB / s. For a 1000-qubit QPU, this corresponds to a data flow of approximately 50 GB / s between the DAC and the controller. Designing a suitable interface is no easy task and in practice requires, for example, the integration of waveforms, compression, or further electronics for the controller itself.

[0009] Thirdly, integrated DACs typically occupy a much larger chip area than the electrodes themselves. For example, Non-Patent Document 6 describes a single unfiltered DAC block with an area of ​​130 μm × 270 μm. Relatively low-noise controllers, in particular, are likely to have an even larger footprint to accommodate the integrated filters. Developing a low-noise voltage source area (e.g., approximately 50 μm × 50 μm) comparable to the top layer electrodes is a challenge in itself. [Prior art documents] [Non-patent literature]

[0010] [Non-Patent Document 1] D. Kielpinski, C. Monroe, DJ Wineland, Nature 417, 709(2002), number:6890 [Non-Patent Document 2] JMPino,JMDreiling,C.Figgatt,JPGaebler,SAMoses,MSAllman,CHBaldwin,M.Foss-Feig,D.Hayes,K.Mayer,C.Ryan-Anderson,B.Nyenhuis,Nature 592,209(2021),arXiv:2003.01293[quantph] [Non-Patent Document 3] V. Kaushal, B. Lekitsch, A. Stahl, J. Hilder, D. Pijn, C. Schmiegelow, A. Bermudez, M. Muller, F. Schmidt-Kaler, U. Poschinger, “Shuttling-Based Trapped-Ion Quantum Information Processing”, (2019), arXiv:1912.04712[quant-ph] [Non-Patent Document 4] N.D. Guise, S.D. Fallek, H. Hayden, C.S. Pai, C. Volin, K.R. Brown, J.T. Merrill, A.W. Harter, J.M. Amini, L.M. Lust, K. Muldoon, D. Carlson, J. Budach, Review of Scientific Instruments 85, 063101 (2014), arXiv:1403.3662[physics,physics:quant-ph]

Non-Patent Document 5

Non-Patent Document 6

Non-Patent Document 7

Non-Patent Document 8

Non-licensed literature 9

Non-licensed literature 10

Non-licensed Document 11

Non-licensed Document 12

Non-licensed Document 13

Non-licensed Document 14

[0011] According to a first aspect of the present invention, an apparatus including a charged particle trap is provided. The charged particle trap comprises a set of electrodes for generating an electric field for manipulating charged particles. The apparatus comprises a voltage source having an output, and a demultiplexer having an input and a plurality of outputs, wherein the output of the voltage source is coupled to the input of the demultiplexer, and each of the plurality of outputs of the demultiplexer is coupled to each of the electrodes of the set of electrodes. The demultiplexer is configured to sequentially charge the electrodes in a first phase, and to be disconnected from the electrodes for a given time in a second phase to provide a relatively low-noise environment in which operation can be performed on charged particles.

[0012] Using a demultiplexer may allow for the use of a much smaller voltage source, while arranging the demultiplexer to be disconnected may help reduce, or even avoid, the noise introduced by using the demultiplexer. Electrodes in a set of electrodes may be used to compensate for local stray fields.

[0013] The apparatus may further comprise at least one additional electrode coupled to the demultiplexer, the demultiplexer being configured to be connected to at least one additional electrode in a second phase.

[0014] The device may further include a set of capacitors, with each electrode in the set of electrodes having its own capacitor arranged between the electrode and ground.

[0015] The device may include a charged particle trap chip supporting a charged particle trap, with a capacitor monolithically integrated on the charged particle trap chip. The device may also include a charged particle trap chip supporting a charged particle trap and at least one further chip stacked on the charged particle trap chip, with a capacitor integrated on at least one further chip. A voltage source may be integrated on the charged particle trap chip or at least one further chip.

[0016] A given time may be sufficient to execute a series of at least one quantum gates. Therefore, a given time may be between 1 μs and 1 s.

[0017] A given time may be sufficient to transport at least one charged particle from a first configuration of charged particles to a second different configuration of charged particles. Thus, a given time may be between 1 ms and 500 ms (for example, when charged particles are transported between quantum gates), or between 1 μs and 1800 s (for example, when the apparatus is not used for quantum gates). A given time may also be between 60 s and 1000 s.

[0018] Each electrode may be layered and have thickness, and each electrode may have at least one dimension perpendicular to the thickness between 10 μm and 2000 μm.

[0019] The apparatus may further include a shim controller, which is configured to cause charging of electrodes in a set of electrodes. The shim controller may be configured to cause charging of electrodes in a set of electrodes to each appropriate level for compensating for a stray electric field. The shim controller may be a classic computer system, such as a desktop computer, which includes at least one processor and memory.

[0020] The device may be a quantum computer. The device may be an atomic clock.

[0021] According to a second aspect of the present invention, a system is provided which includes an apparatus and a cryogenic system for cooling at least a charged particle trap.

[0022] A third aspect of the present invention provides a method for operating the above-described apparatus or system, comprising: in a first phase, the step of sequentially charging electrodes to a demultiplexer; and in a second phase, the step of disconnecting the demultiplexer from the electrodes for a given time in order to provide a relatively low-noise environment in which operation can be performed on charged particles. [Brief explanation of the drawing]

[0023] [Figure 1] This diagram schematically shows the electrical wiring of an ion trap type quantum computer. [Figure 2] This diagram schematically shows the electrical wiring of an ion trap quantum computer employing a switch network and a multiplexed network, and using dynamic electrodes and shim electrodes. [Figure 3] This diagram schematically shows an array of electrodes that may be configured to provide electrodes of different shapes and / or for different purposes. [Figure 4] This is a schematic diagram showing charged particles on an electrode. [Figure 5A] This diagram schematically shows the first simple parallel control configuration. [Figure 5B] This diagram schematically shows a second simple parallel control configuration. [Figure 5C] This diagram schematically illustrates a third, more complex parallel control configuration. [Figure 5D] This diagram schematically shows a fourth, more complex parallel control configuration. [Figure 5E] This diagram schematically shows a fifth, more complex parallel control configuration. [Figure 6A] This diagram schematically illustrates the state before and after a so-called "switchable swap" involving two qubits in adjacent zones. [Figure 6B] This diagram schematically illustrates parallel odd swaps in a linear one-dimensional qubit array, where qubits in six of the eight zones undergo a swap operation, while qubits in two zones remain stationary. [Figure 7] This diagram schematically illustrates two-dimensional ion swapping in a 4x4 ion trap. [Figure 8A] This diagram schematically illustrates a one-dimensional physical swap of two adjacent qubits in a one-dimensional trap, or in a two-dimensional trap segment without a junction between the qubits. [Figure 8B] This diagram schematically illustrates a two-dimensional physical swap between two adjacent qubits that share a junction. [Figure 9] This diagram schematically shows the extended 1D swap waveform. [Figure 10] This diagram schematically illustrates the implementation of a parallel digitally controlled single switch. [Figure 11A] This diagram schematically shows a switch system for controlling dynamic electrodes. [Figure 11B] This is a circuit diagram showing the implementation of an SPDT switch in the system shown in Figure 8A, using two transistors in a path configuration. [Figure 11C]This is a circuit diagram showing the implementation of an SPDT switch in the system shown in Figure 8A, which uses two transmission gates. [Figure 12] This diagram schematically illustrates the implementation of a multi-switch with parallel dynamic control. [Figure 13] This diagram schematically shows a two-dimensional trap with four qubits per junction. [Figure 14A] This figure plots the worst-case scenario reconstruction time and number of time steps for the reconstruction of a 2D trap array of qubits in the so-called "optimal configuration," assuming a swap time of t0 = 100 μs. [Figure 14B] This figure shows a plot of associated memory errors in the worst-case scenario for the reconstruction of a two-dimensional trap array of qubits in the so-called "optimal configuration," assuming a swap time of t0 = 100 μs. [Figure 15] This diagram schematically illustrates an example of a shim multiplexing architecture in which shim electrodes are connected one by one to a voltage source via a demultiplexer. [Figure 16] This diagram schematically shows an analog sim demultiplexer based on a multi-stage network of switches. [Figure 17] This diagram schematically illustrates the implementation of a hybrid sim demultiplexer. [Figure 18] This diagram schematically illustrates a method for implementing quantum gates. [Figure 19] This diagram schematically illustrates an example of the electrical wiring for a 1000-qubit chip, where the quantum processing unit requires only about 200 electrical inputs to control 1000 qubits. [Modes for carrying out the invention]

[0024] Specific embodiments of the present invention are described below by reference to Figures 2 to 19 of the accompanying drawings.

[0025] I. Introduction This specification describes embodiments of ion trap wiring techniques that enable high-speed and arbitrary qubit routing with a small number of control lines. As an example, a 1000-qubit chip that can be controlled with approximately 200 input lines and minimal on-chip power consumption is shown.

[0026] In quantum charge-coupled devices (QCCDs), electrodes can serve two distinct purposes. The first purpose is dynamic, i.e., to deliver waveforms that change over time, performing desired transport primitives such as shuttling, merging, splitting, or crystal rotation. The second purpose is quasi-static, i.e., to compensate for stray electric fields generated by local charges, for example. Typically, each electrode serves both purposes. In the methods described herein, each electrode is explicitly assigned to be either dynamic or quasi-static.

[0027] Two techniques are employed: (1) parallelization of dynamic electrodes, where the dynamic electrodes are co-wired to a fixed number of voltage sources to which they are potentially allocated via an integrated switch; and (2) multiplexing of quasi-static electrodes, where quasi-static electrodes (referred to herein as "shim electrodes") are controlled by a small number of voltage sources via an integrated demultiplexer. The voltage sources include or may take the form of digital-to-analog converters (DACs).

[0028] In the methods described herein, switch integration is used instead of voltage source integration. Unlike voltage sources, switches and demultiplexers require very low data input rates and can be operated with negligible power consumption. Furthermore, switches and demultiplexers have relatively simple structures made up of a small number of transistors and inverters. Therefore, switches and demultiplexers can be easily manufactured using CMOS processes and are suitable for cryogenic temperatures.

[0029] In the techniques described herein, dynamic operation is massively parallelized across the entire processor. This reduces operational flexibility but significantly relaxes control requirements. As will be explained later, instead of requiring approximately 10 voltage sources per qubit, approximately 100 of these voltage sources are sufficient, regardless of the processor size. Shim electrodes require local voltage tuning and therefore cannot be driven in parallel. However, since shim electrodes do not require dynamic tuning, the electrodes can be set to a target voltage and then disconnected from the voltage source. This allows one voltage source to work for multiple shim electrodes. As will be explained in detail later, one voltage source should be sufficient to work in the range of 100 to 1000 electrodes. Thus, with 2 to 10 shim electrodes per qubit, the technique allows approximately 10 to 500 qubits per voltage source.

[0030] Referring to Figure 2, a quantum computing system 1 incorporating a chip wiring architecture is shown.

[0031] Quantum computing system 1, in this case 43 Ca + The QPU2 includes an N-qubit ion trap 3 having a dynamic electrode 4 (or "dynamic electrode"), an RF electrode 5, and a quasi-static electrode 6 (or "shim electrode") for controlling charged particles 7 that take the form of ions or other ionic objects. However, charged particles may take the form of atoms or molecules, each having a net charge, electrons, or positrons.

[0032] Electrodes 4, 5, and 6 are generally supported on the main surface 8 of the substrate 9. However, at least a portion of the electrodes may be embedded, and components such as capacitors, switches (formed by transistors), and interconnects may be embedded, as will be described in more detail later.

[0033] In this example, the dynamic electrodes 4 extend in pairs within row 10 along the central axis 11 and individually within column 12 across row 10. The RF electrodes 5 extend along the outer edge of row 10, and the quasi-static electrodes 6 extend along the outer edge of RF electrodes 5.

[0034] Electrodes 4, 5, and 6 may have other different configurations. For example, the dynamic electrode 4 does not have to be formed between the RF electrode 5 and the quasi-static electrode 6. Electrodes 4, 5, and 6 do not have to be rectangular and do not have to be the same shape.

[0035] Referring to Figure 3, electrodes 4, 5, and 6 may be provided by an array 13 of blank electrodes 14, and the function of each electrode 14 is defined or programmed by control electronics.

[0036] Referring also to Figure 4, the N-qubit ion trap 3 is configured to hold charged particles 7 at a height h from the surface 15 of the N-qubit ion trap 3. The electrode 4 (such as the dynamic electrode 4) used for transporting the charged particles 7 may have lateral dimensions d1, d2 (such as width or length) that are approximately the same as the height h. The height h may be, for example, between 5 μm and 2 mm, or between 10 μm and 200 μm. Thus, the electrode 4 may have a width d1 between 5 μm and 2 mm, or between 10 μm and 200 μm.

[0037] Referring again to Figure 2, QPU2 includes a switch / multiplexing network 21 which has a switch network 22 having multiple switches 23 and switch lines 24, and a multiplexing network 25 having multiple demultiplexers 26 and demux lines 27.

[0038] A transport controller 31 in the form of a computer system receives the permutation of qubits and outputs a transport control signal to a transport voltage source 34, which includes, for example, a digital-to-analog converter (DAC), and generates a signal to be provided to a first transport control line 36. The first transport control line 36 is provided with a corresponding filter 37, and the filtered signal is provided to a second transport control line 39 which is coupled to a switch network 22.

[0039] A shim controller 41 in the form of a computer system receives calibration data and outputs a control signal to a shim voltage source 44, including a DAC, which generates a signal to be provided to the shim control line 46.

[0040] In this example, for transport control there are approximately 10 × N (hereinafter, 10N) switch lines (where N is the number of qubits, which in this case is approximately 1000), 100 transport DACs 34, approximately 100 first transport control lines 36, approximately 100 filters 37, and approximately 100 second transport control lines 39. For shim control there are multiplexing lines 27 ranging from 3N to 10N, shim DACs ranging from (N / 300) to (N / 10), and shim control lines 46 ranging from (N / 300) to (N / 10).

[0041] The N-qubit ion trap 3, and optionally other parts of System 1, may be housed in a cryogenic refrigerator (not shown) for cooling the N-qubit ion trap 3 to a suitable low temperature T (e.g., below 77K or 4.2K). The N-qubit ion trap 3 may be housed in a vacuum chamber (not shown) that provides an ultra-high vacuum environment, allowing individual charged particles to be isolated.

[0042] In this specification, the term "qubit" is used more frequently than "ion." Therefore, when referring to the physical movement of a qubit, for example, when we say "a qubit is moved," this physically corresponds to shutting out one or more ions that encode that qubit, and potentially ancilla ions that help to recool it.

[0043] Next, the chip wiring architecture will be explained in more detail.

[0044] First, the parallelization of dynamic control is explained, including examples of how parallel dynamic control is used and methods for routing qubits that are compatible with parallel control. Then, multiplexed shim operations are explained, including exemplary implementations.

[0045] II. Parallel Dynamic Control Referring to Figure 5A, a first parallel control arrangement for group 15 of transport electrodes 4 is shown.

[0046] Each dynamic electrode 4 is provided with a switch 23 (either a single-pole single-throw switch or a single-pole double-throw switch) configured to selectively connect the electrode 4 to the output of a transport voltage source 34 (e.g., a DAC). In this case, each electrode 4 is provided with its own transport voltage source 34. However, two or more electrodes 4 may share the same voltage source 34. The electrodes 4 and switches 23 are located on a chip. The voltage source 34 is preferably located off-chip, but may be located on-chip.

[0047] With respect to the group 15 of dynamic electrodes 4, the switch 23 is configured to operate together, in other words, to close together (thus connecting all electrodes 4 of the same group to the voltage source 34) and to open together (thus disconnecting all electrodes 4 of the group from the voltage source 34). In other words, the switch 23 can be considered to operate together as a multi-pole single-throw switch or a multi-pole double-throw switch.

[0048] The switch 23 can be controlled using a single control signal, for example, by a single control bit s. For example, when s=1, each switch 23 is closed, so each electrode 4 is connected to the output of the voltage source 34, and when s=0, the switch is open, so each electrode 4 is not connected to the output of the voltage source 34, or vice versa.

[0049] Referring to Figure 5B, a second parallel control configuration is shown.

[0050] The second parallel control configuration is the same as the first parallel control configuration shown in Figure 5A, except that the second parallel control configuration includes a second set of transport DACs 34, and each switch is a multi-throw switch with one terminal connected to the first transport voltage source 34 and the other terminal connected to the second transport voltage source 34. In this case, each electrode 4 is provided with two respective transport voltage sources 34. However, two or more electrodes 4 may share the same voltage source 34.

[0051] The switch 23 can be controlled by a single control bit s. For example, when s=1, electrode 4 is connected to one voltage source 34, and when s=0, electrode 4 is connected to another different voltage source 34. In some cases, the switch may have a third terminal that allows electrode 4 to be connected to one of the two voltage sources 34 or not connected at all.

[0052] More complex parallel control configurations may be used.

[0053] Referring to Figure 5C, a third parallel control configuration is shown.

[0054] The third parallel control configuration is similar to the first parallel control configuration shown in Figure 5A, except that there are first and second groups 151, 152 of electrodes 4 that share the same set of transport voltage sources 34. For example, the first electrode 4 of the first group 151 and the second electrode 4 of the second group 152 may share the same voltage source 34. The electrodes 4 of one group 151, 152 can be switched simultaneously, but each group 151, 152 of electrodes can be switched independently of the other groups 151, 152.

[0055] There may be three or more groups 15 of electrodes 4, and the output of the voltage source 34 may be shared among the three or more groups 15. Furthermore, the output of the voltage source 34 may be shared among two or more electrodes 4 of one group 15. The output of the voltage source 34 may not be shared among all groups 15.

[0056] Referring to Figure 5D, a fourth parallel control configuration is shown.

[0057] The fourth parallel control configuration is similar to the second parallel control configuration shown in Figure 5B, except that there are first and second groups 151 and 152 of electrodes 4 that share the same set of transport voltage sources 34. For example, the first electrode 4 of the first group 151 and the second electrode 4 of the second group 152 may share the same voltage source 34, while the second electrode 4 of the first group 151 and the first electrode 4 of the second group 152 may share a different voltage source 34.

[0058] Similar to the third parallel control configuration, electrodes 4 of one group 151,152 can be switched simultaneously, while each group 151,152 of electrodes can be switched independently of the other groups 151,152.

[0059] Similar to the third parallel control configuration, there may be three or more groups 15 of electrodes 4, and the output of the voltage source 34 may be shared among the three or more groups 15. Furthermore, the output of the voltage source 34 may be shared among two or more electrodes 4 of one group 15. The output of the voltage source 34 may not be shared among all groups 15.

[0060] Referring to Figure 5E, a fifth parallel control configuration is shown.

[0061] This configuration, namely the fifth parallel control configuration, shows that the output of one voltage source may be shared among the electrodes 4 between different groups 15 (or "zones"), while within one group 15 ("zone"), each electrode 4 is connected to a different voltage source 34. (Simplified for ease of understanding) In this configuration, there are four electrodes per zone 15. However, there may be more electrodes 4 per zone.

[0062] In this configuration, electrode 4 is labeled using notation (electrode index, zone type, zone index).

[0063] Figure 5E shows how the same voltage source can be shared between different electrodes in different zones, even though electrodes in the same zone can be controlled in parallel. For example, "V 1,1,3 A voltage source labeled as such is shared between the third electrode in Zone 1 (labeled (3,1,1)), the third electrode in Zone 5 (labeled (3,1,5)), and the third electrode in Zone 7 (labeled (3,1,7)).

[0064] To help provide a deeper understanding of parallel dynamic control, a simple example of how parallel dynamic control is used is provided first.

[0065] Referring to FIG. 6A, two qubits (1, 2) (labeled 71, 72) are within adjacent trap zones 1, 2 (also labeled 511, 512).

[0066] The swap of qubits can be achieved by connecting all electrodes to a set of voltage sources 34 (FIG. 2) that execute a swap waveform. When a swap is not required (i.e., when the qubits should remain stationary), one approach is simply to modify the waveform of the voltage source. However, instead, according to the method of the present invention, the swap waveform continues to be reproduced from (or "generated by") the voltage source, but a set of switches 23 (FIG. 2) within the QPU 2 are used to select whether ion 7 moves. In particular, the action in zone i is controlled by digital line s i . When s i = 1, the qubits within zone i receive the swap waveform, while when s i = 0, the qubits remain stationary. Thus, in a two-zone trap, the qubits are swapped when (s1, s2) = (1, 1) and remain in the same order when (s1, s2) = (0, 0). Note that (0, 1) and (1, 0) are not valid instructions in this case. [[ID=十二]]

[0067] Referring to FIG. 6B, the processor may be scaled up to a linear repeating array with zones i = 1, 2,..., N, where in this case N = 6. Every other zone is connected to the same fixed set of voltage sources, i.e., when s i = s i + 2, all dynamic electrodes within zone i + 2 execute the same waveform as the corresponding dynamic electrodes within zone i. Thus, applying the same swap waveform as above, the N-bit word s = (s1, s2,..., s NBy sending ) to the QPU, it is possible to select in parallel whether to swap the qubit (i,i+1) every odd number of i. This step is called an "odd swap". Similarly, an "even swap", in which it is selected in parallel whether to swap the qubit (i,i+1) every even number of i, can be achieved by replaying a modified swap waveform and sending another N-bit word s.

[0068] As described above, swapping any parallel qubits can be achieved in one dimension (1D) using a fixed number of voltage sources 34 and an N-bit digital signal. In 1D, there are two types of zones 51 ODD ,51 EVEN , in other words, odd and even zones 41 ODD ,41 EVEN A voltage source 34 is used. ODD ,34 EVEN Two sets are used: one set for odd-numbered zones and one set for even-numbered zones.

[0069] Referring to Figure 7, if every zone is connected to its four neighboring zones via transport paths, providing a cross-shaped junction, this technique can be extended to a two-dimensional (2D) array. In such a 2D array, "odd horizontal swaps" and "even horizontal swaps" can be performed in the same way as previously described for a 1D array. Vertical swaps can be performed by first tilting the view by 90 degrees. Later in Section IID, it will be shown how these primitives enable efficient reconstruction of arbitrary qubits.

[0070] 2D processors can be more complex. For example, it may be beneficial to separate the gate zone from the junction zone, or to create special read or storage zones. Nevertheless, parallel dynamic control remains applicable. For instance, as will be described later in Section IID, a trap with separate junction and gate zones can be controlled by using eight sets of voltage sources instead of the four mentioned above. Overall, parallel dynamic control is compatible with complex processors and special zones, insofar as the complex processors and special zones consist of repeating patterns of nominally identical unit cells. Similarly, the technique can be extended beyond swapping to a larger set of parallel primitive actions by using more sets of voltage sources and more switch settings per zone.

[0071] A. Swap waveform The logical primitive of the architecture is the swapping of qubits, but this is not necessarily a physical primitive. There are several ways in which qubit swapping can be physically performed.

[0072] Referring to Figure 8A, the sequence of the 1D physical swap is shown. Two qubits 7 in separate wells 61 are brought together by shuttle and merged into a single crystal 62. The crystal then undergoes a rotation that swaps the order of the qubits. For these, see, for example, the aforementioned Non-Patent Literature 7. Finally, the crystal is split and the qubits are shuttled so that they are separated from each other.

[0073] Referring to Figure 8B, a sequence of 2D physical swaps that can be used when junction 53 is present is shown. By using the junction, the two qubits 7 can be reordered in a few steps of shuttle (steps S8.1 to S8.3) without requiring crystal rotation. This can be advantageous in terms of speed and heating. Finally, logical swaps can be performed through quantum gates. This can lead to further errors, but may allow for faster reconfiguration, especially in longer chains.

[0074] First and second qubits 7 A ,7 B These are adjacent first and second channels 63 UL ,63 UR Located within, the first and second channels 63 UL ,63 UR These are the third and fourth channels 63, respectively, connected by a common central channel 63c. LR ,63 LL It is located opposite the second qubit 7. B This is the fourth channel 63 located on the opposite side. LR It can be shut out (step S8.1). First qubit 7 A This is the second channel 63 UR It is shuttled and takes its designated position (step S8.2). Second qubit 7 B This is the first channel 63 UL It is then shut down and can return to the position where the first qubit was located (step S8.3).

[0075] The swap waveforms described above assume that all qubits start in separate zones, but this is not necessarily the case. For example, consider an initial configuration where N qubits are arranged in a chain of length 2c, where c is a positive non-zero integer. Before routing begins, a sequence of c split waveforms is applied to every pair of zones until every qubit is placed in a separate zone. After routing, the procedure is repeated in reverse to collect the qubits and apply the next layer of gates. More complex procedures may be used to control the length of other chains. The algorithm is also flexible with regard to the handling of auxiliary ions. For example, every qubit could represent a pair of ions, i.e., one qubit ion and one auxiliary ion. In that case, primitive operation could involve a 4-ion crystal rotation or a 2-ion junction shuttle.

[0076] The transport waveform is determined using an electrostatic model of charged particle trapping. From initial position x1 to end position x N A path for charged particles is provided (for example, from a routing module) to intermediate positions x1, x2, ..., x N It can be divided into two parts. The trap electrostatic model is used to calculate the electrostatic potential generated by applying a fixed voltage, for example 1V, to each electrode individually. Then, for each i (i.e., i=1,2,...,N), location x i An optimization algorithm is executed to calculate a linear combination of electrode voltages that generate a potential to hold ions. Finally, the resulting voltage (i.e., the calculated linear combination of electrode voltages) is interpolated to generate a smooth waveform. An example of how to determine the waveform in this way, and an example of the resulting waveform, can be found in the aforementioned Non-Patent Document 8, which is incorporated herein by reference (see, for example, Figures 6.4, 6.5, and 6.6). Another method can be found, for example, in the aforementioned Non-Patent Document 9.

[0077] B. Implementation of a single switch Referring to Figure 9, an extension of the 1D swap waveform between zones (1,2) is shown. The first qubit 71 is swapped, while the second qubit 72 remains stationary.

[0078] Referring to Figure 10, alternative methods using this waveform are as follows:

[0079] Assume there are only two qubits 71,72, namely one in the first zone 511 ("zone 1") and the other in the second zone 512 ("zone 2"). A switchable push field can be used to push qubits 71,72 either to the left or to the right within each zone 511,512. In particular, s i If = 1, the qubits in zone i are pushed into their respective first locations 711, while s i If (s1,s2)=(1,1), the qubits are pushed into their respective second positions 712. After the switch is set, the waveform is executed. Thus, if (s1,s2)=(1,1), the qubits are swapped, while if (s1,s2)=(0,0), the qubits remain in their original order.

[0080] This swap waveform can be physically implemented as follows:

[0081] A fixed voltage source is used to run the extended swap waveform in parallel in every zone. Simultaneously, in each zone, whether ions 71,72 are pushed into the second well 622 or into the first well 621 at t=0 can be selected by (a) generating a dual well potential (step S10.1a) and (b) applying either a positive voltage +V or a negative voltage -V to one or more electrodes (step S10.1b). This allows for local and digital selection of whether or not ions are swapped. Thus, one switch per zone is sufficient to implement parallel dynamic control. The same method can be used to condition the execution of a 2D swap waveform. Steps S10.1a and S10.1B can be performed sequentially or simultaneously.

[0082] Referring to Figure 11A, an example of the switch system 81 is shown. The selected bit word s = (s1, ..., s N This is loaded into the serial-parallel register 82 and is used to select whether zone i is connected to the + rail 83 or the - rail 84 using the selection switch 85.

[0083] See also Figures 11B and 11C, the selection switch 85 can be physically implemented using a pair of pass transistors 86, or as two transmission gates 87, each implemented using an NMOS / PMOS transistor pair 88, 89 and an inverter.

[0084] In one embodiment, the ± rails 83 and 84 are connected to separate voltage sources 34 (Figure 2) and initially set to the same voltage V0. When each electrode 4 is connected to one rail 83 or 84, the voltage on the + rail 83 is raised to V0+V and the voltage on the - rail 84 is lowered to V0-V. This ramping can be performed smoothly to avoid undesirable motional excitation by ensuring that the voltage source output is filtered off-chip. After all electrodes 4 are set to either V0+V or V0-V, the swap waveform is regenerated and rails 83 and 84 return to V0. This performs one cycle of parallel swapping.

[0085] Alternatively, parallel switching can be implemented by purely digital means. In this method, ±rails 83,84 are permanently set to V0±V. This greatly simplifies the circuit design and allows it to be adapted to standard digital CMOS. However, the digital implementation may require a capacitor after switch 85 to smooth the switching impulses. Alternatively, the bang-bang method can be used to displace qubits with minimal kinetic excitation and without filtering by the sequence of switching events.

[0086] Regarding capacitive shunting of electrodes to ground, there are technologies to manufacture low-loss switches with resistance R < 10Ω, but transistor switches with R ≈ 100Ω are more common. The larger the resistance R, the greater the RF pickup on the dynamic electrode.

[0087] Continuing to refer to Figure 11A, this pickup can be mitigated by placing a shunt capacitor 90 between the switch 85 and electrode 4. However, significantly reducing the RF impedance to ground requires a large capacitor, for example, Ω RFAt 2π × 50MHz, an impedance Z < 10Ω requires a capacitance C > 300pF. Implementing such a large capacitor on a chip would likely require a large footprint and vertical capacitor technology (as described in Section IIIA). Furthermore, such on-chip filtering also means that the total capacitive load of each voltage source can vary significantly from sequence to sequence, leading to waveform distortion. Therefore, filtering the signal off-chip and reducing the resistance of the transmission gate as needed is generally preferable.

[0088] C. Implementation of a multi-switch In the implementation of a multi-switch, multiple or all of the dynamic electrodes 4 (Figure 2) within each zone are connected to the switch.

[0089] Figure 12 shows an implementation of the 1D single parallel odd-swap capable multiswitch described earlier with reference to Figure 6B.

[0090] Referring to Figure 12, zone i (labeled 52) is odd if i is odd (52 ODD ) is called, otherwise it is an even number (52 EVEN ) is called. Every dynamic electrode 4 in zone i is the same switch s i It is controlled by the following: In particular, the dynamic electrode 4 in zone i is controlled by the voltage source set V i(mod2),si It is connected to the following. Therefore, the shown implementation requires four sets of voltage sources 34, and for six dynamic electrodes 4 per zone, a total of 24 voltage sources 34 are used.

[0091] More broadly, with respect to e switchable dynamic electrodes per zone, each connected to a switch with N zones, t zone types, and k settings, the implementation of a multi-switch requires t × e × k voltage sources and N × e on-chip switches. Each electrode 4 is wired individually, similar to the implementation of a single switch.

[0092] The implementation of multi-switches allows for maximum flexibility in waveform design, as every action can have a completely separate custom waveform. All switches in zone i are on the same digital line s i Since it is controlled by [a certain mechanism], the length of the bit selection word s is still N.

[0093] D. Routing Algorithms As previously explained, parallel dynamic control enables parallel "odd swaps" and parallel "even swaps" in a 1D array. In a 2D array, they can be performed either in parallel across all rows ("horizontal odd / even swaps") or in parallel across all columns ("vertical odd / even swaps"). This section explains how this capability enables the routing of arbitrary qubits in complex traps.

[0094] In its simplest case, consider the 1D trap described with reference to Figure 6B. In this case, any qubit arrangement can be optimally generated by an algorithm known as "odd-even sort". The current qubit configuration is expressed as shown in equation (1). The target configuration is expressed as shown in equation (2).

[0095]

number

[0096]

number

[0097] In the first time step, for any odd number i, π(x i )>π(x i+1 ) If the qubit x i and x i+1These are swapped. These swaps are performed in parallel across the entire processor. In the second time step, for any even i, π(x i )>π(x i+1 ) If the qubit x i and x i+1 It will be swapped.

[0098] These steps are repeated until equation (3) below is satisfied.

[0099]

number

[0100] Odd-even transpose sort is the time-optimal way to sort qubits in 1D, with a worst-case execution time of N time steps (if the two qubits at each end need to be swapped).

[0101] Next, the method can be extended to the 2D architecture described with reference to Figure 8B. For details, please refer to Non-Patent Documents 10 and 11 mentioned above.

[0102] Consider a grid of m × n qubits arranged in a 2D array, where the zones are enumerated as (i,j), where i=1,2,...,m and j=1,2,...,n. A zone is considered "odd" if i+j is odd, and "even" otherwise. In this way, every odd zone is adjacent only to an even zone, and vice versa. The qubits are reconfigured as follows:

[0103] First, for every column, the qubits in every row are rearranged in parallel so that every qubit is in a different target row. This is possible by repeatedly applying Hall's marriage theorem. This rearrangement proceeds by horizontal odd-even swaps outlined above and takes a maximum of m time steps. Then, the qubits in every column are rearranged in parallel so that every qubit is in a target row. This is done by vertical odd-even swaps and takes a maximum of n time steps. Finally, the final row-by-row rearrangement proceeds, which takes a maximum of n time steps. Thus, the architecture allows for a maximum of 2m+n swap steps and any sorting of N=m×n qubits in 2D in two types of zones. Changing the sorting order to column-row-column allows for any sorting in a maximum of 2n+m steps, which may be more efficient.

[0104] The above considerations assume that every qubit can be swapped with any of its four neighboring qubits, i.e., one junction per qubit. However, junctions take up space, and high-performance quantum processors can benefit from higher qubit densities. Therefore, it may be beneficial to operate with multiple qubits per junction.

[0105] Referring to Figure 13, an N-qubit ion trap 3 is shown, illustrating one possible solution. A chip of linear segments 101 is shown, each holding k qubits. Between each group of k qubits, there are X junctions 102.

[0106] Any routing in the processor described above can be achieved by extending the method described above. Unlike the previous example which used two types of zones, there are four types of zones: junction odd, junction even, inner odd, and inner even.

[0107] In the first step, the qubits are arranged in parallel in each row, as before. An additional zone type is required because the physical waveform needed to control the qubit differs depending on whether it is in junction zone 102 or internal zone 101. Secondly, the qubits are sorted vertically in parallel in every junction zone. Then, the qubits are swapped with the qubit directly to its right in each junction zone, and the vertical sorting is repeated. This procedure is repeated k times until all columns are sorted. Thus, the only difference from the fully-connected 2D case is that the “vertical sort” step takes about k × m steps instead of m steps as before. Finally, the horizontal sort is repeated as before. In total, any sorting of an array with m × n qubits requires four types of zones and about 2m + kn steps.

[0108] Given any given (N,k), equations (4) and (5) below may hold. It is straightforward to verify that the reconstruction time is minimized in this case.

[0109]

number

[0110]

number

[0111] In the above case, any reconfiguration of the N-qubit array requires a swap step, as shown in item (6) below.

[0112]

number

[0113] This solution is called the "optimal configuration" and will be examined in more detail later.

[0114] E. Performance and Time Measurement The total duration of a qubit rearrangement depends on the time required to perform a single step of the parallel swap. This also depends on the duration of other primitives such as ion splitting, merging, rotation, linear shuttle (for 1D swaps), or junction shuttle (for 2D swaps). A qubit swap duration of t0 = 100 μs is used as a decimal point, which is realistic given the typical performance of existing systems.

[0115] Referring to Figure 14A, the time required to perform routing of any qubit in an optimal 2D array is shown (using that assumption). With k=6, any reconstruction of a 1000-qubit array is achieved in 22ms, while 10000 qubits require 70ms.

[0116] Referring to Figure 14B, the plot shows that in the aforementioned Non-Patent Document 13 43 Ca + These are the associated memory errors, assuming an error model measured for clock qubits. With k=6, 2e-5 memory errors (per qubit per reconstruction) are expected for a 1000-qubit array, and 1e-4 memory errors for a 10000-qubit system. This demonstrates that parallel dynamic control is compatible with large-scale, fast, and high-fidelity reconstruction, despite the limited degrees of freedom in operation.

[0117] The analysis described above only calculates the worst-case reconstruction time. It is reasonable to ask whether typical reconstruction times differ significantly. Numerical analysis shows that for random qubit sorting matrices, the average reconstruction time is very close to the worst-case reconstruction time. This is especially true for large 2D arrays, because the time required to perform parallel horizontal / vertical sorting is given by the time required to sort the slowest row / column. Therefore, significantly reducing reconstruction time requires a large amount of structure within the sorting matrix, i.e., careful qubit mapping in the algorithm.

[0118] III. Multiple Separable Sim Operations Referring to Figure 15, the underlying principle of the multiplexed shim operation is that multiple shim electrodes 6 can be set by a single shim voltage source 44.

[0119] In particular, one shim voltage source 44 is connected to multiple shim electrodes 6 via a demultiplexer 26. However, naive multiplexing risks degrading the performance of quantum operation due to noise injection. This risk can be mitigated or mitigated by operating by (1) charging the electrodes 6 one by one, (2) turning off the demultiplexer 26, and (3) performing the quantum operation. Therefore, during reconstruction, the shim voltage is maintained not by the shim voltage source 44 but by the on-chip capacitor 20, which also serves to shunt the RF pickup to ground. If the ion trap is a Penning trap rather than an RF trap, these capacitors 20 may be unnecessary.

[0120] A. Shim capacitors and RF pickups The i-th shim electrode 6 is V iIt shall be set to . A residual RF voltage may exist at the shim electrode, and this residual RF voltage may be particularly noticeable when electrode 6 is disconnected from the shim voltage source 44. The shim electrode 6 shall be shunted to ground through capacitance C. When the switch is open, the voltage at the shim electrode is V i +V RF ×C i / Ccos(Ωt), where Ω is the RF frequency and V RF is the voltage across the RF electrode, and Ci is the parasitic capacitance between the RF and DC electrodes. This is especially true between the electrodes. i Variations in / C can lead to further micromotion. From this perspective, it is desirable to keep C very large.

[0121] Since each shim electrode 6 has its own capacitor 20, they are integrated into the QPU2 to avoid interconnect count (e.g., on-chip or co-packaged in a stacked structure). Once the capacitors 20 are integrated, the maximum value of C may be limited by the constraints of the chip footprint. Examples include the ion height h and the zone area A. z Consider a device with dimensions of 10h x 10h. Each zone has an area of ​​A. c It includes Ns shim electrodes connected to each of the capacitors. s ×A c z As long as this is the case, capacitor 20 does not exhibit a significant bottleneck in device size. Thin-film planar capacitors have a C / A ratio of approximately 3 fF / μm. 2 This makes it possible. Therefore, dimension A c A capacitor C with dimensions of 100 μm × 100 μm provides a capacitance of approximately 30 pF. Assuming h = 30 μm, such a capacitor can be supplied with N per zone without becoming a bottleneck in the device footprint. s =10 shims can be connected. Considering a typical parasitic capacitance of about 1 fF between the RF and the shim electrode, the above means that the RF pickup can be about 3 × 10​-5 This reduces it by a factor of two. This is expected to allow for better operation, particularly ensuring that the pickup is nearly uniform across the entire chip. Nevertheless, parasitic capacitance can also be managed.

[0122] If necessary, the RF pickup can be further reduced by using a larger value of C. There are several ways this can be achieved on-chip. First, a larger planar capacitor can be used. For example, N s Achieving C≈300pF at =10 means approximately 1mm per zone. 2 This requires an area of ​​10,000 qubits. This means that a chip with N=10,000 qubits must be mounted on a 10cm x 10cm capacitor die. More realistically, multiple planar capacitors can be placed on different layers of the same chip. For example, using a 10-layer process, the effective C / A can be increased to approximately 30 fF / μm², enabling a shim capacitance of C≒300pF without increasing the footprint. Finally, vertical fabrication of trench capacitors allows for a C / A of approximately 10 fF / μm 2 Or even better, it makes C / A ≈ 100 fF / μm² possible.

[0123] B. Implementation of a demultiplexer Referring to Figure 16, the shim demultiplexer 26 can be implemented as a multistage switch network 131. The network 131 has a set of individual switches 132 arranged in pairs between the shim voltage source 44 and each electrode 6. When s=1, the switch 132 connects the input 133 to the output 134, and otherwise leaves the input 133 and output 134 disconnected. Each individual switch 132 can be implemented, for example, as a transmission gate (similar to the transmission gate described above).

[0124] In this configuration, a digital word s of length k = (s1, s2, ..., s kThis controls which of the 2k electrodes is connected to the voltage source voltage V. The word s can be transmitted to the chip either through a parallel interface, in other words, through k cables, or through a serial interface 19 (Figure 2), or it can be generated on-chip using a flip-flop circuit that cycles through the switch settings in a fixed order.

[0125] Referring to Figure 17, as an alternative hybrid implementation to the one described above, the switch can be divided into a digital part and an analog part.

[0126] First, word s is sent to the digital demultiplexer 135. This is 2 k The lines of the book x1, x2, ..., x 2k One of these is selected to be pulled up, while the rest are set to ground. Secondly, for each i=1,2,...,2k, electrode i is connected to the shim voltage source 44 via a single switch 136 controlled by xi. Thus, the demultiplexer 135 works to connect only one of the shim electrodes to V.

[0127] There are two advantages to the hybrid implementation. First, the digital demultiplexer 135 is easy to design and manufacture. Second, the analog signal V only needs to pass through a single switch 136, regardless of how many electrodes are connected to the same voltage source. This helps to mitigate potential time-dependent problems associated with transmission gates, such as those caused by resistive loads or charge injection.

[0128] C. Electrode charging Before reconstruction, electrode 6 is charged to the correct voltage. The switching speed is basically limited by the filter function of the switch resistance and load capacitance, but in practice, it may be desirable to lower the switching rate to reduce noise and ion motion excitation.

[0129] The transmission gate may have a resistance of R=100Ω, and the on-chip capacitor may have a capacitance of C=30pF. Therefore, the on-chip component has a cutoff frequency f c It acts as a low-pass filter at 53 MHz, and this cutoff frequency is higher than the typical motion frequency of captured ions (f=1-10 MHz). Therefore, charging electrode 6 with a smooth waveform for several microseconds can help avoid significant motion excitation while simultaneously avoiding the bandwidth limitations imposed by the on-chip load.

[0130] In the following, it is assumed that the charging sequence requires t=3μs per electrode. Using k=7, it is possible to charge M×2k=M×128 electrodes in 2k×t=380μs using M voltage sources. Therefore, the time required to charge the shim electrodes 6 is equivalent to the time required to perform 3 to 4 swaps. Thus, if necessary, electrodes 6 can be recharged between any reconfiguration layers without significantly impacting execution time. As will be explained later, recharging the shim electrodes 6 between any reconfiguration layers can be used to perform parallel gate operations. If this is not necessary, it may suffice to recharge the shim electrodes 6 much less frequently, for example, once per quantum circuit shot. In that case, it should be possible to work for many more electrodes 6 from a single shim voltage source 44.

[0131] One challenge in multiple isolation operations is charge injection. When electrode 6 is charged to voltage V, residual charge on switches 132 and 136 is injected into electrode 6 when switches 132 and 136 are open. In a simple model, each transistor switch has a charge Q=C t (V g -V th -V) stores, C t V is the gate-source capacitance of a transistor. g V is the gate control voltage. thΔV = Q / C = (V) is the threshold voltage of the transistor. This charge is redistributed equally between the source and drain, and therefore, after the source is disconnected, the electrode voltage is ΔV = Q / C = (V) g -V th -V)×C t / C increases only V g -V th Assuming -V to V, the resulting voltage is approximately V × C. t Only / C is systematically offset.

[0132] In this model, charge injection is expected to be stable shot by shot and is therefore a local, systematic offset that can be calibrated even with channel-to-channel variability. However, since no physical process is perfectly stable, it is desirable to minimize systematic shifts in the first place. The main way to reduce systematic charge injection is by reducing the switch capacitance. The gate-source capacitance C of the transistor. t A single-transistor switch with a capacitance of approximately 20 fF, or even as low as 1 fF, is possible.

[0133] D. Electrode discharge Ideally, the voltage V remains constant after the switch is released, but in reality, it decays over time. The main loss channels are due to the current flowing through the capacitor and the transistor. The former is dominant, and the decay through the capacitor is characterized by the time constant τ = RC, where R is the insulation resistance of the capacitor. Area A, dielectric gap t, dielectric constant ε r For a parallel plate capacitor with ε0 and dielectric resistivity ρ, C = ε r ε = 0A / t and R = ρt / A. Therefore, in this simple model, the time constant τ = ε rε0ρ is independent of capacitance. Naturally, this is merely an approximation, as ρ can be affected by manufacturing imperfections that may depend on the size of the capacitor. Nevertheless, given the typical dielectric resistivity at room temperature, a time constant exceeding several minutes can be expected. τ ≈ 270 s has been measured for thin-film capacitors made of alumina, and for further analysis of this value, refer to Non-Patent Document 14 mentioned above.

[0134] Assuming τ = 270 s, the duration for which the electrodes can remain disconnected before needing to be recharged can be determined. The most stringent target is related not to transport but to the entanglement gate, i.e., changes in electrode voltage lead to changes in the floating field, and changes in the floating field lead to changes in the motion frequency due to trap anharmonicity. This is particularly serious with respect to radial modes and mixed-species crystals in surface electrode traps. As an order of magnitude, Δf ≈ 1 kHz per 1 V / m is used.

[0135] For entanglement gates, Δf should be much lower than the sideband Rabi frequency Ω'. A stray-field error of Δf < ≈ 100 Hz, and therefore E < ≈ 0.1 V / m, is required. In principle, much larger stray-field variations can be tolerated, as long as they are known and taken into account in the gate drive configuration. Note that in this specification, "<≈" may mean a nearly equal sign directly below the less-than sign on the line ≈.

[0136] Regarding transport, the splitting of ions is the most delicate operation, and an axial levitation field error of E ≒ 5 V / m is required for the operation to be carried out successfully. However, as long as they are in the radial direction, larger levitation field drifts can be tolerated. Finally, levitation field errors can lead to heating during transport operations such as crystal rotation or junction transport and, moreover, to the loss of ions. However, these can usually tolerate errors of up to E ≒ 100 V / m.

[0137] Measurements from surface traps generally show that the levitation field varies along the trap axis by E ≒ 100 V / m, but the presence of unshielded structures can cause variations that are one order of magnitude larger than that. Furthermore, the offset is mainly in the out-of-plane direction. Let the shim electrodes be used to compensate for a levitation field range of E = 200 V / m. Thus, (a) a high-fidelity gate requires a voltage error of ΔV / V < ≒ 0.1 / 200 = 5×10 -4 less than, (b) splitting requires a voltage error of ΔV / V < ≒ 0.1 / 200 = 2.5×10 -2 less than, and (c) other transports require a voltage error of ΔV / V < ≒ 100 / 200 = 0.5 less than. These values are approximate, and the actual requirements can vary significantly depending on the anharmonicity of the trap, the choice of gate mode, the sideband Rabi frequency, and whether the attenuation is uniform throughout the processor.

[0138] Nevertheless, these figures are a useful starting point for considering the timescale of discharge. Assuming τ = 270 s as described above, we can see that the shim electrode may require recharging every (a) 135 ms for the gate, (b) 7 s for the split, and (c) every 3 min for the transport. Thus, given the timescale of the typical qubit reconstruction described herein, the shim electrode is likely to require recharging midway through the circuit, for example, between subsequent reconstructions, unless the sideband drive can be adjusted to track the shifting mode frequency. On the other hand, if the gate drive can compensate for local offsets, it may be sufficient to simply recharge the shim electrode between circuit operations.

[0139] IV. Quantum operation The aforementioned method could also be useful in improving the control of the internal state of qubits.

[0140] In fault-tolerant quantum computing, the problem of implementing arbitrary unitaries is reduced to the problem of implementing primitive gates, such as a fixed set of 1-qubit gates and 2-qubit gates. Typically, a quantum gate for N qubits is implemented by applying an O(N) signal from an O(N) qubit drive (such as a laser or microwave). However, instead, parallel dynamic control and sim multiplexing methods can be used to implement primitive gates with fewer qubit drives.

[0141] The term "qubit drive" is broadly intended to refer to a signal source that is coupled to the state of a qubit. For example, if a laser is divided into N paths, each modulated by a separate acousto-optic modulator (AOM) and focused to a different qubit, it can be said that there are "N individual qubit drives." On the other hand, if the laser is modulated by a single AOM and focused to N qubits, it can be said that there is only a single global qubit drive. Typical qubit drives include laser light near-resonant to a qubit's quadrupole transition, pairs of laser beams near-resonant to a qubit's Raman transition, and microwave / RF B-fields near-resonant to a qubit's transition. DC or AC electric fields from trap electrodes, on the other hand, are not typically used as qubit drives because they are coupled only to the motion of an ion, not to its internal state.

[0142] Referring to Figures 18(A) through (E), the operation of the quantum gate can be demonstrated using an exemplary 1D linear N-qubit ion trap 3 with a microwave conductor 19 extending along the trap axis. The conductor 19 acts as a global qubit drive, generating the same B-field and B-field gradient at the qubit frequency and near-resonance in parallel across all zones. This corresponds to the Rabi frequency Ω(r) ≈ Ω0 + Ω'. r This results in the coupling of qubits, where r is the distance from the trap axis. Furthermore, for the sake of simplicity, it is assumed that Ω0 ≈ 0, which can be achieved by using multiple conductors or by "partial nulling" where the generated B field is polarized so as to avoid coupling of qubits.

[0143] A. Quantum gates with parallel dynamic control Referring to (A) of FIG. 18, a method of single qubit control is shown. Using parallel dynamic control, ion 7 can be moved to one of two locations in any zone. When s = 1, ion 7 is moved to location r1 = r, while when s = 0, ion 7 is moved to location r0 = 0. The locations are selected such that when the qubit drive is turned on, the ion at location 1 receives a Rabi frequency Ω ≈ Ω0 + Ω' r and the ion at location 0 receives a Rabi frequency Ω0 ≈ 0. When the drive is resonant with the qubit frequency, this generates the Hamiltonian of equation (7) shown below.

[0144] [Number]

[0145] In the above case, σ φ = cos φσ x + sin φσ y where φ and Ω can be tuned by adjusting the phase and amplitude of the global drive respectively. When the drive is detuned from the qubit by δ ≫ Ω, instead, the Hamiltonian of equation (8) shown below is obtained.

[0146] [Number]

[0147] Using this toolbox, any single qubit rotation can be performed in parallel for any subset of qubits. For example, the Hadamard gate for qubits (1, 3, 4) can be performed by setting s1 = s3 = s4 = 1, φ = -π / 4, and applying H φ for a time t = π / (2Ω).

[0148] Due to unavoidable experimental imperfections, it is impossible to guarantee that Ω0 = 0, and the qubit at location 0 will always receive some residual Rabi frequency Ω0 = ε × Ω. This, if not corrected, is approximately ε per qubit per gate. 2 This results in a degree of fidelity. Several methods exist to mitigate this error. Firstly, if ε is known, it is possible to reverse the undesirable rotation with an additional layer of pulses. Secondly, whether ε is known or not, composite pulse schemes such as SK1 or CORPSE can be used to cancel out all systematic imperfections, see Non-Patent Document 15 mentioned above.

[0149] Referring to Figure 18(B), a similar method can be used to implement a multi-qubit gate using parallel dynamic control, where pairs and dynamic electrodes at the zone intersections are used to tune the motion frequency. i ,s i If (+1)=(1,1), the motion frequency of the Hamiltonian pair represented by equation (10) for the qubit represented by equation (9) is tuned to ω1.

[0150]

number

[0151]

number

[0152] (s i ,s i When (+1) = (0,0), the motion frequency is tuned to ω0. The global drive parameters are tuned to ω1, that is, they produce the actual interaction when ω = ω1, while leaving the ions at motion frequency ω1 unchanged. Thus, the Hamiltonian is generated.

[0153] Similar to the case of a single qubit, composite pulses can be used to suppress fidelity associated with undesirable spin-motion coupling in the zone where s=0.

[0154] In Figure 18(B), the tuning of the motion frequency is shown by the displacement of the qubit from the trap axis. However, it is possible to tune the motion frequency by adjusting the curvature of the shim while keeping the position of the qubit the same.

[0155] B. Quantum gates using sim multiplexing The method described above allows for the parallel implementation of single-qubit and multi-qubit gates, but the gate angles and phases are set globally. While this is sufficient for fault-tolerant regimes, in NISQ regimes, it is highly desirable to implement parallel control where gate parameters can be adjusted locally. Figures 18(C) and (D) illustrate how sim multiplexing can be used for the aforementioned purposes.

[0156] First, referring to Figure 18(C), using shim multiplexing, the shim voltage in every zone is V i Set to local ion displacement r i ∝V i This displacement results in Ω i ≒Ω' r ∝V i It can be directly converted to the Rabi frequency. Therefore, Shim multiplexing allows the Hamiltonian represented by equation (11) below to be implemented, Ω i It is locally adjustable.

[0157]

number

[0158] The Hamiltonian in equation (11) allows for the parallel rotation of a single qubit at an angle that is locally tunable across the entire processor, while using only a single qubit drive.

[0159] Next, referring to Figure 18(D), we see Ω', similar to what was described above. i By implementing the Hamiltonian shown in equation (12) below, which is locally tunable, and by locally tuning the motion frequency and direction of motion, it is possible to implement parallel multi-qubit gates with locally tunable pulse angles.

[0160]

number

[0161] However, the lack of local phase control limits the use of composite pulses to reduce unknown coherent errors in these schemes.

[0162] C. Quantum gates using modulator multiplexing Parallel local amplitude and phase control of a single qubit can be achieved by multiplexing on-chip signal modulators. Previously, the focus has been on developing on-chip qubit drive modulators, such as laser amplitude modulators. Alternatively, the qubit drive can be locally tuned in terms of Rabi frequency and phase using globally conserved but locally multiplexed low-frequency voltage sources.

[0163] Referring to Figure 18(E), a possible architecture is shown in which single-qubit control is achieved by a global qubit drive combined with a local low-frequency (e.g., 1–10 MHz) electric field generated by a locally tunable IQ mixer 150. Mixer inputs I1,I N ,Q1,...,Q NThis can be controlled by multiplexing a small number of voltage sources. This can be used to implement the Hamiltonian shown in equation (13) below.

[0164]

number

[0165] Ω i This can be adjusted by tuning the amplitude of the AC electric field, φ i This can be adjusted by tuning the phase of the AC electric field. The Hamiltonian in equation (13) allows for fully parallel 1-qubit control, and the resulting phase control allows for the use of composite pulses to suppress systematic calibration errors.

[0166] D. Summary Table 1 summarizes the available 1-qubit and 2-qubit control Hamiltonians for different parallelization methods.

[0167] [Table 1]

[0168] The examples presented above demonstrate parallel one-qubit and two-qubit control in traps using a global microwave gradient, but these methods are similarly applicable to laser-based gates. In this case, the trap voltage is used to parallel-shift ions within the laser beam, thereby modifying the resulting laser intensity and, consequently, the Rabi frequency of the photo-ion interaction. Furthermore, the method can be extended to multi-qubit gates with more than two qubits.

[0169] Wiring of V.1000 qubit chip Referring to Figure 19, the electrical wiring arrangement of the N-qubit chip 160 is shown. In this case, N = 1000. However, N may be between 100 and 1000, or between 1000 and 10000 or more.

[0170] In this example, there are 10 dynamic electrodes 4 and 10 shim electrodes 6 for every 7 qubits, resulting in a total of 20 electrodes for every 7 qubits. In this case, the height h of the ion-electrode is approximately 50 μm, and a 2D layout with k=6 qubits per junction is used. In the so-called "optimal configuration," this requires an array of m × n zones where (m,n)=(54,19). Assuming a zone size of 10h × 10h (as described in Section IIIA above), this requires a footprint of at least 27 mm × 10 mm.

[0171] Dynamic operation is performed using four different zone types of a 2D architecture, each performing one of two possible actions. This requires a total of 80 off-chip voltage sources 34 (Figure 2). Action selection is performed via a 4-wire SPI interface (not shown) using the action selection word s=(s1,s2,...,s N This is done by sending a selected word s. Assuming an SPI data streaming rate of f = 50 Mb / s, the selected word s can be updated in 20 μs. Since this update is faster than the timescale of a typical transport operation (t0 = 100 μs for one swap), the SPI interface does not become a bottleneck for dynamic performance.

[0172] Multiplexed operation is performed by connecting each shim voltage source 44 to 128 shim electrodes 6. Therefore, approximately 10000 / 128 ≈ 78 shim voltage sources 34 are arranged. Each shim electrode 6 is connected to an on-chip capacitor 20 of C=30pF (Figure 15), and all capacitors 20 can be arranged in a single layer without increasing the device footprint. The digital shim multiplexer 26 is controlled by an on-chip shift register (not shown) and switches every 3μs. Therefore, shim switching requires only two external inputs, namely a 333kHz clock (not shown) and an enable line (not shown). This is a careful approach, and the number of shim voltage sources 34 can be significantly reduced by decreasing the number of shim electrodes 6 per qubit 7 and increasing the number of shim electrodes 6 per shim voltage source 44.

[0173] The core of QPU2 is an N-qubit ion trap in the surface layer, which can take the form of a multilayer surface trap.

[0174] On the uppermost layer 161 of the N-qubit ion trap 3, approximately 20,000 electrodes 4, 5, and 6 capture and transport 1,000 qubits provided by 2,000 (i.e., half are used to encode qubits and the other half are used as auxiliary readouts in the circuit).

[0175] One or more embedded ion trap layers 162 may be used to (a) route and deliver voltage to the top layer electrode, (b) route current and deliver the B-field and B-field gradient of a qubit drive to the ion, (c) route a laser to the ion via integrated photonics, and (d) collect and / or read out ion fluorescence. The electrode voltage is delivered from the bottom layer 162 of the chip implementing the switch network 22 via approximately 20,000 vias 163. Alternatively, the switch network may be implemented on a separate chip 164 connected to the ion trap chip 3 via a high-density IC interconnect with approximately 20,000 bumps (not shown). The separate chip 164 may additionally or alternatively house other circuits (not shown) that provide signal conditioning, for example, and may include DC filters, RF resonators, and microwave impedance matching circuits.

[0176] The first embedded layer 1621 (or "capacitor layer") may contain approximately 10,000 thin-film planar capacitors 20 (Figure 15), one for each shim electrode 6.

[0177] The second buried layer 1622 (or “switch layer”) may provide, for example, (a) about 10,000 dynamic electrode switches 23 (Figure 2), each made up of two transmission gates 87 (Figure 11C), (b) about 10,000 shim electrode switches 136 (Figure 17), each made up of one transmission gate, (c) a digital serial-to-parallel converter 82 (Figure 11A) for dynamic electrode control, and (d) a digital demultiplexer 135 (Figure 17) for shim control.

[0178] The allocation of QPUs to specific functional layers, as well as the strict ordering and stack-up of these layers, may differ from those presented above.

[0179] Table 2 summarizes the electrical connections to a 1000-qubit chip. To perform arbitrary qubit reconstruction on a 1000-qubit chip, a total of 167 wire bonds are sufficient. In addition to transport voltage lines, additional electrical connections may be required to execute quantum gates. To execute non-laser quantum gates, a small number (1 to 10) of current lines are added to simultaneously generate magnetic field gradients across multiple zones throughout the chip. Furthermore, a pulse trap requires a small number of high-voltage inputs to generate trapping potentials. Therefore, fewer than 200 electrical input connections are sufficient to control a 1000-qubit ion-trap quantum computer.

[0180] [Table 2]

[0181] Additional optical control may be used to perform dissipative operations such as state preparation, ion cooling, and qubit measurement. In this architecture, these operations can be performed globally by connecting a small number of optical fibers to the chip and then passively splitting those optical fibers between zones to enable light delivery. Furthermore, qubit readout can be performed by integrating multiplexed photodetectors into the QPU.

[0182] 〔change〕 It will be understood that various modifications may be made to the embodiments described herein. Such modifications may include equivalent and other features already known in the design, manufacture, and use of charged particle trapping devices and their components, which may be used in place of or in addition to the features already described herein. Features of one embodiment may be replaced or supplemented by features of another embodiment.

[0183] A charged particle trapping device does not necessarily have to be a quantum information processing (or "qubit" processing) device such as a quantum computer; for example, it could be an atomic clock.

[0184] While the claims set forth in the claims below are constructed in this application for specific combinations of features, it should be understood that the scope of the disclosure of the present invention also includes all new features or all new combinations of features disclosed herein, or all generalizations thereof, whether they relate to the same invention claimed herein in any of the claims and whether they mitigate any or all of the same technical problems as the present invention. The applicants hereby notify that new claims may be made for such features and / or combinations of such features during the proceedings of this application or any further application derived therefrom. [Explanation of Symbols]

[0185] 1. Quantum Computing Systems 2 QPUs 3 N qubit ion trap 4. Dynamic electrode, transport electrode, first electrode, second electrode, electrode 5 RF electrode 6. Quasi-static electrodes, shim electrodes 7 Charged particles 71 qubits 72 qubits 7 A First qubit 7 B Second qubit 8 Main surface 9 circuit boards 10 lines 11 Center axis 12 columns 13 Arrays 14 Blank electrodes 15 Surfaces, Groups 151 Group 1 152nd Group 19 Serial interface, microwave conductor 20 On-chip capacitor, capacitor 21 Switch / multiplexing network 22 Switch network 23 Switch 24 Switch line 25 Multiplexing network 26 Demultiplexer 27 Multiplexing line 31 Transport controller 34 Transport voltage source, transport DAC 34 ODD Voltage source 34 EVEN Voltage source 36 First transport control line 37 Filter 39 Second transport control line 41 ODD Odd zone 41 EVEN Even zone<\ 44 Shim voltage source 46 Shim control line 511 Trap zone 512 Trap zone 51 ODD Zone 51 EVEN Zone[[ID=NO]] 61 Well 62 Crystal 621 First well 622 Second well 63 C Central channel 63 UL First channel 63 UR Second channel 63 LR Third channel 63 LL Fourth channel 711 First respective location 712 Second respective location 81 Switch system 82 Serial-parallel register 83 + Rails 84 - Rail 85 Selector switch 86 Pass Transistors 87 Transmission Gate 88 NMOS / PMOS transistor pairs 89 NMOS / PMOS transistor pairs 90 Shunt Capacitor 101 segments 102 X Junction 131 Multi-stage switch network 132 switches 133 Input 134 Output 135 Digital Demultiplexer 136 switches 150 IQ Mixer 160 N qubit chip 161 Top Floor 162 Ion trap layer 162 Lowest level 1621 First buried layer 1622 Second buried layer 163 Beer 164 separate chips 165 Wire Bond

Claims

1. A charged particle trap (3), A charged particle trap (3) includes a set of trap electrodes (4, 5, 6) including a set of electrodes (6) for generating an electric field for manipulating charged particles, A voltage source (44) having an output, A demultiplexer (26) having an input and a plurality of outputs, wherein the output of the voltage source is coupled to the input of the demultiplexer, and each of the plurality of outputs of the demultiplexer is coupled to each of the electrodes of the set of electrodes, The demultiplexer is configured to sequentially charge the electrodes in a first phase and to be disconnected from the electrodes for a given time in a second phase to provide a relatively low-noise environment in which the operation can be performed on the charged particles.

2. The demultiplexer (26) further comprises at least one additional electrode coupled to the demultiplexer, The apparatus according to claim 1, wherein the demultiplexer is configured to be connected to the at least one further electrode in the second phase.

3. The apparatus according to claim 1 or 2, further comprising a set of capacitors (20), wherein each electrode (6) of the set of electrodes is provided with a capacitor arranged between the electrode and ground.

4. The charged particle trap includes a charged particle trap tip (9) that supports the charged particle trap, The apparatus according to any one of claims 1 to 3, wherein a capacitor (20) is integrated on the charged particle trap chip.

5. Charged particle trap chip (9), The charged particle trap chip comprises at least one further chip stacked on top of the charged particle trap chip, The apparatus according to any one of claims 1 to 3, wherein the capacitor (20) is integrated into the at least one further chip.

6. The apparatus according to claim 4, wherein the voltage source (44) is integrated on the charged particle trap chip or at least one further chip.

7. The apparatus according to any one of claims 1 to 6, wherein the given time is sufficient to execute a series of at least one quantum gates.

8. The apparatus according to any one of claims 1 to 6 or 7, wherein the given time is between 1 μs and 1 s.

9. The apparatus according to any one of claims 1 to 6, wherein the given time is sufficient to transport at least one charged particle from a first arrangement of charged particles to a second different arrangement of charged particles.

10. The apparatus according to any one of claims 1 to 6 or 9, wherein the given time is between 1 ms and 500 ms.

11. The apparatus according to any one of claims 1 to 6 or 9, wherein the given time is between 1 μs and 1800 s.

12. The apparatus according to claim 11, wherein the given time is between 60 s and 1000 s.

13. The apparatus according to any one of claims 1 to 12, wherein each electrode (6) is layered and has thickness, and each electrode has at least one dimension (d1, d2) perpendicular to the thickness between 10 μm and 2000 μm.

14. It also includes a sim controller (41), The apparatus according to any one of claims 1 to 13, wherein the shim controller is configured to cause charging of the electrodes (6) of the set of electrodes.

15. The apparatus according to claim 14, wherein the shim controller (41) is configured to cause the electrodes (6) of the set of electrodes to charge to a level appropriate for compensating for the stray electric field.

16. The apparatus according to any one of claims 1 to 15, configured to be a quantum computer.

17. The apparatus according to any one of claims 1 to 16, A system comprising at least a cryogenic system for cooling the charged particle trap (3).

18. A method for operating the apparatus according to any one of claims 1 to 16, or the system according to claim 17, In the first phase, the steps include sequentially charging the electrodes with the demultiplexer, A method comprising the step of, in a second phase, disconnecting a demultiplexer from the electrode for a given time in order to provide a relatively low-noise environment in which an operation can be performed on the charged particles.

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