Adaptive channel equalization for duo-binary transceivers

Abstract

A system and method relating to a duo-binary transceiver having adaptive channel equalization are described. An exemplary method for adapting the channel between a first duo-binary transceiver and a second duo-binary transceiver different from the first duo-binary transceiver is described, wherein the transmitter includes a feedforward equalizer (FFE). The method includes, in a receiver associated with the second duo-binary transceiver, selectively processing information from only the upper eye or lower eye of the received duo-binary signal at a given time to determine an update factor for the feedforward equalizer (FFE) of the transmitter associated with the first duo-binary transceiver. The method further includes transmitting the update factor to the transmitter using a back channel between the transmitter and the receiver. The method further includes transmitting a duo-binary signal that is equalized using the update factor for the FFE of the transmitter associated with the first duo-binary transceiver.

Description

[Background technology]

[0001] background

[0001] Many systems require high data rate communication between components associated with such systems. Such high data rate communication is made possible by transceivers using various multilevel modulation schemes, including duo-binary modulation, 3-level pulse amplitude (PAM3) modulation, or 4-level pulse amplitude (PAM4) modulation. Such multilevel modulation schemes are preferred because they typically require a Nyquist frequency for the data signal that is lower than the Nyquist frequency for the non-zero return (NRZ) data signal. Each of these multilevel modulation schemes presents various challenges depending on the context in which such modulation schemes are used.

[0002]

[0002] Duo-binary modulation-based transceivers are promising candidates for use in systems requiring high data rate communication because duo-binary modulation provides similar spectral efficiency to PAM4 modulation, but requires only three signal levels instead of the four signal levels required by PAM4 modulation. Furthermore, duo-binary modulation is less susceptible to crosstalk than PAM3 modulation. [Overview of the Initiative] [Problems that the invention aims to solve]

[0003]

[0003] Even when duo-binary modulation schemes are superior in certain scenarios, high data-rate communications, including the use of high-frequency signals, are subject to intersymbol interference (ISI), particularly due to frequency-dependent channel attenuation. While previous methods have used transmitters with feedforward equalization (FFE) to address such ISI, improved systems and methods are still needed to address these issues in the context of high data-rate communication systems. [Means for solving the problem]

[0004] overview

[0004] In one example, the present disclosure relates to a method for adapting a channel between a first duo-binary transceiver and a second duo-binary transceiver different from the first duo-binary transceiver, wherein the transmitter includes a feedforward equalizer (FFE). The method may include, in a receiver associated with the second duo-binary transceiver, selectively processing information from only the upper eye or lower eye of the received duo-binary signal at a given time to determine an update coefficient for the FFE of the transmitter associated with the first duo-binary transceiver.

[0005]

[0005] The method may further include transmitting an update factor to the transmitter associated with the first duo-binary transceiver using a back channel between the transmitter associated with the first duo-binary transceiver and the receiver associated with the second duo-binary transceiver. The method may further include transmitting a duo-binary signal, which is equalized using the update factor for the FFE of the transmitter associated with the first duo-binary transceiver, to the receiver associated with the second duo-binary transceiver.

[0006]

[0006] In another example, the present disclosure relates to a system for adapting a channel between a first duo-binary transceiver and a second duo-binary transceiver different from the first duo-binary transceiver, wherein the transmitter includes a feedforward equalizer (FFE). The system may further include logic for determining an update coefficient for the FFE of the transmitter associated with the first duo-binary transceiver by selectively processing information from only the upper eye or lower eye of the received duo-binary signal with given time information.

[0007]

[0007] The system may further include a backchannel between a transmitter associated with a first duobinary transceiver and a receiver associated with a second duobinary transceiver for transmitting an update coefficient to the transmitter associated with the first duobinary transceiver, whereby the transmitter is operable to transmit a duobinary signal equalized using the update coefficient for the FFE of the transmitter to the receiver associated with the second duobinary transceiver.

[0008]

[0008] In yet another example, the present disclosure relates to a method of adapting a channel between a transmitter associated with a first duobinary transceiver and the first duobinary transceiver and a second duobinary transceiver different from the first duobinary transceiver, the transmitter including a feed forward equalizer (FFE). The method may include, at a receiver associated with the second duobinary transceiver, (1) selectively processing level information from only the upper eye or lower eye of the received duobinary signal at a given point in time to determine an update coefficient for the FFE of the transmitter, and (2) selectively processing peak information from only the upper eye or lower eye of the received duobinary at a given point in time to automatically control the gain of one or more variable gain amplifiers of the receiver.

[0009]

[0009] The method may further include transmitting an update coefficient to a transmitter associated with a first duobinary transceiver using a backchannel between the transmitter associated with the first duobinary transceiver and a receiver associated with the second duobinary transceiver. The method may further include transmitting a duobinary signal equalized using an update coefficient for the FFE of a transmitter associated with the first duobinary transceiver to a receiver associated with the second duobinary transceiver.

[0010]

[0010] This summary is provided to introduce selected concepts in a simplified form that will be further described later in the detailed description. This summary is not intended to identify the key features or essential features of the subject matter recited in the claims, nor is it intended to be used to limit the scope of the subject matter recited in the claims.

[0011] Brief Description of the Drawings

[0011] The present disclosure is illustrated by way of example and is not limited by the accompanying drawings in which like reference numerals indicate like elements. The elements in the drawings are illustrated for simplicity and clarity and are not necessarily drawn to scale.

Brief Description of the Drawings

[0012] [Figure 1]

[0012] It is a block diagram of an exemplary system including a duo-binary transceiver configured to transmit and receive data over a channel. [Figure 2A]

[0013] It shows a block diagram of an exemplary transmitter used in the duo-binary transceiver of FIG. 1. [Figure 2B]

[0013] It shows a block diagram of an exemplary receiver used in the duo-binary transceiver of FIG. 1. [Figure 3]

[0014] It is a block diagram of a duo-binary transceiver having adaptive channel equalization. [Figure 4]

[0015] It shows exemplary code for a data slicer, an error slicer and an automatic gain controller (AGC) related to the duo-binary transceiver of FIG. 3. [Figure 5]

[0016] It shows adaptive equalization by processing non-return-to-zero (NRZ) data selectively derived from the upper eye or lower eye of a duo-binary signal. [Figure 6]

[0017] It shows exemplary waveforms of transmitted data and received data. [Figure 7]

[0018] An example shows an encoder coupled to an FFE for a transmitter. [Figure 8]

[0019] One example demonstrates how to determine the update coefficients for the FFE in Figure 7 by performing a convolution between the current set of coefficients and the encoder response. [Figure 9]

[0020] A flowchart illustrating an exemplary method for performing adaptive channel equalization as part of a duo-binary transceiver is shown. [Figure 10]

[0021] Another flowchart illustrating an exemplary method for performing adaptive channel equalization as part of a duo-binary transceiver is shown. [Modes for carrying out the invention]

[0013] Detailed explanation

[0022] The examples described herein relate to systems and methods for duo-binary transceivers having adaptive channel equalization. Certain systems and methods relate to adapting a channel between a first duo-binary transceiver and a second duo-binary transceiver different from the first, wherein the transmitter includes a feedforward equalizer (FFE). Certain examples of the disclosure also relate to transceiver architectures for implementing duo-binary channels, including digital solutions for adapting the channel to minimize intersymbol interference (ISI) at the receiver. Further described below, in one example, the transmitter of a duo-binary transceiver features feedforward equalization (FFE) at the transmitter. A back channel between the transmitter and receiver allows the receiver to adapt coefficients related to the feedforward equalizer (FFE) at the transmitting end. An exemplary receiver features a duo-binary equalizing eye with two thresholds for reconstructing data from the upper and lower eyes, and a slicer with thresholds for measuring the heights of the upper and lower eyes. Another slicer with two thresholds is used to provide edge information. This receiver configuration provides reconstructed data information to the Clock Data Reconstruction (CDR) circuit. The receiver configuration further uses the level information to provide FFE coefficient information to the transmitter using the back channel. In this example, equalization processes the level information using the code-code least squares mean (SS-LMS) algorithm to extract the correlation between the current data symbol and the previous or subsequent data symbol. This correlation provides the transmitter with the necessary changes to the pre-cursor and post-cursor coefficients. The equalization solution uses the transmitter FFE and channel inter-code interference (ISI) together to obtain 1+Z -1 Generate a filtered response.

[0014]

[0023] Figure 1 is a block diagram of an exemplary system 100, which includes a duo-binary transceiver configured to transmit and receive data on a channel. System 100 includes device 102, device 104, duo-binary transceiver 106, and duo-binary transceiver 108. In this example, device 102 is coupled to duo-binary transceiver 106, and device 104 is coupled to duo-binary transceiver 108. Each of device 102 and device 104 may include components that enable one or more of the following functions: storage, computing, or networking. Depending on the configuration, each of device 102 and device 104 may combine one or more of these functions. Duo-binary transceiver 106 may communicate with duo-binary transceiver 108 via a transmission medium 120. The transmission medium 120 may be an optical transmission medium, an electrical transmission medium, an electro-optical transmission medium, and the like. As an example, the transmission medium 120 may include channels consisting of bidirectional links 122 and 124 that can exchange signals between a duo-binary transceiver 106 and a duo-binary transceiver 108. Such bidirectional links 122 and 124 may be implemented using an electrical conductor (e.g., copper) or an optical material (e.g., optical fiber). The transmission medium 120 may further include a back channel 126 that enables each duo-binary transceiver to provide feedback regarding adaptive channel equalization.

[0015]

[0024] An interface card used in any device requiring communication over a high data rate channel may include a duo-binary transceiver 106. An exemplary interface card includes one that conforms to one or more standards for high-speed interface cards. For example, an interface card may conform to one or more versions of the Peripheral Components Internet Express (PCIe) standard. Other interface cards conforming to other standards may also include one or more duo-binary transceivers. While Figure 1 shows system 100 as including a specific number of components arranged in a particular manner, system 100 may include fewer or additional components arranged differently. For example, as part of a single system-on-chip (SoC) or as another such arrangement, device 102 may be integrated with the duo-binary transceiver 106. The duo-binary transceiver 106 may be implemented as part of a controller, such as a memory controller (e.g., any type of dynamic data rate (DDR) controller), a network controller, or a bus controller.

[0016]

[0025] Duo-binary modulation shapes the data stream by limiting its spectrum to lower frequencies. (1+Z in the transmitter) -1Instead of a transfer function, the proposed duobinary scheme uses channel inter-code interference (ISI) to generate a duobinary response at the receiver. An adaptive engine measures the ISI at the receiver and adjusts the equalization at the transmitter to generate the duobinary response. This type of adaptation using a receiver and transmitter working together reduces the requirement for a continuous-time linear equalizer (CTLE) at the receiver. The adaptive engine can process one eye (upper or lower eye) simultaneously and provide feedforward equalization (FFE) coefficient information to the transmitter. Before adaptation, the duobinary upper or lower eye is mapped to a non-zero return (NRZ) eye. A code-code least squares mean mean (SS-LMS) algorithm processes the NRZ eye, data information, and level information to extract the correlation between the current data symbol and the previous or subsequent data symbol. This correlation provides the transmitter with the necessary changes to the pre-cursor and post-cursor coefficients.

[0017]

[0026] Transmitter 1+Z -1 A duo-binary link implemented as a filter cannot use channel ISI, placing a burden of channel equalization on the receiver. The proposed example described herein uses the transmitter FFE and channel ISI together to achieve 1+Z -1 Generates a filtered response. This solution reduces the equalization requirement at the receiver. 1+Z -1 Instead of an FFE after the filter, two filters are combined into a single FFE filter, and the FFE filter is adapted using receiver-provided information. The significance of this design is to remove complexity from the receiver, which would incur higher power consumption due to the implementation of equalization using analog circuitry. Instead, the equalization adaptation is moved to the transmitter, where equalization is performed in the digital domain. Advantageously, this results in both lower power consumption and savings in terms of the area occupied by the duo-binary transceiver as part of the integrated circuit.

[0018]

[0027] Figures 2A and 2B show block diagrams of an exemplary transmitter 200 (e.g., related to the duo-binary transceiver 106 in Figure 1) and an exemplary receiver 250 (e.g., related to the duo-binary transceiver 108 in Figure 1), respectively. Each duo-binary transceiver includes both a transmitter and a receiver that enable bidirectional transmission of data signals and other signals. The transmitter 200 is configured to transmit signals over a transmission medium (e.g., the transmission medium 120 in Figure 1). The transmitter 200 is coupled to terminals labeled TXP and TXN, which are coupled via channel 202 to terminals labeled TXP and TXN associated with the receiver 250. In this example, channel 202 is an exemplary transmission medium for the exchange of data signals between the transmitter 200 and the receiver 250. Channel 202 is configured for the transmission of different signals modulated as duo-binary signals. In addition, a back channel 204 is provided between the transmitter 200 and the receiver 250 to enable adaptive feedback from the receiver 250 to the transmitter 200.

[0019]

[0028] Continuing to refer to Figure 2A, the data for transmission (labeled TXDATA[N:0]) is received by transmitter 200 from a device (e.g., device 102 in Figure 1) via transmitter interface 210. This example shows N bits of data being received in parallel via the transmitter interface. Transmitter interface 210 can receive both the system clock (labeled SYSCLK) and the transmitter clock (labeled TXCLK).

[0020]

[0029] The transmitter 200 further includes a feedforward equalizer (FFE) 220. The FFE 220 includes circuitry that applies tap coefficients to convert non-zero return (1 bit / unit interval (UI)) data into duo-binary data. The tap coefficients are generated by a transmitter FFE coefficient generator 222. An exemplary FFE has taps for two pre-cursors, a main-cursor, and two post-cursors. Converting the NRZ data into a duo-binary signal yields a three-level signal containing two eyes stacked on top of each other.

[0021]

[0030] Referring further to Figure 2A, the transmitter 200 further includes a serializer 230 coupled to receive the output of the FFE 220. The serializer 230 is configured to convert the parallel data stream received from the FFE 220 into a serial data stream. The output of the serializer 230 is provided to a driver 240, which is then coupled to a T-COIL & ESD block 242. The driver 240 is further configured to provide a clock that is divided into quarter rates and transmitted to the receiver 250 along with the serialized data stream. The driver 240 is further configured to provide a transmitter loopback signal (TXLPBK) containing management and control information. The T-COIL & ESD block 242 includes an inductor for impedance matching with channel 202. In addition, the T-COIL & ESD block 242 includes an electrostatic discharge circuit including a diode for electrostatic discharge protection. The T-COIL & ESD block 242 is coupled to channel 202 via terminals TXP and TXN. Figure 2A shows transmitter 200 as including a specific number of components arranged and coupled in a particular way, but transmitter 200 may include fewer or additional components arranged and coupled differently. Figure 2A shows a clock transfer series link, but the series link may also be implemented using clock embedding.

[0022]

[0031] Figure 2B is a block diagram of an exemplary receiver 250 associated with a duo-binary transceiver with adaptive channel equalization (e.g., duo-binary transceiver 108 in Figure 1). Each duo-binary transceiver includes both a transmitter and a receiver, enabling bidirectional transmission of data signals and other signals. Receiver 250 can receive duo-binary data from channel 202 to T-COIL&ESD block 252 via terminals labeled RXP and RXN. T-COIL&ESD block 252 includes an inductor for impedance matching with channel 202. In addition, T-COIL&ESD block 252 includes an electrostatic discharge circuit including a diode for electrostatic discharge protection. The output of T-COIL&ESD block 252 is a continuous-time linear equalizer (CTLE) and a variable-gain amplifier (VGA) 254. The CTLE is a linear filter configured to attenuate low-frequency signals, amplify high-frequency signals, and compensate for some of the channel loss. One or more VGAs are configured to amplify the signal output by the CTLE. Each of the one or more VGAs can provide a variable amount of gain to the signal. The gain of the VGAs can be changed using an automatic gain controller (AGC), as described below. The AGC may be included as part of the VGA adaptive block 270. Control and management information is provided to the CTLE&VGA254 via the receiver loopback signal (RXLPBK).

[0023]

[0032] Continuing to refer to Figure 2B, the output of CTLE&VGA254 is provided to the deserializer 256. The unserialized data is provided as parallel data (RXDATA[N:0]) via the receiver interface 290. The receiver clock (RXCLK) is also output via the receiver interface 290. The receiver 250 further includes a clock data restoration (CDR) circuit 280, which includes a phase detector and a phase interpolator. The CDR circuit 280 receives digital data from the slicer and extracts the clock signal from the received signal. Edge information may be provided to the CDR circuit using another slicer having two thresholds. The CDR circuit uses the edge information to align the clock phase. The clock signal is provided to a phase interpolation (PI) and sampling clock generator 282, which provides the phase interpolation and clock signal to the slicer and deserializer 256. Figure 2B shows receiver 250 as containing a specific number of components arranged and combined in a particular manner, but receiver 250 may contain fewer or additional components arranged and combined differently. For example, receiver 250 may contain additional filters, equalizers, or other components not shown in Figure 2B.

[0024]

[0033] Figure 3 is a block diagram of a duo-binary transceiver 300 having components for restored data, error data, and level data used in an adaptive channel equalization algorithm. A duo-binary transceiver 300 is shown having specific sub-components for a transmitter portion 310 and a receiver portion 350 that are most relevant to a further description of the adaptive channel equalization algorithm. The transmitter portion 310 includes components related to the transmitter 210 of FIG. 2, and the receiver portion 350 includes components related to the receiver 250 of FIG. 2. The two portions are coupled via a channel 302. The transmitter portion 310 includes an FFE 320, a serializer 330, and a driver 340. As described above with respect to the FFE 220 of FIG. 2, the FFE 320 includes circuitry that applies tap coefficients to convert non-zero return (1 bit / UI) data to duo-binary data. N streams of data are serialized using the serializer 330 and transmitted after being processed by the driver 340.

[0025]

[0034] Continuing to refer to FIG. 3, after the processing described in FIG. 2 and after the transmitted signal is received by the receiver portion 350, the received signal is processed by a CTLE&VGA 354 having a similar function as described with respect to the CTLE&VGA 254 of FIG. 2. The output of the CTLE&VGA 354 is provided to a data slicer constructed such that one set of slicers compares the upper eye of the duo-binary signal to one threshold voltage (e.g., VTH1) and another set of slicers compares the lower eye of the duo-binary signal to another threshold voltage (e.g., VTH0). As shown in FIG. 3, a quarter-rate clock is converted by a delay lock loop (DLL) 356 into a four-phase clock (Φ0, Φ 90 , Φ 180 and Φ 270 ) output by a clock distribution block 358). Different phases of the quarter clock signal are used to time the data slicer. Further details regarding the processing of the duo-binary signal by the data slicer are provided with respect to FIG. 4. The clock distribution block 358 provides a clock signal (Φ E ) to an edge slicer 364 and another clock signal (ΦL ) is further configured to provide the error slicer 366. Figure 3 shows the duo-binary transceiver 300 as including a certain number of components arranged in a particular way, but the duo-binary transceiver 300 may include additional or fewer components arranged differently.

[0026]

[0035] Figure 4 shows exemplary codes for a data slicer, error slicer, and automatic gain controller (AGC) associated with the duo-binary transceiver 300 of Figure 3. As described above, the data signal lies between the three levels associated with the 3-level duo-binary signal. A data slicer 410 performing the function corresponding to code 420 is shown in the upper left of Figure 4. An error slicer 430 performing the function corresponding to code 440 is shown in the lower left of Figure 4. An exemplary code 460 for the automatic gain controller (AGC) 450 is shown on the right side of Figure 4. The data slicer 410 processes the upper eye and / or lower eye by comparing the received level with voltage thresholds (e.g., VTH1 and VTH0) shown in Figure 4. Comparing the received signal with voltage threshold VTH1 yields data (D) with a value of 1 or 2. Comparing the received signal with voltage threshold VTH0 yields data (D) with a value of 1 or 0. This function can be implemented by implementing code 420 using appropriate hardware.

[0027]

[0036] Continuing to refer to Figure 4, the error slicer 430 processes the upper and / or lower eye by comparing the received level with reference voltages (e.g., VREFP and -VREFP) shown in Figure 4. This comparison of the received signal with these reference voltages is an effective comparison between the eye peaks in each direction to determine the range of the signal intersecting the positive maximum value (e.g., VREFP) and the negative maximum value (e.g., -VREFP). Comparing the received signal with the positive VREFP voltage yields an error (E1) value for the upper eye, which has a value of either 1 or 0. Comparing the received signal with the negative VREFP voltage yields an error (E0) value for the lower eye, which also has a value of either 1 or 0. This function can be implemented by implementing the Verilog code 440 using appropriate hardware.

[0028]

[0037] Furthermore, referring to Figure 4, using the increase or decrease in gain for each step (gstep) value for the automatic gain controller (AGC) 450 (calculated using the hardware implementation of Verilog code 460), the following equation (VGAGAIN(n)=VGAGAIN(n-1)+u g The update value for the gain relative to VGA is determined using ×gstep). Figure 4 shows a data slicer 410 and an error slicer 430 that process both the upper and lower eyes of a duo-binary signal, but it is not necessary to process both eyes for duo-binary adaptive equalization. Instead, only the upper or lower eye may be processed. This may allow for implementations that include slicers that process only the upper or lower eye, resulting in savings in both domain and power.

[0029]

[0038] Figure 5 shows a duobinary adaptive equalization block 500 of a duobinary transceiver configured to selectively process non-zero return (NRZ) data derived from the upper or lower eye of a duobinary signal. The duobinary adaptive equalization block 500 includes processing the received duobinary signal using a data slicer 510 and an error slicer 520 used to analyze the upper and lower eyes. The duobinary adaptive equalization block 500 further includes a duobinary signal-to-NRZ signal mapper 530, control logic 540, and a transmitter back-channel adaptive block 550. The data slicer 510 and the error slicer 520 perform similar functions to those described above with respect to Figure 4. For each time instance N, the data signal for the upper eye (D1(N)) and the data signal for the lower eye (D0(N)) are output by the data slicer. These data signals are then provided to the "duobinary signal-to-NRZ signal mapper" 530. Similarly, for each time instance N, the error signal (E1(N)) for the upper eye and the error signal (E0(N)) for the lower eye are output by the error slicer. These error signals are then provided to the "duobinary signal versus NRZ signal mapper" 530. These data and error signals are acquired as part of the processing of the duobinary signals received by the duobinary transceiver and do not need to be generated again for the duobinary adaptive equalization block 500.

[0030]

[0039] Continuing to refer to Figure 5, the upper and / or lower eyes of the duo-binary signal (which in this example has levels A, 0, and -A) are mapped to their respective NRZ signals using the duo-binary signal-to-NRZ signal mapper 530. Table 1 below shows an exemplary formula used to map the upper eye of the duo-binary signal to the NRZ signal. Similar formulas implemented via hardware may be used to map the lower eye of the duo-binary signal to the corresponding NRZ signal.

[0031] [Table 1]

[0032]

[0040] The control logic 540 includes other logic to enable control of the duo-binary signal-to-NRZ signal mapper 530 so that it selectively analyzes registers, finite state machines, and / or only the upper eye or lower eye simultaneously. Table 2 below shows an exemplary formula for equalizing the upper eye of a duo-binary signal. Similar formulas implemented via hardware may be used to equalize the lower eye of a duo-binary signal. In Table 2, EQ k The value for (n) corresponds to the equalization value for the k-th tap. Similarly, C k The value for (n) corresponds to the coefficient for the k-th tap and the nth time instance. The constant μ k This controls the step size of the adaptation performed by the transmitter back-channel adaptation block 550. The value of this constant is programmable, so that it can initially have a larger value and decrease over time to perform adaptation using finer steps.

[0033] [Table 2]

[0034]

[0041] In the example above, EQ k The expression for (n) is, Upper A u Level information for (n), I u Correlates with pre-cursor or post-cursor information represented by (nk). In an ideal scenario, the level information for the eye should be uncorrelated with the pre-cursor and post-cursor, so that the current data value is uncorrelated with the pre-processed data and the data to be processed in the future. However, if the duo-binary signal consistently outputs values ​​correlated with the pre-cursor or post-cursor, the channel requires equalization.

[0035]

[0042] Referring further to Figure 5, in this example, the sign-sign least squares mean (SS-LMS) algorithm is used to perform EQ adaptation as part of the transmitter back-channel adaptive block 550. The SS-LMS algorithm can be used because the level information is quantized to two values ​​(1 or 0) which are further mapped to one positive or one negative value. Thus, the absolute magnitude of the quantized data is not important, and the SS-LMS algorithm is only concerned with the sign of the level. Advantageously, this selective mapping and analysis saves power because only one of the two eyes is analyzed at a given time. In addition, the use of digital circuits for mapping and analysis instead of analog circuits saves power further. Although the EQ adaptive algorithm is described as the SS-LMS algorithm, other algorithms (e.g., sign-magnitude LMS algorithm) may also be used.

[0036]

[0043] Table 2 shows C k With respect to the operations related to coefficient generation, expressed by the formulas for (n) and C0(n), these calculations are performed for each decimation. As described above with respect to Figures 2B and 3, the deserializer 256 in Figure 2B transforms the received signal into four streams that are processed by different slicers that receive one of four phase clocks generated in response to the quarter-rate clock signal shown in Figure 3. The coefficients are generated using information from the patterns of the 16-bit or 32-bit data packets. This enables a many-minority type equalization decision by counting or otherwise accumulating information corresponding to the pattern being analyzed.

[0037]

[0044] The transmitter FFE is trained using the formulas shown in Table 3 below.

[0038] [Table 3]

[0039]

[0045] formula EQ k(n) performs the same function as described above with respect to Table 2. Table 4 below shows the level information (A j ), data information (I j and I k Values ​​and formulas for EQ k (n) shows an example value of the equalization value generated by (n). Level information (A j ) corresponds to the information generated by the error slicer described above, and the data information (I j and I k ) corresponds to the information generated by the data slicer. Therefore, in this example, level information (A j ) indicates whether the peak associated with the received duo-binary signal has a value greater than the reference voltage (e.g., VREFP). Furthermore, in this example, data information (I j and I k This shows a comparison of the received duo-binary signal with a voltage threshold, as described for the data slicer.

[0040] [Table 4]

[0041]

[0046] Figure 6 shows exemplary waveforms 600 of transmitted and received data for two examples from Table 4. Waveform 610 is I k The value of 1 for I j This corresponds to the transmitted data having a value of 1 for I. Waveform 650 is I k The value of 0 for I j This corresponds to transmitted data with a value of 1 for . Waveforms 620 and 630 are similar in that the received data information is the same as the transmitted data because the data value exceeds the central threshold. However, in the case of waveform 620 corresponding to Example 7 from Table 4, the level information (A j ) has a value of 0. Therefore, in this case, the determined EQ value is -1. In the case of waveform 630 corresponding to Example 8 from Table 4 above, the value for the received data information is the same as in the case of waveform 620, but the level information (A j ) has a value of 1. Therefore, in this case, the determined value of EQ is 1.

[0042]

[0047] Continuing to refer to Figure 6, as described above, waveform 650 is I k The value of 0 for I j This corresponds to transmitted data with a value of 1 for . Waveforms 660 and 670 are similar in that the received data information is the same as the transmitted data because the data value exceeds the central threshold. However, in the case of waveform 660, which corresponds to Example 3 from Table 4, the level information (A j ) has a value of 0. Therefore, in this case, the determined EQ value is 1. In the case of waveform 670 corresponding to Example 4 from Table 4 above, the value for the received data information is the same as in the case of waveform 660, but the level information (A j ) has a value of 1. Therefore, in this case, the determined value of EQ is -1.

[0043]

[0048] Figure 7 shows an encoder 710 coupled to the FFE720 for a transmitter in one example. In this example, the encoder 710 is Z -1 Includes filter 712 and adder 714. In this example, the channel impulse response is (H E The FFE720 adds a unit interval (UI) delay to the signal received by each filter, and then adds several Z -1 Filter (for example, Z -1 This includes filters 722, 724, 726, 728, and 730. Next, the tap coefficients are applied to the delayed signal before adding using adder 760. Coefficient C0742 corresponds to the main cursor in this example. Coefficient C -1 744 and coefficient C -2 746 corresponds to the pre-cursor. Coefficients C1748, C2750, and C3752 correspond to the post-cursor.

[0044]

[0049] Figure 8 shows how to determine the update coefficients for the FFE720 in Figure 7 by performing a convolution between the current set of coefficients and the encoder response, using one example. The FFE720 adds a Z interval (UI) delay to the signal received by each filter. -1Filter (for example, Z -1 This includes filters 722, 724, 726, 728, 730, and 732). Next, tap coefficients (e.g., coefficients C'0840, C'1842, C'2844, C'3846, C'4848, C'5850, and C'6852) are applied to the delayed signal before being added using adder 760. As shown in Figure 8, the channel impulse response (H E ) and FFE coefficient (H FFE By performing a convolution between ) and , the update coefficient (H' FFE ) determines. That is, as described above, equalization processes level information using the sign-sign least squares mean (SS-LMS) algorithm to extract the correlation between the current data symbol and the previous or subsequent data symbol. This correlation leads to the necessary changes for the transmitter in the pre-cursor coefficients and post-cursor coefficients. Advantageously, the equalization solution uses the transmitter FFE and channel ISI together to determine 1+Z -1 Generate a filtered response.

[0045]

[0050] Figure 9 shows a flowchart 900 of an exemplary method for performing adaptive channel equalization as part of a duo-binary transceiver. In one example, this method may be performed using the duo-binary transceiver of system 100 in Figure 1 and specific components and algorithms described with respect to Figures 2A to 8. Step 910 may include selectively processing information from only the upper eye or lower eye of the received duo-binary signal at a given time to determine the update coefficient for the transmitter's FFE. In one example, selectively processing information from only the upper eye or lower eye of the received duo-binary signal at a given time includes extracting correlation information between the main cursor and the pre-cursor or post-cursor associated with the received duo-binary signal. As part of this step, data information (e.g., D0(N) and D1(N) in Figure 5) and error information (e.g., E0(N) and E1(N) in Figure 5) may be extracted using data slicers and error slicers as described above with respect to Figures 4 and 5. In addition, as part of this step, level information may be determined by analyzing the NRZ signal associated with the upper eye or lower eye. As described above, level information is obtained by mapping the received duo-binary signal to a first non-zero return (NRZ) signal corresponding to the upper eye and a second NRZ signal corresponding to the lower eye of the received duo-binary signal. The data information and level information can be further processed to determine equalization information. The equalization information can then be used to calculate the update coefficient for the transmitter's FFE.

[0046]

[0051] EQ adaptation is performed using the sign-sign least squares mean (SS-LMS) algorithm. The SS-LMS algorithm can be used because the level information is quantized to two values ​​(1 or 0) which are further mapped to one positive or one negative value. Therefore, the absolute magnitude of the quantized data is irrelevant, and the SS-LMS algorithm is only concerned with the sign of the level. Advantageously, this selective mapping and analysis saves power because only one of the two eyes is analyzed at a given time. In addition, the use of digital circuits for mapping and analysis instead of analog circuits saves power further. Furthermore, as mentioned above, the calculations determining the equalization information are performed per decimation. As described above with respect to Figures 2B and 3, the deserializer 256 in Figure 2B transforms the received signal into four streams, each processed by a different slicer that receives one of four phase clock signals generated according to the quarter-rate clock signal shown in Figure 3. Coefficients are generated using information from the patterns of 16-bit or 32-bit data packets. This enables a majority-minority type of equalization decision by counting or otherwise accumulating information corresponding to the pattern being analyzed.

[0047]

[0052] Continuing with reference to Figure 9, step 920 may include transmitting an update coefficient to the transmitter associated with the first duo-binary transceiver using a back channel between the transmitter associated with the first duo-binary transceiver and the receiver associated with the second duo-binary transceiver. As part of this step, the back channel described with respect to Figures 1, 2A, 2B, and 5 may be used.

[0048]

[0053] Referring further to Figure 9, step 930 may include transmitting a duo-binary signal, equalized using update coefficients for the transmitter's FFE associated with the first duo-binary transceiver, to a receiver associated with the second duo-binary transceiver. As described above with respect to Figures 7 and 8, the transmitter may perform a convolution operation using the update coefficients received via the back channel and the channel impulse response of the channel for use in the transmitter's FFE. Figure 9 shows a specific number of steps performed in a particular order, but additional or fewer steps in a different order may be performed as part of the method described with respect to flowchart 900.

[0049]

[0054] Figure 10 shows a flowchart 1000 of an exemplary method for performing adaptive channel equalization as part of a duo-binary transceiver. In one example, this method may be performed using the duo-binary transceiver of system 100 in Figure 1 and specific components and algorithms described with respect to Figures 2A to 8. Step 1010 may include, in a receiver associated with a second duo-binary transceiver, (1) selectively processing level information from only the upper eye or lower eye of the received duo-binary signal at a given time to determine the update coefficient for the transmitter's FFE, and (2) selectively processing peak information from only the upper eye or lower eye of the received duo-binary signal at a given time to automatically control the gain of one or more variable gain amplifiers in the receiver.

[0050]

[0055] As part of this step, data information (e.g., D0(N) and D1(N) in Figure 5) and error information (e.g., E0(N) and E1(N) in Figure 5) can be extracted using data slicers and error slicers as described above with respect to Figures 4 and 5. Error information can be obtained by comparing the received level with reference voltages (e.g., VREFP and -VREFP) shown in Figure 4. The comparison of the received signal with these reference voltages is an effective comparison between the eye peaks in each direction to determine the range of the signal that intersects the positive maximum value (e.g., VREFP) and the negative maximum value (e.g., -VREFP).

[0051]

[0056] In addition, as part of this step, level information can be determined by analyzing the NRZ signal associated with the upper or lower eye. As described above, level information is obtained by mapping the received duo-binary signal to a first non-zero return (NRZ) signal corresponding to the upper eye and a second NRZ signal corresponding to the lower eye of the received duo-binary signal. The data information and level information can be further processed to determine equalization information. The equalization information can then be used to calculate the update coefficient for the transmitter's FFE.

[0052]

[0057] EQ adaptation is performed using the sign-sign least squares mean (SS-LMS) algorithm. The SS-LMS algorithm can be used because the level information is quantized to two values ​​(1 or 0) which are further mapped to one positive or one negative value. Therefore, the absolute magnitude of the quantized data is irrelevant, and the SS-LMS algorithm is only concerned with the sign of the level. Advantageously, this selective mapping and analysis saves power because only one of the two eyes is analyzed at a given time. In addition, the use of digital circuits for mapping and analysis instead of analog circuits saves power further. Furthermore, as mentioned above, the calculations determining the equalization information are performed per decimation. As described above with respect to Figures 2B and 3, the deserializer 256 in Figure 2B transforms the received signal into four streams, each processed by a different slicer that receives one of four phase clock signals generated according to the quarter-rate clock signal shown in Figure 3. Coefficients are generated using information from the patterns of 16-bit or 32-bit data packets. This enables a majority-minority type of equalization decision by counting or otherwise accumulating information corresponding to the pattern being analyzed.

[0053]

[0058] Continuing to refer to Figure 10, step 1020 may include transmitting an update coefficient to the transmitter associated with the first duo-binary transceiver using a back channel between the transmitter associated with the first duo-binary transceiver and the receiver associated with the second duo-binary transceiver. As part of this step, the back channel described in relation to Figures 1, 2A, 2B, and 5 may be used.

[0054]

[0059] Referring further to Figure 10, step 1030 may include transmitting a duo-binary signal, equalized using an update coefficient for the transmitter's FFE associated with the first duo-binary transceiver, to a receiver associated with the second duo-binary transceiver. As described above with respect to Figures 7 and 8, the transmitter may perform a convolution operation using the update coefficient received via the back channel and the channel impulse response of the channel for use in the transmitter's FFE. Figure 10 shows a specific number of steps performed in a particular order, but additional or fewer steps in a different order may be performed as part of the method described with respect to flowchart 1000.

[0055]

[0060] In conclusion, the disclosure relates to a method for adapting a channel between a first duo-binary transceiver and a second duo-binary transceiver different from the first duo-binary transceiver, wherein the transmitter includes a feedforward equalizer (FFE). The method may include, in a receiver associated with the second duo-binary transceiver, selectively processing information from only the upper eye or lower eye of the received duo-binary signal at a given time to determine an update coefficient for the FFE of the transmitter associated with the first duo-binary transceiver.

[0056]

[0061] The method may further include transmitting an update factor to the transmitter associated with the first duo-binary transceiver using a back channel between the transmitter associated with the first duo-binary transceiver and the receiver associated with the second duo-binary transceiver. The method may further include transmitting a duo-binary signal, equalized using the update factor for the FFE of the transmitter associated with the first duo-binary transceiver, to the receiver associated with the second duo-binary transceiver.

[0057]

[0062] As part of this method, selectively processing information from only the upper eye or lower eye of the received duo-binary signal at a given point in time may include extracting correlation information between the main cursor and the pre-cursor or post-cursor associated with the received duo-binary signal. The method may further include obtaining level information by mapping the received duo-binary signal to a first non-zero return (NRZ) signal corresponding to the upper eye of the received duo-binary signal, or to a second NRZ signal corresponding to the lower eye of the received duo-binary signal.

[0058]

[0063] The method may further include determining equalization information based on both level information from either the upper or lower eye and data information obtained from the received duo-binary signal, and using the equalization information to calculate the update coefficient for the transmitter's FFE. Determining the equalization information may include using a code-code least squares mean (SS-LMS) algorithm.

[0059]

[0064] As part of the method, selectively processing information from only the upper eye or lower eye of a received duo-binary signal at a given time may include periodically switching the processing of information from the upper eye or lower eye to determine the update coefficient for the transmitter's FFE. The method may further include performing a convolution operation using the update coefficient received via the back channel and the channel impulse response of the channel for use in the transmitter's FFE associated with a first duo-binary transceiver.

[0060]

[0065] In another example, the disclosure relates to a system for adapting a channel between a first duo-binary transceiver and a second duo-binary transceiver different from the first duo-binary transceiver, wherein the transmitter includes a feedforward equalizer (FFE). The system may further include logic for determining an update coefficient for the FFE of the transmitter associated with the first duo-binary transceiver by selectively processing information from only the upper eye or lower eye of the received duo-binary signal with given time information.

[0061]

[0066] The system may further include a back channel between a transmitter associated with a first duo-binary transceiver and a receiver associated with a second duo-binary transceiver for transmitting an update factor to a transmitter associated with a first duo-binary transceiver, thereby enabling the transmitter to transmit a duo-binary signal, equalized using the update factor for the transmitter's FFE, to the receiver associated with the second duo-binary transceiver.

[0062]

[0067] Logic for selectively processing information from only the upper eye or lower eye of a received duo-binary signal at a given time may include logic for extracting correlation information between the main cursor and the pre-cursor or post-cursor associated with the received duo-binary signal. Level information may be obtained by mapping the received duo-binary signal to a first non-zero return (NRZ) signal corresponding to the upper eye of the received duo-binary signal, or by mapping the received duo-binary signal to a second NRZ signal corresponding to the lower eye of the received duo-binary signal.

[0063]

[0068] The system may further include logic for determining equalization information based on both level information from either the upper or lower eye and data information obtained from the received duo-binary signal, and for using the equalization information to calculate update coefficients for the transmitter's FFE. The logic for determining the equalization information may include logic for implementing a code-code least squares mean (SS-LMS) algorithm. The system may further include logic for selectively processing peak information from either the upper or lower eye of the received duo-binary signal at a given time to automatically control the gain of one or more variable gain amplifiers in the receiver.

[0064]

[0069] In yet another example, the disclosure relates to a transmitter associated with a first duo-binary transceiver, and a method for adapting a channel between the first duo-binary transceiver and a second duo-binary transceiver different from the first duo-binary transceiver, wherein the transmitter includes a feedforward equalizer (FFE). The method may include, in a receiver associated with a second duo-binary transceiver, (1) selectively processing level information from only the upper eye or lower eye of the received duo-binary signal at a given time to determine an update coefficient for the transmitter's FFE, and (2) selectively processing peak information from only the upper eye or lower eye of the received duo-binary signal at a given time to automatically control the gain of one or more variable-gain amplifiers in the receiver.

[0065]

[0070] The method may further include transmitting an update factor to the transmitter associated with the first duo-binary transceiver using a back channel between the transmitter associated with the first duo-binary transceiver and the receiver associated with the second duo-binary transceiver. The method may further include transmitting a duo-binary signal, equalized using the update factor for the FFE of the transmitter associated with the first duo-binary transceiver, to the receiver associated with the second duo-binary transceiver.

[0066]

[0071] As part of the method, selectively processing information from only the upper eye or lower eye of the received duo-binary signal at a given time to determine the update coefficient for the transmitter's FFE may include extracting correlation information between the main cursor and the pre-cursor or post-cursor associated with the received duo-binary signal. The method may further include obtaining level information by mapping the received duo-binary signal to a first non-zero return (NRZ) signal corresponding to the upper eye of the received duo-binary signal, or to a second NRZ signal corresponding to the lower eye of the received duo-binary signal.

[0067]

[0072] The method may further include determining equalization information based on both level information from either the upper or lower eye and data information obtained from the received duo-binary signal, and using the equalization information to calculate the update coefficient for the transmitter's FFE. Determining the equalization information may include using a code-code least squares mean (SS-LMS) algorithm.

[0068]

[0073] The method may further include processing edge information from only the upper eye or lower eye for use in a receiver clock data recovery (CDR) circuit associated with a second duo-binary transceiver. Selectively processing information from only the upper eye or lower eye of a received duo-binary signal at a given time to determine the update factor for the transmitter's FFE may include periodically switching the processing of information from the upper eye or lower eye to determine the update factor for the transmitter's FFE.

[0069]

[0074] The methods, modules, and components described herein are illustrative only. Alternatively, or in addition, the functions described herein may be performed at least partially by one or more hardware logic components. For example, without limitation, exemplary hardware logic components that can be used include field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standards (ASSPs), system-on-chip systems (SOCs), and composite programmable logic devices (CPLDs). In an abstract but still clear sense, any arrangement of components to achieve the same function is effectively “related” to achieve the desired function. Thus, any two components described herein that are combined to achieve a particular function may be considered “related” to achieve the desired function, regardless of architecture or intermediate components. Similarly, any two such related components may also be considered “operably connected” or “combined” to achieve the desired function.

[0070]

[0075] Some of the functions relating to certain examples described herein may also include instructions stored on non-temporary media. As used herein, “non-temporary media” means any medium that stores data and / or instructions that enable a machine to operate in a particular way. Exemplary non-temporary media include non-volatile media and / or volatile media. Non-volatile media include, for example, hard disks, solid-state drives, magnetic disks or tapes, optical disks or tapes, flash memory, EPROM, NVRAM, PRAM, or other such media or network versions thereof. Volatile media include, for example, dynamic memory (e.g., DRAM, SRAM), caches, or other such media. Non-temporary media are different from transmission media, but can be used in conjunction with transmission media. Transmission media are used to transfer data and / or instructions to or from a machine. Exemplary transmission media include coaxial cables, fiber optic cables, copper wires, and wireless media (e.g., radio waves).

[0071]

[0076] Furthermore, those skilled in the art will recognize that the boundaries between the functions of the operations described above are merely illustrative. The functions of multiple operations may be combined into a single operation, and / or the functions of a single operation may be distributed among additional operations. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be modified in various other embodiments.

[0072]

[0077] While this disclosure provides specific examples, various modifications and alterations can be made without departing from the scope of this disclosure as set forth in the claims below. Accordingly, this specification and drawings should be considered illustrative rather than restrictive, and all such modifications are intended to be included within the scope of this disclosure. Any benefit, advantage, or solution to a problem described in relation to a specific example is not intended to be construed as an important, necessary, or essential feature or element of any or all of the claims.

[0073]

[0078] Furthermore, as used herein, the terms “one (a)” or “one (an)” are defined as one or more. Also, the use of introductory phrases such as “at least one” and “one or more” in the claims should not be interpreted as meaning that the introduction of another claim element by the indefinite article “one (a)” or “one (an)” limits any particular claim containing such introduced claim element to an invention containing only one such element, even if the same claim contains the introductory phrase “one or more” or “at least one” and an indefinite article (e.g., “one (a)” or “one (an)”). The same applies to the use of the definite article.

[0074]

[0079] Unless otherwise specified, terms such as "1st" and "2nd" are used to appropriately distinguish the elements described by such terms. Therefore, these terms are not necessarily intended to indicate a temporal or other priority of such elements.

Claims

1. A method for adapting the channel between a first duo-binary transceiver (106) and a second duo-binary transceiver (108) that is different from the first duo-binary transceiver (106), In the receiver (250) associated with the second duo-binary transceiver (108), information from only the upper eye or lower eye of the received duo-binary signal is selectively processed at a given time to determine the update coefficient for the feedforward equalizer (FFE) of the transmitter (200) associated with the first duo-binary transceiver (106) (step 910), The update coefficient is transmitted to the transmitter (200) associated with the first duo-binary transceiver (106) using the back channel (204) between the transmitter (200) associated with the first duo-binary transceiver (106) and the receiver (220) associated with the second duo-binary transceiver (108). A method that includes this.

2. The method according to claim 1, further comprising transmitting a duo-binary signal, which is equalized using the update coefficient for the FFE of the transmitter associated with the first duo-binary transceiver, to the receiver associated with the second duo-binary transceiver.

3. The method according to claim 1, wherein the selective processing of information from only the upper eye or the lower eye of the received duo-binary signal at a given time includes extracting correlation information between a main cursor and a pre-cursor or post-cursor related to the received duo-binary signal.

4. The method according to claim 1, further comprising obtaining level information by mapping the received duo-binary signal to a first non-zero return (NRZ) signal corresponding to the upper eye of the received duo-binary signal, or by mapping the received duo-binary signal to a second NRZ signal corresponding to the lower eye of the received duo-binary signal.

5. The method according to claim 4, further comprising determining equalization information based on both the level information from either the upper eye or the lower eye and data information obtained from the received duo-binary signal, and using the equalization information to calculate the update coefficient for the FFE of the transmitter.

6. The method according to claim 5, wherein determining the equalization information involves using a sign-sign least squares mean (SS-LMS) algorithm.

7. The method according to claim 1, wherein the selective processing of information from only the upper eye or the lower eye of the received duo-binary signal at a given time includes periodically switching the processing of information from the upper eye or the lower eye to determine the update coefficient for the FFE of the transmitter.

8. The method of claim 2, further comprising performing a convolution operation using the update coefficient received via the back channel and the transmitter's response for use in the FFE of the transmitter associated with the first duo-binary transceiver.

9. A system (100) for adapting the channel between a first duo-binary transceiver (106) and a second duo-binary transceiver (108) different from the first duo-binary transceiver (106), Logic (500) for selectively processing information from only the upper eye or lower eye of the received duo-binary signal with given time information to determine update coefficients for the feedforward equalizer (FFE) of the transmitter (200) associated with the first duo-binary transceiver (106), A back channel (204) between the transmitter (200) associated with the first duo-binary transceiver (106) and the receiver (250) associated with the second duo-binary transceiver (108) for transmitting the update coefficient to the transmitter (200) associated with the first duo-binary transceiver (106) and A system (100) including the above.

10. The system according to claim 9, wherein the transmitter is operable to transmit a duo-binary signal, which is equalized using the update coefficient for the FFE of the transmitter, to the receiver associated with the second duo-binary transceiver.

11. The system according to claim 9, wherein the logic for selectively processing information from only the upper eye or only the lower eye of the received duo-binary signal at a given time includes logic for extracting correlation information between a main cursor and a pre-cursor or post-cursor related to the received duo-binary signal.

12. The system according to claim 9, wherein level information is obtained by mapping the received duo-binary signal to a first non-zero return (NRZ) signal corresponding to the upper eye of the received duo-binary signal, or by mapping the received duo-binary signal to a second NRZ signal corresponding to the lower eye of the received duo-binary signal.

13. The system according to claim 12, further comprising logic for determining equalization information based on both the level information from either the upper eye or the lower eye and data information obtained from the received duo-binary signal, and for calculating the update coefficient for the FFE of the transmitter using the equalization information.

14. The system according to claim 9, wherein the logic for determining equalization information includes logic for implementing a sign-sign least squares mean (SS-LMS) algorithm.

15. The system according to claim 9, further comprising logic for selectively processing peak information from only the upper eye or only the lower eye of the receiving duo-binary at a given time, in order to automatically control the gain of one or more variable gain amplifiers of the receiver.

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