Sequence detection device and sequence detection method

Abstract

The invention provides a sequence detection device which comprises a feed-forward filter and a sequence detection circuit. The feed-forward filter is used for processing a received signal to generate an equalized signal. The sequence detection circuit is used for carrying out sequence detection on the equalization signal to generate and output a symbol sequence. The sequence detection circuit comprises a region estimation circuit and a grid selection circuit. The region estimation circuit is configured to classify each of a plurality of samples included in the equalized signal into one of a plurality of regions. The grid selection circuit is used for selecting one of a plurality of grid schemes to perform branch metric calculation according to the area estimation results of two of the plurality of samples output by the area estimation circuit.

Description

Technical Field

[0001] This invention relates to data communication, and more particularly to a sequence detection apparatus and related sequence detection method that uses a programmable branch metric (hereinafter referred to as "BM") to compute a simplified maximum likelihood sequence detection (hereinafter referred to as "MLSD"). Background Technology

[0002] In high-speed data communication systems, existing filtering and equalization schemes may be insufficient to support challenging channels. For example, due to the high demands on data communication speeds, data bandwidth increases significantly, making inter-symbol interference (ISI) and crosstalk interference from neighboring data channels more severe, and data modulation schemes more complex. Traditional feed-forward equalizers (FFEs) can remove pre-cursor and post-cursor ISI by using information from neighboring symbols. However, because traditional FFEs do not use any noise-free estimated symbols (e.g., noise-free sliced ​​symbols), noise other than ISI may be amplified by traditional FFEs. Traditional decision-feedback equalizers (DFEs) can remove inter-symbol interference (ISI) by using one or more noise-free estimated previous symbols (e.g., one or more noise-free previous truncated symbols). However, because they rely on previous decisions, traditional DFEs can cause error propagation. In other words, traditional linear equalization methods (e.g., feedforward equalization) and nonlinear equalization methods (e.g., decision-feedback equalization) may not provide sufficient performance in certain situations. Multi-Syllable Delayed Equalization (MLSD) utilizes ISI and further eliminates it to handle noise interference, thus becoming a popular technique for enhancing performance and overcoming nonlinear errors in high-speed data communication systems. However, MLSD requires implementing the Viterbi algorithm, resulting in high implementation complexity and computational resource consumption. For example, to implement the Viterbi algorithm in a system with K data states, the number of BM calculations within a data cycle could be K. 2 This means that a large amount of computing resources are needed to acquire BM information. Therefore, the sequence detectors used in high-speed data communication systems require an innovative low-complexity and power-efficient MLSD. Summary of the Invention

[0003] One of the objectives of this invention is to provide a sequence detection device and related sequence detection method that uses a simplified maximum probability sequence detection method with a programmable branch metric.

[0004] In one embodiment of the present invention, a sequence detection apparatus is disclosed. The sequence detection apparatus includes a feedforward filter and a sequence detection circuit. The feedforward filter processes a received signal to generate an equalization signal. The sequence detection circuit performs sequence detection on the equalization signal to generate and output a symbol sequence. The sequence detection circuit includes a region estimation circuit and a grid selection circuit. The region estimation circuit classifies each sample among a plurality of samples contained in the equalization signal into one of a plurality of regions. The grid selection circuit selects one of a plurality of grid schemes for branch metric calculation based on the region estimation results of two samples among the plurality of samples output by the region estimation circuit.

[0005] In one embodiment of the present invention, a sequence detection apparatus is disclosed. The sequence detection apparatus includes a sequence detection circuit. The sequence detection circuit is used to perform sequence detection on a received signal to generate and output a symbol sequence. The received signal is the output of an analog-to-digital converter. The sequence detection circuit includes a region estimation circuit and a grid selection circuit. The region estimation circuit is used to classify each sample among a plurality of samples contained in the received signal into one of a plurality of regions. The grid selection circuit is used to select one of a plurality of grid schemes for branch metric calculation based on the region estimation results of two samples among the plurality of samples output by the region estimation circuit.

[0006] In one embodiment of the present invention, a sequence detection method is disclosed. The sequence detection method includes: obtaining a data signal and performing a sequence detection operation on the data signal to generate and output a symbol sequence. The step of obtaining the data signal includes: receiving an output of an analog-to-digital converter as the data signal, or performing a feedforward filtering operation on the output of the analog-to-digital converter to generate an equalization signal as the data signal. The sequence detection operation includes: performing a region estimation operation to classify each sample among a plurality of samples contained in the data signal into one of a plurality of regions, and performing a grid selection operation to select one of a plurality of grid schemes for branch metric calculation based on the region estimation results of two samples among the plurality of samples output by the region estimation operation.

[0007] When the channel state and / or signal state changes, the probability distribution of different symbols transmitted via the data channel may change. Therefore, the control circuit in the sequence detection device of the present invention will adaptively adjust the threshold and / or grid scheme according to the channel state pointer and signal quality pointer, thereby improving the performance of sequence detection. Attached Figure Description

[0008] Figure 1This is a schematic diagram of a sequence detection device with a simplified MLSD calculation based on a programmable BM calculation, used in an embodiment of the present invention.

[0009] Figure 2 for Figure 1 The diagram shows the BM calculation unit used in the BM calculation circuit.

[0010] Figure 3 This is a schematic diagram of a first configuration of two programmable thresholds used by a region estimation circuit implemented by a third-order truncate in an embodiment of the present invention.

[0011] Figure 4 This is a schematic diagram of a second configuration of two programmable thresholds used by a region estimation circuit implemented by a third-order truncate in an embodiment of the present invention.

[0012] Figure 5 This is a schematic diagram of a third configuration of two programmable thresholds used by a region estimation circuit implemented by a third-order truncate in an embodiment of the present invention.

[0013] Figure 6 This is a schematic diagram of a fourth configuration of two programmable thresholds used by a region estimation circuit implemented by a third-order truncate in an embodiment of the present invention.

[0014] Figure 7 This is a schematic diagram of multiple fixed grid schemes used in a grid selection circuit according to an embodiment of the present invention.

[0015] Figure 8 This is a schematic diagram of a first configuration of four programmable thresholds used by a region estimation circuit implemented by a 5th-order truncate in an embodiment of the present invention.

[0016] Figure 9 This is a schematic diagram of a second configuration of four programmable thresholds used by a region estimation circuit implemented by a 5th-order truncate in an embodiment of the present invention.

[0017] Figure 10 This is a schematic diagram of a third configuration of four programmable thresholds used by a region estimation circuit implemented by a 5th-order pruner according to an embodiment of the present invention.

[0018] Figure 11 This is a schematic diagram of a fourth configuration of four programmable thresholds used by a region estimation circuit implemented by a 5th-order pruner according to an embodiment of the present invention.

[0019] Figure 12 This is a schematic diagram of multiple fixed grid schemes used in a grid selection circuit according to an embodiment of the present invention.

[0020] Figure 13This is a schematic diagram of a first configuration of two programmable thresholds used by a region estimation circuit implemented by a third-order truncate in an embodiment of the present invention.

[0021] Figure 14 This is a schematic diagram of a second configuration of two programmable thresholds used by a region estimation circuit implemented by a third-order truncate in an embodiment of the present invention.

[0022] Figure 15 This is a schematic diagram of a third configuration of two programmable thresholds used by a region estimation circuit implemented by a third-order truncate in an embodiment of the present invention.

[0023] Figure 16 This is a schematic diagram of a fourth configuration of two programmable thresholds used by a region estimation circuit implemented by a third-order truncate in an embodiment of the present invention.

[0024] Figure 17 This is a schematic diagram of multiple fixed grid schemes used in a grid selection circuit according to an embodiment of the present invention.

[0025] Figure 18 This is a schematic diagram of another sequence detection device using MLSD with a programmable BM calculation simplification according to an embodiment of the present invention.

[0026] [Symbol Explanation]

[0027] 100, 1800: Sequence detection device

[0028] 102: Feedforward filter

[0029] 104: Sequence Detection Circuit

[0030] 106: Region Estimation Circuit

[0031] 108: Mesh Selection Circuit

[0032] 110: Branch metric calculation circuit

[0033] 112: Addition-Comparison-Selection and Path Metric Calculation Circuit

[0034] 114: Survival Paths and Backtracking Circuits

[0035] 116: Control Circuit

[0036] 200: Branch metric calculation unit

[0037] 1802: Analog-to-digital converter

[0038] S_IN[k]: Received signal

[0039] S_FFF: Equalization signal

[0040] h1: Channel status pointer

[0041] SQ: Signal Quality Indicator

[0042] S_OUT: Symbol sequence

[0043] FFF[0]~FFF[n]: Feedforward equalizer coefficients

[0044] BM XY [n]: Branch metric Detailed Implementation

[0045] Certain terms are used in this specification and the claims to refer to specific components. Those skilled in the art will understand that hardware manufacturers may use different names to refer to the same component. This specification and the claims do not distinguish components by name differences, but by functional differences. The terms "comprising" and "including" used throughout this specification and the claims are open-ended and should be interpreted as "including but not limited to". Furthermore, the terms "coupled" or "coupled" herein include any direct and indirect electrical connection means. Therefore, if a first device is described as coupled to a second device, it means that the first device can be directly electrically connected to the second device, or indirectly electrically connected to the second device through other devices and connection means.

[0046] Figure 1 This is a schematic diagram of a sequence detection device using a simplified MLSD with programmable BM calculation according to an embodiment of the present invention. The sequence detection device 100 can be part of a receiver in a data communication system. In this embodiment, the sequence detection device 100 is a digital circuit and includes a feed-forward filter (FFF) 102 and a sequence detection circuit 104. For example, the feed-forward filter 102 can be a feed-forward equalizer, such as... Figure 1 As shown, the feedforward filter 102 can be implemented by using a feedforward equalizer with (n+1) taps of (n+1) feedforward equalizer coefficients FFF[0] to FFF[n] (n≥0). However, this is only an example and is not intended to limit the invention. In fact, any suitable feedforward filter structure can be used by the feedforward filter 102. In other words, the invention does not impose any restrictions on the design of the feedforward filter.

[0047] Feedforward filter 102 is used to process the received signal S_IN[k] to generate an equalized signal S_FFF, which is used as the data signal to be processed by sequence detection (e.g., MLSD). The received signal S_IN[k] is a digital signal generated by the analog-to-digital converter (ADC) of the receiver. For example, a pulse-amplitude modulation (PAM) signal is generated from the transmitter of the data communication system and transmitted to the receiver of the data communication system through the channel. The received signal S_IN[k] is a digital signal derived from the PAM signal. Taking the transmission of a 4-level PAM (PAM4) signal as an example, there will be four symbols {-3, -1, +1, +3}, each symbol corresponding to a set of two bits. For example, the four bit selections 00, 01, 10 and 11 can be associated with the amplitudes of -3, -1, +1 and +3, respectively.

[0048] Sequence detection circuit 104 is used to perform sequence detection on data signals (e.g., equalization signal S_FFF) to generate and output a symbol sequence S_OUT. Taking PAM4 signal transmission as an example, the symbol sequence S_OUT is a series of symbols, and each symbol is determined to be one of four PAM symbols through sequence detection. In this embodiment, sequence detection circuit 104 is used to employ the MLSD with programmable BM calculation simplification proposed in this invention. Figure 1 As shown, the sequence detection circuit 104 includes a region estimation circuit (labeled "region estimation") 106, a trellis selection circuit (labeled "trellis selection") 108, a BM calculation circuit (labeled "BMCAL") 110, an add-compare-select (ACS) and path metric (PM) calculation circuit (labeled "ACS & PMCAL") 112, a surviving path and traceback circuit (labeled "surviving path traceback") 114, and a control circuit (labeled "CTRL") 116.

[0049] The BM calculation circuit 110 is used to calculate the BM value BMXY[n] of the branch between the previous state X of the grid at the previous time point T[n-1] and the next state Y of the grid at the next time point T[n-1]. Figure 2 for Figure 1 The diagram shows the BM calculation unit used in the BM calculation circuit 110. The BM calculation unit 200 is used to calculate and output the BM value BMXY[n], where the calculation of the BM value BMXY[n] can be represented by the following equation.

[0050] (1)

[0051] In equation (1) above, X represents the hard data of state X at time point T[n-1] (i.e., X=HD[n-1]), Y represents the hard data of state Y at time point T[n] (i.e., Y=HD[n]), S[n] represents the soft data of the received symbols at time point T[n] (e.g., S[n]=S_FFF[n] or S_IN[n]), and h1 is an indicator of the channel state (e.g., the channel loss state). Specifically, BM value BM XY [n] is the error distance indicating the deviation of the target position from state X at time point T[n-1] to state Y at time point T[n].

[0052] The ACS and PM calculation circuit 112 is used to calculate the PM value PM of a state Y of the grid at time point T[n]. Y [n], where PM value PM Y [n] indicates the survival path SP Y The accumulated error distance of [n]. Survival path and backtracking circuit 114 is used to record the survival path SP. Y [n]. Furthermore, the survival path and backtracking circuit 114 employs a backtracking method to find the symbol sequence based on the survival path. Since the focus of this invention is on the BM calculation simplification technique proposed herein, and those skilled in the art should easily understand the operational principles of the remaining operations performed by the sequence detection circuit 104 (e.g., path metric calculation, survival path determination, and survival path-based backtracking), further descriptions of the remaining operations performed by the sequence detection circuit 104 are omitted here for the sake of brevity.

[0053] Region estimation circuit 106 is used to classify each of the multiple samples contained in the equalization signal S_FFF into one of multiple regions, where these regions are defined by multiple thresholds. Mesh selection circuit 108 is used to select one of multiple mesh schemes for BM calculation based on the region estimation results of the two samples output by region estimation circuit 106, where each mesh scheme indicates multiple selected branches with a high probability between the states of two time points T[n-1] and T[n]. Specifically, the multiple mesh schemes may include a first mesh scheme and a second mesh scheme, where the selected branches included in the first mesh scheme may be different from the selected branches included in the second mesh scheme, and / or the number of selected branches included in the first mesh scheme may be different from the number of selected branches included in the second mesh scheme.

[0054] In this embodiment, the multiple regions (specifically, multiple thresholds defining these regions) used by the region estimation circuit 106 to perform region estimation for each sample (soft data) in the equalization signal S_FFF can be adaptively adjusted, and / or the multiple grid schemes used by the grid selection circuit 108 to perform grid scheme selection can be adaptively adjusted. In one example, the control circuit 116 is used to obtain a channel state indicator h1 (which indicates channel loss) and a signal quality indicator SQ, such as a signal-to-noise ratio (SNRIND) indicator or an error level (ELIND) indicator, and adaptively adjusts multiple thresholds (which are programmable) based on the channel state indicator h1 and the signal quality indicator SQ (e.g., SQ = SNRIND or ELIND); furthermore, the multiple grid schemes used by the grid selection circuit 108 are fixed. In another example, control circuit 116 is used to obtain a channel state pointer h1 (which indicates channel loss) and a signal quality pointer SQ (e.g., SQ = SNRIND or ELIND), and adaptively adjusts multiple trellis schemes (which are programmable) based on the channel state pointer h1 and the signal quality pointer SQ; furthermore, the multiple thresholds (regions) used by region estimation circuit 106 are fixed. In yet another example, control circuit 116 is used to obtain a channel state pointer h1 (which indicates channel loss) and a signal quality pointer SQ (e.g., SQ = SNRIND or ELIND), and adaptively adjusts multiple thresholds (which are programmable) and multiple trellis schemes (which are programmable) based on the channel state pointer h1 and the signal quality pointer SQ.

[0055] In some embodiments of the present invention, the region estimation circuit 106 may be composed of an X-level slicer. The implementation is done using (X-1) thresholds required by the X-order pruner, and these thresholds are programmable. Figure 3 These are the two programmable thresholds TH used by the region estimation circuit 106 implemented by a third-order truncation (X=3) in one embodiment of the present invention. H TH L A schematic diagram of the first configuration. The region estimation circuit 106 can be used to process multiple samples of the equalization signal S_FFF, which is generated by performing a feedforward filtering operation (e.g., feedforward equalization) on the received signal S_IN[k] derived from the PAM4 signal. The probability density function of the symbol +3 transmitted via the data channel is represented by the probability distribution curve PMF3. The probability density function of the symbol +1 transmitted via the data channel is represented by the probability distribution curve PMF1. The probability density function of the symbol -1 transmitted via the data channel is represented by the probability distribution curve PMFm1. The probability density function of the symbol -3 transmitted via the data channel is represented by the probability distribution curve PMFm3. When the channel state and / or signal state changes, the probability distribution of different symbols {-3, -1, +1, +3} transmitted via the data channel may change; therefore, the control circuit 116 instructs the region estimation circuit 106 to adaptively adjust the threshold TH for different channel states and / or different signal states. L TH H This improves the performance of sequence detection. For example, when the channel state pointer h1 indicates that the current channel state is high loss and the signal quality pointer SQ (e.g., SQ = SNRIND) indicates that the current signal state is high signal-to-noise ratio (high SNR), the control circuit 116 instructs the region estimation circuit 106 to use... Figure 3 The threshold TH shown L and TH H .

[0056] Figure 4 These are the two programmable thresholds TH used by the region estimation circuit 106 implemented by a third-order truncation (X=3) in one embodiment of the present invention. H TH L The diagram illustrates the second configuration. When the channel state pointer h1 indicates that the current channel state is a high-loss state and the signal quality pointer SQ (e.g., SQ = SNRIND) indicates that the current signal state is a low signal-to-noise ratio (low SNR) state, the control circuit 116 instructs the region estimation circuit 106 to adopt... Figure 4 The threshold TH shown L and THH .

[0057] Figure 5 These are the two programmable thresholds TH used by the region estimation circuit 106 implemented by a third-order truncation (X=3) in one embodiment of the present invention. H TH L The diagram illustrates the third configuration. When the channel state pointer h1 indicates that the current channel state is low loss and the signal quality pointer SQ (e.g., SQ = SNRIND) indicates that the current signal state is high signal-to-noise ratio, the control circuit 116 instructs the region estimation circuit 106 to adopt... Figure 5 The threshold TH shown L and TH H .

[0058] Figure 6 These are the two programmable thresholds TH used by the region estimation circuit 106 implemented by a third-order truncation (X=3) in one embodiment of the present invention. H TH L The diagram illustrates the fourth configuration. When the channel state pointer h1 indicates that the current channel state is a low-loss state and the signal quality pointer SQ (e.g., SQ = SNRIND) indicates that the current signal state is a low signal-to-noise ratio state, the control circuit 116 instructs the region estimation circuit 106 to adopt... Figure 6 The threshold TH shown L and TH H .

[0059] When the region estimation circuit 106 classifies a sample (soft data) of the equalization signal S_FFF into region 2, it indicates a higher probability of transmitting the symbol +3 or +1 via the data channel, and a lower probability of transmitting the symbol -3 or -1 via the data channel. When the region estimation circuit 106 classifies a sample (soft data) of the equalization signal S_FFF into region 1, it indicates a higher probability of transmitting the symbol -1 or +1 via the data channel, and a lower probability of transmitting the symbol -3 or +3 via the data channel. When the region estimation circuit 106 classifies a sample (soft data) of the equalization signal S_FFF into region 0, it indicates a higher probability of transmitting the symbol -3 or -1 via the data channel, and a lower probability of transmitting the symbol +3 or +1 via the data channel. Therefore, based on the region estimation results of two consecutive samples (e.g., the sample at time point T[n-1] and the sample at time point T[n]), some branches between the state at time point T[n-1] and the state at time point T[n] may have high probability, while some branches between the state at time point T[n-1] and the state at time point T[n] may have low probability. Therefore, branches with lower probability can be omitted to simplify BM calculation. Specifically, since the probability of some branches is too low and these low probability branches are not worth performing BM calculation, the number of BM calculations per symbol can be reduced.

[0060] Figure 7 This is a schematic diagram of multiple fixed grid schemes used by the grid selection circuit 108 according to an embodiment of the present invention. Figure 7 The multiple fixed grid schemes shown are shared under different channel states (e.g., high-loss and low-loss states) and different signal states (e.g., high SNR and low SNR states). Therefore, each grid scheme is indexed by the region estimation results of samples at time point T[n-1] and samples at time point T[n]. The region estimation results of samples at time point T[n-1] and samples at time point T[n] are obtained by using... Figures 3-6 The threshold TH shown in any of the figures L TH HThe grid selection circuit 108 selects one of the multiple fixed grid schemes for BM calculation based on the region estimation results of the samples at time point T[n-1] and the samples at time point T[n]. For example, when both the samples at time point T[n-1] and T[n] are classified into region 2, branches starting from and ending at states +3 and +1 will be selected for BM calculation, while branches starting from or ending at states -3 and -1 will not be selected. Similarly, when both the samples at time point T[n-1] and T[n] are classified into region 1, branches starting from and ending at states -1 and +1 will be selected for BM calculation, while branches starting from or ending at states -3 and -1 will not be selected. This is easily understood by those skilled in the art after reading the above description. Figure 7 For the sake of brevity, further details of the remaining mesh schemes are omitted here.

[0061] The region estimation circuit 106 can be implemented by an X-order truncation (X≥2), and the (X-1) thresholds used by the X-order truncation can be programmable or fixed. Note that the value of X can be adjusted according to actual design considerations.

[0062] Figure 8 These are the four programmable thresholds TH used by the region estimation circuit 106 implemented by a 5th-order pruner (X=5) in one embodiment of the present invention. m3 TH m1 A schematic diagram of the first configuration of TH1 and TH3. The region estimation circuit 106 can be used to process samples of the equalization signal S_FFF, which is generated by performing a feedforward filtering operation (e.g., feedforward equalization) on the received signal S_IN[k] derived from the PAM4 signal. When the channel state and / or signal state changes, the probability distribution of different symbols {-3, -1, +1, +3} transmitted through the data channel may change; therefore, the control circuit 116 instructs the region estimation circuit 106 to adaptively adjust the threshold TH for different channel states and / or different signal states. m3 TH m1 TH1, TH3, thereby improving the performance of sequence detection. For example, when the channel state pointer h1 indicates that the current channel state is a high-loss state and the signal quality pointer SQ (e.g., SQ = SNRIND) indicates that the current signal state is a high-noise ratio state, the control circuit 116 instructs the region estimation circuit 106 to use TH1, TH3, etc. Figure 8 The threshold TH shown m3 TH m1TH1, TH3.

[0063] Figure 9 These are the four programmable thresholds TH used by the region estimation circuit 106 implemented by a 5th-order pruner (X=5) in one embodiment of the present invention. m3 TH m1 A schematic diagram of the second configuration of TH1 and TH3. When the channel state pointer h1 indicates that the current channel state is a high-loss state and the signal quality pointer SQ (e.g., SQ = SNRIND) indicates that the current signal state is a low signal-to-noise ratio state, the control circuit 116 instructs the region estimation circuit 106 to adopt... Figure 9 The threshold TH shown m3 TH m1 TH1, TH3.

[0064] Figure 10 These are the four programmable thresholds TH used by the region estimation circuit 106 implemented by a 5th-order pruner (X=5) in one embodiment of the present invention. m3 TH m1 A schematic diagram of the third configuration of TH1 and TH3. When the channel state pointer h1 indicates that the current channel state is a low-loss state and the signal quality pointer SQ (e.g., SQ = SNRIND) indicates that the current signal state is a high signal-to-noise ratio state, the control circuit 116 instructs the region estimation circuit 106 to adopt... Figure 10 The threshold TH shown m3 TH m1 TH1, TH3.

[0065] Figure 11 These are the four programmable thresholds TH used by the region estimation circuit 106 implemented by a 5th-order pruner (X=5) in one embodiment of the present invention. m3 TH m1 A schematic diagram of the fourth configuration of TH1 and TH3. When the channel state pointer h1 indicates that the current channel state is a low-loss state and the signal quality pointer SQ (e.g., SQ = SNRIND) indicates that the current signal state is a low signal-to-noise ratio state, the control circuit 116 instructs the region estimation circuit 106 to adopt... Figure 11 The threshold TH shown m3 TH m1 TH1, TH3.

[0066] Figure 12 This is a schematic diagram of multiple fixed grid schemes used by the grid selection circuit 108 according to an embodiment of the present invention. Figure 12The multiple fixed grid schemes shown are shared under different channel states (e.g., high-loss and low-loss states) and different signal states (e.g., high SNR and low SNR states). Therefore, each grid scheme is indexed by the region estimation results of samples at time point T[n-1] and samples at time point T[n], where the region estimation results of samples at time point T[n-1] and samples at time point T[n] are used... Figures 8-11 The threshold TH shown in any of the figures m3 TH m1 The grid selection circuit 108 will select one of the multiple fixed grid schemes for BM calculation based on the region estimation results of the samples at time point T[n-1] and the region estimation results of the samples at time point T[].

[0067] In the above embodiment, the region estimation circuit 106 can be used to process samples of the equalization signal S_FFF, which is generated for the received signal S_IN[k] derived from the PAM4 signal. However, this is only an example and not a limitation of the invention. In fact, the received signal S_IN[k] to be processed by the sequence detection device 100 can be derived from any PAM signal. For example, the received signal S_IN[k] can be obtained from a non-return-to-zero (NRZ) signal (also known as a PAM2 signal).

[0068] Figure 13 These are the two programmable thresholds TH used by the region estimation circuit 106 implemented by a third-order truncation (X=3) in one embodiment of the present invention. H TH L A schematic diagram of the first configuration. The region estimation circuit 106 can be used to process samples of the equalization signal S_FFF, which is generated by performing a feedforward filtering operation (e.g., feedforward equalization) on the received signal S_IN[k] derived from the NRZ signal. The probability density function of the symbol +3 transmitted via the data channel is represented by the probability distribution curve PMF3, while the probability density function of the symbol -3 transmitted via the data channel is represented by the probability distribution curve PMFm3. When the channel state and / or signal state changes, the probability distribution of different symbols {-3, +3} transmitted via the data channel may change; therefore, the control circuit 116 instructs the region estimation circuit 106 to adaptively adjust the threshold TH for different channel states and / or different signal states. L TH HThis improves the performance of sequence detection. For example, when the channel state pointer h1 indicates that the current channel state is a high-loss state and the signal quality pointer SQ (e.g., SQ = SNRIND) indicates that the current signal state is a high signal-to-noise ratio state, the control circuit 116 instructs the region estimation circuit 106 to use... Figure 13 The threshold TH shown L and TH H .

[0069] Figure 14 These are the two programmable thresholds TH used by the region estimation circuit 106 implemented by a third-order truncation (X=3) in one embodiment of the present invention. H TH L The diagram illustrates the second configuration. When the channel state pointer h1 indicates that the current channel state is a high-loss state and the signal quality pointer SQ (e.g., SQ = SNRIND) indicates that the current signal state is a low signal-to-noise ratio state, the control circuit 116 instructs the region estimation circuit 106 to adopt... Figure 14 The threshold TH shown L and TH H .

[0070] Figure 15 These are the two programmable thresholds TH used by the region estimation circuit 106 implemented by a third-order truncation (X=3) in one embodiment of the present invention. H TH L The diagram illustrates the third configuration. When the channel state pointer h1 indicates that the current channel state is low-loss and the signal quality pointer SQ (e.g., SQ = SNRIND) indicates that the current signal state is high signal-to-noise ratio, the control circuit 116 instructs the region estimation circuit 106 to adopt... Figure 15 The threshold TH shown L and TH H .

[0071] Figure 16 These are the two programmable thresholds TH used by the region estimation circuit 106 implemented by a third-order truncation (X=3) in one embodiment of the present invention. H TH L The diagram illustrates the fourth configuration. When the channel state pointer h1 indicates that the current channel state is a low-loss state and the signal quality pointer SQ (e.g., SQ = SNRIND) indicates that the current signal state is a low signal-to-noise ratio state, the control circuit 116 instructs the region estimation circuit 106 to adopt... Figure 16 The threshold TH shown L and TH H .

[0072] Figure 17 This is a schematic diagram of multiple fixed grid schemes used by the grid selection circuit 108 according to an embodiment of the present invention. Figure 17 The multiple fixed grid schemes shown are shared under different channel states (e.g., high-loss and low-loss states) and different signal states (e.g., high SNR and low SNR states). Therefore, each grid scheme is indexed by the region estimation results of the samples at time point T[n-1] and the region estimation results of the samples at time point T[n], where the region estimation results of the samples at time point T[n-1] and the region estimation results of the samples at time point T[n] are obtained by using... Figures 13-16 The threshold TH shown in any of the figures L TH H The grid selection circuit 108 will select one of the multiple fixed grid schemes for BM calculation based on the region estimation results of the samples at time point T[n-1] and the region estimation results of the samples at time point T[n].

[0073] In the above embodiment, the data signal to be processed by the sequence detection circuit 104 is the equalized signal S_FFF generated by the feedforward filter (e.g., feedforward equalizer) 102. Specifically, the data signal fed into the region estimation circuit 106 is the equalized signal S_FFF generated by performing a feedforward filtering operation (e.g., feedforward equalization) on the received signal S_IN[k]. However, this is only for illustrative purposes and is not intended to limit the invention. In another design, the data signal to be processed by the sequence detection circuit 100 may be the received signal S_IN[k] (which is the output of the ADC), and the feedforward filter (e.g., feedforward equalizer) 102 may be omitted.

[0074] Figure 18This is a schematic diagram of another sequence detection device using a simplified MLSD with a programmable BM calculation according to an embodiment of the present invention. The main difference between sequence detection device 100 and sequence detection device 1800 is that sequence detection device 1800 uses the output of analog-to-digital converter 1802 (i.e., the received signal S_IN[k] generated from analog-to-digital converter 1802) as its input signal. The sequence detection device 1800 can be obtained by appropriate modifications to the sequence detection device 100, wherein the modifications may include omitting the feedforward filter 102 and replacing the equalization signal S_FFF of the input node of the sequence detection circuit 104 with the received signal S_IN[k]. Therefore, in this embodiment, the region estimation circuit 106 will classify each of the multiple samples contained in the received signal S_IN[k] (which is the output of the ADC) into one of the multiple regions. Similarly, the multiple regions (specifically, the multiple thresholds defining the multiple regions) used by the region estimation circuit 106 to perform region estimation on each sample (soft data) contained in the received signal S_IN[k] can be adaptively adjusted, and / or the multiple grid schemes used by the grid selection circuit 108 to perform grid scheme selection can be adaptively adjusted. Since those skilled in the art can easily understand the details of the region estimation circuit 106 and the grid selection circuit 108 used by the sequence detection device 1800 (which uses the received signal S_IN[k] as the data signal to be processed by the sequence detection circuit 104) after reading the above paragraphs on the sequence detection device 100, further descriptions are omitted here for the sake of brevity.

[0075] Please note that neither the sequence detection devices 100 nor 1800 have a feedback filter (e.g., the feedback filter could be a decision feedback equalizer). Therefore, each of the sequence detection devices 100 and 1800 can be a sequence detector without a decision feedback equalizer (DFE-free). In this way, additional power consumption reduction can be achieved due to the absence of a feedback filter (e.g., a decision feedback equalizer).

[0076] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made within the scope of the claims of the present invention should be included in the scope of the present invention.

Claims

1. A sequence detection device, comprising: A feedforward filter is used to process a received signal to generate an equalized signal; and Sequence detection circuitry is configured to perform sequence detection on the equalization signal to generate and output a symbol sequence, wherein the sequence detection circuitry comprises: A region estimation circuit is used to classify each of the multiple samples contained in the equalization signal into one of a plurality of regions; and A grid selection circuit is used to select one of a plurality of grid schemes for branch metric calculation based on the region estimation results of two samples out of the plurality of samples output by the region estimation circuit.

2. The sequence detection apparatus of claim 1, wherein the plurality of samples comprises a plurality of consecutive samples, the plurality of consecutive samples comprises a first sample and a second sample immediately following the first sample, the region estimation circuit generates a first region estimation result for the first sample and generates a second region estimation result for the second sample, and the grid selection circuit selects a grid scheme indexed by the first and second region estimation results from the plurality of grid schemes.

3. The sequence detection device as claimed in claim 1, wherein the sequence detection circuit further comprises: A control circuit is used to adaptively adjust the multiple regions.

4. The sequence detection apparatus of claim 3, wherein the plurality of grid schemes is fixed.

5. The sequence detection apparatus of claim 3, wherein the control circuit is further configured to obtain a channel state pointer and a signal quality pointer, and adaptively adjust a plurality of thresholds based on the channel state pointer and the signal quality pointer, wherein the plurality of regions are defined by the plurality of thresholds.

6. The sequence detection device as claimed in claim 1, wherein the sequence detection circuit further comprises: Control circuitry for adaptively adjusting the multiple grid schemes.

7. The sequence detection apparatus of claim 6, wherein the plurality of regions are fixed.

8. The sequence detection apparatus of claim 6, wherein the control circuit is further configured to obtain a channel state pointer and a signal quality pointer, and to adaptively adjust the plurality of grid schemes based on the channel state pointer and the signal quality pointer.

9. The sequence detection apparatus of claim 1, wherein the received signal is derived from a pulse amplitude modulation signal.

10. A sequence detection device, comprising: A sequence detection circuit is used to perform sequence detection on a received signal to generate and output a symbol sequence, wherein the received signal is the output of an analog-to-digital converter, and the sequence detection circuit comprises: A region estimation circuit is used to classify each of a plurality of samples contained in the received signal into one of a plurality of regions; and A grid selection circuit is used to select one of a plurality of grid schemes for branch metric calculation based on the region estimation results of two samples out of the plurality of samples output by the region estimation circuit.

11. The sequence detection apparatus of claim 10, wherein the plurality of samples comprises a plurality of consecutive samples, the plurality of consecutive samples comprises a first sample and a second sample immediately following the first sample, the region estimation circuit generates a first region estimation result for the first sample and generates a second region estimation result for the second sample, and the grid selection circuit selects a grid scheme indexed by the first and second region estimation results from the plurality of grid schemes.

12. The sequence detection apparatus of claim 10, wherein the sequence detection circuit further comprises: Control circuitry for adaptively adjusting the multiple regions.

13. The sequence detection apparatus of claim 12, wherein the plurality of grid schemes is fixed.

14. The sequence detection apparatus of claim 12, wherein the control circuit is further configured to obtain a channel state pointer and a signal quality pointer, and adaptively adjust a plurality of thresholds based on the channel state pointer and the signal quality pointer, wherein the plurality of regions are defined by the plurality of thresholds.

15. The sequence detection apparatus of claim 10, wherein the sequence detection circuit further comprises: Control circuitry for adaptively adjusting the multiple grid schemes.

16. The sequence detection apparatus of claim 15, wherein the plurality of regions are fixed.

17. The sequence detection apparatus of claim 15, wherein the control circuit is further configured to obtain a channel state pointer and a signal quality pointer, and to adaptively adjust the plurality of grid schemes based on the channel state pointer and the signal quality pointer.

18. The sequence detection apparatus of claim 10, wherein the received signal is derived from a pulse amplitude modulation signal.

19. A sequence detection method, comprising: A data signal is obtained, including: Receive an output from an analog-to-digital converter as the data signal; or A feedforward filter is applied to the output of the analog-to-digital converter to generate an equalized signal as the data signal. A sequence detection operation is performed on the data signal to generate and output a symbol sequence, wherein the sequence detection operation includes: Perform a region estimation operation to classify each of the multiple samples contained in the data signal into one of a plurality of regions; and A grid selection operation is performed to select one of a plurality of grid schemes for branch metric calculation based on the region estimation results of two samples out of the plurality of samples output by the region estimation operation.

20. The sequence detection method of claim 19, wherein the sequence detection operation further comprises: Adaptively adjust the multiple regions; or The multiple grid schemes are adaptively adjusted.

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