Method for providing a coated graphene layer structure on a silicon-containing wafer

Abstract

A method for providing a coated graphene layer structure (410) on a silicon-containing wafer (435), comprising: (1) providing a wafer stack (420) comprising, in order, a transparent substrate (400), a nitride layer (405), a graphene layer structure (410), and a dielectric passivation layer (415), wherein the dielectric passivation layer (415) has an exposed upper surface; (2) forming or bonding a further layer (435) on the exposed upper surface of the dielectric passivation layer (415) (300); and (3) removing the substrate (400) by laser lift-off (305) to expose the surface of the nitride layer (405) distal to the graphene layer structure (410). A method is provided comprising the steps of: 125 (Figure 2) removing a substrate (225, Figure 2), and further comprising the step of wafer bonding (130, Figure 2) the exposed surface of the nitride layer (405) of a wafer stack (420) to the surface (235b', Figure 2) of a silicon-containing wafer (235, Figure 2), or the step of forming or bonding comprising the step of wafer bonding (300), wherein the further layer is a silicon-containing wafer (435). The laminate (440) is suitable for manufacturing an electronic device (460).

Description

[Technical Field]

[0001] The present invention relates to a method for providing a coated graphene layer structure on a silicon-containing wafer, and to graphene-containing laminates and electronic devices that can be obtained therefrom. More specifically, the present invention relates to a method comprising the steps of laser lift-off for separating a nitride layer together with the graphene layer structure from a transparent substrate, and wafer bonding to a silicon-containing wafer. [Background technology]

[0002] Two-dimensional (2D) materials, particularly graphene, and their electronic devices are currently the focus of intensive research and development worldwide. 2D materials have been shown to possess exceptional properties, both theoretically and practically, leading to a surge in products incorporating such materials, including, to name just a few, coatings, batteries, and sensors. Graphene is the most well-known and is being studied for a wide range of potential applications. Most notably, graphene is being used in electronic devices and their components, including transistors, diodes, LEDs, solar cells, Hall effect sensors, current sensors, and biosensors. [Overview of the project] [Problems that the invention aims to solve]

[0003] Therefore, there is a wide range of electronic devices known in the prior art that have integrated graphene layer structures (single-layer or multi-layer graphene) and / or other 2D materials as key materials for bringing about improvements to such devices that surpass previous devices and electronic products. These improvements include structural improvements through the use of thinner and lighter materials (which can lead to flexible electronics), as well as performance improvements such as increased electrical and thermal conductance leading to higher operating efficiency.

[0004] The preparation of sufficiently large areas of graphene with high uniformity has been a major problem in the art that has hindered the incorporation of graphene into commercial processes and electronic devices. The standard in the art is to produce graphene by CVD on copper foil or other catalytic metal substrates. Since then, a considerable amount of research and development has focused on the need to optimize the process of transferring graphene from such substrates to target substrates for electronic devices (i.e., non-metallic substrates, such as semiconductors like silicon and insulators like sapphire).

[0005] However, the inventors have found that graphene grown on copper is inevitably contaminated with additional materials that are essential for the transfer, if not copper. These include transfer polymers such as PMMA, metal etching agents, and solvents for removing the polymer. However, polymer residues are never completely removed, and graphene provided in such a way cannot be without the transfer polymer and / or copper. Furthermore, the physical manipulation of graphene during transfer introduces defects in the atomically thin material. The use of copper at any stage of the manufacturing process is also a barrier to integration with standard silicon wafer fabrication (i.e., CMOS wafers), and consequently, a barrier to the commercial adoption of graphene and 2D materials in mass-produced electronic devices.

[0006] Nanomaterials, 2021, 11, 2837, "Graphene Transfer: A Physical Perspective," provides a recent review of graphene transfer methods.

[0007] Nature Communications, 2021, 12, 917, "Large-area integration of two-dimensional materials and their heterostructures by wafer bonding," describes a method for transferring CVD graphene from copper foil to a silicon wafer.

[0008] Adv.Mater.Technol.2023,2201587, "Assessment of Wafer-Level Transfer Techniques of Graphene with Respect to Semiconductor Industry Requirements," is a recent example of wafer-scale graphene transfer techniques, both of which have been observed to result in significant copper contamination.

[0009] U.S. Patent Application Publication No. 2013 / 240839(A1) relates to a graphene channel-based device and a technique for fabricating the same, which may include a wafer bonding step for forming an oxide-oxide junction between an oxide-coated graphene layer and a corresponding CMOS device wafer.

[0010] U.S. Patent Application Publication No. 2013 / 256629(A1) relates to a graphene semiconductor device and a method for manufacturing a graphene semiconductor device, which may include the steps of: depositing a semiconductor layer of a laminate further comprising a sacrificial substrate and a sacrificial layer between the graphene layer and etching the sacrificial layer to remove the sacrificial substrate.

[0011] It is also known in the art that graphene may be synthesized, manufactured, and formed directly on non-metallic surfaces of substrates. The inventors have found that the most effective method for manufacturing high-quality graphene, in particular directly on such non-metallic surfaces, is the method disclosed in International Publication No. 2017 / 029470 (the contents of which are incorporated herein by reference), which provides a two-dimensional material, in particular graphene, having several advantageous properties, including very good crystal quality, large material grain size, minimal material defects, large sheet size, and the absence of metallic or organic polymer contaminants. The method of International Publication No. 2017 / 029470 may be carried out using a vapor-phase epitaxy (VPE) system and a metal-organic chemical vapor deposition (MOCVD) reactor.

[0012] The method described in International Publication No. 2017 / 029470 enables the production of high-quality graphene with excellent uniformity and a certain number of layers (as desired) across its entire surface on a substrate, without the presence of additional carbon fragments or islands. However, the inventors have found that this presents problems in the formation of dielectric layers on the graphene (e.g., by atomic layer deposition). Such problems are far less of a concern, or even less problematic, in the prior art where graphene is transferred due to the inevitable presence of defects that function as nucleation sites. Therefore, the inventors have found that there are significant challenges associated with the formation of dielectric layers on the clean surface of CVD-grown graphene.

[0013] International Publication No. 2022 / 175273(A1) (the contents thereof are incorporated herein by reference in their entirety), and corresponding UK Patent Application Publication No. 2603905 and Taiwan Patent Application Publication No. 202246175 are publications originating from the inventors relating to the formation of a thin graphene-containing conductive substrate that can be obtained by etching a sacrificial silicon wafer from a graphene layer structure formed on an insulating layer formed on a silicon wafer itself.

[0014] U.S. Patent Application Publication No. 2011 / 068320(A1) relates to an electronic device comprising a lower layer composed of a highly ordered crystalline material having a high dielectric constant, an upper layer composed of a crystalline material having a high dielectric constant, and a graphene layer located between the upper and lower layers. This document does not disclose a manufacturing method, but it does disclose that these layers can be formed on a substrate material.

[0015] U.S. Patent Application Publication No. 2019 / 273166(A1) provides a microelectronic device comprising a gate graphene component. The gate graphene component comprises a graphite layer including one or more graphene layers, a patterned hexagonal boron nitride (hBN) layer on the graphite layer above a channel region, and a gate on the patterned hBN layer above the channel region.

[0016] Chinese Patent Application Publication No. 110828550(A) relates to the construction of a boron nitride / graphene heterojunction, characterized in that the device has a rotation angle of 5° to 15° between the hexagonal boron nitride layer and the graphene layer. The boron nitride / graphene heterojunction is prepared by mechanical transfer methods and conventional micro-nano fabrication techniques.

[0017] U.S. Patent Application Publication 2020 / 403068(A1) relates to a chemically doped graphene transistor, one embodiment of which is fabricated by first depositing n-type graphene on a substrate (e.g., sapphire) or on a semiconductor layer formed on a substrate (e.g., AlN).

[0018] IEEE Spectrum, 2020, 57(2), 44, "Atom-thick transistors," provides an overview of devices fabricated from 2D materials.

[0019] Similar to the integration of high-quality 2D materials, technologies that enable the provision of generally high-quality semiconductors, especially thin layers (e.g., on the nm or μm scale, up to approximately 100 μm generally), are still continuously needed. A recent overview of transfer technologies for the heterogeneous integration of ultra-thin semiconductor layers is presented in Nanomaterials, 2021, 11, 842 “Layer-Scale and Chip-Scale Transfer Techniques for Functional Devices and Systems: A Review”.

[0020] One such technology known to those skilled in the art is “laser lift-off” (LLO). An overview of LLO is presented in Physics Procedia, 2013, 41, 241 “Large-area laser-lift-off processing in microelectronics”. This technology is most commonly encountered in the field of light emitting diodes (LEDs), and LLO is used to separate an epitaxial GaN layer from a sapphire substrate in most situations. This can be achieved using a 248 nm wavelength laser that irradiates through the sapphire wafer.

[0021] As known in the art, the wavelength of the laser is selected based on the bandgap of the material such that it is absorbed by only one material. The surface of the absorption layer decomposes, thereby separating the layer. For example, GaN decomposes into metallic gallium and nitrogen gas. GaN is always the material selected in the art for the LLO process, but other layers such as AlN can also be used. Phys.Status Solidi C, 2012, 9, 753 “Laser lift-off of AlN / sapphire for UV light-emitting diodes” describes the process of LLO of AlN / sapphire using a 193 nm laser.

[0022] Other techniques involve 2D layer-assisted delamination, whereby weak van der Waals adhesion to the semiconductor layer enables mechanical delamination. Adv. Funct. Mater., 2023, 2209880, "Recent Advances in Mechanically Transferable III-Nitride Based on 2D Buffer Strategy" provides a recent overview of 2D material-assisted delamination. Nature, 2012, 484, 223, "Layered boron nitride as a release layer for mechanical transfer of GaN-based devices" discloses the use of h-BN as an alternative to laser lift-off, providing a buffer layer for the growth of high-quality GaN-based semiconductors and a cleavage plane for releasing the resulting devices. Materials, 2020, 13, 5118, "Epitaxial Growth of GaN on Magnetron Sputtered AlN / Hexagonal BN / Sapphire Substrates" provides an example of using magnetron sputtered AlN on h-BN as a buffer layer to facilitate the growth of high-quality GaN.

[0023] The present invention aims to overcome, or at least reduce, a combination of the aforementioned problems in the prior art in order to enable wafer-scale integration of high-quality graphene without defects and impurities and high-quality dielectrics into electronic devices, or to provide at least a commercially viable alternative thereto.

Means for Solving the Problems

[0024] In a first aspect, the present invention is a method of providing a coated graphene layer structure on a silicon-containing wafer, comprising: (i) providing a wafer stack comprising, in order, a substrate having a bandgap of 6.5 eV or more, a nitride layer, a graphene layer structure, and a dielectric passivation layer, the dielectric passivation layer having an exposed upper surface; (ii) The step of forming or adhering a further layer on the exposed upper surface of the dielectric passivation layer, (iii) The step of removing the substrate by laser lift-off to expose the surface of the nitride layer distal to the graphene layer structure, (iv) The step of wafer bonding the exposed surface of the nitride layer to the surface of a silicon-containing wafer, The present invention provides a method in which the nitride layer of a wafer stack includes a first surface adjacent to the substrate and a second surface adjacent to the graphene layer structure, wherein the first and second surfaces are each independently formed from aluminum nitride or boron nitride.

[0025] In a second aspect, the present invention provides a method for providing a coated graphene layer structure on a silicon-containing wafer, (I) A step of providing a wafer stack comprising, in order, a substrate having a bandgap of 6.5 eV or more, a nitride layer, a graphene layer structure, and a dielectric passivation layer, wherein the dielectric passivation layer has an exposed upper surface, (II) A step of wafer bonding the exposed upper surface of the dielectric passivation layer to the surface of a silicon-containing wafer, (III) The step of removing the substrate by laser lift-off to expose the surface of the nitride layer distal to the graphene layer structure, The present invention provides a method in which the nitride layer of a wafer stack includes a first surface directly adjacent to the substrate and a second surface directly adjacent to the graphene layer structure, wherein the first and second surfaces are each independently formed from aluminum nitride or boron nitride.

[0026] Accordingly, the first and second embodiments share novel features compared to the prior art for providing a coated graphene layer structure on a silicon-containing wafer through the wafer bonding step. Accordingly, the present invention is equivalent to a method for providing a coated graphene layer structure on a silicon-containing wafer, (1) A step of providing a wafer stack comprising, in order, a transparent substrate, a nitride layer, a graphene layer structure, and a dielectric passivation layer, wherein the dielectric passivation layer has an exposed upper surface, (2) The step of forming or adhering a further layer on the exposed upper surface of the dielectric passivation layer, (3) The step of removing the substrate by laser lift-off to expose the surface of the nitride layer distal to the graphene layer structure, The nitride layer of the wafer stack includes a first surface directly adjacent to the substrate and a second surface directly adjacent to the graphene layer structure, wherein the first and second surfaces are each independently formed from aluminum nitride or boron nitride. The method further includes, after the step of removing the substrate, the step of wafer bonding the exposed surface of the nitride layer to the surface of a silicon-containing wafer (in this case, the further layer is preferably a sacrificial layer, such as a metal layer, which is later removed), or The present invention relates to a method in which the step of forming or bonding includes the step of bonding wafers, wherein the further layer is a silicon-containing wafer.

[0027] The present disclosure is described further here. Different aspects / embodiments of the present disclosure are defined in more detail in the following sections. Each of the aspects / embodiments defined in this manner may be combined with any other aspect / embodiment or more aspects / embodiments unless expressly indicated otherwise. In particular, any feature indicated as preferred or advantageous may be combined with any other feature indicated as preferred or advantageous.

[0028] Accordingly, the following features described herein apply equally to both the first and second embodiments unless the context clearly indicates otherwise (e.g., the properties of the further layers and / or which surfaces are wafer-bonded to the silicon-containing wafer). Similarly, in further embodiments, the present invention provides a graphene-containing laminate that can be obtained by the method described herein, thereby any features described in relation to the method may describe the graphene-containing laminate (or any subsequent electronic device manufactured using the method or the graphene-containing laminate).

[0029] The present invention relates to a method for providing a coated graphene layer structure on a silicon-containing wafer. The graphene layer structure in the resulting product (i.e., graphene-containing laminate) is coated over its entire surface with a further layer which is either a nitride layer or a dielectric passivation layer as described herein.

[0030] In the first step, the method provides a wafer stack comprising, in order, a substrate, a nitride layer, a graphene layer structure, and a dielectric passivation layer, wherein the dielectric passivation layer has an exposed upper surface.

[0031] As is well known in the field of semiconductor manufacturing, the terms substrate and wafer can be used interchangeably. Therefore, the term “wafer stack” is used to define a wafer or substrate that includes a substrate on which the described layers forming the stack are located. As understood, a given wafer or substrate may still be referred to as a wafer throughout the entire process of forming a stacked wafer and, ultimately, additional layers from which electronic devices are formed.

[0032] The substrate is transparent to allow the subsequent laser lift-off step. That is, the substrate is transparent to lasers of such wavelengths so that the laser can reach the nitride layer and be absorbed by the nitride layer. Therefore, the substrate may have a band gap of 6.5 eV or more, and the band gap of the nitride layer (i.e., AlN or BN) is lower than this. As a result, the laser is absorbed by the nitride layer and decomposes, separating the nitride layer from the substrate. The band gap of the substrate may preferably be 7.0 eV or more, or 8.0 eV or more. Sapphire is particularly preferred as a transparent substrate and typically has a band gap of at least about 9.0 eV. The following description focuses on the use of sapphire, but other transparent substrates, generally inorganic oxides and fluorides (such as silicon oxide or YSZ, which have a band gap similar to that of sapphire) can be used.

[0033] Sapphire wafers are well known in the art and provide excellent supports for wafer stacks. As a support, sapphire is generally much thicker than any layers later formed on it. Typically, the support layer has a thickness of 250 μm to 1.5 mm, for example, 400 μm to 1 mm. The surface of the sapphire substrate adjacent to the nitride layer may have a specific crystal orientation. For example, the c-plane. <0001> ) or the r-plane (<1-102>) may be preferable for the epitaxial growth of the nitride layer.

[0034] The nitride layer of the wafer stack includes a first surface adjacent to (i.e., directly adjacent to) the sapphire substrate and a second surface directly adjacent to the graphene layer structure. That is, the nitride layer may be formed from a single material (in which case the first and second surfaces are formed from the single material) or may consist of two or more sublayers, so that the first surface is provided by a first sublayer and the second surface is provided by a second sublayer. According to the present invention, it is beneficial that the surfaces adjacent to the sapphire substrate and the graphene layer structure are formed from either aluminum nitride or boron nitride. As will be further described herein, these materials are particularly suitable for this process and can be used to address some of the problems associated with incorporating two-dimensional materials into silicon-based processes. Thus, the first and second surfaces are each independently formed from either aluminum nitride or boron nitride.

[0035] Therefore, in some embodiments, the nitride layer consists of aluminum nitride or boron nitride. It is generally preferable that the nitride layer includes at least a sublayer of aluminum nitride. Therefore, in some preferred embodiments, the nitride layer is formed of two sublayers, namely a first sublayer of aluminum nitride or boron nitride that provides a first surface and a second sublayer of aluminum nitride or boron nitride that provides a second surface (the first and second sublayers being different).

[0036] In some embodiments, the nitride layer includes one or more further sublayers between a first sublayer and a second sublayer, the further sublayers being formed from nitride. For example, the nitride layer may include one further sublayer and / or be formed from a metallic nitride such as gallium nitride. In one preferred embodiment, one or more further sublayers include a multiple quantum well (MQW) structure, or otherwise take the form of a multiple quantum well (MQW) structure. MQWs are known and, as mere examples, may include a plurality of thin GaN layers, each separated from each other by AlN, AlGaN, or InGaN. Preferred materials and thicknesses are known to those skilled in the art, and each GaN layer of the MQW may typically have a thickness of, for example, 3 nm to 20 nm.

[0037] Generally, nitride layers containing three or more sublayers are thicker than nitride layers formed from a single material or two sublayers. The thickness of the nitride layer is generally up to 10 μm, but this can be much thinner if there are no intermediate sublayers.

[0038] The aluminum nitride layer of the wafer stack preferably has a thickness of at least 100 nm (as either a single layer or a sublayer), for example, at least 150 nm. Generally, the layer thickness is at most 5 μm, preferably at most 2 μm. As described herein, the nitride layer may be etched to reduce its thickness in a manner particularly useful for reducing the thickness of the aluminum nitride layer.

[0039] The boron nitride layer may have a thickness equivalent to that of the aluminum nitride layer, which may depend on the crystal structure of the boron nitride. Aluminum nitride is always supplied in its wurtzite crystal structure. Boron nitride may be supplied in an equivalent wurtzite crystal structure (w-BN) or in a cubic morphology (c-BN) similar to that of diamond. Boron nitride is preferably supplied in a hexagonal morphology (h-BN), a known two-dimensional morphology similar to that of graphene. In such situations, the thickness of the boron nitride layer may be much thinner, for example, about 0.6 nm to 100 nm, preferably about 0.9 nm to 20 nm. A thickness of at least 0.3 nm essentially corresponds to at least one layer of h-BN, which may be preferred for a second sublayer adjacent to the graphene layer structure. However, a thicker boron nitride layer may be required adjacent to the sapphire substrate to allow laser ablation of the layer at the interface with the sapphire substrate while retaining portions for integration into electronic devices.

[0040] Preferably, the nitride layer of the wafer stack is provided by forming the nitride layer directly onto the sapphire substrate by epitaxy. Generally, the nitride layer, and each sublayer if formed from sublayers, is preferably formed by MOCVD. Such techniques for forming nitride layers are known in the art, particularly on sapphire, which enables high-quality AlN and BN growth. Furthermore, forming the layer by MOCVD allows for in-situ formation of the graphene layer structure immediately thereafter, which is beneficial for high-quality graphene formation. With respect to graphene, and particularly with respect to h-BN, as described herein, such a step avoids the need to transfer two-dimensional material, thereby avoiding the introduction of contaminants and defects.

[0041] Therefore, the wafer stack is particularly preferably provided by forming a graphene layer structure directly on a nitride layer (i.e., on the nitride layer of a “first” wafer containing a sapphire substrate and a nitride layer) by CVD. The nitride layer described herein is particularly beneficial for CVD growth of graphene because the layer can withstand the high temperatures required for CVD and can support the growth of graphene. In particular, the inventors have found that forming graphene on an exposed surface of GaN, for example, carries the risk of decomposition of the growth surface. Therefore, this method makes it possible to integrate high-quality graphene with a nitride layer on a silicon-based wafer.

[0042] Graphene is a well-known two-dimensional material that refers to an allotrope of carbon containing a single layer of carbon atoms in a hexagonal lattice. As used herein, a graphene layer structure refers to one or more layers of graphene. Accordingly, the present invention relates to the formation of monolayer graphene and multilayer graphene. A graphene layer structure preferably has 1 to 10 monolayer graphene. In many subsequent applications of graphene-containing laminates for forming electronic devices, a single monolayer of graphene is particularly preferred. Therefore, a graphene layer structure is preferably a single layer of graphene. Nevertheless, multilayer graphene may be preferred for certain applications, and two or three layers of graphene may be preferred.

[0043] CVD generally refers to a variety of chemical vapor deposition techniques, each involving the deposition of thin film materials, such as two-dimensional crystalline materials like graphene. Volatile precursors (in the gaseous phase or suspended in a gas) decompose to release the necessary species to form the desired material (carbon in the case of graphene). As described herein, CVD is intended to refer to thermal CVD, where the formation of graphene from the decomposition of a carbon-containing precursor is a result of the thermal decomposition of the carbon-containing precursor. Forming can be considered synonymous with synthesizing, manufacturing, producing, depositing, and growing.

[0044] Preferably, the method involves forming graphene by thermal CVD such that the decomposition is a result of heating a carbon-containing precursor. Preferably, the temperature of the growth surface (i.e., the exposed upper surface of the wafer) during CVD is 700°C to 1350°C, preferably 800°C to 1250°C, and more preferably 1000°C to 1250°C. The inventors have found that such temperatures are particularly effective in providing graphene growth directly on a nitride layer by CVD. Preferably, the CVD reaction chamber used in the method disclosed herein is a cold-wall reaction chamber in which a heater coupled to the wafer is the sole heat source to the chamber.

[0045] In a preferred embodiment, the CVD reaction chamber comprises a tightly coupled showerhead having a plurality of precursor inlet points or an array of precursor inlet points. Such CVD apparatuses with a tightly coupled showerhead may be known for use in MOCVD processes. Thus, it can be said that the method is alternatively carried out using an MOCVD reactor with a tightly coupled showerhead. In either case, preferably, the showerhead is configured to provide a minimum spacing of less than 100 mm, more preferably less than 25 mm, and even more preferably less than 10 mm between the substrate / wafer surface and the plurality of precursor inlet points. As understood, constant spacing means that the minimum spacing between the substrate surface and each precursor inlet point is substantially the same. Minimum spacing refers to the minimum spacing between a precursor inlet point and the substrate surface. Thus, such embodiments involve a “perpendicular” arrangement where the plane containing the precursor inlet points is substantially parallel to the plane of the substrate growth surface (i.e., the nitride layer).

[0046] The precursor inlet points into the reaction chamber are preferably cooled. To maintain a relatively low temperature at the precursor inlet points, such that the temperature of the precursor is below 100°C, preferably below 50°C, as the precursor passes through multiple precursor inlet points and enters the reaction chamber, the inlet, or showerhead if used, is preferably actively cooled with an external coolant, such as water. To avoid doubt, adding the precursor at a temperature higher than the ambient temperature does not constitute heating of the chamber, because it is a waste of heat within the chamber and is partly involved in creating a temperature gradient within the chamber.

[0047] Preferably, a combination of a sufficiently small gap between the growth surface and a plurality of precursor inlet points, and cooling of the precursor inlet points, coupled with heating the growth surface within the precursor decomposition range, generates a sufficiently steep temperature gradient extending from the surface to the precursor inlet points, enabling graphene formation on the surface. As disclosed in International Publication No. 2017 / 029470, a very steep temperature gradient may be used to facilitate the formation of high-quality, uniform graphene directly on such a non-metallic substrate, preferably across the entire surface of the substrate. The substrate / wafer may have a diameter of at least 5 cm (2 inches), at least 15 cm (6 inches), or at least 30 cm (12 inches). Particularly suitable apparatus for the method described herein include the Aixtron® Close-Coupled Showerhead® reactor and the Veeco® TurboDisk reactor.

[0048] Therefore, in a particularly preferred embodiment of the present invention, which involves using the method disclosed in International Publication No. 2017 / 029470, forming a graphene layer structure on the growth surface by CVD is To provide a first wafer on a heated susceptor in a tightly coupled reaction chamber, wherein the tightly coupled reaction chamber has a plurality of cooled inlets, and the plurality of cooled inlets are arranged such that, during use, the inlets are distributed across the growth surface and are at a certain distance from the first wafer. Cool the inlet to below 100°C, Introducing a carbon-containing precursor suspended in the gas phase and / or gas into a tightly coupled reaction chamber through the inlet, This includes heating the susceptor until a growth plane temperature is achieved that exceeds the precursor decomposition temperature of at least 50°C, thereby providing a thermal gradient between the growth surface and the inlet that is steep enough to allow the formation of graphene from the carbon released from the decomposed precursor, The interval is less than 100 mm, preferably less than 25 mm, and more preferably less than 10 mm.

[0049] In another particularly preferred embodiment, the method involves using the method disclosed in International Publication No. 2019 / 138231 (the contents of which are incorporated herein by reference in their entirety), in which a graphene layer structure is formed on the growth surface by CVD, To provide a first wafer on a heated susceptor in a reaction chamber, wherein the reaction chamber has a plurality of inlets, and the plurality of cooled inlets are arranged such that, during use, the inlets are distributed across the growth surface and are at a certain distance from the first wafer. The heated susceptor is rotated at a rotational speed of at least 600 rpm, preferably up to 3000 rpm, Introducing a carbon-containing precursor suspended in the gas phase and / or gas into the reaction chamber through the inlet, This includes heating the susceptor to achieve a growth surface temperature at which the precursor decomposition temperature is at least 50°C, The spacing is at least 12 cm, preferably up to 20 cm.

[0050] The most common carbon-containing precursor in the art for graphene growth is methane (CH4). The inventors have found that the carbon-containing precursor used to form graphene is preferably an organic compound, i.e., a compound or molecule containing two or more carbon atoms and containing carbon-hydrogen covalent bonds. Such precursors have a lower decomposition temperature than methane, which favorably allows for graphene growth at lower temperatures when using the methods described herein, which is particularly advantageous for growth on such nonmetallic nitride surfaces. Preferably, the precursor is liquid when measured at 20°C and a pressure of 1 bar (i.e., under standard conditions according to IUPAC). Therefore, the precursor preferably has a melting point below 20°C, preferably below 10°C, and a boiling point above 20°C, preferably above 30°C. Liquid precursors are easier to store and handle compared to gaseous precursors, which typically require high-pressure cylinders. Compared to gaseous precursors, their relatively low volatility means they pose a lower safety risk during large-scale production. 10 Beyond, especially about C 12 Increasing beyond a certain point typically reduces their volatility and suitability for CVD growth of graphene on nonmetallic surfaces. Preferably, the organic compound consists of carbon and hydrogen, and optionally oxygen, nitrogen, fluorine, chlorine, and / or bromine.

[0051] As described above, the methods described herein preferably involve organic compounds containing two or more carbon atoms, i.e., C 2+ A carbon-containing precursor, which is an organic compound, is used. Preferably, the carbon-containing precursor consists of carbon and hydrogen, and optionally oxygen, nitrogen, fluorine, chlorine, and / or bromine (C3-C3). 12 It is an organic compound. As described herein, C nThe organic compound refers to those containing "n" carbon atoms and optionally one or more additional heteroatoms oxygen, nitrogen, fluorine, chlorine, and / or bromine. Preferably, the organic compound contains at most one heteroatom, and such organic compounds are typically of higher purity and more readily available, for example, ethers, amines, and haloalkanes.

[0052] The carbon-containing precursor preferably consists of carbon and hydrogen, and optionally oxygen, nitrogen, fluorine, chlorine, and / or bromine, and is C3 to C 10 An organic compound, more preferably a C6 - C9 organic compound. In a preferred embodiment, the precursor does not contain heteroatoms, and as a result, the precursor consists of carbon and hydrogen. In other words, preferably, the carbon-containing precursor is a hydrocarbon, preferably an alkane.

[0053] Also, the organic compound preferably contains at least two methyl groups (-CH3). Particularly preferred organic compounds for use as the carbon-containing precursor and the method of forming graphene therefrom by CVD are described in UK Patent Application Publication No. 2604377 (the content of which is incorporated herein in its entirety). The inventors have found that when forming graphene directly on a non-metallic substrate, precursors beyond the conventional hydrocarbons methane and acetylene enable the formation of higher-quality graphene. Preferably, the precursor is a C4 - C 10 organic compound, and more preferably, the organic compound is branched such that the organic compound has at least three methyl groups.

[0054] Without being bound by theory, the inventors believe that heavier organic compounds (i.e., C 12 larger ones or C 10Larger compounds (and / or solid under standard conditions) are considered to provide a “less pure” source of CH3 radicals. As the size and complexity of the organic compounds increase, the number of decomposition pathways increases, and the range of by-products that can result in graphene defects may increase. The organic compounds described herein offer a balance that is large enough to yield the desired high fraction of methyl groups required under thermal decomposition. However, the organic compounds are small enough to be easily purified, especially when the precursor is liquid, and have a relatively simple thermal decomposition chemistry with limited decomposition pathways. Furthermore, unlike heavier compounds, they do not readily condense in the reactor piping, which is particularly disadvantageous for the industrial production of graphene due to the greater risk of reactor downtime.

[0055] The wafer stack further includes a dielectric passivation layer on the graphene layer structure that provides the exposed upper surface of the wafer stack. Therefore, providing a wafer stack preferably includes the step of forming a further layer containing dielectric material on the graphene layer structure, particularly when the graphene layer structure is formed directly on the first wafer by CVD.

[0056] One advantage of the second embodiment is that it provides a high-quality nitride layer on solid graphene by avoiding the need to form a layer on graphene. However, the present invention still requires forming a dielectric passivation layer on the graphene before the wafer bonding step in order to protect the graphene. In the second embodiment, this layer then simply forms part of the underlying support after being "inverted," but still provides a passivation layer in the laminate obtained from the method of the first embodiment. As described herein with respect to the nitride layer, the dielectric passivation layer may consist of a single material or two or more sublayers. Preferably, the dielectric passivation layer is formed from an inorganic oxide, nitride, carbide, fluoride, or sulfide, preferably a metal oxide. Preferably, the dielectric passivation layer has a thickness of 0.5 nm to 500 nm, preferably 1 nm to 100 nm.

[0057] The inventors have found that additional layers may be formed on the graphene layer structure to dope the graphene. The additional layers preferably comprise dielectric metal oxides, preferably molybdenum oxide. Another preferred group of materials is transition metal dichalcogenides (TMDs), which are well known two-dimensional materials (most commonly molybdenum or tungsten, disulfides, diselenides, or diterlides). TMDs and molybdenum oxide are particularly preferred materials, and molybdenum oxide in particular has been found by the inventors to be suitable for counter-doping CVD-grown graphene (which is typically n-type, although the intrinsic doping of transferred graphene is typically p-type due to exposure to a catalytic metal substrate and / or transfer polymer and / or wet processing chemicals). Therefore, the dielectric passivation layer preferably comprises a first sublayer formed from a transition metal dichalcogenide or molybdenum oxide, the first sublayer preferably provided on the graphene layer structure. The second sublayer may be formed from a conventional inorganic oxide, nitride, carbide, fluoride, or sulfide, such as aluminum oxide.

[0058] The thickness of such a first sublayer is preferably less than 5 nm, more preferably less than 3 nm, for example, 0.1 nm to 5 nm. The inventors have found that this thickness can be used to control the degree of doping of the graphene layer structure to reach a desired charge carrier concentration, thereby resulting in greater thickness resulting in greater p-doping. The desired apparent thickness can be achieved, in particular, by using a quartz crystal microbalance (QCM) during the formation of molybdenum oxide, which provides in-situ measurement of the amount of material deposited when carrying out the present method. Thus, the thickness of the layer is the average thickness of the layer. In this case, the thickness can be determined equally easily by a person skilled in the art using the prior art, e.g., AFM. Further layers may be deposited using conventional means in the art, e.g., PVD techniques such as sputtering or vapor deposition (e.g., thermal deposition). Techniques for forming TMDs are known in the art.

[0059] In some embodiments, the graphene layer structure is 5 × 10 as a result of the combination of materials and manufacturing methods described herein. 12 cm -2 Less than 2 × 10 12 cm -2 Less than 10 12 cm -2 It has a charge carrier concentration of less than 0.0.0. The charge carrier concentration is measured under ambient conditions (e.g., 25°C) after manufacturing is complete. Graphene-containing laminates can be incorporated into the manufacturing of devices; therefore, the charge carrier concentration refers to the charge carrier concentration of the laminate or device as it is at the time of final manufacturing.

[0060] The method further includes the steps of forming or bonding a further layer on the exposed upper surface of the dielectric passivation layer (i.e., on the wafer stack), and then removing the sapphire substrate by laser lift-off to expose the surface of the nitride layer distal to the graphene layer structure.

[0061] According to a first embodiment, the method further includes, after the step of removing the sapphire wafer, the step of wafer bonding the exposed surface of the nitride layer to the surface of the silicon-containing wafer. In this embodiment, the further layer is a sacrificial layer, and thereby the method generally preferably subsequently includes the step of removing the further layer after the wafer bonding step. In some preferred embodiments, the layer is an etchable layer formed from, for example, a metal. Copper is a common metal used in the LLO process for GaN-based LED manufacturing. However, other metals such as aluminum, titanium, and / or nickel may be preferred to avoid copper contamination in the CMOS process. Such a layer may be formed by depositing it over the exposed upper surface of a dielectric passivation layer. Other techniques known in the art include electroplating. Alternatively, the metal layer may be bonded to the upper surface exposed by wafer bonding, for example, optionally via a bonding layer of indium, nickel, gold, or palladium.

[0062] In some embodiments, the additional layers are completely removed. However, it may also be preferable to etch the metal layer to form the gate contacts of an electronic device such as a transistor.

[0063] According to a second embodiment, the step of forming or bonding includes a wafer bonding step, wherein the further layer is a silicon-containing wafer, thereby bonding the dielectric passivation layer to the surface of the silicon-containing wafer.

[0064] The silicon-containing wafers of any particular form are not particularly limited. In some preferred embodiments, the wafer is a CMOS wafer. Such wafers are typically silicon wafers having associated circuits embedded therein along with a appropriately patterned dielectric layer. Preferred silicon-containing wafers may also include regions or channels of embedding material, such as waveguide material, including silicon nitride embedded in silicon dioxide, which are suitable for electro-optic modulators and photodetectors (which may be provided on a silicon support). The exposed contact surfaces of the wafer may also be formed from regions of different materials. For example, a silicon support may have a surface including a patterned region of silicon and a region of embedded dielectric material. Such wafers may be suitable for the manufacture of graphene varistors. The silicon-containing wafer or silicon support may preferably be "pure" silicon (essentially consisting of doped or undoped silicon). When a silicon-containing wafer includes a layer of silicon oxide or silicon nitride on a silicon support, the exposed surface of the layer is distal to the silicon support (the non-exposed surface on the opposite side of the layer is the surface in contact with the support). The silicon oxide and / or silicon nitride may have a thickness of 50 to 500 nm. In some embodiments for the manufacture of very thin electronic devices, the method preferably further includes the step of removing the silicon support after the wafer bonding step.

[0065] A silicon-containing wafer is advantageous in that its exposed surface can include metal contacts (with any associated circuits embedded therein). This is particularly beneficial when a CVD-grown graphene layer structure is used, because direct growth on metal contacts rather than non-metallic surfaces is undesirable, as is the case with growth by the MOCVD process described herein. Therefore, this method makes it possible to incorporate graphene formed by such a method into a device having underlying contacts.

[0066] Wafer bonding processes are generally known. Preferably, the wafer bonding step is direct bonding (sometimes called fusion bonding). Such a process is typically used, for example, to bond two layers of dielectric oxide, nitride, and / or metal contacts, thereby resulting in a chemical bond between the two surfaces, as the two surfaces are sufficiently clean and smooth and have bonding sites available for hydrogen and / or covalent bonding.

[0067] Such steps can be performed in conventional wafer bonding equipment. Typically, the process includes heating the contacted wafers while applying an optional force. This step is particularly preferably performed under vacuum to remove as much oxygen and / or moisture as possible from the surfaces of the two wafers.

[0068] Preferably, wafer bonding is performed at a temperature of 100°C to 850°C, preferably 150°C to 450°C, for example, 200°C to 400°C. These temperatures are generally preferable because a protective layer, such as molybdenum oxide, protects the graphene, reducing the risk of damaging the graphene, and the additional layer facilitates wafer bonding. If the silicon-containing wafer is a CMOS wafer, a maximum of 850°C is preferred. Typical dielectric layers on the silicon support include silicon oxide, silicon nitride, alumina, hafnia, etc., and may also incorporate surface-exposed metal contacts and embedded metal vias, as described herein. A force of at least 100 N, for example, at least 500 N, may be applied during wafer bonding, and / or in some embodiments, a force of up to 10 kN may be applied.

[0069] The method may further include, before wafer bonding, a step of patterning the layers to be provided on any of the above-described wafers, in particular a support (e.g., a sapphire support in a wafer stack, or a support provided by further layers according to the first embodiment, either of which may be referred to as the first wafer, or a silicon support in a silicon-containing wafer, which may be referred to as the second wafer). That is, one or more of the nitride layers, graphene layer structures, and dielectric layers of the first wafer, and / or any layers and / or metal contacts of the second wafer may be patterned. This can be done using conventional photolithography techniques, and may also be used to provide metal contacts, as described below.

[0070] For example, the first wafer may be patterned before the wafer bonding step to pattern the graphene layer structure into a desired device shape (i.e., an array of individual devices across the wafer), along with any further layers provided on the surface, preferably retaining the same shape as the graphene and thereby acting as a protective cap. The underlying layers (e.g., nitride or dielectric passivation layers) may also be optionally patterned at this stage, and may be optionally patterned to the same shape. Alternatively, as described in the exemplary embodiments herein, such patterning may be performed after wafer bonding and removal of the support of the first wafer. As understood, any layers beneath the graphene layer structure then become "on top" of the graphene surface, and any further layers or metal contacts that may be deposited then become beneath the graphene layer structure in the resulting laminate (when viewed together with the silicon support at the bottom of the resulting laminate).

[0071] The second wafer may also be patterned before wafer bonding. In some preferred embodiments, the pattern is substantially a "negative" of the pattern on the first wafer in order to ensure conformal contact between the two patterned surfaces of the first and second wafers. Each wafer may further include patterning alignment markers to facilitate the orientation and optical alignment of the two wafer surfaces for the subsequent wafer bonding step. In this way, a complete device structure can be obtained without requiring further patterning after the support of the first wafer is removed. As understood, further layers and / or further metal contacts may nevertheless be deposited and patterned after wafer bonding (e.g., to provide gate contacts).

[0072] Therefore, in some embodiments, it is particularly preferable to form metal contacts that come into contact with the graphene layer structure before laser lift-off, preferably, for example, a dielectric passivation layer, before wafer bonding. The contacts may be deposited during the patterning step (for example, before or after patterning the graphene layer structure into the desired shape of the device).

[0073] The exposed surfaces of the metal contacts on the first and / or second wafers may preferably be coplanar with the exposed surfaces of the surrounding material (e.g., dielectric or nitride layers). Substantially flat layers are particularly preferred for wafer bonding without metal contacts to ensure good interlayer contact and bonding. Advantageously, complementary metal contacts (i.e., metal-to-metal) are typically easier to bond together during the wafer bonding step (requiring lower temperatures and / or pressures, which is advantageous in avoiding excessive damage to other layers, particularly the graphene layer structure). In other embodiments, the metal contacts on one of the wafers may protrude from the exposed top surface. Typically, the height difference between the metal contact and the surface of the adjacent layer is less than 10 μm, more preferably less than 5 μm. This difference may also be at least 100 nm, at least 500 nm, or at least 1 μm.

[0074] This method includes the step of removing the sapphire substrate by laser lift-off. LLO is a process known in the art, involving irradiation of the interface between a suitably transparent substrate, such as sapphire, and an absorption layer. As those skilled in the art will understand, the laser is irradiated through the transparent substrate, ablating and vaporizing the layer at the interface. Although not bound by theory, even when the nitride (sub)layer adjacent to the sapphire substrate is formed from h-BN, the two-dimensional material inevitably involves some covalent interactions with the sapphire substrate, especially when formed epitaxy on the substrate, and as a result, LLO provides a novel and unique approach for incorporating a combination of high-quality nitride and graphene layer structures into silicon-based wafers.

[0075] As is well known in the art, the laser wavelength for LLO is selected based on the band gap of the material; for example, a wavelength of about 193 nm is suitable for AlN (whose band gap is about 6.0 eV). A similar wavelength may also be suitable for BN, although the interfacial amorphous or semi-amorphous phase of h-BN may have a lower band gap (e.g., about 4.5 eV) and is thought to require a laser with a lower energy wavelength (e.g., about 275 nm). Nevertheless, suitable wavelengths for separating a sapphire substrate from an aluminum nitride or boron nitride layer can be determined by those skilled in the art as a routine experimental procedure.

[0076] In some embodiments, the nitride layer is etched. Methods for etching nitrides are known in the art, and any suitable method can be used. For example, the nitride layer may be etched by dry techniques such as inductively coupled plasma (ICP) etching or reactive ion etching. These can use, for example, chlorine and / or fluorine-containing gases (Cl2 gas is common, and one exemplary gas mixture is Cl2 / BCl3 / Ar). The nitride layer may also be etched by wet techniques such as chemical etching using a solution of KOH, H3PO4, HF, and / or TMAH. According to a first embodiment in which the nitride layer is wafer-bonded to a silicon-containing wafer after the LLO step, the nitride layer may preferably be etched or polished after LLO to ensure that a suitably smooth and flat surface is provided for the wafer bonding step. According to a second embodiment in which the resulting laminate includes a nitride layer on a graphene layer structure, the nitride layer may also preferably be etched after the sapphire substrate has been removed by LLO. After etching, the nitride layer may have a thickness of less than 50 nm, preferably less than 10 nm, particularly in the second embodiment, so that the nitride layer can function as a high-quality thin gate dielectric layer in an electronic device.

[0077] Considering the above, one particularly preferred embodiment is a method, A step of providing a wafer comprising a sapphire substrate and a nitride layer, wherein the nitride layer is made of aluminum nitride and has an exposed upper surface, A step of forming a graphene layer structure by CVD directly on the exposed upper surface of a nitride layer of a wafer, the graphene layer structure having an exposed upper surface, A wafer stack comprising the steps of forming a dielectric passivation layer on the exposed upper surface of a graphene layer structure, thereby forming a wafer stack comprising, in order, a sapphire substrate, a nitride layer, a graphene layer structure, and a dielectric passivation layer, wherein the dielectric passivation layer has an exposed upper surface, The steps include forming or bonding a further layer on the exposed upper surface of the dielectric passivation layer, The process includes the step of removing the sapphire substrate by laser lift-off to expose the surface of the nitride layer distal to the graphene layer structure, The method further includes, after the step of removing the sapphire wafer, the step of wafer bonding the exposed surface of the nitride layer to the surface of a silicon-containing wafer, or A method comprising the step of forming or bonding, wherein the step of bonding wafers is a wafer bonding step, and the further layer is a silicon-containing wafer.

[0078] According to a further aspect of the present invention, a method for manufacturing an electronic device, The steps include providing a coated graphene layer structure on a silicon-containing wafer by any method described herein, A step of patterning a graphene layer structure and at least a layer on it, for example, a dielectric passivation layer or a nitride layer, or both; A method is provided which includes the step of forming one or more electrical contacts that come into contact with a graphene layer structure.

[0079] As can be understood, such a process is particularly suitable for fabricating an array of electronic devices on a single wafer. Patterning of the graphene layer structure can be carried out using conventional techniques in the field of microelectronics fabrication of electronic devices, such as photolithography. Such a process is not particularly limited because the graphene is protected by a coating layer. One or more electrical contacts may be formed to contact only the edges of the graphene layer structure. In some embodiments, gate contacts may be formed on the graphene layer structure on a nitride or passivation layer.

[0080] Preferably, after patterning, and optionally after contact formation, The method further includes, for example, forming a dielectric coating layer across a wafer by ALD, thereby encapsulating the graphene layer structure and any edges (and surfaces) of the graphene exposed by the patterning step.

[0081] Preferably, the method for manufacturing an electronic device further includes the step of dicing a silicon-containing wafer. As understood, additional layers, such as any unpatterned nitride layer or dielectric passivation layer, may also be diced simultaneously. Dicing is a process known in the art of silicon-based, for example, CMOS fabrication processes, which divides a wafer containing an array of stacks of patterned semiconductor layers so that each stack forms an electronic device sharing a common substrate. For example, dicing may involve mechanical sawing or laser cutting.

[0082] Preferably, the step of providing the wafer stack is: (A) A step of providing a first wafer including the nitride layer on the sapphire substrate, wherein the nitride layer has an exposed growth surface distal to the sapphire substrate, and the nitride layer has a first region extending at least 2 nm below the exposed growth surface, and the first region is a) 5,000 cm² measured by TEM -2Dislocation density less than, b) A step that satisfies the requirement of a surface roughness (Ra) of less than 1 nm as measured by AFM, (B) The step of forming a graphene layer structure on a growth surface exposed by CVD, and forming a further layer containing a dielectric material on the graphene layer structure to form a dielectric passivation layer, The method is, (IV) Further comprising the step of removing a portion of the nitride layer to leave a retaining portion of the nitride layer formed from the first region and having a thickness of less than 20 nm.

[0083] Since the nitride layer is provided as a top layer (i.e., on top of the graphene layer structure) in the resulting graphene-containing laminate, such a step is particularly preferred in a second aspect of the present invention. Accordingly, the method provides a process that enables the incorporation of a thin (less than 20 nm) layer of nitride, particularly aluminum nitride, onto a high-quality graphene layer (i.e., a layer lacking essential defects and nucleation sites that would allow for the formation of a nitride layer).

[0084] The first region is characterized by at least a portion (or the entire nitride layer) of a nitride layer having a thickness of at least 2 nm. Dislocation density helps characterize the high degree of single crystallinity of the first region and can be measured using conventional techniques known to those skilled in the art, such as TEM (e.g., cross-sectional TEM). 4,000 cm -2 Less than 2,000 cm -2 While lower dislocation densities are generally preferred, and although not theoretically bound by convention, a minimum number of dislocations may still be desirable, as these defect sites on the exposed surface of the nitride layer are thought to provide sites for graphene nucleation by CVD. Therefore, the minimum defect density is at least 1 cm³. -2 at least 10cm -2 , or at least 100cm -2 That's fine.

[0085] The first region also has a surface roughness of less than 1 nm, which can be measured again by conventional techniques known to those skilled in the art, such as AFM. As understood, this is a measurement of the exposed growth surface of the nitride layer. Such low surface roughness facilitates the formation of high-quality graphene by CVD. In some embodiments, the surface roughness may be less than 0.8 nm or less than 0.6 nm. As used herein, surface roughness refers to the arithmetic mean roughness known as Ra.

[0086] Preferably, the first region of the first layer extends at least 5 nm, preferably at least 10 nm, and preferably at least 20 nm downward from the exposed growth surface. Dislocation density is a parameter known in the art, but is typically used to characterize significantly thicker layers (e.g., GaAs layers in LED structures). Dislocation density is often measured by XRD, which provides an average dislocation density over the entire layer (which may be several micrometers thick). In the above example of GaAs, the dislocation density over the entire layer is important for the characteristics of the final device. In contrast, this embodiment utilizes a much thinner top region that is retained in the final laminate. TEM is a measurement technique that allows for the measurement of dislocation density close to the surface of the layer, but in practice, it becomes difficult to accurately measure the dislocation density in regions less than 2 nm thick. Therefore, it is preferable to characterize the first region with a thickness of at least 10 nm, for example. Since the nitride layer portion held in the resulting laminate is less than 20 nm, it is sufficient for the first region to extend 20 nm down from the exposed growth surface (for example, 2 nm to 20 nm or 10 nm to 20 nm) (of course, it may extend further).

[0087] Where described herein, the method may include a step of removing a portion (and optionally a first region) of the nitride layer to provide a thin nitride layer of less than 20 nm. In some preferred embodiments, the thickness of the nitride layer and / or its first region is such that the method does not involve a step of later removing a portion. For example, a nitride layer formed from a single material may have a thickness of about 5 nm, and the entire first layer and the entire layer that satisfy the requirements of the first region may be used as a layer in the final device without the need to remove a portion of it in a later step described herein.

[0088] In a further embodiment, the present invention relates to a graphene-containing laminate, which in turn, (i) A silicon support of any choice, (ii) Primary dielectric layer and (iii) Graphene layer structure, (iv) A nitride layer having a thickness of less than 20 nm, which is measured by TEM at 5,000 cm -2 A nitride layer having a dislocation density of less than , The nitride layer includes a primary surface directly adjacent to the graphene layer structure and a secondary exposed upper surface, and the primary and secondary surfaces are each independently formed from aluminum nitride or boron nitride. The present invention provides a graphene-containing laminate in which one or more further dielectric layers are provided between the primary dielectric layer and the graphene layer structure.

[0089] Therefore, graphene grown directly on a secondary dielectric layer by CVD avoids physical transfer processing. Normally, the physical migration of graphene from a copper substrate can introduce numerous defects that adversely affect the physical and electronic properties of the graphene. Thus, those skilled in the art can easily determine whether a graphene layer structure, and by extension a graphene-containing laminate, includes a CVD-grown graphene layer structure grown directly using conventional techniques in the art, such as AFM and energy-dispersive X-ray (EDX) spectroscopy. Graphene layer structures are free from metallic, particularly copper, impurities, and organic polymer residues because these materials are completely absent in the process of obtaining the graphene-containing laminate. Furthermore, such processing is unsuitable for large-scale manufacturing (such as on CMOS substrates in a manufacturing plant). Unintentional doping, especially from catalytic metal substrates together with etching solutions, also results in the generation of graphene that is not sufficiently consistent between samples, as required for the commercial production of electronic devices.

[0090] The primary dielectric layer is a layer derived from a silicon-containing wafer, as described in relation to a method that allows for the removal of the underlying silicon support. In some embodiments, the silicon support and the primary dielectric layer are provided in the form of a CMOS wafer. One or more further dielectric layers are derived from dielectric passivation layers, as described in relation to the method.

[0091] The present invention will now be further described with reference to the following non-limiting figures. [Brief explanation of the drawing]

[0092] [Figure 1] This invention provides a wafer stack suitable for use in this invention. [Figure 2] One method of the present invention using a wafer stack provided by the process shown in Figure 1 is illustrated. [Figure 3] Figure 2 shows an exemplary fabrication of an electronic device from a graphene-containing laminate provided by the method described therein. [Figure 4] Further methods of the present invention are shown. [Modes for carrying out the invention]

[0093] The diagram shows the manufacturing method, with the wafer shown in cross-section.

[0094] Figure 1 shows an exemplary process that provides a wafer stack 220 suitable for use in the present invention. In the first step 100, an aluminum nitride layer 205a is formed on the surface of the sapphire substrate 200 to a thickness of more than 150 nm by MOCVD. In the second step 105, an h-BN layer 205b is formed in situ by MOCVD, thereby forming nitride layers 205a and 205b, so that the aluminum nitride layer 205a has a surface 205a' directly adjacent to the sapphire substrate 200.

[0095] Next, in the third step 110, a graphene monolayer 210 is formed in situ on the exposed upper surface 205b' of the h-BN layer 205b at a temperature exceeding 700°C, and in the fourth step 115, a dielectric passivation layer 215 is formed on the exposed surface 210' of the graphene monolayer 210, thereby forming a coating. Preferably, the further layer 215 contains molybdenum oxide having a maximum thickness of about 5 nm on the graphene monolayer 210, and may also contain further layers such as aluminum oxide. The resulting wafer stack 220 has an exposed upper surface 215' provided by the dielectric passivation layer 215.

[0096] Figure 2 shows an exemplary method according to a first aspect of the present invention using the wafer stack 220 provided by the process of Figure 1. In step 120, a sacrificial layer of an etchable metal 225, for example nickel, is formed or bonded to the exposed upper surface 215' of the dielectric passivation layer 215. Then, in step 125, the sapphire substrate 200 is removed by irradiating the interface between the sapphire substrate 200 and the aluminum nitride layer 205a with a laser suitable for decomposing the aluminum nitride surface 205a'. For example, an ArF pulsed excimer laser having a wavelength of about 193 nm is preferred, so that the laser irradiation 230 passes through the wide-bandgap sapphire substrate 200 and is absorbed by the aluminum nitride 205a.

[0097] The exposed surface of the aluminum nitride layer 205a may be etched or polished before step 130 of wafer bonding to the surface 235b' of the silicon-containing wafer 235. The wafer 235 may comprise a silicon support 235a having a dielectric upper layer 235b such as silicon oxide. The silicon-containing wafer is not particularly limited, and many suitable variations are known to those skilled in the art and can be selected depending on the intended end device application. The wafer bonding step 130 results in a coated graphene layer structure (i.e., a graphene-containing laminate) 240 on the silicon-containing wafer.

[0098] Figure 3 shows an exemplary manufacturing process for a transistor 260 from a graphene-containing laminate 240 provided by the method of Figure 2. One advantage of the method according to the first embodiment is the option in step 135 to etch the sacrificial metal layer to provide electrical contacts 245 for electronic devices such as gate contacts. The resulting wafer may be processed in one or more further steps 140 using conventional fabrication processes such as photolithography to deposit further electrical contacts 250a, 250b that can function as source and drain contacts. Each of these contacts contacts at least the edge of the graphene monolayer 210 (together with at least the edges of the dielectric passivation layer 215 and the h-BN layer 205b), thereby forming the transistor 260. The dielectric passivation layer 215 and the h-BN layer 205b may be co-patterned to have the same shape as the graphene monolayer 210. The transistor 260 further includes a coating layer 255 over the entire wafer, which may be formed, for example, by ALD and / or aluminum oxide. Although only one device is shown, it will be understood that this process can produce an array of devices that share a common underlying substrate (silicon support 235a), and each device can be separated by dicing for packaging.

[0099] Figure 4 shows an exemplary method according to a second aspect of the present invention, using a wafer stack 420 formed from, in order, a sapphire substrate 400, a nitride layer 405 made of aluminum nitride, a CVD-grown graphene monolayer 410, and a dielectric passivation layer 415.

[0100] In the embodiment shown in Figure 4, the wafer stack 420 is wafer-bonded to the surface of the CMOS wafer 435 via a dielectric passivation layer 415 in step 300. Laser irradiation 430 is applied in laser lift-off step 305 (as described above with respect to Figure 2) to remove the sapphire substrate 400 and obtain a graphene-containing laminate 440 including a graphene monolayer 410 coated with a high-quality nitride layer 405. The laminate 440 may be fabricated in one or more steps 310 using known microfabrication processes to deposit the source, drain, and gate contacts 450a, 450b, and 450c, respectively, and to deposit the dielectric coating 455, thereby encapsulating the components of the transistor 460 (as described above with respect to Figure 3). Preferably, the nitride layer 405 is etched to a thickness of, for example, 20 nm or less before the deposition of the gate contacts 450c, thereby preserving the uppermost region and highest quality portion of the nitride layer 405 of the wafer stack 420.

[0101] Where used herein, the singular forms “a,” “an,” and “the” include plural references unless the context explicitly indicates otherwise. The use of the term “comprising” is intended to be interpreted as including such features but not excluding other features, and is also intended to include a selection of features that are necessarily limited to those described. In other words, the term also includes the limitations “essentially consisting of” (intended to mean that certain further components may be present on the condition that they do not substantially affect the essential properties of the described feature) and “consisting of” (intended to mean that no other features may be included such that, if the components were expressed as percentages by their proportions, they would total 100%, taking into account any unavoidable impurities).

[0102] Terms such as “first,” “second,” “primary,” and “secondary” may be used herein to describe various elements, layers, and / or parts, but it should be understood that elements, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, layer, or part from another or further elements, layers, or parts. The term “above” will be understood to mean “directly above,” such that there is no intervening layer between one material said to be “above” another material or between layers of wafers described “in order.” Spatially relative terms such as “under,” “below,” “beneath,” “lower,” “over,” “above,” and “upper” may be used herein to facilitate descriptions of the relationship between one element or feature and another element or feature. It will be understood that spatially relative terms are intended to encompass different orientations of wafers / stacks / devices in use or operation, in addition to the orientation shown in the figures. For example, if a wafer / stack / device described herein is inverted, elements described as "below" or "down" other elements or features will face "above" or "up" other elements or features. Thus, the exemplary term "below" can encompass both upward and downward orientations. Wafers / stacks / devices may be oriented in other ways, and spatially relative descriptors used herein will be interpreted accordingly.

[0103] The detailed description provided herein is for illustrative purposes only and is not intended to limit the scope of the appended claims. Many variations of the currently preferred embodiments illustrated herein will be apparent to those skilled in the art and fall within the scope of the appended claims and their equivalents.

Claims

1. A method for providing a coated graphene layer structure on a silicon-containing wafer, (i) A step of providing a wafer stack comprising, in order, a substrate having a band gap of 6.5 eV or more, a nitride layer, a graphene layer structure, and a dielectric passivation layer, wherein the dielectric passivation layer has an exposed upper surface, (ii) The step of forming or adhering a further layer on the exposed upper surface of the dielectric passivation layer, (iii) The step of removing the substrate by laser lift-off to expose the surface of the nitride layer distal to the graphene layer structure, (iv) The step of wafer bonding the exposed surface of the nitride layer to the surface of a silicon-containing wafer, A method wherein the nitride layer of the wafer stack includes a first surface adjacent to the substrate and a second surface adjacent to the graphene layer structure, and the first and second surfaces are each independently formed from aluminum nitride or boron nitride.

2. The method according to claim 1, wherein the wafer stack is provided by forming the graphene layer structure directly on the nitride layer of a wafer including the substrate and the nitride layer by CVD.

3. The method according to claim 1 or 2, wherein the graphene layer structure is a single layer of graphene.

4. The method according to any one of claims 1 to 3, wherein the substrate is sapphire.

5. The method according to any one of claims 1 to 4, wherein the nitride layer of the wafer stack is provided by directly forming the nitride layer on the substrate by epitaxy.

6. The method according to any one of claims 1 to 5, wherein the nitride layer is made of aluminum nitride or boron nitride.

7. The method according to any one of claims 1 to 5, wherein the nitride layer is formed from a first sublayer of aluminum nitride or boron nitride that provides the first surface, a second sublayer of aluminum nitride or boron nitride that provides the second surface, and one or more further sublayers formed from a metal nitride between them, preferably the one or more further sublayers include a multiple quantum well structure.

8. The method according to any one of claims 1 to 7, wherein the boron nitride is hexagonal boron nitride.

9. The method according to any one of claims 1 to 8, wherein the nitride layer of the wafer stack has a thickness of 100 nm to 10 μm.

10. The method according to claim 9, wherein, after removing the substrate, the nitride layer is etched to a thickness of less than 50 nm, preferably less than 10 nm.

11. The method according to any one of claims 1 to 10, wherein the dielectric passivation layer has a thickness of 0.5 nm to 500 nm, preferably 1 nm to 100 nm.

12. The method according to any one of claims 1 to 11, wherein the dielectric passivation layer is formed of an inorganic oxide, nitride, carbide, fluoride, or sulfide, preferably a metal oxide.

13. The method according to any one of claims 1 to 12, wherein the dielectric passivation layer is formed from two or more sublayers.

14. The method according to claim 13, wherein the dielectric passivation layer includes a first sublayer formed from a transition metal dichalcogenide or molybdenum oxide, and the first sublayer is provided on the graphene layer structure.

15. The method according to any one of claims 1 to 14, further comprising the step of removing the further layer after the step of bonding wafers.

16. The method according to any one of claims 1 to 15, wherein the further layer is formed of a metal, preferably copper, aluminum, titanium, and / or nickel.

17. The method according to claim 16, wherein the further layer is etched to form a gate contact.

18. The method according to any one of claims 1 to 17, wherein the silicon-containing wafer comprises a layer of silicon oxide and / or silicon nitride, and the layer of silicon oxide and / or silicon nitride provides the surface of the silicon-containing wafer to which the nitride layer of the wafer stack is wafer-bonded.

19. The method according to claim 18, wherein the silicon oxide and / or silicon nitride has a thickness of 50 to 500 nm, and the silicon oxide and / or silicon nitride is provided on a support formed from silicon.

20. The method according to claim 19, further comprising the step of removing the silicon support after the wafer bonding step.

21. The method according to any one of claims 1 to 19, wherein the silicon-containing wafer is a CMOS wafer.

22. A method for manufacturing electronic devices, A method according to any one of claims 1 to 21, comprising the steps of providing a coated graphene layer structure on a silicon-containing wafer, The steps include patterning the graphene layer structure and the dielectric passivation layer, A method comprising the step of forming one or more electrical contacts that come into contact with the graphene layer structure.

23. The method according to claim 22, further comprising the step of dicing the silicon-containing wafer.

24. A method for providing a coated graphene layer structure on a silicon-containing wafer, (I) A step of providing a wafer stack comprising, in order, a substrate having a band gap of 6.5 eV or more, a nitride layer, a graphene layer structure, and a dielectric passivation layer, wherein the dielectric passivation layer has an exposed upper surface, (II) A step of wafer bonding the exposed upper surface of the dielectric passivation layer to the surface of a silicon-containing wafer, (III) The step of removing the substrate by laser lift-off to expose the surface of the nitride layer distal to the graphene layer structure, A method wherein the nitride layer of the wafer stack includes a first surface directly adjacent to the substrate and a second surface directly adjacent to the graphene layer structure, and the first and second surfaces are each independently formed from aluminum nitride or boron nitride.

25. Step (I) of providing the wafer stack, (A) A step of providing a first wafer including the nitride layer on the substrate, wherein the nitride layer has an exposed growth surface distal to the substrate, and the nitride layer has a first region extending at least 2 nm below the exposed growth surface, and the first region is a) 5,000 cm as measured by TEM －２ Dislocation density less than, b) A step that satisfies the requirement of a surface roughness (Ra) of less than 1 nm as measured by AFM, (B) The step of forming the graphene layer structure on the exposed growth surface of the nitride layer by CVD, and forming a further layer containing a dielectric material on the graphene layer structure to form the dielectric passivation layer, The method described above is (IV) The method according to claim 24, further comprising the step of removing a portion of the nitride layer to leave a retaining portion of the nitride layer formed from the first region and having a thickness of less than 20 nm.

26. A graphene-containing laminate, in order, (i) A silicon support of any choice, (ii) Primary dielectric layer and (iii) Graphene layer structure and (iv) A nitride layer having a thickness of less than 20 nm, which is measured by TEM at 5,000 cm². －２ A nitride layer having a dislocation density of less than , The nitride layer comprises a primary surface directly adjacent to the graphene layer structure and a secondary exposed upper surface, and the primary and secondary surfaces are each independently formed from aluminum nitride or boron nitride. A graphene-containing laminate in which one or more further dielectric layers are provided between the primary dielectric layer and the graphene layer structure.

27. The graphene-containing laminate according to claim 26, wherein the primary surface is formed from aluminum nitride, and preferably the secondary surface is also formed from aluminum nitride.

28. The graphene-containing laminate according to claim 26 or 27, wherein the graphene layer structure is free from interference by metals and organic polymers.

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