N-Way Fault Tolerance Processing System

Abstract

The processor [102] includes two or more core dies [104], each containing one or more processor cores [106, 108]. The first core die of the processor is associated with a first operating system [112], and the processor core of the first core die executes a set of instructions according to the first operating system to produce a first result. The second core of the processor is associated with a second operating system [112], and the processor core of the second core die executes a set of instructions according to the second operating system to produce a second result. The first and second core dies provide the first and second results to a voting circuit [338] that generates an output based on the first and second results.

Description

Background Art

[0001] A processing system executes one or more operating systems configured to manage and allocate the hardware and software resources of the processing system to support the execution of applications. Further, the processing system includes one or more processors (e.g., central processing units) each having an architecture defined by one or more instruction set architectures (ISAs) to execute instructions for these applications. However, a particular operating system used to manage applications, a particular ISA of a processor configured to execute instructions for an application, or both may introduce errors or security vulnerabilities into the processing system when the application is executed. For example, a particular ISA increases the risk of transient execution attacks and sampling of microarchitecture data into the processing system, reducing the security and reliability of the processing system. As another example, an operating system controlled by a malicious entity can remap memory addresses or replace function calls, increasing the risk that data within the processing system is exposed to one or more malicious entities and increasing the risk that one or more errors occur when instructions for an application are executed.

[0002] The present disclosure may be better understood by reference to the accompanying drawings, and numerous features and advantages thereof will become apparent to those skilled in the art. The use of the same reference numerals in different drawings indicates similar or identical items.

Brief Description of the Drawings

[0003] [Figure 1] FIG. 17 is a block diagram of a processing system 100 implementing N-way fault tolerance according to some embodiments. [Figure 2]This is a block diagram of a central processing unit (CPU) implementing an N-way redundancy framework in several embodiments. [Figure 3] This is an exemplary CPU block diagram implementing an N-way operating system redundancy framework in several embodiments. [Figure 4] This is a block diagram of an exemplary CPU and N-way hardware redundancy framework according to several embodiments. [Figure 5] This is an exemplary CPU block diagram of an N-way hardware redundancy framework in several embodiments. [Figure 6] This flowchart illustrates exemplary methods for implementing N-way fault tolerance through several embodiments. [Modes for carrying out the invention]

[0004] To support the execution of applications by a processing system, the processing system runs one or more operating systems configured to manage (e.g., allocate, configure) the processing system's resources (e.g., hardware resources, software resources) to execute instructions, workloads, and operations for the application. However, the specific operating systems running on a processing system may introduce errors and security vulnerabilities into the processing system. For example, the interaction between the operating system and the application (e.g., how resources are allocated to the application) may introduce one or more errors (e.g., incorrect values) when the processor executes instructions for the application, reducing the reliability of the processing system. As another example, an operating system controlled by a malicious entity may introduce security vulnerabilities by remapping memory addresses (e.g., page tables), altering memory requests (e.g., direct memory access (DMA) requests, memory-mapped I / O (MMIO) requests), replacing function calls, etc. These security vulnerabilities reduce the security of the processing system, for example, by increasing the risk that data within the processing system may be exposed to one or more malicious entities.

[0005] Furthermore, to support the execution of one or more applications, the processing system includes one or more processors, each containing one or more processor cores configured to execute instructions, workloads, and operations for the applications, and to store data resulting from the execution of instructions, workloads, and operations, for example, in the processing system's memory. The architecture of these processors (e.g., the architecture of the processor cores of the processors) is defined by the instruction set architecture (ISA), which indicates the instructions, data types, registers, memory management, memory consistency, addressing modes, virtual memory, input / output models or any combination thereof, how machine code behaves on the processor architecture, or both. However, executing instructions for several applications on a processor defined by a particular ISA may introduce errors and security vulnerabilities (e.g., transient execution attacks, microarchitecture data sampling) into the processing system due to the ISA architecture (e.g., the processor architecture), potentially reducing the security and reliability of the processing system.

[0006] For this purpose, the systems and technologies disclosed herein relate to processing systems that implement N-way fault tolerance. For this purpose, the processing system includes a central processing unit (CPU) comprising one or more core dies (e.g., core chiplet dies). Each core die includes one or more processor cores, each configured to execute instructions, workloads, operations, or any combination thereof for an application run by the processing system. To support N-way fault tolerance, one or more core dies of the CPU are each associated with a different operating system, ISA, or both, which are different from the operating systems, ISAs, or both associated with one or more other core dies of the CPU. For example, in an implementation, the CPU includes a first core die associated with a first operating system and a second core die associated with a second operating system different from the first operating system. As another example, the CPU includes a first core die associated with a first ISA (e.g., having processor cores defined thereby) and a second core die associated with a second ISA different from the first ISA.

[0007] In the implementation, each core die of the CPU (e.g., the processor core of each core die) is configured to simultaneously execute the same set of instructions, workloads, operations, or any combination thereof for an application. For example, each core die is configured to execute the same set of instructions, workloads, operations, or any combination thereof for an application, such that results (e.g., data resulting from the execution of instructions, workloads, or operations) are generated based on the respective operating system and ISA associated with the core die. Since one or more core dies of the CPU are each associated with a different operating system, ISA, or both, which are different from the operating systems, ISAs, or both associated with one or more other core dies of the CPU, a core die can generate multiple results together based on its respective operating system, ISA, or both (e.g., the operating system and ISA of the core die that produced the result). In this way, results based on different operating systems, ISAs, or both are generated. For example, a first result is generated based on a first operating system, a first ISA, or both, and a second result is generated based on a second operating system, a second ISA, or both, where the first and second operating systems are different from each other, and the first and second ISAs are different from each other.

[0008] After generating results, each core die is configured to provide its results to a voting circuitry, either contained within the CPU or otherwise connected, which determines the CPU's output based on the results received from two or more core dies. Depending on the results received from two or more core dies, the voting circuitry determines the CPU's output based on the received results. For example, to determine the output, the voting circuitry is configured to determine a majority result (e.g., the most frequently occurring result or most common result among the received results), a minority result (e.g., the least frequently occurring result among the received results), or both. In this way, the processing system implements N-way fault tolerance, helping to minimize errors, security vulnerabilities, or both introduced into the processing system by a particular operating system, ISA, or both. As an example, in an implementation, three or more core dies of the CPU are each associated with a different operating system, ISA, or both, distinct from the operating system, ISA, or both associated with one or more other core dies of the CPU. Each of these core dies executes the same set of instructions and provides the results to a voting circuit, which then determines the majority result to determine the output for the CPU. Therefore, if any of the core dies provides an incorrect result due to one or more errors, security vulnerabilities, or both introduced by the specific operating system, ISA, or both associated with the core die, the voting circuit still determines the correct output by determining the majority result and ignoring the incorrect result. Since the incorrect result is discarded, the security and reliability of the processing system are improved.

[0009] Figure 1 is a block diagram of a processing system 100 implementing N-way fault tolerance according to several embodiments. As an example, the processing system 100 includes a server system (e.g., one or more physical servers, virtual servers) configured to run one or more applications (e.g., machine learning applications, artificial intelligence (AI) applications, deep learning applications, shader applications, high-performance computing (HPC) applications, data center applications, cloud computing applications). To support the execution of such applications, the processing system 100 includes, or accesses, memory 118 or other storage components implemented using non-temporary computer-readable storage media (e.g., dynamic random access memory (DRAM)). However, depending on the implementation, memory 118 may be implemented using other types of memory, such as static random access memory (SRAM), double data rate SDRAM (DDR SRAM), non-volatile RAM, etc. Depending on the implementation, memory 118 may include external memory implemented outside the processing unit implemented in the processing system 100. Furthermore, the processing system 100 includes a bus 101 for supporting communication between entities implemented within the processing system 100, such as memory 118, an accelerated processing unit (APU) 114, a central processing unit (CPU) 102, input / output (I / O) devices 120, or any combination thereof.

[0010] In the implementation, memory 118 is configured to store one or more operating systems 112 to support the execution of one or more applications. Such an operating system 112 includes, for example, data (e.g., program code) that represents one or more operations, instructions, or both, to support the execution of the application by the processing system 100. These operations and instructions include, for example, scheduling tasks (e.g., workloads, instructions) for one or more applications, allocating resources (e.g., registers, local data shares, scratch memory) to tasks for one or more applications, providing interfaces to I / O devices 120 (e.g., hard disks, network interface controllers, modems) for one or more applications, or any combination thereof. The exemplary implementation shown in Figure 1 shows memory 118 as storing two operating systems (112-1, 112-P) representing P operating systems 112, but in other implementations, memory 118 can store any number of operating systems 112.

[0011] Furthermore, to support the execution of one or more applications, the processing system 100 includes a CPU 102. The CPU 102 includes, for example, various parallel processors, vector processors, coprocessors, non-scalar processors, highly parallel processors, artificial intelligence (AI) processors, inference engines, machine learning processors, other multithreaded processing units, scalar processors, serial processors, or any combination thereof. As an example, the CPU 102 includes one or more dies (e.g., core die 104, core chiplet die), each die including one or more parallel processors, vector processors, coprocessors, non-scalar processors, highly parallel processors, AI processors, inference engines, machine learning processors, other multithreaded processing units, scalar processors, serial processors, or any combination thereof. In the implementation, the CPU 102 is configured to receive and execute one or more instructions for one or more applications executed by the processing system 100.

[0012] In the implementation, memory 118 contains program code 110 for one or more applications executed by the processing system 100. Such program code 110 contains, for example, data indicating one or more workloads, instructions, operations, or any combination thereof to be executed for one or more applications. As an example, program code 110 contains data indicating one or more instructions for an AI application, machine learning application, HPC application, or any combination thereof executed by the processing system 100. According to the implementation, CPU 102 is configured to receive one or more instructions from program code 110 and to use multiple processor cores (e.g., processor cores 106, 108) to execute one or more operations for the instructions (e.g., one or more operations indicated in the instructions). For this purpose, CPU 102 includes two or more core dies 104 (e.g., core chiplet dies) each containing one or more processor cores (e.g., one or more integrated circuits (ICs) each containing one or more processor cores). As an example, the implementation shown in Figure 1 represents a CPU 102 having two core dies (104-1, 104-N) representing N core dies 104, where the first core die 104-1 contains three processor cores (106-1, 106-2, 106-M) representing M processor cores 106, and the second core die N 104-N contains three processor cores (108-1, 108-2, 108-K) representing K processor cores 108. While the exemplary implementation in Figure 1 shows the CPU 102 having two core dies (104-1, 104-N) representing N core dies, other implementations may include any number of core dies 104 in the CPU 102. Furthermore, while the exemplary implementation in Figure 1 shows each core die 104 having three processor cores (106-1, 106-2, 106-M, 108-1, 108-2, 108-K) representing M and K processor cores 106 and 108 respectively, other implementations may include any number of processor cores in each core die 104.For example, in the implementation, the first core die 104 may have the same number of processor cores as one or more other core dies 104, or it may have a different number of processor cores than one or more other core dies 104, or both.

[0013] In the implementation, one or more processor cores 106, 108 of one or more core dies 104 of the CPU 102 each operate as a compute unit to perform one or more operations for one or more instructions of an application executed by the processing system 100. Each of these compute units includes one or more single-instruction multiple data (SIMD) units that perform the same operation on different datasets to produce one or more results. Such results include, for example, data resulting from the execution of one or more operations by one or more processor cores 106, 108. After producing one or more results, the compute unit is configured to store the results in a cache within the compute unit (processor cores 106, 108, etc., operating as compute units), or in a cache, memory 118, or both, that is coupled to the compute unit. Furthermore, in the implementation, one or more processor cores 106, 108 of the core die 104 are configured to support one or more instruction set architectures (ISAs) to perform one or more instructions, or both, in order to perform one or more instructions of an application executed by the processing system 100. Such an ISA includes, for example, a model that represents instructions, data types, registers, memory management, virtual memory management, I / O models, or any combination thereof, that are supported by one or more processors (e.g., by one or more processor cores 106, 108 on a core die 104). That is, one or more processor cores 106, 108 on a core die 104 include an architecture configured to support an instruction set defined by one or more ISAs. As an example, one or more processor cores 106, 108 on one or more core dies 104 include an architecture that supports an instruction set defined by a composite instruction set (CISC) ISA (e.g., x86). As another example, one or more processor cores 106, 108 on one or more core dies 104 include an architecture that supports an instruction set defined by a reduced instruction set (RISC) ISA (e.g., an advanced RISC machine (ARM)).

[0014] In this way, one or more processor cores 106, 108 of one or more core dies 104 of the CPU 102 are configured to execute instructions, run workloads, perform operations, or any combination thereof for one or more applications being run by the processing system 100. However, executing instructions for several applications on processor cores 106, 108 associated with a particular ISA (e.g., x86, ARM) may introduce errors and security vulnerabilities (e.g., transient execution attacks, microarchitecture data sampling) into the processing system 100 due to the architecture associated with the ISA (e.g., processor architecture), how the instruction set (e.g., kernel code) is executed according to the ISA, or both. Furthermore, a particular operating system 112 that supports the execution of instructions for one or more applications may also introduce errors and security vulnerabilities into the processing system 100. For example, an operating system 112 controlled by a malicious entity may introduce security vulnerabilities by remapping memory addresses (e.g., page tables), altering memory requests (e.g., direct memory access (DMA) requests, memory-mapped I / O (MMIO) requests), or replacing function calls.

[0015] To help reduce the potential for such errors and security vulnerabilities in the processing system 100, the CPU 102 is configured to implement N-way fault tolerance. To implement N-way fault tolerance, one or more core dies 104 of the CPU 102 each include processor cores 106, 108 associated with their respective ISA, respective operating system 112, or both, which are different from the ISA, respective operating system 112, or both associated with one or more other core dies 104 of the CPU 102. For example, in some implementations, the first core die 104-1 of the CPU 102 includes a processor core 106 having an architecture associated with a first ISA (e.g., x86), and the second core die 104-N of the CPU 102 includes a processor core 108 having an architecture associated with a second ISA (e.g., ARM). As another example, the first core die 104-1 of the CPU 102 includes a processor core 106 configured to execute instructions for a first operating system 112-1 (e.g., instructions managed by the first operating system 112-1), and the second core die 104-N of the CPU 102 includes a processor core 108 configured to execute instructions for a second operating system 112-P, which is different from the first operating system 112-1. As yet another example, the first core die 104-1 of the CPU 102 includes a processor core 106 having an architecture associated with a first ISA (e.g., x86) and configured to execute instructions for a first operating system 112-1, and the second core die 104-N of the CPU 102 includes a processor core 108 having an architecture associated with a second ISA (e.g., ARM) and configured to execute instructions for a second operating system 112-P, which is different from the first operating system 112-1.

[0016] To run different operating systems 112 on different core dies 104 of the CPU 102, the processing system 100 is configured to run two or more virtual machines (VMs), each associated with a different operating system 112. That is, the processing system 100 runs two or more VMs, each running a different operating system 112. For example, the processing system 100 runs a first VM running a first operating system 112-1 and a second VM running a second operating system 112-P, where the first operating system 112-1 is different from the second operating system 112-P. To help support the VMs, the implementation configures one or more core dies 104 of the CPU 102 to function as a hypervisor (e.g., a system manager). Such a hypervisor includes, for example, hardware-based circuitry, software-based circuitry, or both, configured to generate and manage the VMs run by the processing system 100. For example, the core die 104 includes one or more processor cores 104, 106 configured to execute instructions, commands, operations, or any combination thereof in order to generate and manage VMs executed by the processing system 100.

[0017] In the implementation, one or more processor cores 104, 106 of the core die 104, which functions as a hypervisor, are configured to assign the core die 104 of the CPU 102 to a VM run by the processing system 100. For example, one or more processor cores 104, 106 of the core die 104, which functions as a hypervisor, are configured to assign the first core die 0 104-1 to a first VM running a first operating system 112-1. After the core die 104 is assigned to the VM, one or more processor cores 104, 106 of the core die 104 are configured to execute one or more instructions, workloads, operations, or any combination thereof for one or more applications (machine learning applications, AI applications, deep learning applications, shader applications, HPC applications, data center applications, cloud computing applications) running by the VM, the processing system 100, or both, based on (for example, as managed by) the operating system 112 running on the VM. As an example, after core die 0 104-1 is assigned to a first VM running a first operating system 112-1, one or more processor cores of core die 0 104-1 are configured to execute one or more instructions, workloads, operations, or any combination thereof for an application based on the first operating system 112-1. Since each core die 104 of CPU 102 is assigned to a respective VM running its respective operating system 112, the core dies 104 of CPU 102 are configured to execute instructions, workloads, and operations simultaneously based on two or more different operating systems 112.

[0018] Furthermore, in some implementations, in order to implement N-way fault tolerance, one or more core dies 104 of the CPU 102 have programmable hardware configured to execute one or more instructions, workloads, operations, or any combination thereof for one or more applications executed by the processing system 100. Such programmable hardware includes one or more programmable logic devices, such as simple programmable logic devices (SPLDs), complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), etc. For example, in an implementation, one or more core dies 104 of the CPU 102 include one or more FPGAs configured to execute one or more instructions, workloads, operations, or any combination thereof for one or more applications executed by the processing system 100. In response to executing one or more instructions, workloads, or operations, one or more programmable logic devices are configured to store the results (e.g., data resulting from the execution of instructions, workloads, or operations) in, for example, memory 118. In some implementations, the CPU 102 includes one or more core dies 104, each associated with a respective ISA and operating system 112 (for example, core dies 104 having processor cores 104, 106 associated with each ISA), and one or more core dies 104, each containing one or more programmable logic devices (for example, FPGAs).

[0019] In the implementation, to implement N-way fault tolerance, two or more core dies 104 of the CPU 102 are configured to execute the same workload, instructions, operations, or any combination thereof in parallel for one or more applications. That is, the processor cores 106, 108 of each core die 104 are configured to execute the same workload, instructions, operations, or any combination thereof simultaneously for the same application. Thus, within the N-way redundancy framework, the instructions, workloads, and operations for an application are executed on two or more core dies 104, ISAs, or both, each associated with a respective operating system 112 (e.g., each assigned to each VM running each operating system 112 on which the application runs). In other words, the instructions, workloads, and operations for an application are executed simultaneously on two or more core dies 104 so that the instructions, workloads, and operations are executed according to two or more operating systems 112 (e.g., the operating systems 112 of the VMs assigned to each core die 104), two or more ISAs (e.g., the ISAs associated with each core die 104), or both. As an example, the processor core 106 of the first core die 104-1 is configured to execute instructions for an application run by a first VM running a first operating system 112-1, and the processor core 108 of the second core die 104-2 is configured to execute the same instructions for an application run by a second VM running a second operating system 112-P. As another example, the processor core 106 of the first core die 104-1 having an architecture associated with the first ISA is configured to execute instructions for an application, and the processor core 108 of the second core die 104-N having an architecture associated with the second ISA is configured to execute the same instructions for an application.Furthermore, in some implementations, instructions, workloads, and operations for an application are executed on a core die having one or more programmable logic devices, in addition to two or more core dies 104, ISAs, or both, each associated with a respective operating system 112 (e.g., each assigned to each VM running each operating system 112 on which the application runs). For example, a CPU 102 in an implementation includes a first core die 104 having one or more programmable logic devices (e.g., FPGAs) configured to execute instructions for an application, a second core die 104 having processor cores 106, 108 associated with a first ISA (e.g., x86) configured to execute instructions for an application, and a third core die 104 having processor cores 106, 108 associated with a second ISA (e.g., ARM) configured to execute instructions for an application.

[0020] In some implementations, when one or more processor cores 106, 108, programmable logic devices, or both of them on the core die 104 complete the execution of one or more instructions, workloads, operations, or any combination thereof, one or more processor cores 106, 108, programmable logic devices, or both of them on the core die 104 are configured to provide the results (e.g., data obtained from the execution of one or more instructions, workloads, operations, or any combination thereof) to a voting circuit. Such a voting circuit includes, for example, a hardware-based circuit, a software-based circuit, or both configured to determine an output based on two or more results received from two or more core dies 104. In some implementations, the voting circuit is contained within the core die 104 (e.g., one or more processor cores 106, 108 on the core die 104 act as the voting circuit), and in other implementations, the CPU 102 is connected to the voting circuit in other ways. Upon receiving results from two or more core dies 104, each resulting from the execution of the same instruction, workload, operation, or any combination thereof, the voting circuit is configured to determine an output based on the received results. For example, to determine an output, a voting circuit (e.g., including a majority logic gate) is configured to determine a majority result (e.g., the most frequently occurring result or most frequent result among the received results), a minority result (e.g., the least frequently occurring result among the received results), or both, from the received results. In this way, the CPU 102 implements N-way fault tolerance, helping to minimize errors, security vulnerabilities, or both introduced into the processing system 100 by one or more operating systems 112, ISAs, or both. For example, in an implementation, three or more core dies 104 of the CPU 102, each associated with a respective operating system 112, ISA, or both, each execute the same set of instructions and provide the results to the voting circuit. The voting circuit then determines a majority result (e.g., the most frequently occurring result or most frequent result among the received results) to determine an output for the CPU 102.In this way, if any of the core dies 104 of the CPU 102 provide an incorrect result due to one or more errors, security vulnerabilities, or both introduced by the operating system 112, ISA, or both associated with the core die 104, the voting circuit still determines the correct output by determining the majority result and ignoring the incorrect result. Thus, voting security helps to ensure that errors introduced by a particular operating system 112, ISA, or both do not affect the output of the CPU 102, thereby improving the security and fault tolerance of the processing system 100.

[0021] The processing system 100 also includes an APU 114 connected to a bus 101 and communicating with the CPU 102 and memory 118 via the bus 101. The APU 114 implements multiple processor cores 116-1 to 116-N that execute instructions concurrently or in parallel. In the implementation, one or more processor cores 116 each operate as one or more compute units (e.g., SIMD units) that perform the same operation on different datasets. In the exemplary implementation shown in Figure 1, three processor cores (116-1, 116-2, 116-L) representing L cores are shown, but the number of processor cores 116 implemented in the APU 114 is a design choice. Therefore, in other implementations, the APU 114 can contain any number of processor cores 116. The processor core 116 executes instructions such as program code 110 (e.g., shader program) stored in memory 118, and the APU 114 stores information such as the results of the executed instructions (e.g., instructions from the shader program) in memory 118.

[0022] Referring to Figure 2, a CPU 102 implementing the N-way redundancy framework 200 is shown. In the implementation, the CPU 102 implementing the N-way redundancy framework 200 includes, for example, core die 0 104-1, core die 1 104-2, core die 2 104-3, core die N 104-N, input / output (I / O) die 228, or any combination thereof. The exemplary implementation shown in Figure 2 shows the CPU 102 having four core dies (104-1, 104-2, 104-3, 104N) representing N core dies 104, but in other implementations, the CPU 102 may have any number of core dies 104. According to the implementation, one or more core dies 104 each include one or more processor cores similar to or identical to processor cores 106, 108, each configured to execute one or more instructions, workloads, operations, or any combination thereof for one or more applications being run by the processing system 100, VM, or both. As an example, referring to the implementation shown in Figure 3, the CPU 102 includes a first core die 0 104-1 containing three processor cores (106-1, 106-2, 106-M) representing M processor cores, a second core die 1 104-2 containing three processor cores (108-1, 108-2, 108-J) representing J processor cores, and a third core die N 104-N containing three processor cores (232-1, 232-2, 232-L) representing L processor cores. The exemplary implementation shown in Figure 2 shows core dies 104-1, 104-2, and 104-N having three processor cores each, but in other implementations, each core die 104 may have any number of processor cores. Furthermore, in the implementation, two or more core dies 104 of the CPU 102 may have an equal number of processor cores, or two or more core dies 104 of the CPU 102 may have different numbers of processor cores, or both. Furthermore, in the implementation, one or more core dies 104 of the CPU 102 may include one or more programmable logic devices 230. Such programmable logic devices 230 may include, to give some examples, SPLDs, CPLDs, FPGAs, or any combination thereof.The exemplary implementation shown in Figure 2 shows core die 2104-3 having two programmable logic devices (230-1, 230-K) representing K programmable logic devices, but in other implementations, core die 104 can contain any number of programmable logic devices 230.

[0023] According to the implementation, one or more core dies 104 are configured to act as a hypervisor. That is, one or more processor cores 106, 108, and 232 of the core die 104 are configured to generate and manage one or more VMs that run on processing systems 100, each running on a different operating system 112. For this purpose, the core die 104 acting as a hypervisor is configured to assign one or more other core dies 104 of the CPU 102 to one or more VMs, each running on a different operating system 112. After being assigned to a VM running a different operating system 112, the processor cores 106, 108, and 232 of the assigned core die 104 are configured to execute instructions, workloads, operations, or any combination thereof for one or more applications run on the VM, based on the operating system 112 running on the VM (for example, managed by the operating system 210). By assigning VMs running different operating systems to their respective core dies 104, two or more core dies 104 are each associated with different operating systems 112. In other words, the processor cores 106, 108, and 232 of two or more core dies 104 are each configured to execute instructions, workloads, operations, or any combination thereof for applications managed by different operating systems 112.

[0024] In the implementation, one or more core dies 104 of the CPU are each associated with a respective operating system 112 (e.g., assigned to each VM running each respective operating system 112), a respective ISA (e.g., the processor cores 106, 108, 232 of the core die 104 have architectures defined by their respective ISAs), and include one or more programmable logic devices 230, or any combination thereof. For example, in the implementation, two or more core dies 104 of the CPU are each associated with a respective different operating system 112 (e.g., each core die 104 is assigned to a respective VM running each respective different operating system 112), two or more core dies 104 are each associated with a respective different ISA, and one or more core dies 104 include one or more programmable logic devices (e.g., FPGAs) or any combination thereof. In this way, the CPU 102 is configured to use one or more operating systems 112, ISAs, programmable devices 230, or any combination thereof simultaneously to execute the same set of instructions, workloads, operations, or any combination thereof for one or more applications. For example, the CPU 102 is configured to simultaneously execute an instruction set for an application on a first core die 0 104-1 including a processor core 106 associated with a first operating system 112-1 (for example, the processor core 106 is configured to execute instructions, workloads and operations such as those managed by the operating system 112-1), a second core die 1 104-2 including a processor core 108 associated with a second operating system 112-P, and a third core die 2 104-2 having one or more programmable logic devices 230, wherein the first operating system 112-1 and the second operating system 112-P are distinct from each other.As another example, the CPU 102 is configured to simultaneously execute a set of instructions for an application with a first core die 0 104-1 that includes a processor core 106 associated with a first ISA (e.g., a processor core 106 having an architecture based on the first ISA) and a second core die 1 104-2 that includes a processor core 108 associated with a second ISA, and the first ISA is different from the second ISA. As yet another example, the CPU 102 is configured to simultaneously execute the same set of instructions with a first core die 0 104-1 that includes a first operating system 112-1 and a processor core 106 associated with a first ISA and a second core die 1 104-2 that includes a second operating system 112-P and a processor core 108 associated with a second ISA, the first operating system 112-1 is different from the second operating system 112-P, and the first ISA is different from the second ISA.

[0025] To help support the execution of instructions, workloads, and operations on the CPU 102, the CPU 102 includes an I / O die 228 connected to each of the core dies 104. The I / O die 228 includes hardware-based circuitry, software-based circuitry, or both, configured to provide an interface between the core dies 104 and memory 118, one or more I / O devices 120, or both. For this purpose, the I / O die 228 includes, or is otherwise connected to, a data fabric 224, which includes hardware-based circuitry, software-based circuitry, or both, providing an interconnection architecture between the core dies 104, the I / O die 228 (e.g., I / O controller 222, memory controller 226), memory 118, one or more I / O devices 120, bus 101, or any combination thereof. As an example, the data fabric 224 provides an interconnection architecture between the core dies 104, memory controller 226, and memory 118. As another example, the data fabric 224 provides an interconnection architecture between the core die 104, one or more I / O controllers 222, and one or more I / O devices 120. Furthermore, to provide an interface between the core die 104 and the memory 118, the I / O die 228 includes a memory controller 226. The memory controller 226 includes, for example, hardware-based circuitry, software-based circuitry, or both, configured to access, modify, and delete data in the memory 118. For example, the memory controller 226 is configured to access, modify, and delete data in the memory 118 to help manage read operations, write operations, fetch operations, prefetch operations, copy operations, or any combination thereof between the core die 104 and the memory 118. Furthermore, to provide an interface between the core die 104 and one or more I / O devices 120, the I / O die 228 includes one or more I / O controllers 222.Such an I / O controller 222 includes, for example, hardware-based circuitry, software-based circuitry, or both, configured to manage data transfers (e.g., memory access requests) between the core die 104, the memory 118, and one or more I / O devices 120. For example, the I / O controller 222 is configured to manage direct memory access (DMA) requests for accessing the memory 118 from the I / O devices 120. As another example, the I / O controller 222 is configured to manage memory-mapped input / output (MMIO) requests from one or more core dies 104 for accessing the memory or registers of the I / O devices 120.

[0026] According to some implementations, one or more core dies 104 of the CPU 102 function as a voting circuit, and in other implementations, the CPU 102 is connected to such a voting circuit in other ways. The voting circuit is, for example, a hardware-based circuit, a software-based circuit, or both, configured to determine the output of the CPU 102 based on two or more results received from two or more core dies 104 (e.g., data obtained from the execution of one or more instructions, workloads, operations, or any combination thereof of an application executed by the processing system 100, a VM, or both). As an example, in an implementation, one or more core dies 104 each include one or more processor cores 106, 108, 232 configured to determine an output based on results received from two or more other core dies 104. For this purpose, in response to receiving results from two or more core dies 104 respectively resulting from the execution of the same instruction, workload, operation, or any combination thereof for an application, one or more processor cores 106, 108, 232 of the core die 104 operating as a voting circuit are configured to determine, for example, the majority result (e.g., the most frequently occurring or most common result within the received results), the minority result (e.g., the result that occurs least frequently within the received results), or both, from the received results, to determine the output of the CPU 102. In this way, the CPU 102 implements an N-way redundancy framework 200 to help minimize errors, security vulnerabilities, or both introduced into the processing system 100 by one or more operating systems 112, ISAs, or both.

[0027] Referring here to Figures 3 to 5, a CPU 102 implementing an exemplary N-way redundancy framework is shown. In the implementation, the exemplary N-way operating system redundancy framework 300 includes a CPU 102 having core die 0 104-1, core die 1 104-2, core die 2 104-3, and core die 104-N. Furthermore, to provide an interface between the core dies 104 and memory 118, one or more I / O devices 120, or both, the CPU 102 includes an I / O die 228. The exemplary implementation shown in Figures 3 to 5 shows the CPU 102 having four core dies (104-1, 104-2, 104-3, 104-N) representing N core dies 104, but in other implementations, the CPU 102 can have any number of core dies 104.

[0028] In the implementation, the processing system 100 is configured to run one or more VMs. Each VM run by the processing system 100 is configured to run, for example, its own operating system 112. For example, one or more VMs run by the processing system 100 are configured to run a different operating system 112 than one or more operating systems 112 run by the one or more VMs. Furthermore, each VM is configured to run applications managed by the operating system 112 running on the VM. According to the implementation, one or more core dies 104 of the CPU 102 are configured to function as hypervisors configured to generate and manage VMs run by the processing system 100. That is, one or more core dies 104 run a hypervisor, a system management program, or both for the processing system 100. For this purpose, the core die 104 (e.g., core die N 104-N) includes a hypervisor circuit 336 which includes hardware-based circuitry, software-based circuitry, or both, configured to generate and manage VMs. For example, the hypervisor circuit 336 includes one or more processor cores 106, 108, 232 configured to execute instructions, commands, operations, or any combination thereof to generate and manage VMs. Depending on the implementation, the hypervisor circuit 336 is configured to assign one or more core dies 104 to each of the one or more VMs running on the processing system 100. In some implementations, the hypervisor circuit 336 is configured to assign an equal number of core dies 104 to each VM run by the processing system 100, while in other implementations, the hypervisor circuit 336 is configured to assign different numbers of core dies 104 to two or more VMs run by the processing system 100.

[0029] Next, referring to Figure 3, a CPU 102 implementing the N-way operating system redundancy framework 300 is shown. Since each VM runs its own operating system 112 within the N-way operating system redundancy framework 300, the hypervisor circuit 336 is configured to assign core dies 104 to VMs so that two or more core dies 104 are associated with different operating systems 112. That is, the hypervisor circuit 336 is configured to assign one or more core dies 104 to a first VM running a first operating system 112, and one or more other core dies 104 to one or more other VMs each running a different operating system 112 than the first operating system 112, one or more operating systems 112 run by the other VMs, or both. For example, the hypervisor circuit 336 is configured to assign the first core die 0 104-1 to a first VM running the first operating system 0 112-1, the second core die 1 104-2 to a second VM running the second operating system 1 112-2, and the third core die 2 104-3 to a third VM running the third operating system 2 112-3, where the first operating system 112-1, the second operating system 112-2, and the third operating system 112-3 are all different from each other. After being assigned to a VM running their respective operating systems 112, the core dies 104 (for example, the processor cores 106, 108, and 232 of core die 104) are configured to execute instructions, workloads, operations, or any combination thereof for the application run by the VM, based on the operating system 112 running on the VM. In the implementation, each core die 104 is assigned to a separate VM running the same application. In this way, each core die 104 associated with each operating system 112 is configured to simultaneously execute the same instructions, workloads, operations, or any combination thereof for the same application.In other words, two or more core dies 104 of the CPU 102 simultaneously execute the same instructions, workloads, operations, or any combination thereof for an application, according to (for example, as managed by) two or more respective operating systems 112 (e.g., the operating system 112 associated with each core die 104). Thus, the CPU 102 is configured to execute the same instructions, workloads, operations, or any combination thereof for an application according to different operating systems 112.

[0030] Depending on the execution of one or more instructions, workloads, operations, or any combination thereof for an application, each core die 104 is configured to provide results 342 (e.g., data obtained from the execution of instructions, workloads, operations, or any combination thereof) to a voting circuit 338 included in or otherwise connected to the CPU 102. That is, the core die 104 provides results 342 from the execution of the same set of instructions, workloads, operations, or any combination thereof, according to (e.g., managed by) two or more operating systems 112 (e.g., an operating system 112 associated with each core die 104 that provides the results 342). The voting circuit 338 includes, for example, hardware-based circuitry, software-based circuitry, or both, configured to determine an output 344 for the CPU 102 based on the received results 342 (e.g., results 342 received from each core die 104 associated with each respective operating system 112). For example, to determine output 344, a voting circuit (including, for example, a majority logic gate) is configured to determine a majority result from the received result 342 (e.g., the most frequently occurring or most common result in the received result 342), a minority result from the received result 342 (e.g., the least frequently occurring result in the received result 342), or both. In this way, the CPU 102 implements an N-way operating system redundancy framework 300 to help minimize errors, security vulnerabilities, or both, introduced into the processing system 100 by one or more operating systems 112. For example, in an implementation, the CPU 102 includes a first core die 0 104-1 associated with a first operating system 0 112, a second core die 1 104-2 associated with a second operating system 1 112-2, and a third core die 2 104-3 associated with a third operating system 2 112-3, each configured to execute the same set of instructions for an application.In response to executing a set of instructions, each core die 104 is configured to provide a result (e.g., data resulting from the execution of the set of instructions) to a voting circuit 338. The voting circuit 336 then determines the majority result (e.g., the most frequently occurring or most frequent result among the received results 342) in order to determine the output 344 for the CPU 102. In this way, if any of the core dies 104 of the CPU 102 provides an incorrect result due to one or more errors, security vulnerabilities, or both introduced by the operating system associated with the core die 104 (e.g., operating system 0 112-1, operating system 1 112-2, operating system 2 112-3), the voting circuit still determines the correct output 344 by determining the majority result and ignoring the incorrect result caused by the operating system 112 that introduced one or more errors, security vulnerabilities, or both.

[0031] Referring now to Figure 4, a CPU 102 implementing an exemplary N-way hardware redundancy framework 400 is shown. Within the N-way hardware redundancy framework 400, the CPU 102 includes one or more core dies 104 associated with one or more ISAs 440 (e.g., one or more cores 104 including processor cores 106, 108, 232 having architectures associated with one or more ISAs 440), one or more core dies 104 each including one or more programmable logic devices 230, or both. For example, the CPU 102 includes a first core die 0 104-1 associated with a first ISA 0 440-1 (e.g., x86), a second core die 1 104-2 associated with a second ISA 1 440-2 (e.g., ARM), and a third core die 2 104-3 including one or more programmable logic devices 230 (e.g., FPGA). The exemplary implementation shown in Figure 4 presents core die 104-3 as having two programmable logic devices (230-1, 230-K) representing K programmable logic devices 230, but in other implementations, core die 104 can contain any number of programmable logic devices 230. According to the implementation, the hypervisor circuit 336 is configured to assign each core die 104 to its respective VM so that each core die 104 executes the same instructions, workloads, operations, or any combination thereof for the application run by each VM. In this way, each core die 104 is configured to execute the same instructions, workloads, operations, or any combination thereof for the same application simultaneously. Thus, CPU 102 is configured to execute the same instructions, workloads, operations, or any combination thereof for an application using different hardware (for example, based on core die 104). For example, CPU 102 is configured to execute the same instructions, workloads, operations, or any combination thereof using core die 104 associated with two or more different ISA440s (e.g., x86, ARM).Furthermore, the CPU 102 is configured to execute the same instructions, workloads, operations, or any combination thereof for applications that use a core die 104 associated with one or more ISA440s (e.g., x86, ARM), applications that have one or more programmable logic devices 230, or both.

[0032] Depending on the execution of one or more instructions, workloads, operations, or any combination thereof for an application, each core die 104 is configured to provide results 342 (e.g., data obtained from the execution of instructions, workloads, operations, or any combination thereof) to a voting circuit 338 included in or otherwise connected to the CPU 102. That is, the core die 104 provides results 342 from the execution of the same set of instructions, workloads, operations, or any combination thereof, based on the hardware associated with the core die 104 (ISA440, a programmable logic device). To determine the output 344, the voting circuit 338 (e.g., including a majority logic gate) is configured to determine a majority result from the received result 342 (e.g., the most frequently occurring result or most frequent result in the received result 342), a minority result from the received result 342 (e.g., the least frequently occurring result in the received result 342), or both. In this way, the CPU 102 implements an N-way hardware redundancy framework 300 to help minimize errors, security vulnerabilities, or both introduced into the processing system 100 by one or more ISAs 440. For example, in an implementation, the CPU 102 includes a first core die 0 104-1 associated with a first ISA 0 440-1 (e.g., x86), a second core die 1 104-2 associated with a second ISA 1 440-2 (e.g., ARM), and a third core die 2 104-3 including one or more programmable logic devices 230 (e.g., FPGAs) each configured to execute the same set of instructions for an application. Depending on the set of instructions executed, each core die 104 is configured to provide results (e.g., data resulting from the execution of the set of instructions) to a voting circuit 338. The voting circuit 338 then determines a majority result (e.g., the most frequently occurring or most frequent result among the received results 342) in order to determine an output 344 for the CPU 102.In this manner, if any of the core dies 104 of the CPU 102 provide an incorrect result due to one or more errors, security vulnerabilities, or both introduced by the ISA 440 associated with the core die 104, the voting circuit still determines the correct output 344 by determining the majority result and ignoring the incorrect result caused by the ISA 440 that introduced one or more errors, security vulnerabilities, or both.

[0033] Next, referring to Figure 5, a CPU 102 implementing an exemplary N-way hardware redundancy framework 500 is shown. Within the N-way hardware redundancy framework 500, the CPU 102 includes one or more core dies 104 associated with one or more ISA440s (for example, one or more cores 104 including processor cores 106, 108, 232 having architectures associated with one or more ISA440s). For example, the CPU 102 includes a first core die 0 104-1 associated with a first ISA0 440-1 (e.g., x86), a second core die 1 104-2 associated with a second ISA1 440-2 (e.g., ARM), and a third core die 2 104-3 associated with a second ISA1 440-2 (e.g., ARM). According to the implementation, the hypervisor circuit 336 is configured to assign each core die 104 to each VM so that each core die 104 executes the same instructions, workloads, operations, or any combination thereof for the application run by each VM. In this way, each core die 104 is configured to execute the same instructions, workloads, operations, or any combination thereof for the same application simultaneously. Therefore, the CPU 102 is configured to execute the same instructions, workloads, operations, or any combination thereof for an application using different hardware (for example, based on the core die 104). For example, the CPU 102 is configured to execute the same instructions, workloads, operations, or any combination thereof using core dies 104 associated with two or more different ISA440s (e.g., x86, ARM).

[0034] To support the execution of one or more instructions, workloads, operations, or any combination thereof by the core die 104 of an application, the CPU 102 includes each I / O die 544, similar to or identical to the I / O die 228, for one or more core dies 104 of the CPU 102. For example, the CPU 102 includes each I / O die 544 connected to each core die 104 of the CPU 102. In some implementations, each I / O die 544 includes a separate, distinct die, while in other implementations, each I / O die 544 is formed by a partition of a larger I / O die (e.g., I / O die 228). The exemplary implementation shown in Figure 5 shows a CPU 102 containing four I / O dies (544-1, 544-2, 544-3, 544-N) representing N I / O dies 544, but in other implementations, the CPU 102 may have any number of I / O dies 544. For example, in the implementation, the CPU 102 has I / O dies 544 for each core die 104 of the CPU 102.

[0035] In the implementation, each I / O die 544 is associated with (e.g., connected to) its respective core die 104. For example, the first I / O die 0 544-1 is associated with the first core die 0 104-1, the second I / O die 1 544-2 is associated with the second core die 1 104-2, the third I / O die 2 544-3 is associated with the third core die 2 104-3, and the fourth I / O die 544-N is associated with the fourth core die N 104-N. Furthermore, each I / O die 544 includes hardware-based circuitry, software-based circuitry, or both, configured to provide an interface between its respective core die 104 and memory 118, one or more I / O devices 120, or both. For example, each I / O die 544 includes its own data fabric 224 or is otherwise connected to its own data fabric 224 to provide an interconnection architecture between its respective core die 104, memory 118, one or more I / O devices 120, bus 101, or any combination thereof. Furthermore, to provide an interface between the core die 104 and the memory 118, each I / O die 544 includes its respective memory controller 226 configured to access, modify, and delete data in the memory 118. Furthermore, to provide an interface between each core die 104 and one or more I / O devices 120, each I / O die 544 includes one or more respective I / O controllers 222 configured to manage data transfers (e.g., memory access requests) between its respective core die 104, the memory 118, and one or more I / O devices 120. Since each core die 104 interfaces with the memory 118 and I / O device 120 via its respective I / O die 544, the processing system 100 can partition the memory 118 and I / O device 120 so that only each partition of the memory 118 and I / O device 120 is accessible by a specific core die 104.Such partitioning improves the level of redundancy in the processing system 100, reducing the likelihood that the operating system 112, ISA, or both may introduce further errors, security vulnerabilities, or both into the processing system 100, thereby improving the reliability of the processing system 100.

[0036] Furthermore, in the implementation, each I / O die 544 is associated with an ISA (e.g., ISA440). That is, each I / O die 544 has an ISA-based architecture such that the I / O die 544 is configured to perform one or more operations (e.g., memory ordering, interrupt distribution, I / O device control, input / output memory management unit (IOMMU) implementation, root complex interaction, memory interaction) according to the ISA. According to the implementation, each I / O die 544 is associated with the same ISA as the core die 104 associated with the I / O die 544. For example, I / O die 0 544-1 associated with core die 0 104-1 is associated with ISA 0 440-1. In this way, each I / O die 544 is configured to support each core die 104 when two or more core dies 104 are associated with different ISAs (e.g., x86, ARM).

[0037] Referring here to Figure 6, an example of method 600 for implementing N-way fault tolerance is shown. In the implementation, method 600 includes a CPU 102 having one or more core dies 104 associated with each ISA 440 (e.g., having one or more processor cores 106, 108, 232 associated with each ISA 440), one or more core dies 104 having programmable logic devices 230 (e.g., FPGA), or both. Furthermore, the CPU 102 includes a core die 104 with a hypervisor circuit 336 (e.g., one or more processing cores 106, 108, 232 that execute one or more instructions for generating and managing VMs). In step 605, the hypervisor circuit 336 is configured to assign two or more core dies 104 of the CPU 102 to each VM executed by the processing system 100. In the implementation, each VM executed by the processing system 100 runs the same application and runs the same operating system 112 as two or more VMs executed by the processing system 100 that run different operating systems 112. As an example, the hypervisor circuit 336 is configured to assign a first core die 104 to a first VM running a first operating system 112, a second core die 104 to a second VM running a second operating system 112, and a third core die 104 to a third VM running a third operating system 112, where the first, second, and third operating systems 112 are each different from one another. As another example, the hypervisor circuit 336 is configured to assign the same operating system to two or more core dies 104 each associated with different ISA440s.As yet another example, the hypervisor circuit 336 is configured to assign a first core die 104 associated with a first ISA440 to a first VM running a first operating system 112, and a second core die 104 associated with a second ISA440 to a second VM running a second operating system 112, wherein the first ISA440 is different from the second ISA440, and the first operating system 112 is different from the second operating system 112.

[0038] In step 610, depending on the VM assigned, the core die 104 is configured to execute a set of instructions, workloads, operations, or any combination thereof for the same application run by the processing system 100, each VM (e.g., the VM to which the core die 104 is assigned), or both. That is, the processor cores 106, 108, 232 of each core die 104 execute a set of instructions, workloads, operations, or any combination thereof for the same application run by the processing system 100, each VM, or both. In this way, the core die 104 executes a set of instructions, workloads, operations, or any combination thereof using two or more operating systems 112, two or more ISA440, or both. In step 615, after executing a set of instructions, workloads, operations, or any combination thereof, each core die 104 provides the results 342 (e.g., data obtained from the execution of instructions, workloads, operations, or any combination thereof) to the voting circuit 336. Such result 342 represents the simultaneous execution of the same set of instructions, workloads, operations, or any combination thereof, according to two or more operating systems 112, ISA440, or both (for example, according to operating systems 112 and ISA440 associated with the core die 104).

[0039] In step 620, upon receiving result 342 from core die 104, voting circuit 336 is configured to determine, for example, output 344 of CPU 102 based on the received result 342. For example, to determine output 344 of CPU 102, voting circuit (including, for example, a majority logic gate) is configured to determine from the received result 342 a majority result (e.g., the most frequently occurring or most frequent result in the received result), a minority result (e.g., the least frequently occurring result in the received result), or both. In this way, CPU 102 implements N-way fault tolerance to help minimize errors, security vulnerabilities, or both introduced into processing system 100 by one or more operating systems 112, ISA, or both.

[0040] As disclosed herein, in some embodiments, the processor comprises: a first core die associated with a first operating system, comprising one or more processor cores, wherein one or more processor cores of the first core die are configured to execute instructions for producing a first result; a second core die associated with a second operating system, comprising one or more processor cores, wherein one or more processor cores of the second core die are configured to execute instructions for producing a second result, and the second operating system is different from the first operating system; and a voting circuit configured to produce outputs based on the first and second results. In one embodiment, the processor comprises a third core die associated with a third operating system, comprising one or more processor cores, wherein one or more processor cores of the third core die are configured to execute instructions for producing a third result. In another embodiment, the voting circuit is configured to produce outputs based on the first, second, and third results. In yet another embodiment, one or more processor cores on a first core die are associated with a first instruction set architecture (ISA), and one or more processor cores on a second core die are associated with a second ISA, the second ISA being different from the first ISA.

[0041] In one embodiment, a first input / output (I / O) die is associated with a first ISA and connected to a first core die, and a second I / O die is associated with a second ISA and connected to a second core die. In another embodiment, the processor includes a third core die containing one or more programmable logic devices. In yet another embodiment, the processor includes a third core die containing one or more processor cores configured to assign the first core die to a first virtual machine (VM) running a first operating system and the second core die to a second VM running a second operating system.

[0042] In some embodiments, the method includes executing an instruction on a first core die of a processor associated with a first operating system to produce a first result, executing an instruction on a second core die of a processor associated with a second operating system different from the first operating system to produce a second result, and producing an output based on the first and second results. In one embodiment, the instructions are executed simultaneously on the first and second core dies. In another embodiment, the method includes executing an instruction on a third core die of a processor to produce a third result, the third core die being associated with a third operating system, and the output being produced based on the first, second and third results. In yet another embodiment, the first core die includes one or more processor cores associated with a first instruction set architecture (ISA), and the second core die includes one or more processor cores associated with a second ISA, the second ISA being different from the first ISA.

[0043] In one embodiment, the method includes assigning a first core die to a first virtual machine (VM) running a first operating system, and assigning a second core die to a second VM running a second operating system. In another embodiment, the processor further includes a third core die containing one or more programmable logical devices.

[0044] In some embodiments, the processor includes a first core die comprising one or more processor cores associated with a first instruction set architecture (ISA), wherein one or more processor cores of the first core die are configured to execute instructions for producing a first result; a second core die comprising one or more processor cores associated with a second ISA, wherein one or more processor cores of the second core die are configured to execute instructions for producing a second result, and the second ISA is different from the first ISA; and voting circuits configured to produce outputs based on the first and second results. In one embodiment, the first core die is associated with a first operating system, and the second core die is associated with a second operating system, the second operating system being different from the first operating system. In another embodiment, the processor includes a third core die comprising one or more processor cores configured to assign the first core die to a first virtual machine (VM) running the first operating system, and to assign the second core die to a second VM running the second operating system.

[0045] In one embodiment, the processor includes a first input / output (I / O) die associated with a first ISA and connected to a first core die, and a second I / O die associated with a second ISA and connected to a second core die. In another embodiment, the processor includes a third core die containing one or more programmable logic devices. In yet another embodiment, the one or more programmable logic devices include one or more field-programmable gate arrays. In yet another embodiment, one or more processor cores on the first core die and one or more processor cores on the second core die are configured to execute instructions concurrently.

[0046] In some embodiments, the apparatus and techniques described above are implemented in a system including one or more integrated circuit (IC) devices (also called integrated circuit packages or microchips), such as the CPU described above, with reference to Figures 1 to 6. Electronic design automation (EDA) and computer-aided design (CAD) software tools can be used to design and manufacture these IC devices. These design tools are typically represented as one or more software programs. One or more software programs include computer-executable code for operating a computer system to operate with code representing the circuit of one or more IC devices, in order to perform at least part of the process of designing or adapting a manufacturing system for manufacturing the circuit. This code may include instructions, data, or combinations of instructions and data. Software instructions representing the design or manufacturing tools are typically stored in a computer-readable storage medium accessible to the computing system. Similarly, code representing one or more stages of designing or manufacturing an IC device is stored in and accessed from the same or different computer-readable storage medium.

[0047] Computer-readable storage media include any non-temporary storage media or combination of non-temporary storage media that are accessible by a computer system during use to provide instructions and / or data to the computer system. Such storage media may include, but are not limited to, optical media (e.g., compact discs (CDs), digital versatile discs (DVDs), Blu-ray® discs), magnetic media (e.g., floppy disks, magnetic tapes, magnetic hard drives), volatile memory (e.g., random access memory (RAM) or cache), non-volatile memory (e.g., read-only memory (ROM) or flash memory), or microelectromechanical system (MEMS) based storage media. Computer-readable storage media (e.g., system RAM or ROM) may be built into the computing system, computer-readable storage media (e.g., magnetic hard drives) may be permanently mounted to the computing system, computer-readable storage media (e.g., optical disks or Universal Serial Bus (USB) based flash memory) may be detachably mounted to the computing system, and computer-readable storage media (e.g., network-accessible storage (NAS)) may be connected to the computer system via a wired or wireless network.

[0048] In some embodiments, certain aspects of the technology described above are implemented by one or more processors of a processing system that executes the software. The software includes one or more sets of executable instructions, which are stored in a non-temporary computer-readable storage medium or otherwise clearly embodied. The software may also include instructions and specific data, which, when executed by one or more processors, operate the one or more processors to execute one or more aspects of the technology described above. Non-temporary computer-readable storage mediums may include, for example, magnetic or optical disk storage devices, solid-state storage devices such as flash memory, caches, random-access memory (RAM), or other non-volatile memory devices (one or more). Executable instructions stored in a non-temporary computer-readable storage medium can be implemented as source code, assembly language code, object code, or other instruction forms that can be interpreted or otherwise executed by one or more processors.

[0049] In addition to the foregoing, it should be noted that not all activities or elements described in the summary are required, and certain activities or parts of devices may not be required, and one or more additional activities may be performed, and one or more additional elements may be included. Furthermore, the order in which the activities are listed does not necessarily indicate the order in which they are performed. Also, the concepts have been described with reference to specific embodiments. However, those skilled in the art will understand that various modifications and variations can be made without departing from the scope of the invention as described in the claims. Therefore, the specification and drawings should be considered illustrative rather than restrictive, and all of these variations are intended to fall within the scope of the invention.

[0050] Benefits, other advantages, and solutions to problems have been described above with respect to specific embodiments. However, benefits, advantages, solutions to problems, and features that may give rise to or manifest any benefits, advantages, or solutions are not to be construed as essential, necessary, or indispensable features to any or all of the claims. Furthermore, the disclosed invention can be modified and implemented in different but similar ways, in ways that are obvious to those skilled in the art who are interested in the teachings of this specification; therefore, the specific embodiments described above are merely illustrative. There are no limitations to the details of the configuration or design shown herein beyond those described in the appended claims. Accordingly, the specific embodiments described above may be modified or altered, and it is clear that all such modifications are within the scope of the disclosed invention. Accordingly, the protection sought herein is described in the appended claims.

Claims

1. It is a processor, A first core die associated with a first operating system, comprising one or more processor cores, wherein the one or more processor cores of the first core die are configured to execute instructions for producing a first result, A second core die associated with a second operating system, comprising one or more processor cores, wherein the one or more processor cores of the second core die are configured to execute instructions for producing a second result, and the second operating system is different from the first operating system, and comprises the second core die. A voting circuit configured to generate an output based on the first result and the second result, Processor.

2. A third core die associated with a third operating system, comprising one or more processor cores, wherein the one or more processor cores of the third core die are configured to execute instructions to produce a third result. The processor according to claim 1.

3. The voting circuit is configured to generate the output based on the first result, the second result, and the third result. The processor according to claim 2.

4. The one or more processor cores of the first core die are associated with a first instruction set architecture (ISA), The one or more processor cores of the second core die are associated with the second ISA, The second ISA is different from the first ISA. The processor according to claim 1.

5. A first input / output (I / O) die associated with the first ISA and connected to the first core die, A second I / O die associated with the second ISA and connected to the second core die, The processor according to claim 4.

6. A third core die comprising one or more programmable logic devices, The processor according to claim 1.

7. It comprises a third core die containing one or more processor cores, The one or more processor cores of the third core die are The first core die is assigned to a first virtual machine (VM) that runs the first operating system, Assigning the second core die to a second VM that runs the second operating system, It is configured to do, The processor according to claim 1.

8. It is a method, The first core die of a processor executes an instruction for generating a first result, wherein the first core die is associated with a first operating system. The second core die of the processor executes an instruction for generating a second result, wherein the second core die is associated with a second operating system different from the first operating system. This includes generating an output based on the first result and the second result, method.

9. The instruction is executed simultaneously on the first core die and the second core die. The method of claim 8.

10. The third core die of the processor includes executing an instruction for generating a third result, The aforementioned third core die is associated with a third operating system, The output is generated based on the first result, the second result, and the third result. The method of claim 8.

11. The first core die includes one or more processor cores associated with a first instruction set architecture (ISA), The second core die includes one or more processor cores associated with the second ISA, The second ISA is different from the first ISA. The method of claim 8.

12. The first core die is assigned to a first virtual machine (VM) that runs the first operating system, This includes assigning the second core die to a second VM that runs the second operating system, The method of claim 8.

13. The processor comprises a third core die including one or more programmable logic devices. The method of claim 8.

14. It is a processor, A first core die comprising one or more processor cores associated with a first instruction set architecture (ISA), wherein the one or more processor cores of the first core die are configured to execute instructions for producing a first result, A second core die comprising one or more processor cores associated with a second ISA, wherein the one or more processor cores of the second core die are configured to execute instructions for producing a second result, and the second ISA is different from the first ISA and the second core die. A voting circuit configured to generate an output based on the first result and the second result, Processor.

15. The first core die is associated with a first operating system, The aforementioned second core die is associated with a second operating system, The second operating system is different from the first operating system. The processor according to claim 14.

16. It comprises a third core die containing one or more processor cores, The one or more processor cores of the third core die are The first core die is assigned to a first virtual machine (VM) that runs the first operating system, Assigning the second core die to a second VM that runs the second operating system, It is configured to do, The processor according to claim 15.

17. A first input / output (I / O) die associated with the first ISA and connected to the first core die, A second I / O die associated with the second ISA and connected to the second core die, The processor according to claim 14.

18. A third core die comprising one or more programmable logic devices, The processor according to claim 14.

19. The one or more programmable logic devices include one or more field-programmable gate arrays. The processor according to claim 18.

20. The one or more processor cores of the first core die and the one or more processor cores of the second core die are configured to execute the instructions simultaneously. The processor according to claim 14.

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