Laser-assisted multilevel microchannel fabrication method

Abstract

This invention provides a method for fabricating multi-level, high-quality, high-aspect-ratio, and fully embedded microchannels with various geometric shapes and architectures within a silicon (Si) bulk.

Description

Technical Field

[0001] This invention is a method for fabricating microchannels that have various geometries and architectures inside the bulk of a silicon (Si) substrate, are multi-level, high-quality, high aspect ratio, and completely embedded.

Background Art

[0002] Semiconductors, especially together with electronics and computing, underlie modern technology. Si has the unique advantage of being compatible with complementary metal oxide semiconductor (CMOS), unlike most other materials. Throughout the semiconductor industry to date, applications have been made on the top surface of wafers. Although proof-of-concept of optical elements in Si has been shown, to date, the possibility of fabricating completely embedded multi-level channels with diversity in length, depth, geometry, and architecture has not been shown. If it were possible to use creating such embedded microchannels, one of the most important current limitations of computers, namely the well-known heat-wall problem, could be addressed. Currently, the performance of computers cannot be further increased by increasing the clock speed because hot spots on the chip surface are not effectively cooled. If microchannels can be fabricated buried just below the surface, a design can be made to locally remove heat by flowing cooling water within the chip, greatly improving performance. Therefore, microchannels made within Si without changing the chip surface would be a very powerful platform for integrating "on-chip" systems into "in-chip" devices to greatly improve the performance of the device.

[0003] EP1427010A1 discloses a method for first creating surface channels and then partially closing them by an epitaxial growth process. This corresponds to a method for creating silicon-on-insulator (SOI) wafers in which channels are created very close to the wafer surface (i.e., to a depth of about 10 μm just below the 1–10 μm epitaxial layer). Using the method of EP1427010A1, there is a limitation in controlling the geometric shape of the channels, and they are not completely inside the crystalline silicon bulk.

[0004] Similarly, CN110379780A discloses microchannels that are fabricated on the surface of silicon and then covered with a film.

[0005] US7471866B2 discloses a method for controlling the fabrication of a planar waveguide structure using a mask-based silicon-based glass material with embedded microchannels having substantially circular or elliptical cross-sections.

[0006] Therefore, conventional lithography techniques and laser ablation methods are used to create surface channels in Si. However, there are no techniques available to create non-linear or multi-level channels embedded within Si. While it may be possible (in principle) to create some limited versions of linear subsurface channels using reactive ion etching, this would be extremely costly and laborious and impractical. An interesting goal for fabrication in transparent materials is to develop a direct laser writing technique with chemical etching. Similar laser-assisted chemical etching methods have been shown for creating channels in glass, but highly controlled microchannel fabrication in Si remains impossible.

[0007] In cutting-edge technology, the fabrication of through-Si vias has been reported by first polishing the sample, approaching the modified area, and then treating it with a developed chemical etchant (Petro Deminsky et al. in APS March Meeting Abstracts. Vol. 2018, 2018; Tokel et al. in Nature Photonics 11, 639, 2017). These early attempts were limited to the wafer surface or required many post-processing steps. Furthermore, there were limitations in fabrication regarding channel architecture, multi-level wiring, curved in-chip microchannels, high-throughput fabrication capabilities, and, most importantly, protection of the wafer surface for future CMOS integration. By developing these methods, we will arrive at a comprehensive in-chip microchannel fabrication technology encompassing all the claims of this invention, and will also introduce multi-level and non-linear channel fabrication. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1: A schematic block diagram of the method of the invention. [Figure 2] Figure 2 is a schematic diagram illustrating two laser writing modalities: (a) a transverse writing modality in which the laser scans perpendicular to the direction of propagation, and (b) a longitudinal writing modality in which the laser propagation is parallel to the sample scanning direction. [Figure 3]Figure 3: (a) shows the effective etching rate measured as a function of pulse energy. When the subsurface separation Λ = 11 μm and the number of faces is 16, the cutoff for pulse energy is observed at 4.3 μJ. Up to this point, regenerative and high-quality channel fabrication is achieved. (b) shows the effective etching rate obtained as a function of the number of subsurface faces. When Λ = 11 μm and Ep = 4.3 μJ, the cutoff for the number of faces was found to be 20. The maximum etching rate corresponding to the in-chip array is 750 μm / h. [Figure 4] Figure 4: (a) is a scanning electron microscope (SEM) image of a cross-section of one channel of a microchannel fabricated and embedded in Si. (b) is an SEM image (in this case, of the xz plane) showing depth control of the microchannel in Si. (c) is an SEM image of a 3x3 multilevel array of microchannels fabricated in Si. [Figure 5] Figure 5: (a) is a SEM image of a curved channel exposed through CMP. (b) is a high-resolution camera image of a set of four curved channels. The inset is a magnified view of one curved channel. (c) is an IR transmission microscopy image of a curved microchannel located within Si, with open ends and within volume. [Figure 6] Figure 6: (a) is an SEM image of a high aspect ratio (25) channel, with various port geometric shapes such as (i) circular, (ii) rectangular, and (iii) triangular. These are fabricated using a Bessel beam, which is a highly localized, spatially modulated beam. (b) is an SEM image of a through-silicon via (TSV) with a rectangular cross-section. [Figure 7]Figure 7: (a) is an optical profilometer (OPD) image of the wafer surface after channel fabrication. The average roughness (Ra) was measured to be 2.2 nm. (b) is an OPD image of the control sample, which is the initial Si surface, with a surface roughness of 2.0 nm. (c) is an SEM image of the Si surface after channel fabrication, showing no morphological changes. [Modes for carrying out the invention]

[0009] Brief description of the invention For over 50 years, computers have been made faster through better packaging and increased clock speeds. However, Moore's Law is now reaching its limits, and new solutions to overcome the problems of heat dissipation and associated clock speeds are urgently needed. Chip manufacturers responded by switching to multi-core architectures, but the problem of unmanageable heat buildup quickly resurfaced. This is especially true for GPUs, which represent the cutting edge of computing across a wide range of applications, from scientific calculations to autonomous vehicles. Current GPUs dissipate 500 watts of heat, which limits high-density embedding and therefore ultimately limits performance. A possible solution is to create curved subsurface microchannels to deliver coolant to the hot spots. However, this requires a true 3D architecture, which would involve a network of truly embedded (in-chip) microfluidic channels to efficiently dissipate heat, similar to the cooling by blood vessels in the human brain, for example. In this invention, laser writing of tightly controlled, in-chip multi-level multi-architecture microchannels is presented as a pioneer for this holy grail.

[0010] Conventional techniques have not provided a method for creating nonlinear channels within silicon. While reactive ion etching may (in principle) allow for the creation of some limited versions of linear subsurface channels, it would be extremely costly and labor-intensive, making it impractical.

[0011] Prior art does not disclose methods for fabricating curved or multi-level embedded microchannels in bulk silicon. Furthermore, controlling the geometric shape of the inlet port of a horizontal channel, such as a triangular or rectangular shape, is not possible using methods disclosed in the prior art.

[0012] Objects of the persons of this invention • To create high-quality, multi-level, and high-aspect-ratio (up to 25) microchannels embedded within silicon wafers. The maximum length of the embedded microchannel is 5 mm. • Create various architectures using a variety of laser writing modalities. This includes fabricating multi-level and curved channels, as well as top-to-bottom (through-Si via) or horizontal channels. • Control the geometric shape of the channel's cross-section. This includes ports with circular, triangular, or rectangular shapes. • To maintain device-level wafer surface quality for future on-chip device integration, this is achieved through passivation. The surface has a roughness of 2.2 nm, similar to the initial Si surface. • Achieves the most effective etching rate of the latest technology for the embedded channel, namely 750 μm / h.

[0013] Detailed description of the invention This invention provides a fabrication method for creating microchannels that are fully embedded in the silicon bulk while maintaining device-level quality on the upper surface of the wafer. For this purpose, the invention utilizes state-of-the-art laser cutting technology to form surface microchannels. Overcoming current limitations, this invention provides the fabrication of subsurface microchannels within silicon. Furthermore, this invention allows for the fabrication of through-silicon vias (TSVs) from the top to the bottom of the wafer without requiring any additional steps such as polishing. A schematic block diagram of the method of the invention is shown in Figure 1.

[0014] The technology of this invention enables the fabrication of in-chip (or in-volume) multi-level microchannels without damaging the surface of Si. This employs a two-step method using various laser writing modalities and specific lasers and focusing parameters, as well as novel writing based on the array to be created. Step 1 requires nonlinear writing to create the array by causing permanent modification in Si. Step 2 includes selective etching of the laser-written array to expose the channel array.

[0015] A two-step fabrication approach for subsurface microchannels Step 1 requires a nonlinear laser writing process to induce permanent subsurface modification deep within the silicon. This is followed by Step 2, which involves selective etching of the laser-written structure using a chemical etchant. This approach allows for the description of a first subsurface microchannel with complete wafer surface protection and the ability to control the channel depth, channel cross-sectional geometry, and aspect ratio measured from the wafer surface. Furthermore, the quality of the internal channel walls is improved.

[0016] In a preferred embodiment, an exemplary application of step 1 is shown below.

[0017] Step 1: Laser writing inside the silicon

[0018] The light source in the configuration of this invention is a main oscillator power amplifier (MOPA) system operating in a transparent Si window. This is a custom-built nanosecond laser operating at a wavelength of 1550 nm, a repetition rate of 150 kHz, and a pulse duration of 10 ns. The laser is capable of producing a maximum output of 6 W. The beam output has a Gaussian beam profile. The output from the laser passes through a quarter-wave plate (QWP) and a half-wave plate (HWP) to control its power. This is followed by a polarizing beam splitter that transmits linearly polarized light. In the process of the invention, a spatial light modulator (SLM) is used to control and modulate the beam's shape and phase profile. Before the beam is projected onto the SLM, it passes through a pair of lenses acting as a telescope to collimate and magnify the beam. Lenses L1 and L2 have focal lengths of f1=15 mm and f2=35 mm. Next, the beam is projected onto a silicon SLM liquid crystal with a resolution of 792 × 600 pixels and a pixel size of 20 μm, and reflected through it. The SLM modulates the phase profile of the beam. A Gaussian beam is preferred for laser writing. Thus, the SLM primarily acts as a mirror, but some initial results obtained using the SLM, particularly with respect to controlling the channel aspect ratio, are described later.

[0019] Before the beam passes through the last focusing lens, it is necessary to adjust its diameter according to the aperture of the aspherical focusing lens. Therefore, a 4f system is used to reduce the beam (f3 = 125 mm, f4 = 100 mm). The focusing aspherical lens (AFL) has a focal length of 4.5 mm. The AFL directly focuses the beam into the bulk of the Si sample, where a non-linear interaction is induced at the focus, resulting in a local change in the material. The beam width at the focus is 3 μm at its maximum 1 / e2. To scan the sample with respect to the laser, it is mounted on a 3D positioning stage with a resolution on the order of nanometers. This stage is controlled by computer code, which can create most complex 3D shapes, and thus, laser-written structures in Si.

[0020] Laser writing modalities: The horizontal and vertical laser writing modalities are used alternately due to their corresponding advantages. The horizontal and vertical modalities are to scan the sample perpendicular and parallel to the laser propagation direction, respectively (Figure 2). The horizontal mode can perform writing of any length simply by scanning, while the vertical mode can better control the geometric shape and dimensions of the cross-section. In vertical writing, the length of the modification may seem to be limited by the region where the laser is focused. However, to increase the length, it is possible to coherently stitch the modifications along the optical axis (a length of 5 mm is shown, but this is expected to increase with further optimization of the laser parameters).

[0021] An exemplary application of a preferred embodiment of Step 2 is shown below.

[0022] Step 2: Selective etching of the laser-modified regions in Si

[0023] Once the desired geometric shape has been achieved through laser writing modification in Si, the next step is to selectively remove them to create fully embedded microchannels or TSVs. As described in the section on the interaction of light and material, crystal collapse occurs in the areas where multiphoton absorption occurs. Therefore, a suitable etchant would be one that selectively attacks only the collapsed regions and does not affect the crystalline silicon. This would involve a combination of chemicals that work together simultaneously to perform the desired etching task.

[0024] The etchant consists of a mixture of chemicals having the corresponding components shown in the following sequence: copper(II) nitrate (Cu(NO3)2): 0.05 M (3 gr.), hydrofluoric acid (HF): 10 M (36 ml), nitric acid (HNO3): 4 M (25 ml), and acetic acid (CH3COOH): 3.5 M (24 ml). The etching process involves oxidizing and then decomposing the laser-irradiated area. Each chemical performs a specific function. For example, HNO3 is used as an oxidizing agent, HF removes the oxidized area, Cu(NO3)2 reduces the activation energy of the process and thus increases selectivity, and CH3COOH is used as an excipient. This mixture is carefully prepared in a cleanroom of a wet bench designated for this purpose. When preparing the etchant, all safety measures are taken in accordance with the Material Safety Data Sheets (MSDS) for each chemical used in the process.

[0025] Next, the beam is transmitted or reflected through physical or digital elements for spatial beam modulation. Gaussian beam or axicon-type modulation is used to create a zero-order Bessel function of the first kind. The latter is created using a liquid crystal-on-silicon spatial light modulator (LCOS-SLM). For a zero-order Bessel beam, conical phases with various signs and angles (θ) can be applied to the SLM. A 4f optical arrangement directs the beam to the final focusing lens. This system allows for expanding the cone angle or adjusting the diameter of the Gaussian beam at the aperture of the focusing lens. For focusing in Si, an aspherical lens with a focal length of 4.5 mm is preferred, but lenses with a high numerical aperture (NA) (>0.4) can also be used. The focused beam in Si produces a highly nonlinear effect that results in local material changes. For scanning the sample with respect to the laser, a high-precision, computer-controlled 3D positioning stage is used. The laser system and stage can create most complex 3D shapes, and therefore various laser-written structures embedded in silicon.

[0026] A significant advance is the recognition that creating microchannels with controlled quality and dimensions requires a specific arrangement of individual micro-modifications (Λ) and a large number of individual modified surfaces. Furthermore, it is necessary to ensure that the modified array does not become non-uniform due to excessive stress / strain accumulation and / or that cracks do not develop within the chip. These are all addressed by creating laser-written microchannels from a thin, multi-level array of surfaces.

[0027] Two different types of samples are used as suitable silicon wafers with differences in crystal orientation and resistivity. One is a p-doped wafer with resistivity of 1-10 Ω·cm and a thickness of 1 mm. <100> A molded silicon sample and a p-doped material with a resistivity of 1-10 Ω·cm and a thickness of 1 mm. <111> There are type Si samples. For experiments with Gaussian beam and transverse writing modalities, p-doping is used. <111> The sample was suitable. Similarly, with respect to vertical modality and Bessel writing structures, p-type <100> Laterally polished samples were preferred. No discernible differences in channels were observed between samples. Similarly, with respect to the art of this invention, the sample thickness is not strictly limited to 1 mm.

[0028] Dicing

[0029] The laser modification beneath the surface is completely embedded in three dimensions. This is a simple but crucial step to expose the modification from the side to create a path for the etchant. For this purpose, the wafer is diced using a DISCO DAD3220 dicing machine before immersing the Si in the chemical etchant, exposing the two end ports of the microchannel template. In another embodiment of the method, the laser-written volume extends all the way to the lateral surface of the wafer. In this case, dicing is not required, and the channel can be created through passivation and etching.

[0030] After dicing, the sample is carefully washed to remove any organic and inorganic impurities that may have accumulated on the sample. Acetone, isopropanol, and deionized water are used in sequence, and the sample is washed in an ultrasonic bath for a total of 15 minutes. The sample is then dried with nitrogen gas. This washing procedure is performed before the laser writing and chemical etching steps.

[0031] Photoresist passivation

[0032] To avoid any damage to the sample surface, systematic studies of various photoresist (PR) coatings were conducted. In preferred embodiments, a pipette was used to coat the photoresist to allow for the deposition of a thick protective layer. The PR was then hard-baked at 120 degrees Celsius for 5 minutes. The PR was successful in protecting the sample surface for at least 75 minutes. To fabricate microchannels requiring long etching periods, a time-multiplexed alternative process of coating and etching was employed. The sample was etched with the photoresist for 75 minutes, then removed from the etchant, and then recoated before being immersed in the etchant again. These steps were followed recursively to protect samples requiring long etching times. Two examples of preferred photoresists are trade names AZ-5214E ​​and AZ-4562, which differ in their hard-bake times.

[0033] To verify the methodology, advanced 2D / 3D imaging techniques were used for surface and subsurface characterization. Infrared transmission microscopy was used to obtain in-situ images of the laser-written structure. Scanning electron microscopy (SEM) was used for surface analysis, such as imaging of cross-sections of open microchannels. Optical profilometer (OPD) and energy-dispersive X-ray spectroscopy (EDXS) were used to characterize the wafer surface quality after fabrication. Significant structural limitations and instabilities were overcome by identifying appropriate regimes with respect to the spacing between individual subsurface planes (Λ), laser pulse energy (Ep), and the number of subsurface planes. The maximum etching rate for a given architecture is found through systematic studies of laser pulse energy and channel cross-sections (Figure 3a). The linear dependency of the effective etching rate (defined as the total length of the channel etched per minute) with respect to laser pulse energy shows that for a microchannel with Λ = 11 μm and 16 faces, the maximum etching rate is achieved at Ep = 4.3 μJ. Note that further increases in pulse energy lead to structural instability and cracking due to the accumulation of stress, resulting in a cutoff value for the laser pulse energy. Experiments show that the precise cutoff value depends on the architectural details of the building blocks of the individual channels, in this case, the separation (Λ) between the planar modifications below the surface.

[0034] The cross-sectional area, a feature of the second architecture, has been found to contribute to the effective etching rate. This is because a larger area provides a higher surface area for chemical etchants to open the channel. This, due to the stress induced, creates a cutoff value in terms of the number of faces per channel, as identified below. For example, a microchannel with Λ = 11 μm and Ep = 4.3 μJ was found to have a cutoff value with respect to 20 faces. With respect to these parameters, the effective etching rate was found to be as high as 750 μm / h (Figure 3b). This value is the highest channel etching rate in Si, and is higher than that of a similar experiment in glass (363 μm / h, by CA Ross et al., Optics Express, vol. 26, no. 19, 2018, pp. 24343-24356).

[0035] As a result of this procedure, very high-quality embedded microchannels (Figure 4a) can be obtained that can be placed anywhere within the wafer. For example, three microchannels created at various depths are shown in Figure 4b. Furthermore, a multilevel array of microchannels (Figure 4c) is obtained. These arrays are written level by level, starting from the bottom and going up to the top level, and all are etched together. The laser parameters for each microchannel are Ep = 2.9 μJ, Λ = 10 μm, and number of faces = 14.

[0036] Another claim is the creation of curved channels (Figure 5) in bulk Si. A unique approach was used for these imagings. The structure was first exposed at the surface using chemical mechanical polishing (CMP), and then etching was performed for proof of concept (Figure 5 ab). In parallel, in-situ imaging based on infrared transmission microscopy shows the embedded channels (Figure 5c). These constitute the first fully embedded, open-ended, and curved microchannels. In this method, virtually any channel shape or network can be formed depending on the requirements of the application. Another claim is the control of the cross-sectional geometric shape. Bessel beams and longitudinal writing are used to create long, modified lines (along the optical axis). They are then aligned closely along multiple axes to form various shapes (Figure 6). Thus, long channels with an aspect ratio of 25 and various cross-sections were fabricated (Figure 6 a i-iii). Furthermore, this method makes it possible to create high-quality vertical channels (through-silicon vias) without requiring any pre-polishing steps (Figure 6b).

[0037] Another claim is that the upper / lower wafer surfaces are preserved and remain after laser writing and etching. This will be important for future applications, such as the possibility of in-chip integration with electronic devices. The average surface roughness of the Si after fabrication was 2.2 nm, measured using an OPD (Figure 7). This value is equivalent to that of the initial silicon (2.0 nm). This is achieved by coating the surface with a thin film of AZ-5214E ​​photoresist using a pipette. The sample was baked at 120 degrees Celsius for 5 minutes and left to rest for 2 hours before the etching protocol. Energy-dispersive X-ray spectroscopy (EDXS) analysis is used to confirm that no chemical impurities remain on the surface. Thus, this method protects the wafer surface from any possible modification fabrication. Within these basic concepts, it is possible to develop various embodiments of the novel “Laser-Assisted Multilevel Microchannel Fabrication Method Embedded in Silicon” technique, and this invention is not limited to the examples disclosed herein.

Claims

1. A method for fabricating microchannels that are completely embedded within a silicon wafer, i. A step of operating a laser beam source at a wavelength that is within the transparent window of the silicon wafer, ii. Steps for identifying and selecting the laser writing modality, iii. A step of protecting the upper and / or lower surfaces of the silicon wafer from chemical etching by photoresist passivation, iv. A step of chemical etching for selective removal of the laser-modified region. A method that includes this.

2. A method according to claim 1, characterized in that the laser beam source is a pulsed laser operating in a transparent silicon window, with λ of 1550 nm, a repetition rate of 150 kHz, and a pulse duration of 10 ns.

3. The method according to claim 2, characterized in that the power control of the laser beam source is achieved by a pair of waveplates or attenuation filters.

4. A method according to claim 1, characterized in that, prior to the step of identifying and selecting the laser writing modality, the beam is transmitted or reflected through an element for spatial beam modulation.

5. The method according to claim 4, characterized in that the beam modulation is Gaussian or Bessel type modulation.

6. A method according to claim 1, wherein the laser writing modality is transverse for scanning the wafer perpendicular to the laser propagation direction.

7. A method according to claim 1, characterized in that the laser writing modality is longitudinal for scanning the wafer parallel to the laser propagation direction.

8. A method according to claim 1, characterized in that, with respect to the photoresist passivation, the photoresist material is added to the surface above and / or below the silicon wafer so as to form a protective layer and then baked.

9. A method according to claim 1, characterized in that the chemical etchant is formed using at least one oxidizing agent, at least one activation energy reducing agent, at least one acid, and at least one excipient.

10. The method according to claim 9, characterized in that the oxidizing agent is nitric acid.

11. The method according to claim 9, characterized in that the activation energy reducing agent is copper(II) nitrate.

12. The method according to claim 9, characterized in that the acid is hydrofluoric acid.

13. A method according to claim 9, characterized in that the excipient is acetic acid.

14. A silicon wafer having a fully embedded microchannel architecture manufactured according to claim 1.

15. A silicon wafer according to claim 14, characterized in that the fully embedded microchannels are positioned parallel to the upper wafer surface.

16. A silicon wafer according to claim 14, characterized in that the fully embedded microchannels are positioned perpendicular to the upper wafer surface.

17. A silicon wafer according to claim 14, characterized in that the microchannels are multilevel.

18. A silicon wafer according to claim 14, characterized in that the microchannels are curved.

19. A silicon wafer according to claim 14, characterized in that the wafer surface is left as initial silicon for future on-chip device integration.

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