Vertical word line driver structure and method

Abstract

The present invention relates to a vertical word line driver structure and method. The vertical word line driver comprises a transistor used to drive word lines in a three-dimensional (3D) memory structure. The vertical transistor structure is formed in a semiconductor substrate including a gate-all-around (GAA) structure or a double-gate structure, the GAA structure or double-gate structure including a gate oxide, an amorphous IGZO (indium gallium zinc oxide) channel adjacent to the gate oxide, and a liner adjacent to the amorphous IGZO channel. The GAA structure may have a frustoconical or cylindrical shape with straight walls. The double-gate structure may have straight walls or angled walls. The outer wall of the gate oxide is in contact with a polysilicon gate layer. The upper and lower contacts are electrically coupled to the amorphous IGZO channel.

Description

Technical Field

[0001] (Cross - reference to related applications) This application claims priority to U.S. Patent Application No. 18 / 188,391, filed on March 22, 2023, under 35 U.S.C.§365(c), the entire content of which is incorporated herein by reference.

Background Art

[0002] Flash memory devices may include a memory array that includes a large number of non - volatile memory cells arranged in an array of rows and columns. In recent years, vertical memories such as three - dimensional (3D) memories have been developed in various forms such as NAND, NOR, and cross - point. A 3D flash memory array may include a plurality of memory cells stacked on top of each other. Each group of memory cells may share a plurality of access lines known as word lines and bit lines.

[0003] In NAND memory technology, especially 3D NAND memory technology, the connection between the word - line driver transistors and their respective word lines is an important architectural decision that affects the die area, die performance, and system metrics of 3D NAND. The word - line driver transistors need to support high voltages and breakdown states and occupy a significant area of the 3D NAND die. The memory - tile - based architecture on 3D NAND further increases the total area of the word - line drivers within the die. Generally, the placement of the word - line driver transistors affects the availability of contact areas within the flash memory device and the height dimension of the blocks.

Brief Description of the Drawings

[0004] The foregoing aspects of the present invention and many of the attendant advantages will become more readily apparent as the understanding progresses by referring to the following detailed description in conjunction with the accompanying drawings. Unless otherwise specified, the same reference numerals refer to the same parts throughout the various drawings.

[0005] [Figure 1] This is a block diagram of an example of a system that stores data on a non-volatile (NV) medium. [Figure 2] This is a block diagram of an example system including a three-dimensional (3D) memory device structure. [Figure 3] This figure shows an elevation view and a plan cross-sectional view of a transistor gate structure including a gate-all-around (GAA) thin-film transistor (TFT) structure according to the first embodiment. [Figure 3a] This figure shows a cross-sectional view of a transistor gate structure including a double gate according to the second embodiment. [Figure 3b] This figure shows an elevation cross-sectional view of a transistor device having a structure similar to that shown in Figure 3, but with a first alternative top / drain contact pattern, according to one embodiment. [Figure 3c] This figure shows an elevation cross-sectional view of a transistor device having a structure similar to the structure shown in Figure 3b, which is composed of a copper or polysilicon alternative pad material according to one embodiment. [Figure 3d] This figure shows a cross-sectional view of a transistor gate structure having a double gate containing an IGZO filler, according to one embodiment. [Figure 4a] This is an elevation cross-sectional view of a semiconductor structure after each step of a manufacturing process according to one embodiment. [Figure 4b] This is an elevation cross-sectional view of a semiconductor structure after each step of a manufacturing process according to one embodiment. [Figure 4c] This is an elevation cross-sectional view of a semiconductor structure after each step of a manufacturing process according to one embodiment. [Figure 4d] This is an elevation cross-sectional view of a semiconductor structure after each step of a manufacturing process according to one embodiment. [Figure 4e] This is an elevation cross-sectional view of a semiconductor structure after each step of a manufacturing process according to one embodiment. [Figure 4f]This is an elevation cross-sectional view of a semiconductor structure after each step of a manufacturing process according to one embodiment. [Figure 4g] This is an elevation cross-sectional view of a semiconductor structure after each step of a manufacturing process according to one embodiment. [Figure 4h] This is an elevation cross-sectional view of a semiconductor structure after each step of a manufacturing process according to one embodiment. [Figure 5] This flowchart shows the steps performed to obtain the semiconductor structure shown in Figure 4a. [Figure 6] This flowchart shows the operations performed in the steps to obtain the semiconductor structure shown in Figures 4b to 4h. [Figure 7a] This figure shows an elevation cross-sectional view of a semiconductor structure including two GAA TFT devices having a first alternative configuration according to one embodiment. [Figure 7b] Figure 7a is a cross-sectional view of the semiconductor device according to one embodiment, showing further details of the vertical word line drivers connected to each word line. [Figure 7c] This figure shows the plan view located above the cross-sectional view in Figure 7b. [Figure 7d] This figure shows a partial cross-sectional view of a semiconductor structure, including a double-gate transistor device having a pillar structure employing an amorphous IGZO core, according to one embodiment. [Figure 8a] This figure shows an elevation cross-sectional view of a semiconductor structure including two GAA TFT devices having a second alternative configuration according to one embodiment. [Figure 8b] Figure 8a is a cross-sectional view of the semiconductor device according to one embodiment, showing further details of the vertical word line drivers connected to each word line. [Figure 9a] This figure shows an elevation cross-sectional view of a semiconductor structure including two GAA TFT devices having a third alternative configuration according to one embodiment. [Figure 9b] Figure 9a is a cross-sectional view of the semiconductor device according to one embodiment, showing further details of the vertical word line drivers connected to each word line. [Figure 10] FIG. is a cross-sectional view of a transistor structure including a TiN bottom plug contact. [Figure 11] FIG. shows a 3D view of an abstracted memory device in which aspects of the embodiments described and illustrated herein may be implemented, according to one embodiment.

BRIEF DESCRIPTION OF THE DRAWINGS

[0006] In this specification, embodiments of the structure and method of a vertical word line driver will be described. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the present invention. However, one skilled in the relevant art will recognize that the present invention may be practiced without one or more of these specific details, or with other methods, components, materials, etc. In another example, well-known structures, materials, or operations are not shown or described in detail in order to avoid obscuring aspects of the present invention.

[0007] References throughout this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0008] For clarity, individual components in the figures of this specification may be referred to by labels in the figures rather than specific reference numbers. Moreover, reference numbers that refer to a particular type of component (rather than a particular component) may sometimes be indicated with “(typ)” meaning “typical” after the reference number. The configuration of these components, if any, is understood to be the typical configuration of similar components that may exist but are not shown in the drawing for simplicity and clarity, or similar components that are not assigned separate reference numbers. Conversely, “(typ)” should not be construed to mean that a component, element, etc. is typically used for the disclosed function, implementation, purpose, etc.

[0009] FIG. 1 is a block diagram of an example of a system for storing data in a non-volatile (NV) medium. System 100 includes a host 110 coupled to an NV device 120. Host 110 represents a computing device. Host 110 includes I / O (input / output) 112, which represents the hardware for interconnecting with NV device 120. NV device 120 includes I / O 122 corresponding to I / O 112. I / O 122 represents the hardware for interconnecting with host 110.

[0010] Host 110 provides a hardware platform for operating NV device 120. Host 110 includes one or more processors 114 for performing the operations of host 110. Processor 114 executes a host operating system (OS) that provides a software platform for the operation of NV device 120. The hardware platform provides hardware resources for interfacing with NV device 120, including transceiver hardware for accessing NV device 120. The software platform includes control software for executing other software elements, such as applications or other agents that create access requests to NV device 120 and are executed under the OS.

[0011] I / O112 and I / O122 are interconnected via one or more signal lines 150. The signal lines 150 typically consist of multiple separate lines and can be considered as one or more buses connecting the host 110 to the NV device 120. The host 110 can send host read commands to the NV device 120 via the signal lines 150. In response to a read command, the NV device 120 addresses the request from a transient Vt state according to any provided example.

[0012] In one example, the host 110 includes a controller 116. The controller 116 represents a memory controller or a storage controller. In one example, the controller 116 is integrated with the processor 114. In another example, the controller 116 is separate from the processor 114. The controller 116 enables the host 110 to manage access to the NV device 120. In response to a host operation by the processor 114 requesting access to data on the NV device 120, the controller 116 provides access to the NV device 120. The controller 116 may represent hardware and firmware elements of the host 110 that enable interaction with the NV device 120.

[0013] The NV device 120 includes a controller 124 representing a storage controller on the storage device side, which is separate from the controller 116 of the host 110. The controller 116 of the host 110 represents a component of the host system. The controller 124 represents a component of the storage device or memory device in which the NV medium is incorporated. The controller 124 receives commands sent from the host 110 and determines how to handle commands or requests from the host. In response to host commands, the controller 124 performs actions to access (e.g., read or write) the NV medium 130.

[0014] The NV medium 130 represents the non-volatile storage medium of the NV device 120. In one example, the NV medium 130 includes a three-dimensional (3D) NAND (not AND) memory cell. In another example, the NV medium 130 includes a 3D NOR memory cell. In yet another example, the NV medium 130 includes a 3D crosspoint memory cell.

[0015] The NV medium 130 comprises bit cells or memory cells organized as blocks 132. A block of memory refers to a portion of the NV medium 130 that are jointly charged or activated for access operations. In one example, block 132 is subdivided into subblocks. In one example, a block refers to bit cells that share select gate lines. In one example, multiple subblocks share a select gate (e.g., a common select gate source (SGS) or a common select gate drain (SGD)) connector.

[0016] In one example, a block refers to an erasure unit or unit size of the NV medium 130 that is erased in a batch and whose write count is monitored by the controller 124. In one example, the NV medium 130 includes single-level cell (SLC) media and multi-level cell (MLC) media. For example, the NV medium 130 may contain bit cells of SLC and QLC (quad-level cell) or SLC and TLC (triple-level cell). The block size may vary depending on the type of media.

[0017] In one example, the controller 124 is an ASIC (Application-Specific Integrated Circuit) that controls the operation of the NV device 120. In another example, the controller 124 is a CPU (Central Processing Unit) core or processor device on the NV device 120. In one example, the NV device 120 represents an SSD, and the controller 124 controls multiple NV media dies or NV media chips integrated into the SSD. In another example, the NV device 120 represents a module or PCB (Printed Circuit Board) that integrates multiple NV media dies or NV media chips, and the controller 124 controls the NV media dies of the module. In one example, the controller 124 runs firmware for managing the NV device 120. In another example, the controller 124 runs firmware for managing the NV device 120 (including firmware for controlling the processing of read commands based on whether the NV media is in thermal equilibrium).

[0018] In one example, the controller 124 manages Vt state detection and read command processing based on idle time or delays between consecutive read commands. In one example, the controller 124 monitors one or more media states 126. The media states 126 represent the state of a portion of memory (such as a block), and the controller can determine how to access the media based on the media states 126. For example, if the media state 126 indicates that the target block is in a stable state, the controller 124 can issue a dummy read before accessing the target block. In one example, the NV media device 120 may include one or more timers 142 and counters 144.

[0019] Figure 2 is a block diagram of an exemplary system illustrating further details of the 3D memory device structure. System 200 represents a computing device with 3D memory. Host 210 represents a hardware platform that performs operations to control the functions of System 200. Host 210 includes a processor 212, which is a host processor that performs the operations of the host. In one example, processor 212 is a single-core processor. In one example, processor 212 is a multi-core processor device. Processor 212 may be a general-purpose processor that runs a host operating system or software platform for System 200. In one example, processor 212 may be an application-specific processor, a graphics processor, a peripheral processor, or another controller or processing unit on Host 210. Processor 212 runs multiple agents or software programs (not specifically shown). Agents may be standalone programs and / or threads, processes, software modules, or other code and data that are run by processor 212.

[0020] While the processor 212 is performing an operation, an agent executed by the processor can request data and / or code that is not stored in the host 210 (e.g., cache or main memory) and therefore should be retrieved from memory 220. The storage controller 214 generates and processes memory access commands to memory 220 to perform memory access. The storage controller 214 represents the circuitry, logic, or processor that manages access to memory 220. In one example, the storage controller 214 is part of the host 210. In one example, the storage controller 214 is part of the processor 212. In one example, the storage controller 214 is integrated on a common board with the processor 212. In one example, the storage controller 214 is a separate chip from the processor 212 and may be integrated together with the processor 212 in a multi-chip package (MCP).

[0021] The memory 220 is located in a memory or storage device and includes a controller 240 that represents a controller for processing and handling commands from the storage controller 214. In one example, the controller 240 represents a controller for a memory device. In another example, the controller 240 represents a controller for a memory module. The memory 220 includes a 3D array 222. In one example, the 3D array 222 contains NAND memory blocks. In another example, the 3D array 222 contains QLC NAND memory blocks.

[0022] As shown in the diagram, bit lines (BL) intersect the plane of the word line (WL) layer. For example, each word line WL[0:(N-1)] is one layer. There may be P bit lines (BL[0:(P-1)]). For example, the 3D array 222 is also divided into subblocks by SGD[0:(M-1)], which divides each word line into separate segments within one layer or within the word line plane. Alternatively, SGS may be subdivided to provide subblocks. In such a configuration, SGS is shown to apply to multiple SGD lines, but there may be multiple SGS lines corresponding to a single SGD line. SRC represents the common source.

[0023] Channel 250 represents a vertical channel in the 3D array. A channel refers to a vertical stack of chargeable bit cells via a channel connector. In one example, a channel is coupled to a bit line. It will be understood that the stable Vt state of a channel may be spatially dependent. For example, the flow of charge carriers within a channel may differ at different ends of the channel. Therefore, a block with a particular word line may show more significant degradation than other blocks. The operation of controller 240 to mitigate read interference caused by stable Vt within a channel may be set by a threshold and by mitigating the most sensitive word line.

[0024] Each label WL[0], WL[1], SGD[0], etc., indicates a selection signal provided by the control logic of the decoding logic 224 or by the control logic of the detection / output logic 226. In one example, the decoding logic 224 includes selection logic for selecting each signal line shown. In one example, the detection / output logic 226 enables detection of the contents of bit cells in the 3D array 222 for a read operation of the array or a write operation of values ​​back to the array. The output may be for a read operation that sends data back to the host 210. A write operation involves writing to a buffer for applying values ​​to the array.

[0025] It will be understood that the signal lines within the 3D array 222 are wires, traces, or other conductors that supply charge from the driver to various elements or components. The driver circuit decoding logic 224 supplies charge to each signal line to charge it to the desired voltage for the desired operation. Each signal line may have associated voltage levels that are linked to a particular operation. For example, each word line may have a selection voltage that indicates a word line selected for operation and a deselection voltage that indicates a word line not selected for operation.

[0026] In a 3D array 222, it will be understood that the length of word lines can be substantial. In one example, the number of word line layers is in the tens or dozens (e.g., N=28, 32, 36, 70, or more). In one example, the number of subblocks is in the single digits or tens (e.g., M=8, 76, or more). Typically, the number of bit lines in a 3D array 222 ranges from several hundred to several thousand (e.g., P=2K). Therefore, in one example, each bit line is relatively short compared to the length of a word line.

[0027] Figure 3 shows a transistor gate structure 300 according to one embodiment. Structure 300 comprises a gate-all-around (GAA) thin-film transistor (TFT) device based on a p-type polysilicon gate, an amorphous IGZO (indium gallium zinc oxide) channel, an AlOx (aluminum oxide) liner, a deposited low-temperature gate oxide, and a TiN / W (titanium nitride / tungsten) contact. In one embodiment, an existing polySi gate in a conventional 3D NAND structure is used. Selectively, high-work-function metal-substituted gates / multi-gates may be used. The amorphous IGZO (wide-bandgap) oxide semiconductor channel is deposited to a thickness of 3-10 nm using physical vapor deposition (PVD) or atomic layer deposition (ALD). Channel materials include IGZO, IAZO (indium aluminum zinc oxide), and treatment for post-thermal stabilization (F-implant). The aluminum oxide dielectric channel liner is deposited under specific conditions below critical thickness with low H content / low H content precursors to ensure a positive Vt of the device. In one embodiment, the structure employs a conventional low-temperature oxide gap fill and a conventional TiN / W contact.

[0028] The layers within structure 300 include tungsten (W) filler 302, silicon nitride (Si3N4) layer 304, silicon oxide (SiO2) layer 306, silicon nitride layer 308, polysilicon layer 310, silicon oxide layer 312, polysilicon layer 314, and W x Si y (For example, a tungsten silicide (W5Si3)) layer 316 and a silicon oxide layer 318 are included. The transistor structure has an inverted frustoconical shape and includes an outer wall of gate oxide 324, an amorphous IGZO channel 326, an Al2O3 (aluminum oxide) liner 328, and an SiO2 filler 330 on which TiN / W contacts are formed, the TiN / W contacts including a TiN 332 cap on which W contacts 334 are formed. The TiN structure 320 and Ti structure 322 are formed on the W contacts 334.

[0029] As shown in section detail 335, in one embodiment the cross-section of the gate structure is circular. The diameters of the outer wall of the gate oxide 324, the amorphous IGZO channel 326, the Al2O3 liner 328, and the SiO2 filler 330 vary depending on the depth of the inverted frustoconical pillar. The angle of the sidewall may vary depending on the etching solution used to form the inverted frustoconical pillar and the material in the layer being etched.

[0030] Figure 3a shows a first alternative configuration of a transistor device having a double-gate structure 300a. In this example, the left elevation section is shown as being the same as that of structures 300 and 300a. In addition to the inverted frustoconical shape, as shown in the following embodiments, the pillar shape may be substantially cylindrical with straight sidewalls. Similarly, the double-gate structure may employ angled walls (illustrated in Figure 3a) or straight walls. As shown in detail 337, the rows of the double-gate structure 300a are formed using trench 338 and a number of orthogonal trenches 340 and 342. The trenches 338, 340, and 342 may be formed using known manufacturing techniques, such as using an etching solution.

[0031] Figures 3b and 3c show elevation cross-sectional views of transistor devices 300b and 300c, which have a similar structure to those shown in Figure 3 but differ in their top / drain contact patterns and materials. As shown in Figure 3b, the contact pattern 344 consists of tungsten 346 pads formed on a layer of TiN 348. Generally, in addition to tungsten, materials with a work function equivalent to tungsten may be used for the contact pattern pads. For example, in Figure 3c, the contact pattern 350 consists of copper or polysilicon 352 pads 352 formed on the TiN layer 348, which are non-limiting examples of suitable pad materials. The shapes of the pads 346 and 352 may vary to suit different designs, but they always cover at least the top of the SiO2 filler 330.

[0032] Figure 3d shows a cross-sectional view of a transistor device with a double-gate structure 300d in which the pillars are filled with IGZO 326 without using an (Al2O3) liner or SiO2 filler. As shown in detail 337a, the width of the trench 339 before the deposition of the gate oxide 324 is significantly narrower than that shown in Figure 3a as an IGZO filler and discussed above (note that in the double-gate embodiment shown in Figure 3d, straight walls are employed).

[0033] The construction sequence for manufacturing the transistor gate structure 300 is shown in Figures 4a-4h, and the operation / steps are shown in flowcharts 500 and 600 in Figures 5 and 6. This sequence begins with the intermediate structure 400a formed using the process of flowchart 500, and this step begins with manufacturing the layer in step 502. In the manufacturing operation, the illustrated layers (starting with silicon oxide layer 318, followed by W) are manufactured. x Si y Known techniques for manufacturing the layers may be used, such as depositing or forming layer 316, polysilicon layer 314, silicon oxide layer 312, polysilicon layer 310, silicon nitride layer 308, and silicon oxide layer 306). Next, in step 504, a pillar pattern is formed by etching. A pillar pattern containing pillars 402 within the layered structure is formed using a mask and etching. In step 506, the mask is removed. In step 508, a layer of gate oxide (e.g., SiO2) is deposited on the inner wall of pillar 402.

[0034] Next, in step 510, a material to protect the sidewall oxide, such as an amorphous silicon protective film, is added. In step 512, anisotropic etching is performed on the raw material (W x Si y The layer 316) is exposed. In step 514, the sidewall protective material is removed, and in step 516, the channel and liner are deposited. This involves depositing a layer of IGZO on the gate oxide to form the IGZO channel 326, followed by depositing a layer of AlOx to form the liner 328.

[0035] Moving to flowchart 600 in Figure 6, and referring to structures 400b to 400h in Figures 4b to 4h, the following steps / operations are performed. In step 602, an oxide filling operation is performed by buff polishing using chemical mechanical planarization (CMP). During this step, silicon oxide 330 filler is added. Next, in step 604, the oxide is dry-etched to form recesses. Structure 400c is obtained by selectively etching the recesses 331 in silicon oxide relative to the channel liner, as shown in Figure 4c. In one embodiment, the depth of the recesses 331 is approximately 1100A. In step 606, AlOx and IGZO deposited on top of the silicon oxide layer 306 are polished using CMP, and polishing is stopped at the top of this layer. The result of this step is shown in structure 400d in Figure 4.

[0036] Next, in step 608, wet etching is performed using NH4OH (ammonium hydroxide solution, also called ammonia solution, aqueous ammonia solution, or ammonia water) to remove the AlOx channel liner, leaving an annular hoop of IGZO326 as shown in structure 400e in Figure 4e. In step 610, the voids obtained by the wet etching in step 608 are filled with TiN332 using PVD to obtain structure 400f shown in Figure 4f.

[0037] The process proceeds to step 612, where tungsten filler 334 is added using CVD to obtain structure 400g shown in Figure 4g. This process is completed in step 614, during which the tungsten filler is removed using CMP, and the process is stopped at silicon oxide layer 306 to obtain structure 500h shown in Figure 4h. Subsequently, subsequent operations not shown elsewhere are performed using known prior art to obtain transistor gate structure 300 shown in Figure 3.

[0038] In one embodiment, the silicon oxide layer has the chemical formula SiC8H 20The silicon oxide film is deposited using tetraethyl orthosilicate (TEOS) containing O4. In one embodiment, the silicon nitride layers 304 and 308 are deposited using low-pressure chemical vapor deposition (LPCVP).

[0039] Figure 7a shows a portion of the semiconductor structure 700, which shows two GAA TFT devices 701-1 and 701-2 having a first alternative configuration. The layer structure of the semiconductor substrate includes a silicon oxide layer 702, a silicon nitride layer 704, a polysilicon layer 706, a silicon oxide layer 708, a first word line 710, a second word line 714, and silicon oxide layers 712 and 716. The first word line 710 includes a “staircase structure 720” which includes a pattern of silicon nitride 722 formed on top of a pattern of IGZO 724.

[0040] As shown in the upper right portion of Figure 7a, the GAA TFT device 701 includes an upper W / TiN contact 703 formed on a pillar 705, which includes W728 and TiN730, and the pillar 705 has a straight wall including a gate oxide outer wall 732, an IGZO channel 734, and a silicon oxide core 736. A W / TiN word line contact 707, including W740 and TiN742, is formed below the pillar 705. In some embodiments, a TiN structure 738 including a selective bottom contact conductive liner may be positioned between the base of the IGZO channel 734 and the W / TiN word line contact 707.

[0041] Figure 7b is a cropped view of a portion of semiconductor device 700b, which includes one of the GAA TFT devices 701-1, 701-2, ..., 701-8. The semiconductor device 700b generally consists of a layered structure of semiconductor structure 700 shown in Figure 7a, in addition to layers and structures such as SiO2 layer 746 and word lines 748. The word lines 748 are made of polysilicon, and layers of silicon oxide are placed between the word lines 748. Additional layers below the word lines 748 include silicon oxide layers 750, 754, 760, polysilicon layers 752 and 756, and aluminum oxide layer 758. Figure 7b also shows further details of the stepped structure 720, which includes step-downs, for each of the GAA TFT devices 701-1, 701-2, ..., 701-8. Furthermore, the lower W / TiN contact portion of each GAA TFT device 701-1, 701-2, ..., 701-8 gradually increases in height to connect a given GAA TFT device 701 to its respective word line 748.

[0042] Figure 7c is the same as shown in Figure 7b, but with the addition of a plan view (top of the figure). Those skilled in the art will recognize that actual semiconductor devices (e.g., 3D NAND devices) have a set of GAA TFT devices 701 coupled to each word line 740 arranged in multiple layers. See, for example, Figure 11 below. This includes a material 762 (e.g., tungsten in the illustrated embodiment) coupled to a signal path formed in one or more layers on the layered structure shown in Figures 7b and 7c.

[0043] Figure 7d shows a portion of semiconductor structure 700d, including double-gate transistor devices 701d-1 and 701d-2, which have a pillar structure employing an amorphous IGZO core 734 with channels, instead of using a silicon oxide core as shown in Figure 7a. Similar to the double-gate structure 300d in Figure 3d, the width of the trenches etched before depositing the gate oxide 732 and IGZO filler is narrower than the width of the trenches used in double-gate structures employing liners and silicon oxide fillers.

[0044] Figure 8a shows semiconductor structure 800, and Figure 8b shows a cutaway view of a portion of semiconductor device 800b, which includes GAA TFT device 801, a first variation of GAA TFT device 701. As indicated by the same numbered layers and components, the structures of semiconductor structures 700 and 800 are generally similar, the only difference being the diameter of GAA TFT devices 701 and 801. As shown in the detail view of the lower right portion of Figure 8a, GAA TFT device 801 includes an upper W / TiN contact containing W728b and TiN730b formed on a pillar, the pillar having a straight wall containing a gate oxide outer wall 732b, an IGZO channel 734b, and a silicon oxide core 736b. Similar to GAA TFT device 701, the TiN structure 738 is located between the base of the IGZO channel 734 and the lower W / TiN contact containing W740 and TiN742.

[0045] Generally, the layers and structures within semiconductor devices 700b and 800b are similar, as indicated by the same reference numbers. The notable difference is that in semiconductor device 800b, GAA TFT devices 701 (701-1, 701-2, ..., 701-8) are replaced by GAA TFT devices 801 (801-1, 801-2, ..., 801-8).

[0046] Figure 9a shows semiconductor structure 900, and Figure 9b shows a cutaway view of a portion of semiconductor device 900b, which includes GAA TFT device 901, a second variation of GAA TFT device 701. Generally, most of these structures are similar, as indicated by the layers and structures having the same reference numbers in semiconductor structures 700 and 900. However, beneath semiconductor structure 900, the word line contacts 907 of GAA TFT devices 901 (901-1, 901-2, ..., 901-8) extend to contact their respective word lines, as shown by word lines 910 and 914 in Figure 9a. As shown in the detailed view of GAA TFT device 901, the structure of the upper W / TiN contact 703 and pillar 705 is the same as that of semiconductor structure 700 shown in Figures 7a and 7b above. The difference lies in the structure of the word line contact 907, which comprises a TiN shoulder 941 bonded to a pillar containing an SiO2 insulating liner 943 with a tungsten filler 945. As shown in Figure 9b, the word lines 948 are formed using each polysilicon layer separated by an SiO2 layer. The word line contacts 907 of the GAA TFT devices 901-1, 901-2, ..., 901-8 have different vertical lengths extending to each word line 948.

[0047] Figure 10 shows a semiconductor structure 1000 including a transistor device 1002 having a TiN bottom plug contact 1004. Generally, the layers and structure within the semiconductor substrate 1000 are similar to those shown for semiconductor structures 700 and 900, except for the TiN bottom plug contact shown in the alternative structure.

[0048] Various figures in this specification depict TiN on the lower contact; however, this is merely illustrative and not limiting. The use of TiN on the lower contact is optional, as in some embodiments (not shown separately) in which such a metal liner film is not employed.

[0049] Figure 11 shows a 3D diagram of an abstracted memory device 1100. The memory device includes a 3D array 1102 having a structure similar to the 3D array 222 shown in Figure 2 and discussed above. For brevity, the components of the 3D array 1102 are shown as bit lines 1104 coupled to pillar 1106, an SGD layer 1108, and word lines 1110, 1112, 1114, and 1116. The memory device 1100 further includes drain routing lines 1118, 1120, and 1122, a vertical word line driver gate 1124, drain pads 1126, 1128, and 1130, a vertical word line driver 1132, a word line contact 1134, and an SGD layer 1136. As will be recognized by those skilled in the art, similar components and structures are repeated many times in actual memory devices. Furthermore, the internal structure of a memory device based on the teachings and principles disclosed herein may have configurations similar to any of the embodiments described and illustrated herein, as well as modifications combining features of the illustrated embodiments.

[0050] The figures and diagrams shown herein have been simplified for illustrative purposes and ease of interpretation. Transistor structures are also not depicted to scale and represent a larger number of similar transistor structures in actual devices. As will be recognized by those skilled in the art, such devices typically employ a large number (e.g., hundreds) of word lines and large memory cell arrays within a 3D structure.

[0051] In the embodiments described above, the liner material represents some exemplary and non-limiting materials that may be used as a liner. More generally, the liner comprises a film that satisfies the following considerations: low hydrogen content, need to avoid H2O absorption during processing, thickness being important for stabilizing the device's Vt by fixed charges within the film, and providing hermetically sealed to prevent interaction between the IGZO and downstream steps.

[0052] While some embodiments have been described with reference to specific implementations, other implementations are possible according to some embodiments. Furthermore, the arrangement and / or order of elements or other features shown in the drawings and / or described herein does not necessarily have to be arranged in the specific manner illustrated and described. According to some embodiments, many other arrangements are possible.

[0053] In each system shown in the diagram, elements may, in some cases, have the same or different reference numbers to indicate that the represented elements may be different and / or similar. However, elements may have different implementations and may be flexible enough to work with some or all of the systems illustrated or described herein. The various elements shown in the diagram may be identical or different. It is arbitrary which elements are referred to as the first element and which as the second element.

[0054] In this specification and in the claims, the terms “combined” and “connected,” as well as their derivatives, may be used. It should be understood that these terms are not intended to be synonymous with each other. Rather, in certain embodiments, “connected” may be used to indicate that two or more elements are in direct physical or electrical contact with each other. “Combined” may mean that two or more elements are in direct physical or electrical contact. However, “combined” may also mean that two or more elements are not in direct contact with each other but still cooperate or interact with each other. Furthermore, “communicatively combined” means that two or more elements are able to communicate with each other, whether or not they are in direct contact with each other. For example, if component A is connected to component B, and component B is connected to component C, component A may be communicatively combined with component C using component B as an intermediate component.

[0055] Embodiments are implementations or examples of the present invention. References to “embodiments,” “one embodiment,” “several embodiments,” or “other embodiments” in this specification mean that certain features, structures, or characteristics described in relation to the embodiments are included in at least some embodiments of the present invention, but not necessarily in all embodiments. The various expressions “embodiments,” “one embodiment,” or “several embodiments” do not necessarily refer to the same embodiment.

[0056] All components, features, structures, properties, etc., described and illustrated herein are not necessarily limited to one or more specific embodiments. For example, where a component, feature, structure, or property is described herein as “may be included,” “may be included,” “may be included,” or “may be included,” that particular component, feature, structure, or property is not necessarily included. Where “one” or “one” element is referred to in the specification or claims, it does not mean that there is only one of that element. Where “additional” elements are referred to in the specification or claims, it does not preclude that there may be multiple additional elements.

[0057] As used herein, a list of items linked by the term “at least one” may mean any combination of the enumerated terms. For example, the phrase “one or more of A, B, or C” may mean A, B, C, A and B, A and C, B and C, or A, B and C.

[0058] The above description of illustrated embodiments of the Invention, including those described in the abstract, is not exhaustive and is not intended to limit the Invention to the exact form disclosed. Specific embodiments and examples of the Invention are described herein for illustrative purposes, but various equivalent modifications are possible within the scope of the Invention, as will be recognized by those skilled in the art.

[0059] These modifications may be made to the invention in light of the detailed description above. The terms used in the following claims should not be construed as limiting the invention to the specific embodiments disclosed herein and in the drawings. Rather, the scope of the invention is determined as a whole by the following claims, which should be construed in accordance with established principles of claim interpretation.

Claims

1. A vertical word line driver comprising a vertical transistor structure formed in a semiconductor substrate including a gate-all-around (GAA) structure or a double-gate structure, wherein the GAA structure or double-gate structure is An outer member or wall containing gate oxide, An amorphous IGZO (indium gallium zinc oxide) channel adjacent to the gate oxide, A liner adjacent to the amorphous IGZO channel, Dielectric filling material and A vertical word line driver, including...

2. The vertical word line driver according to claim 1, wherein the vertical transistor structure has a frustoconical shape.

3. The vertical word line driver according to claim 1 or 2, wherein the vertical transistor structure has a substantially cylindrical shape with straight side walls.

4. The vertical word line driver according to any one of claims 1 to 3, wherein the vertical transistor structure comprises a pair of walls arranged opposite to each other, each wall comprising an exterior of gate oxide, an intermediate portion of amorphous IGZO, and an interior of liner material, and the walls are angled or straight.

5. The vertical word line driver according to any one of claims 1 to 4, wherein the semiconductor substrate comprises a plurality of deposited layers including a polysilicon layer having a gate that contacts a portion of the gate oxide.

6. The vertical word line driver according to any one of claims 1 to 5, wherein the liner comprises aluminum oxide or hafnium oxide.

7. The vertical transistor structure is used as a word line driver in a three-dimensional (3D) NAND device, according to any one of claims 1 to 6.

8. A vertical word wire driver according to any one of claims 1 to 7, further comprising a metal contact positioned above the amorphous IGZO channel and electrically coupled thereto.

9. A vertical word line driver according to any one of claims 1 to 8, further comprising word line contacts disposed below the amorphous IGZO channel and electrically coupling the amorphous IGZO channel to each word line formed in the semiconductor substrate.

10. A vertical word wire driver according to any one of claims 1 to 9, further comprising a bottom plug contact containing a metal alloy disposed within the vertical structure.

11. A semiconductor substrate containing multiple layers, Multiple word lines formed within a multi-layered 3D stack, A plurality of vertical word line drivers, each of which comprises a vertical transistor structure formed in the semiconductor substrate including a gate-all-around (GAA) structure or a double-gate structure, and A three-dimensional (3D) memory device comprising, The aforementioned GAA structure or double gate structure is An outer member or wall containing gate oxide, An amorphous IGZO (indium gallium zinc oxide) channel adjacent to the gate oxide, A liner adjacent to the amorphous IGZO channel, Dielectric filling material, An upper contact electrically coupled to the amorphous IGZO channel, Each word line has an electrically coupled lower contact and A 3D memory device equipped with [the following features].

12. The 3D memory device according to claim 11, wherein the 3D memory device includes a 3D NAND memory device.

13. The 3D memory device according to claim 11 or 12, wherein the plurality of layers in the semiconductor substrate include a polysilicon layer that is in contact with the gate oxide and used as a gate.

14. The 3D memory device according to any one of claims 11 to 13, wherein the vertical transistor structure comprises a frustoconical or cylindrical pillar having straight side walls.

15. The vertical transistor structure comprises a pair of walls arranged opposite each other, each wall comprising an exterior of gate oxide, an intermediate portion of amorphous IGZO, and an interior of liner material, wherein the walls are angled or straight, the 3D memory device according to any one of claims 11 to 14.

16. A system comprising a host device including a storage controller operably coupled to one or more memory modules having at least one three-dimensional (3D) memory device, wherein the 3D memory device is A semiconductor substrate containing multiple layers, Multiple word lines formed within a multi-layered 3D stack, A plurality of vertical word line drivers, each of which comprises a vertical transistor structure formed in the semiconductor substrate including a gate-all-around (GAA) structure or a double-gate structure, and Equipped with, The aforementioned GAA structure or double gate structure is Gate oxide and, An amorphous IGZO (indium gallium zinc oxide) channel adjacent to the gate oxide, A liner adjacent to the amorphous IGZO channel, Dielectric filling material, An upper contact electrically coupled to the amorphous IGZO channel, Each word line has an electrically coupled lower contact and A system equipped with these features.

17. The system according to claim 16, wherein the host device comprises a system-on-chip (SoC) or system-on-package (SoP) including a processor operably coupled to the storage controller.

18. The system according to claim 16 or 17, wherein the at least one 3D memory includes a 3D NAND memory device.

19. The system according to any one of claims 16 to 18, wherein the vertical transistor structure comprises a frustoconical or cylindrical pillar having straight side walls.

20. The vertical transistor structure comprises a pair of walls positioned opposite each other, each wall comprising an exterior of gate oxide, an intermediate portion of amorphous IGZO, and an interior of liner material, wherein the walls are angled or straight, according to any one of claims 16 to 19.

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