Semiconductor structure and preparation method therefor

Abstract

A semiconductor structure and a preparation method therefor. The preparation method for a semiconductor structure comprises: providing an initial structure comprising dielectric layers (31) and conductive layers (32) which are stacked, the conductive layers comprising a plurality of conductive strips (320), a first hole (391) penetrating through the dielectric layers and the conductive strips in a first direction (D1), and each conductive strip being separated into two portions (321, 322) by the first hole; laterally thinning each conductive strip to form a first void (381); forming a first indium gallium zinc oxide (331) in the first void; laterally thinning each dielectric layer to expose a portion of the first indium gallium zinc oxide, and forming a second void (382); forming a second indium gallium zinc oxide (332) on the surface of the exposed portion of each first indium gallium zinc oxide, the concentration of indium in the first indium gallium zinc oxide being greater than the concentration of indium in the second indium gallium zinc oxide; and forming a gate structure (35) in the first hole and the second voids. By means of forming the first indium gallium zinc oxide having a higher concentration of indium between the second indium gallium zinc oxide and the conductive strips, contact resistance is reduced.

Description

Semiconductor structure and its preparation method

[0001] This application claims priority to Chinese Patent Application No. 202411449809.2, filed on October 16, 2024, entitled "Semiconductor Structure and Preparation Method Thereof", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to the field of semiconductors, and more particularly to a semiconductor structure and a method for preparing the same. Background Technology

[0003] In the manufacturing process of Dynamic Random Access Memory (DRAM), buried bit lines are commonly used. However, as semiconductor dimensions continue to shrink, existing fabrication processes are becoming increasingly inadequate. Currently, 3D DRAM based on indium gallium zinc oxide (IGZO) material is a key research focus in the industry due to the material's excellent leakage current resistance, low cost, and relatively simple manufacturing process.

[0004] However, the contact resistance between IGZO and the metal electrode is relatively high, which affects the performance of the device. Therefore, how to reduce the contact resistance between IGZO and the metal electrode and improve device performance is a problem that needs to be solved. Summary of the Invention

[0005] The technical problem to be solved by this disclosure is to reduce the contact resistance between IGZO and the metal electrode, improve device performance, and provide a semiconductor structure and its fabrication method.

[0006] To address the aforementioned problems, this disclosure provides a method for fabricating a semiconductor structure, comprising: providing an initial structure, the initial structure including a dielectric layer and a conductive layer stacked sequentially along a first direction, the conductive layer including a plurality of conductive strips extending along a second direction and spaced apart along a third direction, a first hole penetrating the dielectric layer and the conductive strips along the first direction, and the conductive strips being separated into two independent parts by the first hole in the second direction; laterally thinning the conductive strips along the second direction to form a first gap between two adjacent dielectric layers; forming a first indium gallium zinc oxide (IGaZO) within the first gap; laterally thinning the dielectric layer along the second direction to expose a portion of the IGaZO, and forming a second gap between two adjacent IGaZOs; forming a second IGaZO on the surface of the exposed IGaZO, wherein the concentration of indium in the first IGaZO is greater than the concentration of indium in the second IGaZO; and forming a gate structure within the first hole and the second gap.

[0007] In some embodiments, after the step of laterally thinning the dielectric layer along the second direction, the method further includes the step of plasma treating the exposed first indium gallium zinc oxide to form oxygen vacancies within the first indium gallium zinc oxide.

[0008] In some embodiments, during plasma treatment of the exposed first indium gallium zinc oxide, the plasma concentration decreases over time.

[0009] In some embodiments, in the step of laterally thinning the dielectric layer along the second direction, the dielectric layer is thinned laterally along the second direction multiple times to partially expose the first indium gallium zinc oxide; after each lateral thinning of the dielectric layer along the second direction, the exposed first indium gallium zinc oxide is processed to form oxygen holes in the first indium gallium zinc oxide.

[0010] In some embodiments, in the step of processing the exposed first indium gallium zinc oxide after each lateral thinning of the dielectric layer along the second direction, the exposed first indium gallium zinc oxide is subjected to plasma treatment after each lateral thinning of the dielectric layer, and the plasma concentration decreases with the increase of the number of lateral thinnings of the dielectric layer, so as to form an oxygen hole concentration gradient in the first indium gallium zinc oxide.

[0011] In some embodiments, after plasma treatment of the first indium gallium zinc oxide, the process further includes annealing the first indium gallium zinc oxide.

[0012] In some embodiments, the molar ratio of indium gallium zinc in the first indium gallium zinc oxide is (9-10):1:1.

[0013] To address the aforementioned problems, this disclosure also provides a semiconductor structure, comprising: an initial structure including a dielectric layer and a conductive layer stacked sequentially along a first direction; the conductive layer including a plurality of conductive strips extending along a second direction and spaced apart along a third direction; in the second direction, the conductive strips are divided into independent first portions and second portions, and the opposite ends of the first portions and second portions are recessed in the dielectric layer; a first indium gallium zinc oxide, respectively disposed at the opposite ends of the first portions and second portions of the conductive strips, and the ends of the first indium gallium zinc oxide protruding from the dielectric layer; a second indium gallium zinc oxide, covering the surface of the region of the first indium gallium zinc oxide protruding from the dielectric layer, and the indium concentration in the first indium gallium zinc oxide is greater than the indium concentration in the second indium gallium zinc oxide; and a gate structure covering the second indium gallium zinc oxide.

[0014] In some embodiments, the oxygen hole concentration at the end of the first indium gallium zinc oxide closer to the second indium gallium zinc oxide is greater than the oxygen hole concentration at the end farther away from the second indium gallium zinc oxide.

[0015] In some embodiments, the oxygen hole concentration in the first indium gallium zinc oxide exhibits a gradient decrease.

[0016] In some embodiments, the molar ratio of indium gallium zinc in the first indium gallium zinc oxide is (9-10):1:1.

[0017] In some embodiments, the gate structure, the second indium gallium zinc oxide, the first indium gallium zinc oxide, and the conductive strip constitute a transistor, with the first portion of the conductive strip serving as the source region of the transistor and the second portion of the conductive strip serving as the drain region of the transistor.

[0018] In some embodiments, the gate structure further includes a gate and a gate dielectric layer, wherein the gate dielectric layer is disposed at least between the gate and the second indium gallium zinc oxide.

[0019] The aforementioned semiconductor structure fabrication method reduces the contact resistance between the second indium gallium zinc oxide (IGZO) and the conductive strip by forming a first IGZO with a high indium concentration between the second IGZO and the conductive strip. Furthermore, since the first IGZO and the second IGZO are made of the same material, no interface is formed between them, which further helps to reduce the contact resistance between the second IGZO and the conductive strip. Additionally, an oxygen hole concentration gradient is formed within the first IGZO, which can prevent transistor leakage and reduce device power consumption. Moreover, annealing the first IGZO can improve surface damage and enhance its electrical properties, such as conductivity, carrier concentration, and mobility.

[0020] The aforementioned semiconductor structure reduces the contact resistance between the second indium gallium zinc oxide (IGZO) and the conductive strip by placing a first IGZO with a high indium concentration between the second IGZO and the conductive strip. Furthermore, since the first IGZO and the second IGZO are made of the same material, no interface is formed between them, which further helps to reduce the contact resistance between the second IGZO and the conductive strip.

[0021] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Techniques, methods, and apparatus known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and apparatus should be considered part of the specification. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the specific embodiments of this disclosure, the accompanying drawings used in the description of the specific embodiments will be briefly introduced below. Obviously, the drawings described below are only some specific embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0023] Figure 1 is a schematic diagram of the structure of a semiconductor in the prior art.

[0024] Figure 2 is a flowchart of the steps of an embodiment of the semiconductor structure fabrication method disclosed herein.

[0025] Figures 3A to 3H are process flow diagrams of an embodiment of the semiconductor structure fabrication method disclosed herein.

[0026] Figures 4A to 4D are process flow diagrams of another embodiment of the semiconductor structure fabrication method disclosed herein. Detailed Implementation

[0027] The technical solutions in the embodiments of this disclosure will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0028] Please refer to Figure 1, which is a schematic diagram of a semiconductor structure in the prior art. As shown in Figure 1, the semiconductor structure includes: a silicon dioxide layer 11, a metal electrode 12, a ring channel 13, a gate dielectric layer 14, and a gate 15. Multiple layers of silicon dioxide 11 are stacked sequentially, and the metal electrode 12 is located inside the stacked silicon dioxide layers 11. The metal electrode 12 is divided into two parts, located on both sides of the ring channel 13, with the ring channel 13 located on the surface of the portion of the metal electrode 12 protruding from the silicon dioxide layer 11. The gate dielectric layer 14 and the gate 15 are located within the silicon dioxide layer 11 and between the two parts of the metal electrode 12, and are located on the surface of the ring channel 13. The metal electrode 12 of the semiconductor structure is made of tungsten, and the ring channel 13 is made of indium gallium zinc oxide. The contact resistance between tungsten and indium gallium zinc oxide is relatively high, which significantly affects device performance.

[0029] To address the aforementioned problems, this disclosure provides a method for fabricating a semiconductor structure. Please refer to Figure 2 and Figures 3A-3H, where Figure 2 is a flowchart illustrating the steps of one embodiment of the semiconductor structure fabrication method of this disclosure; Figures 3A-3H are process flow diagrams illustrating one embodiment of the semiconductor structure fabrication method of this disclosure. As shown in Figure 2, the method for fabricating a semiconductor structure includes: Step S21, providing an initial structure, the initial structure including a dielectric layer and a conductive layer stacked sequentially along a first direction, the conductive layer including multiple conductive strips extending along a second direction and spaced apart along a third direction, a first hole penetrating the dielectric layer and the conductive strips along the first direction, and the conductive strips being separated into two independent parts by the first hole in the second direction; Step S22, laterally thinning the conductive strips along the second direction to form a first gap between two adjacent dielectric layers; Step S23, forming a first indium gallium zinc oxide in the first gap; Step S24, laterally thinning the dielectric layer along the second direction to expose a portion of the first indium gallium zinc oxide, and forming a second gap between two adjacent first indium gallium zinc oxides; Step S25, forming a second indium gallium zinc oxide on the surface of the exposed first indium gallium zinc oxide, and the concentration of indium in the first indium gallium zinc oxide is greater than the concentration of indium in the second indium gallium zinc oxide; Step S26, forming a gate structure in the first hole and the second gap.

[0030] Referring to Figure 3A and step S21, an initial structure is provided. The initial structure includes a dielectric layer 31 and a conductive layer 32 stacked sequentially along a first direction D1. The conductive layer 32 includes multiple conductive strips 320 extending along a second direction D2 and spaced apart along a third direction D3. A first hole 391 penetrates the dielectric layer 31 and the conductive strips 320 along the first direction D1, and the conductive strips 320 are divided into two independent parts by the first hole 391 in the second direction D2. As shown, the two independent conductive strip parts are a first part 321 and a second part 322. In some embodiments, the dielectric layer 31 is made of silicon oxide, and the conductive strips 320 are made of a metal, such as tungsten.

[0031] The first direction D1 is perpendicular to the initial structure surface, and the second direction D2 and the third direction D3 are parallel to the initial structure surface. The second direction D2 is perpendicular to the third direction D3. In this embodiment, the first direction D1 is the Z direction in the Cartesian coordinate system, the second direction D2 is the X direction in the Cartesian coordinate system, and the third direction is the Y direction in the Cartesian coordinate system as an example for explanation.

[0032] Referring to Figure 3B and step S22, the conductive strip 320 is laterally thinned along the second direction D2 to form a first gap 381 between two adjacent dielectric layers 31. In some embodiments, the conductive strip 320 is laterally thinned along the second direction D2 on the sidewall of the first hole 391 by an etching process, and the portion of the conductive strip 320 exposed on the sidewall of the first hole 391 is removed to form the first gap 381.

[0033] Referring to Figure 3D and step S23, a first indium gallium zinc oxide 331 is formed within the first gap 381. In some embodiments, the step of forming the first indium gallium zinc oxide 331 within the first gap 381 further includes the following steps:

[0034] As shown in Figure 3C, a first indium gallium zinc oxide (IGaZO) material layer 371 is deposited within the first aperture 391 and the first void 381 (illustrated in Figure 3B). In some embodiments, the molar ratio of indium, gallium, and zinc in the first IGaZO material layer 371 is (9-10):1:1, forming a material layer with a high indium-gallium ratio. In this embodiment, the first IGaZO layer 371 can be deposited within the first aperture 391 and the first void 381 using atomic layer deposition (ALD), and the ratio of indium to gallium can be controlled by the gas flow rate of the precursor.

[0035] As shown in Figure 3D, the first indium gallium zinc oxide material layer 371 in the first hole 391 is removed, and the first indium gallium zinc oxide material layer 371 in the first void 381 (shown in Figure 3B) is retained as the first indium gallium zinc oxide 331. In this embodiment, dry etching is used to remove the first indium gallium zinc oxide material layer 371 in the first hole 391.

[0036] After completing the above steps, the first indium gallium zinc oxide 331 located in the first gap 381 (shown in Figure 3B) can be obtained.

[0037] In some embodiments, the molar ratio of indium gallium zinc oxide 331 to zinc indium is (9-10):1:1, that is, the first indium gallium zinc oxide 331 has a high indium structure.

[0038] Referring to Figure 3E and step S24, the dielectric layer 31 is laterally thinned along the second direction D2 to expose a portion of the first indium gallium zinc oxide 331, and a second gap 382 is formed between two adjacent first indium gallium zinc oxide 331. In some embodiments, the dielectric layer 31 can be laterally thinned along the second direction D2 by an etching process on the sidewall of the first hole 391, and the area of ​​the dielectric layer 31 that is removed constitutes the second gap 382.

[0039] As shown in Figure 3F, in some embodiments, after the step of laterally thinning the dielectric layer 31 along the second direction D2, the following step is further included: plasma processing the exposed first indium gallium zinc oxide 331 to form oxygen holes 34 within the first indium gallium zinc oxide 331. Forming oxygen holes 34 within the first indium gallium zinc oxide 331 can prevent leakage current in the semiconductor structure and reduce device power consumption.

[0040] In some embodiments, plasma includes, but is not limited to, methods for increasing oxygen hole concentration such as hydrogen ion plasma treatment, indium ion doping, and argon ion plasma treatment. In this embodiment, the first indium gallium zinc oxide 331 is subjected to plasma treatment using a hydrogen ion plasma treatment process. Hydrogen ions bombard the metal-oxygen bonds, causing them to break, thereby forming oxygen holes within the first indium gallium zinc oxide.

[0041] In this embodiment, during the plasma treatment of the exposed first indium gallium zinc oxide 331, the plasma concentration decreases with the treatment time. This decrease in plasma concentration over time also creates an oxygen hole concentration gradient within the first indium gallium zinc oxide 331, preventing transistor leakage and reducing device power consumption.

[0042] The plasma treatment of the first indium gallium zinc oxide 331 also includes annealing the first indium gallium zinc oxide 331. The annealing process can improve the damage to the first indium gallium zinc oxide 331 caused by plasma treatment and improve its electrical properties, such as conductivity, carrier concentration and mobility.

[0043] In the above embodiments, after thinning the dielectric layer 31 along the second direction, the first indium gallium zinc oxide 331 is subjected to plasma treatment. In other embodiments, during the step of thinning the dielectric layer 31 laterally along the second direction D2, the dielectric layer 31 can be thinned multiple times along the second direction D2, partially exposing the first indium gallium zinc oxide 331. After each thinning of the dielectric layer 31 laterally along the second direction D2, the exposed first indium gallium zinc oxide 331 is treated to form oxygen holes 34 within the first indium gallium zinc oxide 331. Forming oxygen holes 34 within the first indium gallium zinc oxide 331 can prevent transistor leakage and reduce device power consumption. Please refer to Figures 4A to 4D, which are process flow diagrams of another embodiment of plasma treatment of the first indium gallium zinc oxide 331.

[0044] Please refer to the embodiments shown in Figures 4A to 4D:

[0045] As shown in Figure 4A, the dielectric layer 31 is thinned laterally along the second direction D2 to expose the first indium gallium zinc oxide 331. For example, the dielectric layer 31 is thinned laterally along the second direction D2 by an etching process.

[0046] As shown in Figure 4B, the exposed first indium gallium zinc oxide 331 is subjected to plasma treatment to form oxygen holes 34 within the first indium gallium zinc oxide 331. In some embodiments, plasma treatment includes, but is not limited to, methods for increasing the oxygen hole concentration such as hydrogen ion plasma treatment, indium ion doping, and argon ion plasma treatment. In this embodiment, the first indium gallium zinc oxide 331 is plasma treated using a hydrogen ion plasma treatment process.

[0047] As shown in Figure 4C, the dielectric layer 31 is further thinned along the second direction D2 to expose the first indium gallium zinc oxide 331 to the target position, and a second gap 382 is formed between two adjacent first indium gallium zinc oxide 331.

[0048] As shown in Figure 4D, the exposed first indium gallium zinc oxide 331 is subjected to plasma treatment to form oxygen holes 34 within the first indium gallium zinc oxide 331. In some embodiments, plasma treatment includes, but is not limited to, methods for increasing the oxygen hole concentration such as hydrogen ion plasma treatment, indium ion doping, and argon ion plasma treatment. In this embodiment, the first indium gallium zinc oxide 331 is plasma treated using a hydrogen ion plasma treatment process.

[0049] In this step, plasma treatment is performed on all exposed areas of the first indium gallium zinc oxide 331. In areas that have previously undergone plasma treatment, the oxygen hole concentration is superimposed. In the area that undergoes plasma treatment for the first time in this step, the oxygen hole concentration is the same as the oxygen hole concentration formed by the current plasma treatment, thereby creating an oxygen hole concentration gradient in the exposed areas of the first indium gallium zinc oxide 331.

[0050] In some embodiments, in the step of processing the exposed first indium gallium zinc oxide 331 after each lateral thinning of the dielectric layer 31, the exposed first indium gallium zinc oxide 331 is subjected to plasma treatment after each lateral thinning of the dielectric layer 31, and the plasma concentration decreases with the increase of the number of lateral thinnings of the dielectric layer 31, so as to further form an oxygen hole concentration gradient in the first indium gallium zinc oxide 331. Forming an oxygen hole concentration gradient in the first indium gallium zinc oxide 331 can further improve conductivity and reduce contact resistance.

[0051] In the embodiment where the dielectric layer 31 is thinned in stages, and the exposed first indium gallium zinc oxide 331 is subjected to plasma treatment after each lateral thinning of the dielectric layer 31 along the second direction D2, an annealing process is performed uniformly after all thinning and plasma treatment steps are completed. The annealing process can improve the damage to the first indium gallium zinc oxide 331 caused by plasma treatment and improve its electrical properties, such as conductivity, carrier concentration, and mobility.

[0052] The above embodiments only schematically illustrate the process of laterally thinning the dielectric layer 31 twice and performing two plasma treatments. In other embodiments, the dielectric layer 31 may be laterally thinned multiple times and multiple plasma treatments may be performed, for example, three or more times.

[0053] Referring to Figures 2 and 3G, and step S25, a second indium gallium zinc oxide (IGZO) 332 is formed on the exposed surface of the first IGZO 331, wherein the indium concentration in the first IGZO 331 is greater than the indium concentration in the second IGZO 332. The second IGZO 332 covers the exposed surface of the first IGZO 331 and is electrically connected to the conductive strip 320 through the first IGZO 331. The semiconductor structure of this disclosure reduces the contact resistance between the second IGZO 332 and the conductive strip 320 by forming a first IGZO 331 with a higher indium concentration between the second IGZO 332 and the conductive strip 320. In some embodiments, the second IGZO 332 may be deposited using an atomic layer deposition process.

[0054] In this step, the second indium gallium zinc oxide 332 only covers the exposed surface of the first indium gallium zinc oxide 331, the surface of the dielectric layer 31 is not covered by the second indium gallium zinc oxide 332, and the second void 382 is not filled by the second indium gallium zinc oxide 332.

[0055] Furthermore, in the embodiment where the dielectric layer 31 is thinned laterally multiple times and two plasma treatments are performed, the second indium gallium zinc oxide 332 formed in step S25 is the same as in this embodiment.

[0056] Referring to Figures 1 and 3H, and step S26, a gate structure 35 is formed within the first aperture 391 and the second void 382. Methods for forming the gate structure 35 include, but are not limited to, thermal oxidation, chemical vapor deposition, plasma chemical vapor deposition, and atomic layer deposition. The gate structure 35 further includes a gate 351 and a gate dielectric layer 352, with the gate dielectric layer 352 at least disposed between the gate 351 and the second indium gallium zinc oxide 332 to insulate the gate 351 from the second indium gallium zinc oxide 332.

[0057] Furthermore, in the embodiments involving multiple lateral thinning of the dielectric layer 31 and two plasma treatments (i.e., the embodiments shown in Figures 4A to 4D), the gate structure 35 formed in step S26 is the same as in this embodiment. The above technical solution reduces the contact resistance between the second indium gallium zinc oxide and the conductive strip by forming a first indium gallium zinc oxide with a high indium concentration between the second indium gallium zinc oxide and the conductive strip. Furthermore, since the first and second indium gallium zinc oxides are made of the same material, no interface is formed between them, which further helps to reduce contact resistance. Additionally, an oxygen hole concentration gradient is formed within the first indium gallium zinc oxide, which can prevent transistor leakage and reduce device power consumption. Moreover, annealing the first indium gallium zinc oxide can improve surface damage and enhance its electrical properties, such as conductivity, carrier concentration, and mobility.

[0058] Based on the same inventive concept, an embodiment of this disclosure also provides a semiconductor structure.

[0059] Please refer to Figure 3H, which is a schematic diagram of an embodiment of the semiconductor structure disclosed herein. As shown in Figure 3H, the semiconductor structure includes: an initial structure, a first indium gallium zinc oxide (IGZO) 331, a second IGZO 332, and a gate structure 35. The initial structure includes a dielectric layer 31 and a conductive layer 32 stacked sequentially along a first direction D1. The conductive layer 32 includes multiple conductive strips 320 extending along a second direction D2 and spaced apart along a third direction D3. In the second direction D2, the conductive strips 320 are divided into independent first portions 321 and second portions 322, and the opposite ends of the first portions 321 and second portions 322 are recessed into the dielectric layer 31. The first IGZO 331 is respectively disposed at the opposite ends of the first portions 321 and second portions 322 of the conductive strips 320, and the ends of the first IGZO 331 protrude from the dielectric layer 31. The second indium gallium zinc oxide 332 covers the surface of the region of the first indium gallium zinc oxide 331 that protrudes from the dielectric layer 31, and the indium concentration in the first indium gallium zinc oxide 331 is greater than the indium concentration in the second indium gallium zinc oxide 332. The gate structure 15 covers the second indium gallium zinc oxide 332.

[0060] The above technical solution reduces the contact resistance between the second indium gallium zinc oxide (IGZO) and the conductive strip by placing a first IGZO with a high indium concentration between the second IGZO and the conductive strip. Furthermore, since the first IGZO and the second IGZO are made of the same material, no interface is formed between them, which further helps to reduce the contact resistance between the second IGZO and the conductive strip.

[0061] The gate structure, the second indium gallium zinc oxide 332, the first indium gallium zinc oxide 331, and the conductive strip constitute a transistor. The first part of the conductive strip can serve as the source region of the transistor, and the second part of the conductive strip can serve as the drain region of the transistor.

[0062] In some embodiments, the molar ratio of indium gallium zinc oxide 331 to zinc gallium is (9-10):1:1. The high indium gallium ratio in the first indium gallium zinc oxide 331 can reduce the contact resistance between the second indium gallium zinc oxide 332 and the conductive strip.

[0063] In some embodiments, oxygen holes 34 are formed within the first indium gallium zinc oxide (IZO) 331 to prevent transistor leakage and reduce device power consumption. Unlike the embodiment shown in FIG3H, in the embodiment shown in FIG4D, the oxygen hole concentration 34 at the end of the first IZO 331 closer to the second IZO 332 is greater than the oxygen hole concentration at the side farther from the second IZO 332. Furthermore, in the embodiment shown in FIG4D, the oxygen hole concentration 34 in the first IZO 331 decreases in a gradient. Forming an oxygen hole concentration gradient in the first IZO 331 further improves conductivity and reduces the contact resistance between the second IZO and the conductive strip.

[0064] It should be noted that references to "an embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," etc., in the specification indicate that the described embodiments may include specific features, structures, or characteristics, but each embodiment may not necessarily include that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. In addition, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other embodiments is within the knowledge of those skilled in the art.

[0065] Generally, terms can be understood at least partially from their usage in context. For example, the term "one or more," as used herein, depends at least partially on the context and can be used to describe any feature, structure, or characteristic in a singular sense, or in a plural sense, to describe a combination of features, structures, or characteristics. Similarly, terms such as "a," "a," or "the" can also be understood, at least partially on the context, to express either a singular or plural usage. Furthermore, the term "based on" can be understood not necessarily to express an exclusive set of factors, but rather, alternatively, also at least partially on the context, to allow for the presence of other factors that are not necessarily explicitly described. It should also be noted in this specification that "connection / coupling" refers not only to a direct coupling of one component to another, but also to an indirect coupling of one component to another via an intermediate component.

[0066] It should be noted that the terms "comprising" and "having," and their variations, used in this disclosure are intended to cover non-exclusive inclusion. The terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence, unless explicitly indicated by the context. It should be understood that such data used interchangeably where appropriate. Furthermore, embodiments and features within embodiments of this disclosure can be combined with each other unless otherwise specified. In addition, descriptions of well-known components and technologies have been omitted in the above description to avoid unnecessarily obscuring the concepts of this disclosure. In the various embodiments described above, each embodiment focuses on its differences from other embodiments; similar or identical parts between embodiments can be referred to mutually.

[0067] The above are merely preferred embodiments of this disclosure. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of this disclosure, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

1. A method of fabricating a semiconductor structure, characterized by, include: An initial structure is provided, the initial structure comprising a dielectric layer (31) and a conductive layer (32) stacked sequentially along a first direction (D1), the conductive layer comprising a plurality of conductive strips (320) extending along a second direction (D2) and spaced apart along a third direction (D3), a first hole (391) penetrating the dielectric layer and the conductive strips along the first direction, and the conductive strips being divided into two independent parts by the first hole in the second direction; The conductive strip is laterally thinned along the second direction to form a first gap (381) between two adjacent dielectric layers; A first indium gallium zinc oxide (331) is formed within the first void; The dielectric layer is laterally thinned along the second direction to expose a portion of the first indium gallium zinc oxide and a second void (382) is formed between two adjacent first indium gallium zinc oxide layers. A second indium gallium zinc oxide (332) is formed on the exposed surface of the first indium gallium zinc oxide, and the concentration of indium in the first indium gallium zinc oxide is greater than the concentration of indium in the second indium gallium zinc oxide; A gate structure (35) is formed within the first hole and the second gap.

2. The method of claim 1, wherein, Following the step of laterally thinning the dielectric layer along the second direction, the method further includes the following step: subjecting the exposed first indium gallium zinc oxide to plasma treatment to form oxygen holes (34) within the first indium gallium zinc oxide.

3. The method of claim 2, wherein, During the plasma treatment of the exposed first indium gallium zinc oxide, the plasma concentration decreases with the treatment time.

4. The method of claim 1, wherein, In the step of laterally thinning the dielectric layer along the second direction, the dielectric layer is thinned laterally along the second direction multiple times, partially exposing the first indium gallium zinc oxide; After each lateral thinning of the dielectric layer along the second direction, the exposed first indium gallium zinc oxide is treated to form oxygen vacancies within the first indium gallium zinc oxide.

5. The method of claim 4, wherein, In the step of processing the exposed first indium gallium zinc oxide after each lateral thinning of the dielectric layer along the second direction, the exposed first indium gallium zinc oxide is subjected to plasma treatment after each lateral thinning of the dielectric layer, and the plasma concentration decreases with the increase of the number of lateral thinnings of the dielectric layer, so as to form an oxygen hole concentration gradient in the first indium gallium zinc oxide.

6. The method of claim 2, 3, or 5, wherein, The process of plasma treatment of the first indium gallium zinc oxide further includes annealing the first indium gallium zinc oxide.

7. The method of claim 1, wherein, The molar ratio of indium gallium zinc in the first indium gallium zinc oxide is (9-10):1:

1.

8. A semiconductor structure, characterized by include: An initial structure comprising a dielectric layer (31) and a conductive layer (32) stacked sequentially along a first direction (D1), wherein the conductive layer comprises a plurality of conductive strips (320) extending along a second direction (D2) and spaced apart along a third direction (D3), wherein in the second direction the conductive strips are divided into a first part (321) and a second part (322) that are independent of each other, and the opposite ends of the first part and the second part are recessed in the dielectric layer; The first indium gallium zinc oxide (331) is disposed at the opposite ends of the first part and the second part of the conductive strip, and the ends of the first indium gallium zinc oxide protrude from the dielectric layer. The second indium gallium zinc oxide (332) covers the surface of the region of the first indium gallium zinc oxide that protrudes from the dielectric layer, and the concentration of indium in the first indium gallium zinc oxide is greater than the concentration of indium in the second indium gallium zinc oxide. The gate structure (15) covers the second indium gallium zinc oxide.

9. The semiconductor structure of claim 8, wherein, The oxygen hole concentration at the end of the first indium gallium zinc oxide closer to the second indium gallium zinc oxide is greater than the oxygen hole concentration at the end farther away from the second indium gallium zinc oxide.

10. The semiconductor structure of claim 9, wherein, The oxygen hole concentration in the first indium gallium zinc oxide exhibits a gradient decrease.

11. The semiconductor structure according to any of claims 8-10, characterized in that, The molar ratio of indium gallium zinc in the first indium gallium zinc oxide is (9-10):1:

1.

12. The semiconductor structure of any of claims 8-10, wherein, The gate structure, the second indium gallium zinc oxide, the first indium gallium zinc oxide, and the conductive strip constitute a transistor. The first part of the conductive strip serves as the source region of the transistor, and the second part of the conductive strip serves as the drain region of the transistor.

13. The semiconductor structure of claim 12, wherein, The gate structure further includes a gate (351) and a gate dielectric layer (352), wherein the gate dielectric layer is disposed at least between the gate and the second indium gallium zinc oxide.

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