Analog memory-based computing engine and digital memory-based computing engine for performing calculations in neural networks

Abstract

In one example disclosed herein, the system comprises an analog memory-based computation engine for performing operations in a first layer of a neural network, and a digital memory-based computation engine for performing operations in a second layer of the neural network distinct from the first layer. The system optionally comprises a dynamic weight engine for performing operations in a third layer of the neural network distinct from the first and second layers.

Description

[Technical Field]

[0001] (Claiming priority) This application claims priority to U.S. Patent Provisional Application No. 63 / 458,439, filed on April 10, 2023, entitled “Neural Network Comprising Analog Computation-in-Memory Engine and Digital Computation-in-Memory Engine,” and U.S. Patent Application No. 18 / 218,368, filed on July 5, 2023, entitled “Analog Computation-In-Memory Engine And Digital Computation-In-Memory Engine to Perform Operations in a Neural Network.”

[0002] (Field of Invention) Numerous examples of systems comprising one or more analog computation-in-memory engines and one or more digital computation-in-memory engines for performing neural network operations are disclosed. [Background technology]

[0003] Artificial neural networks mimic biological neural networks (such as the central nervous system of animals, particularly the brain), can depend on a large number of inputs, and are generally used to estimate or approximate unknown functions. Artificial neural networks typically consist of layers of interconnected "neurons" that exchange messages with one another.

[0004] Figure 1 shows an artificial neural network, where circles represent the inputs or layers of neurons. Connections (called synapses) are represented by arrows and have numerical weights that can be tuned based on experience. This allows the neural network to adapt to inputs and learn. Typically, a neural network contains multiple input layers. Typically, there are one or more hidden layers of neurons and output layers of neurons that provide the output of the neural network. Neurons at each level make decisions individually or collectively based on the data they receive from synapses.

[0005] One of the major challenges in developing artificial neural networks for high-performance information processing is the lack of suitable hardware technology. In practice, practical neural networks rely on a very large number of synapses, which enables high connectivity between neurons and thus very high levels of parallel processing. In principle, such complexity can be achieved using digital supercomputers or graphics processing unit clusters. However, in addition to their high cost, these approaches also suffer from poor energy efficiency compared to biological networks, which consume far less energy because they primarily perform low-precision analog calculations. While CMOS analog circuits have been used in artificial neural networks, the synapses in most CMOS implementations are too large considering the large number of neurons and synapses.

[0006] The applicant previously disclosed, in U.S. Patent Application Publication No. 2017 / 0337466(A1), incorporated by reference, an artificial (analog) neural network utilizing one or more non-volatile memory arrays as synapses. The non-volatile memory arrays operate as analog neural memory and comprise non-volatile memory cells arranged in rows and columns. The neural network device includes a first plurality of synapses configured to receive a first plurality of inputs and therefrom produce a first plurality of outputs, and a first plurality of neurons configured to receive the first plurality of outputs. The first plurality of synapses comprises a plurality of memory cells, each of which comprises a separated source region and a drain region formed in a semiconductor substrate, with a channel region extending between them, a floating gate disposed above a first portion of the channel region and isolated therefrom, and a non-floating gate disposed above a second portion of the channel region and isolated therefrom. Each of the plurality of memory cells stores weight values ​​corresponding to the number of electrons on the floating gate. The plurality of memory cells generate a first plurality of outputs by multiplying the first plurality of inputs by the stored weight values.

[0007] <Non-volatile skin cell> Non-volatile memories are well known. For example, U.S. Patent No. 5,029,130 (the “’130 Patent”), which is incorporated herein by reference, discloses an array of split gate non-volatile memory cells, which are a type of flash memory cell. Such a memory cell 210 is shown in FIG. 2. Each memory cell 210 includes a source region 14 and a drain region 16 formed in a semiconductor substrate 12, and there is a channel region 18 between the source region 14 and the drain region 16. The floating gate 20 is formed above a first portion of the channel region 18 and is insulated therefrom (and controls its conductivity), and is formed above a portion of the source region 14 and is insulated therefrom. The word line terminal 22 (typically coupled to a word line) has a first portion disposed above a second portion of the channel region 18 and insulated therefrom (and controls its conductivity), and a second portion that extends to and above the floating gate 20. The floating gate 20 and the word line terminal 22 are insulated from the substrate 12 by a gate oxide. The bit line 24 is coupled to the drain region 16.

[0008] By applying a positive high voltage to the word line terminal 22, the memory cell 210 is erased (electrons are removed from the floating gate), whereby electrons on the floating gate 20 pass through the intermediate insulator from the floating gate 20 to the word line terminal 22 via Fowler-Nordheim (FN) tunneling.

[0009] The memory cell 210 is programmed (electrons are added to the floating gate) by source side injection (SSI) with hot electrons by applying a positive voltage to the word line terminal 22 and a positive voltage to the source region 14. The electron flow is from the drain region 16 toward the source region 14. The electrons are accelerated and heat up when they reach the gap between the word line terminal 22 and the floating gate 20. A portion of the heated electrons is injected into the floating gate 20 through the gate oxide due to the electrostatic attraction from the floating gate 20.

[0010] The memory cell 210 is read by applying a positive read voltage to the drain region 16 and the word line terminal 22 (turning on the portion of the channel region 18 below the word line terminal). When the floating gate 20 is positively charged (i.e., electrons are erased), the portion of the channel region 18 below the floating gate 20 is similarly turned on, and current flows through the channel region 18, which is detected as the erased state, i.e., the "1" state. When the floating gate 20 is negatively charged (i.e., programmed with electrons), the portion of the channel region below the floating gate 20 becomes almost or completely off, and current does not flow (or hardly flows) through the channel region 18, which is detected as the programmed state, i.e., the "0" state.

[0011] Table 1 shows the typical voltage and current ranges that can be applied to the terminals of the memory cell 210 to perform read, erase, and program operations. Table 1: Operation of the flash memory cell 210 in FIG. 2

[0012]

Table 1

[0013] Other types of flash memory cells, other split-gate memory cell configurations, are known. For example, Figure 3 shows a four-gate memory cell 310 comprising a source region 14, a drain region 16, a floating gate 20 above a first portion of the channel region 18, a selection gate 22 (typically coupled to a word line WL) above a second portion of the channel region 18, a control gate 28 above the floating gate 20, and an erase gate 30 above the source region 14. This configuration is described in U.S. Patent No. 6,747,310, which is incorporated herein by reference for all purposes. Here, all gates except the floating gate 20 are non-floating gates, meaning they are electrically connected to or can be connected to a voltage source. Programming is performed by heated electrons injecting themselves from the channel region 18 into the floating gate 20. Erasing is performed by electrons tunneling from the floating gate 20 to the erase gate 30.

[0014] Table 2 shows typical voltage and current ranges that may be applied to the terminals of the memory cell 310 to perform read, erase, and program operations. Table 2: Operation of the flash memory cell 310 in Figure 3

[0015] [Table 2]

[0016] Figure 4 shows a different type of flash memory cell, a 3-gate memory cell 410. Memory cell 410 is identical to memory cell 310 in Figure 3, except that memory cell 410 does not have a separate control gate. The erase operation (where erasure occurs through the use of the erase gate) and read operation are the same as those in Figure 3, except that no control gate bias is applied. The programming operation is also performed without a control gate bias; therefore, during the programming operation, a higher voltage is applied to the source line to compensate for the lack of control gate bias.

[0017] Table 3 shows typical voltage and current ranges that may be applied to the terminals of the memory cell 410 to perform read, erase, and program operations. Table 3: Operation of flash memory cell 410 in Figure 4

[0018] [Table 3]

[0019] Figure 5 shows another type of flash memory cell, a stacked gate memory cell 510. Memory cell 510 is similar to memory cell 210 in Figure 2, except that a floating gate 20 extends above the entire channel region 18, and a control gate 22 (coupled here to a word line) extends above the floating gate 20, separated by an insulating layer (not shown). Erasing is performed by FN tunneling of electrons from the FG to the substrate, programming is performed by channel hot electron (CHE) injection in the region between the channel 18 and the drain region 16, with electrons flowing from the source region 14 to the drain region 16, and read operations are performed similarly to the read operations of memory cell 210, which has a higher control gate voltage.

[0020] Table 4 shows typical voltage ranges that can be applied to the terminals of the memory cell 510 and the circuit board 12 for performing read, erase, and program operations. Table 4: Operation of flash memory cell 510 in Figure 5

[0021] [Table 4]

[0022] The methods and means described herein may be applied to other non-volatile memory technologies, including but not limited to FINFET split-gate flash or stack-gate flash memory, NAND flash, SONOS (silicon-oxide-nitride-oxide-silicon, charge trap in nitride), MONOS (metal-oxide-nitride-oxide-silicon, metal charge trap in nitride), ReRAM (resistive random-access memory), PCM (phase change memory), MRAM (magnetic random-access memory), FeRAM (ferroelectric random-access memory), CT (charge trap) memory, CN (carbon-tube) memory, OTP (one-time programmable, bi-level or multi-level), and CeRAM (correlated electron random-access memory).

[0023] Two modifications are made to utilize a memory array containing one of the non-volatile memory cell types in the artificial neural network described above. First, the lines are configured so that each memory cell can be programmed, erased, and read individually without adversely affecting the memory state of other memory cells in the array, as will be further described below. Second, sequential (analog) programming of the memory cells is provided.

[0024] Specifically, the memory state of each memory cell in the array (i.e., the charge on the floating gate) can be changed independently and continuously, with minimal disturbance to other memory cells, from a completely erased state to a fully programmed state, and vice versa. This means that cell memory is substantially analog, or can store at least one of a number of discontinuous values ​​(such as 16 or 64 different values), making every memory cell in the memory array highly precise and individually tunable, and the memory array becomes ideal for memory and fine-tuning of synaptic weights in neural networks.

[0025] <Neural networks using non-volatile memory cell arrays> Figure 6 conceptually illustrates an unrestricted example of a neural network utilizing a non-volatile memory array in this example. While this example uses a non-volatile memory array neural network for a facial recognition application, any other suitable application can be implemented using a non-volatile memory array-based neural network. The non-volatile memory array and associated circuitry used in the neural network are a type of computation-in-memory (CIM) engine or vector-by-matrix (VMM) multiplication system.

[0026] S0 is the input layer, which in this example is a 32x32 pixel RGB image with 5-bit precision (i.e., three 32x32 pixel arrays, one for each color R, G, and B, with each pixel having 5-bit precision). The synapse CB1, going from input layer S0 to layer C1, scans the input image with a 3x3 pixel overlapping filter (kernel), applying different weight sets to some instances and shared weights to others, and shifts the filter by one pixel (or more than one pixel depending on the model). Specifically, the values ​​of nine pixels in the 3x3 portion of the image (i.e., referred to as the filter or kernel) are provided to synapse CB1, where these nine input values ​​are multiplied by appropriate weights, and after adding the outputs of the multiplications, a single output value is determined, which is then given by the first synapse of CB1 to generate one of the pixels in the feature map of layer C1. The 3x3 filter is then shifted one pixel to the right within the input layer S0 (i.e., a column of 3 pixels is added to the right and a column of 3 pixels is dropped to the left), thereby providing the 9 pixel values ​​of this newly positioned filter to synapse CB1, where they are multiplied by the same weights as above, determining a second single output value by the associated synapse. This process continues until the 3x3 filter scans the entire 32x32 pixel image of the input layer S0 for all three colors and all bits (precision values). The process is then repeated with different weight sets to generate different feature maps of layer C1 until all feature maps of layer C1 have been computed.

[0027] In this example, layer C1 contains 16 feature maps, each having 30x30 pixels. Each pixel is a new feature pixel extracted from the multiplication of the input and the kernel; therefore, each feature map is a two-dimensional array, and thus in this example, layer C1 constitutes 16 layers of two-dimensional arrays (note that the layers and arrays referred to herein are logical relationships, not necessarily physical relationships; i.e., arrays are not necessarily oriented to physical two-dimensional arrays). Each of the 16 feature maps in layer C1 is generated by one of 16 different synaptic weight sets applied to the filtered scan. All C1 feature maps can target different aspects of the same image feature, such as boundary identification. For example, a first map (generated using a first weight set shared across all scans used to generate this first map) can identify circular edges, a second map (generated using a second weight set different from the first) can identify rectangular edges or the aspect ratio of a particular feature, and so on.

[0028] Before moving from layer C1 to layer S1, an activation function P1 (pooling) is applied that pools values ​​from non-overlapping, consecutive 2x2 regions within each feature map. The purpose of the pooling function P1 is to average neighbor positions (or the max function can also be used), for example, to reduce dependence on edge positions, and to reduce the data size before moving to the next stage. In layer S1, there are 16 15x15 feature maps (i.e., 16 different arrays, each 15x15 pixels). Synapse CB2, moving from layer S1 to layer C2, scans the maps in layer S1 with a 4x4 filter, resulting in a 1-pixel filter shift. In layer C2, there are 22 12x12 feature maps. Before moving from layer C2 to layer S2, an activation function P2 (pooling) is applied that pools values ​​from non-overlapping, consecutive 2x2 regions within each feature map. In layer S2, there are 22 6x6 feature maps. At synapse CB3, which goes from layer S2 to layer C3, an activation function (pooling) is applied, where all neurons in layer C3 are connected to all maps in layer S2 via each synapse of CB3. There are 64 neurons in layer C3. Synapse CB4, which goes from layer C3 to output layer S3, completely connects C3 to S3; that is, all neurons in layer C3 are connected to all neurons in layer S3. The output in S3 contains 10 neurons, and the highest output neuron determines the class. This output can, for example, indicate the identification or classification (classification) of the content of the original image.

[0029] Each layer of a synapse is implemented using an array or a portion of an array of non-volatile memory cells.

[0030] Figure 7 is a block diagram of an array that can be used for that purpose. The vector-by-matrix multiplication (VMM) array 32 contains non-volatile memory cells and is used as synapses between one layer and the next (e.g., CB1, CB2, CB3, and CB4 in Figure 6). Specifically, the VMM array 32 includes an array of non-volatile memory cells 33, erase gate and word line gate decoders 34, a control gate decoder 35, a bit line decoder 36, and a source line decoder 37, each of which decoders decodes its respective input to the non-volatile memory cell array 33. Input to the VMM array 32 can be from the erase gate and word line gate decoder 34 or from the control gate decoder 35. In this example, the source line decoder 37 also decodes the output of the non-volatile memory cell array 33. Alternatively, the bit line decoder 36 can decode the output of the non-volatile memory cell array 33.

[0031] The non-volatile memory cell array 33 serves two purposes. First, it stores the weights that will be used by the VMM array 32. Second, the non-volatile memory cell array 33 effectively multiplies the weights stored in it by the inputs and adds them together for each output line (source line or bit line) to generate an output, which becomes the input to the next layer or the last layer. By having the non-volatile memory cell array 33 perform the multiplication and addition functions, the need for separate multiplication and addition logic circuits is eliminated, and the calculations are more power-efficient due to being performed in memory.

[0032] The output of the non-volatile memory cell array 33 is fed to a differential adder (such as an adding operational amplifier or adding current mirror) 38, which adds the outputs of the non-volatile memory cell array 33 to create a single value for its convolution. The differential adder 38 is configured to perform the summation of positive and negative weights.

[0033] The summed output values ​​of the differential adder 38 are then fed to an activation function block 39, which normalizes the output. The activation function block 39 may provide a sigmoid, tanh, or ReLU function. The normalized output values ​​of the activation function block 39 become elements of a feature map as the next layer (e.g., C1 in Figure 6), and are then applied to the next synapse to generate the next feature map layer or the final layer. Thus, in this example, the non-volatile memory cell array 33 constitutes multiple synapses (receiving input from the previous layer of the neuron or from an input layer such as an image database), and the summation amplifier 38 and activation function block 39 constitute multiple neurons.

[0034] The inputs to the VMM array 32 in Figure 7 (WLx, EGx, CGx, and optionally BLx and SLx) can be analog level, binary level, or digital bits (in which case a DAC is provided to convert the digital bits to the appropriate input analog level), and the outputs can be analog level, binary level, or digital bits (in which case an output ADC is provided to convert the output analog level to the digital bits).

[0035] Figure 8 is a block diagram showing the use of multiple layers of the VMM array 32, labeled in the figure as VMM arrays 32a, 32b, 32c, 32d, and 32e. As shown in Figure 8, the input (indicated as Inputx) is converted from digital to analog by the digital-to-analog converter 31 and provided to the input VMM array 32a. The converted analog input can be voltage or current. Input D / A conversion of the first layer can be performed by using a function or LUT (look-up table) that maps the input Inputx to the appropriate analog level of the matrix multiplier of the input VMM array 32a. Input conversion can also be performed by an analog-to-analog (A / A) converter to convert an external analog input to the mapped analog input to the input VMM array 32a.

[0036] The output generated by input VMM array 32a is provided as input to the next VMM array (hidden level 1) 32b, the next VMM array (hidden level 1) 32b generates an output provided as input to the next input VMM array (hidden level 2) 32c, and so on. The various layers of VMM array 32 function as different layers of synapses and neurons in a convolutional neural network (CNN). Each VMM array 32a, 32b, 32c, 32d, and 32e can be a standalone physical non-volatile memory array, or multiple VMM arrays can utilize different parts of the same physical non-volatile memory array, or multiple VMM arrays can utilize overlapping parts of the same physical non-volatile memory array. The example shown in Figure 8 includes five layers (32a, 32b, 32c, 32d, 32e), namely one input layer (32a), two hidden layers (32b, 32c), and two fully connected layers (32d, 32e). Those skilled in the art will understand that this is merely an example, and that a system could instead include more than two hidden layers and more than two fully connected layers.

[0037] <Vector × Matrix Multiplication (VMM) Array> Figure 9 shows a neuron VMM array 900, which is particularly suitable for the memory cell 310 shown in Figure 3 and is used as part of a synapse and neuron between the input layer and the next layer. The VMM array 900 includes a memory array 901 of non-volatile memory cells and a reference array 902 of non-volatile reference memory cells (at the top of the array). Alternatively, another reference array may be located at the bottom.

[0038] In the VMM array 900, control gate lines such as control gate line 903 extend vertically (thus the row-direction reference array 902 is perpendicular to the control gate line 903), and erase gate lines such as erase gate line 904 extend horizontally. Here, inputs to the VMM array 900 are provided to the control gate lines (CG0, CG1, CG2, CG3), and outputs of the VMM array 900 appear on the source lines (SL0, SL1). In one example, only even rows are used, and in another example, only odd rows are used. The current on each source line (SL0, SL1, respectively) performs the function of summing all currents from memory cells connected to that particular source line.

[0039] As described herein with respect to neural networks, the non-volatile memory cells of the VMM array 900, i.e., the memory cells 310 of the VMM array 900, may be configured to operate in a region below a threshold.

[0040] The non-volatile reference memory cells and non-volatile memory cells described herein are biased with weak inversion (in the region below the threshold) as follows: Ids = Io × e (Vg-Vth) / nVt =w × Io × e (Vg) / nVt , In the formula, w=e (-Vth) / nVt And, Ids is the drain-source current, Vg is the gate voltage on the memory cell, Vth is the threshold voltage of the memory cell, Vt is the thermal voltage = k × T / q, where k is Boltzmann's constant, T is the Kelvin temperature, q is the electron charge, n is the gradient coefficient = 1 + (Cdep / Cox), where Cdep is the capacitance of the depletion layer, and Cox is the capacitance of the gate oxide layer, Io is the memory cell current at a gate voltage equal to the threshold voltage, and Io is (Wt / L) × u ​​× Cox × (n-1) × Vt 2 It is proportional to , where u is the carrier mobility, and Wt and L are the width and length of the memory cell, respectively.

[0041] For IV logarithmic converters that use memory cells (such as reference memory cells or peripheral memory cells) or transistors to convert input current to input voltage: Vg = n × Vt × log[Ids / wp × Io] In the formula, wp is the w of the reference or peripheral memory cell.

[0042] For a memory array used as a vector × matrix multiplier VMM array with current input, the output current is as follows: Iout=wa×Io×e (Vg) / nVt That is to say Iout = (wa / wp) × Iin = W × Iin W=e (Vthp-Vtha) / nVt Here, wa = w of each memory cell in the memory array.

[0043] Vthp is the effective threshold voltage of the peripheral memory cell, and Vtha is the effective threshold voltage of the main (data) memory cell. Note that the threshold voltage of a transistor is a function of the substrate bias voltage, and the substrate bias voltage, denoted as Vsb, can be modulated to compensate for various conditions at such temperatures. The threshold voltage Vth can be expressed as follows: Vth=Vth0+gamma(SQRT|Vsb-2×φF)-SQRT|2×φF|) In the formula, Vth0 is the threshold voltage with zero substrate bias, φF is the surface potential, and gamma is the body effect parameter.

[0044] Word lines or control gates can be used as inputs to memory cells for input voltage.

[0045] Alternatively, the flash memory cells of the VMM array described herein can be configured to operate in a linear region. Ids = Beta × (Vgs - Vth) × Vds, Beta = u × Cox × Wt / L W=α(Vgs-Vth) In other words, the weight W in the linear domain is proportional to (Vgs - Vth).

[0046] A word line, a control gate, a bit line, or a source line can be used as an input to a memory cell operating in a linear region. A bit line or a source line can be used as an output of a memory cell.

[0047] For an I-V linear converter, a memory cell (such as a reference memory cell or a peripheral memory cell) or a transistor operating in a linear region can be used to linearly convert an input / output current into an input / output voltage.

[0048] Alternatively, the memory cells of the VMM array described herein can be configured to operate in the saturation region. Ids = 1 / 2 × beta × (Vgs - Vth) 2 , where beta = u × Cox × Wt / L W ∝ (Vgs - Vth) 2 , i.e., the weight W is proportional to (Vgs - Vth) 2 and is proportional to.

[0049] A word line, a control gate, or an erase gate can be used as an input to a memory cell operating in the saturation region. A bit line or a source line can be used as an output of an output neuron.

[0050] Alternatively, the memory cells of the VMM array described herein can be used in all regions or combinations thereof (below threshold, linear, or saturation) for each layer or multiple layers of a neural network.

[0051] Another example for the VMM array 32 of FIG. 7 is described in U.S. Patent No. 10,748,630, which is incorporated herein by reference. As described in the above application, a source line or a bit line can be used as a neuron output (current sum output).

[0052] Figure 10 shows a neuron VMM array 1000, particularly suited to the memory cell 210 shown in Figure 2 and used as a synapse between the input layer and the next layer. The VMM array 1000 comprises a memory array 1003 of non-volatile memory cells, a reference array 1001 of first non-volatile reference memory cells, and a reference array 1002 of second non-volatile reference memory cells. The reference arrays 1001 and 1002, arranged in the column direction of the array, function to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs WL0, WL1, WL2, and WL3. In practice, the first and second non-volatile reference memory cells are diode-connected through a multiplexer 1014 (partially shown) with current inputs flowing in. The reference cells are tuned (e.g., programmed) to a target reference level. The target reference level is provided by a reference miniarray matrix (not shown).

[0053] The memory array 1003 serves two purposes. First, it stores the weights used by the VMM array 1000 in each memory cell. Second, the memory array 1003 effectively multiplies the weights stored in it by the inputs (i.e., the current inputs supplied to terminals BLR0, BLR1, BLR2, and BLR3, which are converted into input voltages by the reference arrays 1001 and 1002 and supplied to the word lines WL0, WL1, WL2, and WL3), and then adds all the results (memory cell currents) to generate the outputs of each bit line (BL0~BLN), which become inputs to the next layer or the last layer. By performing multiplication and addition functions, the memory array 1003 eliminates the need for separate multiplication and addition logic circuits and is also power efficient. Here, voltage inputs are supplied to word lines WL0, WL1, WL2, and WL3, and outputs appear on the respective bit lines BL0 to BLN during the read (inference) operation. Each current in bit lines BL0 to BLN performs the function of summing the currents from all non-volatile memory cells connected to that particular bit line.

[0054] Table 5 shows the operating voltages and currents of the VMM array 1000. The columns in the table show the voltages applied to the word lines of selected cells, word lines of unselected cells, bit lines of selected cells, bit lines of unselected cells, source lines of selected cells, and source lines of unselected cells. The rows show the read, erase, and program operations. Table 5: Operation of VMM Array 1000 in Figure 10

[0055] [Table 5]

[0056] Figure 11 shows a neuron VMM array 1100, which is particularly suitable for the memory cell 210 shown in Figure 2 and is used as part of a synapse and neuron between the input layer and the next layer. The VMM array 1100 comprises a memory array 1103 of non-volatile memory cells, a reference array 1101 of first non-volatile reference memory cells, and a reference array 1102 of second non-volatile reference memory cells. The reference arrays 1101 and 1102 extend in the row direction of the VMM array 1100. The VMM array is similar to the VMM 1000, except that the word lines in the VMM array 1100 extend vertically. Here, inputs are provided to the word lines (WLA0, WLB0, WLA1, WLB2, WLA2, WLB2, WLA3, WLB3), and outputs appear on the source lines (SL0, SL1) during read operations. The current on each source line performs the function of summing all the currents from the memory cells connected to that particular source line.

[0057] Table 6 shows the operating voltages and currents of the VMM array 1100. The columns in the table show the voltages applied to the word lines of selected cells, word lines of unselected cells, bit lines of selected cells, bit lines of unselected cells, source lines of selected cells, and source lines of unselected cells. The rows show the read, erase, and program operations. Table 6: Operation of VMM Array 1100 in Figure 11

[0058] [Table 6]

[0059] Figure 12 shows a neuron VMM array 1200, which is particularly suitable for the memory cell 310 shown in Figure 3 and is used as part of a synapse and neuron between the input layer and the next layer. The VMM array 1200 includes a memory array 1203 of non-volatile memory cells, a reference array 1201 of a first non-volatile reference memory cell, and a reference array 1202 of a second non-volatile reference memory cell. The reference arrays 1201 and 1202 function to convert the current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs CG0, CG1, CG2, and CG3. In practice, the first and second non-volatile reference memory cells are diode-connected through a multiplexer 1212 (partially shown) with current inputs flowing through BLR0, BLR1, BLR2, and BLR3. Each multiplexer 1212 includes a separate multiplexer 1205 and a cascoding transistor 1204 to ensure a constant voltage across the respective bit lines (such as BLR0) of the first and second non-volatile reference memory cells during read operations. The reference cells are tuned to a target reference level.

[0060] The memory array 1203 serves two purposes. First, it stores the weights used by the VMM array 1200. Second, the memory array 1203 effectively multiplies the weights stored in the memory array by the inputs (current inputs supplied to terminals BLR0, BLR1, BLR2, and BLR3, which the reference arrays 1201 and 1202 convert into input voltages and supply to the control gates (CG0, CG1, CG2, and CG3)), then adds all the results (cell currents) to produce an output, which appears in BL0~BLN and becomes the input to the next layer or the last layer. By having the memory array perform the multiplication and addition functions, the need for separate multiplication and addition logic circuits is eliminated, and power efficiency is also improved. Here, the inputs are provided to the control gate lines (CG0, CG1, CG2, and CG3), and the output appears in the bit lines (BL0~BLN) during read operations. The current in each bit line performs the function of adding up all the currents from the memory cells connected to that particular bit line.

[0061] The VMM array 1200 implements one-way tuning of non-volatile memory cells within the memory array 1203. That is, each non-volatile memory cell is erased and then partially programmed until the desired charge on the floating gate is reached. If too much charge is applied to the floating gate (resulting in an incorrect value being stored in the cell), the cell is erased and the series of partial programming operations is restarted from the beginning. As shown, two rows sharing the same erase gate (such as EG0 or EG1) are erased together (which may be called a page erase), and then each cell is partially programmed until the desired charge on the floating gate is reached.

[0062] Table 7 shows the operating voltages and currents of the VMM array 1200. The columns in the table show the voltages applied to the word lines of selected cells, word lines of unselected cells, bit lines of selected cells, bit lines of unselected cells, control gates of selected cells, control gates of unselected cells in the same sector as the selected cell, control gates of unselected cells in a different sector than the selected cell, erase gates of selected cells, erase gates of unselected cells, source lines of selected cells, and source lines of unselected cells. The rows show the read, erase, and program operations. Table 7: Operation of VMM Array 1200 in Figure 12

[0063] [Table 7]

[0064] Figure 13 shows a neuron VMM array 1300, which is particularly suitable for the memory cell 310 shown in Figure 3 and is used as part of a synapse and neuron between the input layer and the next layer. The VMM array 1300 comprises a memory array 1303 of nonvolatile memory cells, a reference array 1301 or a first nonvolatile reference memory cell, and a reference array 1302 of a second nonvolatile reference memory cell. The EG lines EGR0, EG0, EG1, and EGR1 extend vertically, and the CG lines CG0, CG1, CG2, and CG3 and the SL lines WL0, WL1, WL2, and WL3 extend horizontally. The VMM array 1300 is similar to the VMM array 1400 except that the VMM array 1300 implements bidirectional tuning, and each individual cell can be completely erased, partially programmed, and partially erased as needed to reach a desired amount of charge on the floating gate by using individual EG lines. As shown, reference arrays 1301 and 1302 convert the input currents at terminals BLR0, BLR1, BLR2, and BLR3 into control gate voltages CG0, CG1, CG2, and CG3 (through the action of diode-connected reference cells via multiplexer 1314), and these voltages are applied to memory cells in the row direction. Current outputs (neurons) are located in the bit lines BL0~BLN, and each bit line sums all the currents from the non-volatile memory cells connected to that particular bit line.

[0065] Table 8 shows the operating voltages and currents of the VMM array 1300. The columns in the table show the voltages applied to the word lines of selected cells, word lines of unselected cells, bit lines of selected cells, bit lines of unselected cells, control gates of selected cells, control gates of unselected cells in the same sector as the selected cell, control gates of unselected cells in a different sector than the selected cell, erase gates of selected cells, erase gates of unselected cells, source lines of selected cells, and source lines of unselected cells. The rows show the read, erase, and program operations. Table 8: Operation of VMM Array 1300 in Figure 13

[0066] [Table 8]

[0067] Figure 22 shows a neuron VMM array 2200 that is particularly suitable for the memory cell 210 shown in Figure 2 and is used as part of the synapse and neuron between the input layer and the next layer. In the VMM array 2200, inputs INPUT0...., INPUT N These are bit lines BL0, ...BL, respectively. N The signal is received, and outputs OUTPUT1, OUTPUT2, OUTPUT3, and OUTPUT4 are generated on source lines SL0, SL1, SL2, and SL3, respectively.

[0068] Figure 23 shows a neuron VMM array 2300 that is particularly suitable for the memory cell 210 shown in Figure 2 and is used as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, INPUT1, INPUT2, and INPUT3 are received by source lines SL0, SL1, SL2, and SL3, respectively, and outputs OUTPUT0, ...OUTPUT N These are bit lines BL0, ..., BL N It is generated by [this method].

[0069] Figure 24 shows a neuron VMM array 2400 that is particularly suitable for the memory cell 210 shown in Figure 2 and is used as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M These are the word lines WL0, ..., WL, respectively. M Received by, output OUTPUT0, ...OUTPUT N These are bit lines BL0, ..., BL N It is generated by [this method].

[0070] Figure 25 shows a neuron VMM array 2500 that is particularly suitable for the memory cell 310 shown in Figure 3 and is used as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M These are the word lines WL0, ..., WL, respectively. MReceived by, output OUTPUT0, ...OUTPUT N These are bit lines BL0, ..., BL N It is generated by [this method].

[0071] Figure 26 shows a neuron VMM array 2600 that is particularly suitable for the memory cell 410 shown in Figure 4 and is used as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT n However, each of them is a vertical control gate line CG0, ..., CG N The signal is received, and outputs OUTPUT1 and OUTPUT2 are generated on source lines SL0 and SL1.

[0072] Figure 27 shows a neuron VMM array 2700 that is particularly suitable for the memory cell 410 shown in Figure 4 and is used as part of the synapses and neurons between the input layer and the next layer. In this example, the inputs are INPUT0, ..., INPUT N These are bit lines BL0, ..., BL, respectively. N The bit line control gates 2701-1, 2701-2, ..., 2701-(N-1) and 2701-N, which are coupled to the bit line control gates, are received by the gates. Exemplary outputs OUTPUT1 and OUTPUT2 are generated on source lines SL0 and SL1.

[0073] Figure 28 shows a neuron VMM array 2800, which is particularly suitable for the memory cell 310 shown in Figure 3, the memory cell 510 shown in Figure 5, and the memory cell 710 shown in Figure 7, and is used as part of synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M These are the word lines WL0, ..., WL, respectively. M Received by, output OUTPUT0, ..., OUTPUT N These are bit lines BL0, ..., BL N It is generated in [location].

[0074] Figure 29 shows a neuron VMM array 2900 that is particularly suitable for the memory cell 310 shown in Figure 3, the memory cell 510 shown in Figure 5, and the memory cell 710 shown in Figure 7, and is used as part of synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M These are control gate lines CG0, ..., CG M It is received as follows. Output OUTPUT0, ..., OUTPUT N These are the vertical source lines SL0, ..., SL, respectively. N It is generated in each source line SL i It is coupled to the source lines of all memory cells in column i.

[0075] Figure 30 shows a neuron VMM array 3000, which is particularly suitable for the memory cell 310 shown in Figure 3, the memory cell 510 shown in Figure 5, and the memory cell 710 shown in Figure 7, and is used as part of synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M These are control gate lines CG0, ..., CG M It is received as follows. Output OUTPUT0, ..., OUTPUT N These are the vertical bit lines BL0, ..., BL N Generated in each bit line BL i It is coupled to the bit lines of all memory cells in column i.

[0076] <Long-term and short-term memory> Prior art includes a concept called long short-term memory (LSTM). LSTM units are often used within neural networks. LSTMs allow neural networks to store information for a predetermined period and use that information in subsequent operations. A conventional LSTM unit includes a cell, an input gate, an output gate, and a forget gate. The three gates regulate the flow of information into and out of the cell, and the duration for which information is stored within the LSTM. VMMs are particularly useful in LSTM units.

[0077] Figure 14 shows an exemplary LSTM1400. In this example, the LSTM1400 includes cells 1401, 1402, 1403, and 1404. Cell 1401 receives the input vector x0 and generates the output vector h0 and the cell state vector c0. Cell 1402 receives the input vector x1 and the output vector (hidden state) h0 from cell 1401. 、 Cell 1401 receives the cell state c0 from cell 1401 and generates the output vector h1 and the cell state vector c1. Cell 1403 receives the input vector x2, the output vector (hidden state) h1 from cell 1402, and the cell state c1 from cell 1402 and generates the output vector h2 and the cell state vector c2. Cell 1404 receives the input vector x3, the output vector (hidden state) h2 from cell 1403, and the cell state c2 from cell 1403 and generates the output vector h3. Additional cells are also available, and an LSTM with four cells is just an example.

[0078] Figure 15 shows an exemplary implementation of LSTM cell 1500 that can be used for cells 1401, 1402, 1403, and 1404 in Figure 14. LSTM cell 1500 receives an input vector x(t), a cell state vector c(t-1) from a preceding cell, and an output vector h(t-1) from a preceding cell, and generates the cell state vector c(t) and output vector h(t).

[0079] LSTM cell 1500 includes sigmoid function devices 1501, 1502, and 1503, each of which applies a number between 0 and 1 to control the extent to which each component of the input vector contributes to the output vector. LSTM cell 1500 also includes tanh devices 1504 and 1505 for applying a hyperbolic tangent function to the input vector, multiplier devices 1506, 1507, and 1508 for multiplying two vectors together, and an adder device 1509 for adding two vectors together. The output vector h(t) can be provided to the next LSTM cell in the system or accessed for other purposes.

[0080] Figure 16 shows an LSTM cell 1600, which is an example implementation of LSTM cell 1500. For the reader's convenience, the same numbering method used in LSTM cell 1500 is used in LSTM cell 1600. Sigmoid function devices 1501, 1502, and 1503, and tanh device 1504 each contain multiple VMM arrays 1601 and activation function blocks 1602. Thus, VMM arrays are found to be particularly useful in LSTM cells used in certain neural network systems. Multiplier devices 1506, 1507, and 1508, and adder device 1509 are implemented in a digital or analog manner. Activation function block 1602 can be implemented in a digital or analog manner.

[0081] An alternative example of the LSTM cell 1600 (and another example of an embodiment of the LSTM cell 1500) is shown in Figure 17. In Figure 17, the sigmoid function devices 1501, 1502, and 1503, and the tanh device 1504 share the same physical hardware (VMM array 1701 and activation function block 1702) in a time-division multiplexed manner. The LSTM cell 1700 also includes a multiplier device 1703 for multiplying two vectors together, an adder device 1708 for adding two vectors together, a tanh device 1505 (including an activation function block 1702), a register 1707 for storing the value i(t) when i(t) is output from the sigmoid function block 1702, a register 1704 for storing the value f(t) × c(t-1) when its value is output from the multiplier device 1703 via the multiplexer 1710, a register 1705 for storing the value i(t) × u(t) when its value is output from the multiplier device 1703 via the multiplexer 1710, a register 1706 for storing the value o(t) × c(t) when its value is output from the multiplier device 1703 via the multiplexer 1710, and a multiplexer 1709.

[0082] While an LSTM cell 1600 contains multiple sets of VMM arrays 1601 and their respective activation function blocks 1602, an LSTM cell 1700 contains one set of VMM arrays 1701 and activation function blocks 1702, which are used to represent multiple layers in the example of an LSTM cell 1700. An LSTM cell 1700 requires less space than an LSTM cell 1600 because it requires 1 / 4 the space for the VMMs and activation function blocks.

[0083] An LSTM unit typically includes multiple VMM arrays, each of which utilizes functionality provided by specific circuit blocks outside the VMM array, such as adder and activation function blocks, and high-voltage generation blocks. Providing separate circuit blocks for each VMM array would require a considerable amount of space within the semiconductor device and would be somewhat inefficient. Therefore, the examples described below reduce the amount of circuitry provided outside the VMM array itself.

[0084] <Gated recurrent unit> Analog VMM implementations can be used in GRU (gated recurrent unit) systems. A GRU is a gate mechanism within an iterative neural network. GRUs are similar to LSTMs, except that GRU cells generally contain fewer components than LSTM cells.

[0085] Figure 18 shows an exemplary GRU1800. In this example, the GRU1800 includes cells 1801, 1802, 1803, and 1804. Cell 1801 receives input vector x0 and produces output vector h0. Cell 1802 receives input vector x1 and output vector h0 from cell 1801 and produces output vector h1. Cell 1803 receives input vector x2 and output vector (hidden state) h1 from cell 1802 and produces output vector h2. Cell 1804 receives input vector x3 and output vector (hidden state) h2 from cell 1803 and produces output vector h3. Additional cells are also available, and a GRU with four cells is just an example.

[0086] Figure 19 shows an exemplary implementation of a GRU cell 1900 that can be used in cells 1801, 1802, 1803, and 1804 of Figure 18. The GRU cell 1900 takes an input vector x(t) and an output vector h(t-1) from a preceding GRU cell and produces an output vector h(t). The GRU cell 1900 includes sigmoid function devices 1901 and 1902, each of which applies a number between 0 and 1 to the components from the output vector h(t-1) and the input vector x(t). The GRU cell 1900 also includes a tanh device 1903 for applying a hyperbolic tangent function to the input vector, multiple multiplier devices 1904, 1905, and 1906 for multiplying two vectors together, an adder device 1907 for adding two vectors together, and a complementary device 1908 for subtracting the input from 1 to produce an output.

[0087] Figure 20 shows GRU cell 2000, an example implementation of GRU cell 1900. For the reader's convenience, the same numbering method used in GRU cell 1900 is used in GRU cell 2000. As can be seen from Figure 20, the sigmoid function devices 1901 and 1902, and the tanh device 1903, each contain multiple VMM arrays 2001 and activation function blocks 2002. Thus, it can be seen that VMM arrays are used in particular in GRU cells used in specific neural network systems. The multiplier devices 1904, 1905, 1906, the adder device 1907, and the complementary device 1908 are implemented in a digital or analog manner. The activation function block 2002 can be implemented in a digital or analog manner.

[0088] Figure 21 shows an alternative example of the GRU cell 2000 (and another example of an implementation of the GRU cell 1900). In Figure 21, the GRU cell 2100 utilizes the VMM array 2101 and the activation function block 2102, which, when configured as a sigmoid function, applies a number between 0 and 1 to control the extent to which each component of the input vector contributes to the output vector. In Figure 21, the sigmoid function devices 1901 and 1902, and the tanh device 1903, share the same physical hardware (VMM array 2101 and activation function block 2102) in a time-division multiplexed manner. The GRU cell 2100 also includes a multiplier device 2103 for multiplying two vectors together, an adder device 2105 for adding two vectors together, a complementary device 2109 for subtracting an input from 1 to produce an output, a multiplexer 2104, a register 2106 for holding the value h(t-1)×r(t) when that value is output from the multiplier device 2103 via the multiplexer 2104, a register 2107 for holding the value h(t-1)×z(t) when that value is output from the multiplier device 2103 via the multiplexer 2104, and a register 2108 for holding the value h^(t)×(1-z(t)) when that value is output from the multiplier device 2103 via the multiplexer 2104.

[0089] While GRU cell 2000 contains multiple sets of VMM arrays 2001 and activation function blocks 2002, GRU cell 2100 contains one set of VMM arrays 2101 and activation function blocks 2102, which are used to represent multiple layers in the example of GRU cell 2100. GRU cell 2100 requires less space than GRU cell 2000 because it requires one-third the space for the VMM and activation function blocks compared to GRU cell 2000.

[0090] A GRU system typically includes multiple VMM arrays, each of which utilizes functionality provided by specific circuit blocks outside the VMM array, such as adder and activation function blocks, and high-voltage generation blocks. Providing separate circuit blocks for each VMM array would require a considerable amount of space within the semiconductor device and would be somewhat inefficient. Therefore, the examples described below reduce the amount of circuitry provided outside the VMM array itself.

[0091] <Input and Output> The input to the VMM array may be analog level, binary level, pulse, time-modulated pulse, or digital bit (in which case a DAC is used to convert the digital bit to an appropriate input analog level), and the output may be analog level, binary level, timing pulse, pulse, or digital bit (in which case an output ADC is used to convert the output analog level to a digital bit).

[0092] <Differential Cell> Typically, for each memory cell in a VMM array, each weight W can be implemented by a single memory cell, a differential cell, or two blended memory cells (the average of two cells). In the case of a differential cell, two memory cells are used to implement the weight W as a differential weight (W = W+-W-). In the case of two blended memory cells, two memory cells are used to implement the weight W as the average of two cells.

[0093] Figure 31 shows the VMM system 3100. In some examples, the weights W stored in the VMM array are stored as differential pairs, W+ (positive weight) and W- (negative weight), where W = (W+) - (W-). In the VMM system 3100, half of the multiple bit lines are designated as W+ lines, i.e., bit lines that will connect to memory cells that will store the positive weight W+, and the other half of the multiple bit lines are designated as W- lines, i.e., bit lines that will connect to memory cells that will implement the negative weight W-. The W- lines are interspersed alternately between the W+ lines. Subtraction operations are performed by adders, such as adders 3101 and 3102, which receive current from the W+ and W- lines. The outputs of the W+ lines and the W- lines are combined to effectively give W = W+ - W- for each pair of (W+, W-) cells in all pairs of (W+, W-) lines. Up to this point, we have described W- lines that are alternately scattered between W+ lines, but in other examples, W+ and W- lines can be arbitrarily placed anywhere within the array.

[0094] Figure 32 shows another example. In the VMM system 3210, positive weights W+ are implemented in the first array 3211, and negative weights W- are implemented in the second array 3212, which is separate from the first array, and the resulting weights are appropriately combined by the adder circuit 3213.

[0095] Figure 33 shows the VMM system 3300. The weights W stored in the VMM array are stored as differential pairs, W+ (positive weight) and W- (negative weight), where W = (W+) - (W-). The VMM system 3300 comprises arrays 3301 and 3302. Half of the multiple bit lines in each of arrays 3301 and 3302 are designated as W+ lines, i.e., bit lines that will connect to memory cells that will store the positive weights W+, and the other half of the multiple bit lines in each of arrays 3301 and 3302 are designated as W- lines, i.e., bit lines that will connect to memory cells that will implement the negative weights W-. The W- lines are interspersed alternately between the W+ lines. Subtraction operations are performed by adders, such as adders 3303, 3304, 3305, and 3306, which receive current from the W+ and W- lines. The outputs of the W+ line and the W- line from each array 3301 and 3302 are combined together to effectively give W=W+-W- for each pair of (W+, W-) cells in all pairs of (W+, W-) lines. In addition, the W values ​​from each array 3301 and 3302 can be further combined through the adders 3307 and 3308, such that each W value is the result of subtracting the W value from array 3302 from the W value from array 3301, and the final result from the adders 3307 and 3308 is the difference of two difference values.

[0096] <Number of weights per layer> Each non-volatile memory cell used in an analog neural memory system can be erased and programmed to hold a very specific and precise amount of charge, i.e., a number of electrons, within a floating gate. Each floating gate can hold one of N different values, where N is the number of different weights that each cell can represent. Examples of N include 16, 32, 64, 128, and 256.

[0097] Referring again to Figures 6 and 8, a neural network contains various layers. Certain layers do not require the use of an analog neural memory system. For example, some layers, such as the first layer of a residual neural network (RESNET), only require that cells be able to store two weights ("0" or "1"), i.e., N=2, which are binary weights. Such layers do not require the use of an analog neural memory system because a simpler digital system suffices. Using an analog neural memory system for such layers is inefficient because it provides a degree of precision (e.g., N=256) that is not utilized by layers that require N=2. [Overview of the project]

[0098] Numerous examples of neural networks comprising one or more analog in-memory computing engines and one or more digital in-memory computing engines are disclosed. This makes it possible to use digital CIM engines in situations where layers contain binary weights but not analog weights. [Brief explanation of the drawing]

[0099] [Figure 1] This is a diagram of an artificial neural network. [Figure 2] This shows a prior art split-gate flash memory cell. [Figure 3] This shows another prior art split-gate flash memory cell. [Figure 4] This shows another prior art split-gate flash memory cell. [Figure 5] This shows another prior art split-gate flash memory cell. [Figure 6] This figure shows various levels of exemplary artificial neural networks that utilize one or more non-volatile memory arrays. [Figure 7]This is a block of VMM systems. [Figure 8] This block diagram shows an exemplary artificial neural network utilizing one or more VMM systems. [Figure 9] Here is another example of a VMM system. [Figure 10] Here is another example of a VMM system. [Figure 11] Here is another example of a VMM system. [Figure 12] Here is another example of a VMM system. [Figure 13] Here is another example of a VMM system. [Figure 14] This demonstrates prior art long- and short-term memory systems. [Figure 15] This shows an example cell used in long- and short-term memory systems. [Figure 16] Figure 15 shows an exemplary embodiment of the cell. [Figure 17] Another exemplary embodiment of the cell shown in Figure 15 is presented. [Figure 18] This shows a prior art gated regression unit system. [Figure 19] An exemplary cell for use in a gated regressive unit system is shown. [Figure 20] Figure 19 shows an exemplary embodiment of the cell. [Figure 21] Another exemplary embodiment of the cell shown in Figure 19 is presented. [Figure 22] Here is another example of a VMM system. [Figure 23] Here is another example of a VMM system. [Figure 24] Here is another example of a VMM system. [Figure 25] Here is another example of a VMM system. [Figure 26] Here is another example of a VMM system. [Figure 27] Here is another example of a VMM system. [Figure 28] Here is another example of a VMM system. [Figure 29]Here is another example of a VMM system. [Figure 30] Here is another example of a VMM system. [Figure 31] Here is another example of a VMM system. [Figure 32] Here is another example of a VMM system. [Figure 33] Here is another example of a VMM system. [Figure 34] This shows a computing system within analog memory. [Figure 35] This demonstrates a computing system within digital memory. [Figure 36] This describes a hybrid system comprising both an analog memory-based computing system and a digital memory-based computing system. [Figure 37] This shows the analog memory-based computing engine. [Figure 38] This illustrates an exemplary in-digital memory computing engine. [Figure 39] Another exemplary in-digital memory computing engine is shown. [Figure 40] Another exemplary in-digital memory computing engine is shown. [Figure 41A] This shows the multiplication logic cell. [Figure 41B] This shows a 2-bit adder logic cell. [Figure 41C] This shows a digital CIM cell. [Figure 42] Another exemplary in-digital memory computing engine is shown. [Figure 43] This shows a shift and adder tree. [Figure 44] Another shift and adder tree is shown. [Figure 45] An exemplary dynamic weighting engine is shown. [Figure 46] Here is another exemplary dynamic weighting engine. [Figure 47] This shows an integrating analog-to-digital converter. [Figure 48] This shows an integrating analog-to-digital converter. [Figure 49A]This shows an output circuit that includes a current-to-voltage converter and an analog-to-digital converter. [Figure 49B] This shows an output circuit that includes a current-to-voltage converter and an analog-to-digital converter. [Figure 50] Figure 36 shows how this is performed by the hybrid system. [Modes for carrying out the invention]

[0100] <Analog memory-based calculation engine> Figure 34 shows a block diagram of the analog in-memory computation (CIM) engine 3400. The analog CIM engine 3400 comprises a VMM array 3401 (sometimes referred to as a neural network array), a row decoder 3402, a high-voltage decoder 3403, a column decoder 3404, a bit line driver 3405 (such as a bit line control circuit for programming), an input circuit 3406, an output circuit 3407, control logic 3408, and a bias generator 3409. The analog CIM engine 3400 further comprises a high-voltage generation block 3410, which includes a charge pump 3411, a charge pump regulator 3412, and a high-voltage level generator 3413. The analog CIM engine 3400 further comprises an algorithm controller 3414 (for programming / erasing or weight tuning), an analog circuit 3415, a control engine 3416 (which may include, but is not limited to, functions such as arithmetic functions, activation functions, and embedded microcontroller logic), a test control logic 3417, and a static random access memory (SRAM) block 3418 for storing intermediate data such as input circuits (e.g., activation data) or output circuits (neuron output data, partial sum output neuron data), or data inputs for programming (such as data inputs for all rows or multiple rows). The VMM array 3401 comprises an array of non-volatile memory cells arranged in rows and columns, where the non-volatile memory cells are of the type shown in Figures 2, 3, 4, or 510, or other types known to those skilled in the art, respectively. In one example, the non-volatile memory cells are split-gate flash memory cells as shown in Figures 2, 3, or 4. In another example, a non-volatile memory cell is a stacked gate flash memory cell, as shown in Figure 5.

[0101] The input circuit 3406 may include circuits such as a DAC (digital to analog converter), DPC (digital to pulses converter, or digital to time modulated pulse converter), AAC (analog to analog converter, e.g., current-to-voltage converter, or logarithmic converter), PAC (pulse to analog level converter), or any other type of converter. The input circuit 3406 may implement one or more of the following: normalization, linear, or nonlinear up / downscaling functions, or arithmetic functions. The input circuit 3406 may implement a temperature compensation function for the input level. The input circuit 3406 may implement an activation function such as a rectified linear activation function (ReLU) or a sigmoid. The input circuit 3406 may store digital activation data that is applied as an input signal during program or read operation, or combined with an input signal. The digital activation data may be stored in a register. The input circuit 3406 may include a sample-and-hold circuit and a buffer, and may also include a circuit for driving array terminals such as CG lines, WL lines, EG lines, and SL lines. A DAC can be used to convert digital activation data into analog input voltages applied to the array.

[0102] The output circuit 3407 may include circuits such as an ITV (current-to-voltage circuit), an ADC (analog-to-digital converter, for converting the analog output of a neuron to digital bits), an AAC (analog-to-analog converter, e.g., a current-to-voltage converter or a logarithmic converter), an APC (analog-to-pulse(s) converter, or an analog-to-time-modulated pulse converter), or any other type of converter. The output circuit 3407 may convert the array output to activation data. The output circuit 3407 may implement an activation function such as ReLU or sigmoid. The output circuit 3407 may implement one or more of the following for the neuron output: statistical normalization, regularization, up / down scaling / gain functions, statistical rounding, or arithmetic functions (e.g., addition, subtraction, division, multiplication, shift, logarithm). The output circuit 3407 may implement a temperature compensation function for the neuron output or array output (such as a bit line output) to keep the array's power consumption nearly constant or to improve the accuracy of the array (neuron) output, by keeping the IV slope nearly the same over temperature. The output circuit 3407 may also include a register for storing the output data.

[0103] <Calculations within digital memory> Figure 35 shows a block diagram of the digital in-memory computation (CIM) engine 3500. The digital CIM engine 3500 includes many, though not all, of the components found in the analog CIM engine 3400.

[0104] The digital CIM engine 3500 comprises an array 3501, a row decoder 3502, a column decoder 3504, a bit line driver 3505 (such as a bit line control circuit for programming), an input circuit 3506, an output circuit 3507, control logic 3508, and a bias generator 3509. The digital CIM engine 3500 further comprises an algorithm controller 3514, an analog circuit 3515, a control engine 3516, and test control logic 3517. The array 3501 comprises an array of non-volatile memory cells arranged in rows and columns, the non-volatile memory cells being of the type shown in Figures 2, 3, 4, or 510, respectively, or other types known to those skilled in the art. In one example, the non-volatile memory cells are split-gate flash memory cells as shown in Figures 2, 3, or 4. In another example, the non-volatile memory cells are stack-gate flash memory cells as shown in Figure 5. The array 3501 operates in the digital domain, and the values ​​stored in each non-volatile memory cell are binary values, in contrast to analog values ​​such as those in the analog CIM engine 3400.

[0105] The input circuit 3506 may include circuits such as a DAC, DPC, AAC, PAC, or any other type of converter. The input circuit 3506 may implement one or more of the following: normalization, linear or nonlinear up / downscaling functions, or arithmetic functions. The input circuit 3506 may implement a temperature compensation function for the input level. The input circuit 3506 may implement an activation function such as ReLU or sigmoid. The input circuit 3506 may store digital activation data that is applied as an input signal during program or read operation, or combined with an input signal. The digital activation data can be stored in a register. The input circuit 3506 may include circuits for driving array terminals such as CG lines, WL lines, EG lines, and SL lines, which may include sample-and-hold circuits and buffers. The digital activation data can be converted to an analog input voltage applied to the array using a DAC. The output circuit 3507 may include circuits such as an ITV, ADC, AAC, APC, or any other type of converter. The output circuit 3507 may convert the array output into activation data. The output circuit 3507 may implement an activation function such as ReLU or sigmoid. The output circuit 3507 may implement one or more of the following for the neuron output: statistical normalization, regularization, up / down scaling / gain functions, statistical rounding, or arithmetic functions (e.g., addition, subtraction, division, multiplication, shift, logarithm). The output circuit 3507 may implement a temperature compensation function for the neuron output or array output (such as a bit line output) to keep the array's power consumption nearly constant or to improve the accuracy of the array (neuron) output, such as by keeping the IV slope nearly constant over temperature. The output circuit 3507 may be provided with registers for storing the output data.

[0106] In an alternative configuration, the digital CIM engine 3500 operates purely in the digital domain, without utilizing any analog circuits. For example, the input circuit 3506 and output circuit 3507 can be formed from purely digital logic circuits operating in the digital domain, and the analog circuit 3515 can be eliminated.

[0107] <A hybrid system comprising an analog memory-based computing engine, a digital memory-based computing engine, and a dynamic weight engine> Figure 36 shows the hybrid system 3600. The hybrid system comprises analog CIM engines 3601, 3602, and 3604, digital CIM engines 3605 and 3607, digital computing engines 3606 and 3608, dynamic weighting engine 3603, and system bus 3609.

[0108] The analog CIM engines 3601, 3602, and 3604 store analog weights (e.g., N=256) in the non-volatile memory cells of their respective VMM arrays (e.g., VMM array 3401) and perform VMM calculations on these analog weights. The VMM systems shown in Figures 9-13 and 22-33 are examples of analog CIM engines.

[0109] The digital in-memory computation (CIM) engines 3605 and 3607 store digital weights (i.e., N=2) in the non-volatile memory cells of their respective VMM arrays (e.g., VMM array 3501) and perform VMM operations on those digital weights. Alternatively, the digital CIM engines 3605 and 3607 can store the digital weights in a non-volatile macro or chip. Unlike analog CIM engines, the digital CIM engines can utilize arrays of SRAM or DRAM cells in addition to non-volatile memory cells with floating gates, as shown in Figures 2 to 5.

[0110] The digital computing engines 3606 and 3608 are microprocessors, digital signal processors, or other digital computing engines such as GPUs (graphic processing units), TPUs (Tensor processing units), dedicated MAC (multiply-add-accumulate) units, dedicated SIMD (single instruction multiple data) processors, and vector extensions. The digital computing engines 3606 and 3608 can perform integer or floating-point calculations. They can use weights from the VMM array within the analog CIM engine, or from digital non-volatile memory macros or chips.

[0111] The dynamic weight engine 3603 is a device that can modify stored weights by changing the bias voltage or bias current without performing a separate erase or program operation. Since the weights can be modified without performing a separate erase or program operation, these weights are considered dynamic weights. The weights can be transferred from the VMM array in the analog CIM engine or from a digital non-volatile memory macro or chip. An example of the dynamic weight engine 3603 is shown in Figures 45 and 46, where the bias voltage is transferred to the gate of a transistor in a unit CIM array cell. The dynamic weight control circuit and bias circuit are not shown.

[0112] The dynamic weighting engine 3603, analog CIM engines 3601, 3602, and 3604, digital CIM engines 3605 and 3607, and digital computing engines 3606 and 3608 are coupled to the system bus 3609, which enables all coupled devices to communicate with each other.

[0113] The microcontroller 3610, SRAM 3611, vector register 3612, and peripheral control and interface logic 3613 support specific functions and operations within the hybrid system 3600, including, but not limited to, controlling access to SRAM 3611, controlling data flow of various computing engines, controlling communication between the internal system bus 3609 and the external bus, executing activation functions, performing read, erase, and program operations on non-volatile memory (NVM) or volatile memory (VM), or performing weight transfers between computing engines.

[0114] Figure 50 shows an exemplary method that can be performed by the hybrid system 3600. First, the system uses the digital memory computing engine 3605 or 3607 to perform a vector × matrix multiplication operation in the first layer of the neural network (5001). Second, the system uses the analog memory computing engine 3601, 3602, or 3604 to perform a vector × matrix multiplication operation in a second layer of the neural network, different from the first layer (5002). Optionally, the system transfers dynamic weights from the dynamic weight engine 3603 to one or more of the analog memory computing engines 3601, 3602, or 3604 and / or the digital memory computing engines 3605 or 3607 (5003). Optionally, the system stores the dynamic weights in the analog memory computing engines 3601, 3602, or 3604.

[0115] Figure 37 shows a portion of an example of the analog CIM engine 3700. Here, a 2x4 non-volatile memory cell array is shown. The memory cells operate in a subthreshold region and can store analog weights. Activation inputs are provided to each selected row on a word line or control gate line, and the memory cells within that row multiply their activation inputs by the stored analog weights and output a current representing the product to a bit line coupled to the column of each cell. The currents are then summed along the bit lines (output lines). The array output current is then converted by an ADC circuit (not shown) to generate digital output bits. The activation inputs can be provided as pulse width (PW) as the output of a fixed-bias 1-bit digital-to-analog converter or as the output of an n-bit DAC. Other examples of portions of the analog CIM engine are shown in Figures 9–13 and 22–33.

[0116] A portion of the analog CIM engine 3700 can also be used as analog memory weight storage. In this case, a word of memory cells (e.g., 64 or 128 cells from a selected row) is selected, and the output digital output bits from the ADC represent the weight values ​​stored by the portion of the analog CIM engine 3700.

[0117] Figure 38 shows a portion of an exemplary digital CIM engine 3800. The portion of the digital CIM engine 3800 comprises an array of current-based CIM SRAM memory cells 3801, 3802, 3803, and 3804 arranged in rows and columns. While the CIM SRAM memory cell 3801 will be described in detail, it should be understood that the other CIM SRAM memory cells 3801 have the same design. In the CIM SRAM memory cell 3801, when the weight stored in the SRAM is "1", the NMOS transistor 3816 turns on, and the current NC flows from transistor 3815 to transistor 3817 toward bit line BL0. When the weight stored in the SRAM is "0", the NMOS transistor 3816 turns off, and the current NC is prevented from flowing from transistor 3815 to transistor 3817 toward bit line BL0. The current NC is the effective value of the weight stored in the CIM SRAM cell.

[0118] During the operation of the digital CIM engine, an input is applied to the input line IN0. The SRAM memory cell 3801 performs multiplication of the input on IN0 with the stored weight. If IN0 is "1", the NMOS transistor 3817 turns on and flows a current NC (representing the stored weight value) to the bit line BL0; if IN0 is "0", the NMOS transistor 3817 turns off and no current NC flows to the bit line BL0.

[0119] If the stored weight is "1" and the input on the input line is "1", then NMOS transistors 3815, 3816, and 3817 are all on, and bit line BL0 receives current NC. If the stored weight is "0", or the input on the input line is "0", then bit line BL0 is disconnected from current NC and does not receive any current from the SRAM memory cell 3801.

[0120] CIM SRAM memory cells 3802, 3803, and 3804, as well as other CIM SRAM memory cells in the digital CIM engine, operate in the same manner as CIM SRAM memory cell 3801.

[0121] The bit lines of the digital CIM engine, such as BL0 and BL1, sum the currents of all CIM SRAM memory cells connected to them. This means that BL0 contains the sum of all currents (all NC currents with weight = "1") from all CIM SRAM memory cells in column 0, BL1 contains the sum of all currents from all CIM SRAM memory cells in column 1, and so on. This current can be converted into digital output bits by an ADC circuit or a multi-bit sense amplifier circuit.

[0122] Figure 39 shows a portion of another exemplary digital CIM engine 3900. The portion of the digital CIM engine 3900 comprises arrays of charge-based CIM SRAM memory cells 3901, 3902, 3903, and 3904 arranged in rows and columns.

[0123] CIM SRAM memory cell 3901 represents CIM SRAM memory cells 3902, 3903, and 3904, as well as other CIM SRAM memory cells in the digital CIM engine, and its operation is described here. SRAM memory cell 3901 comprises inverters 3911 and 3912 that form a latch, NMOS transistors 3913, 3914, 3916, 3917, and 3918, and a capacitor 3915. An amount of charge (representing a weight value) Q equal to C (capacitor capacitance value) × Vdds (the supply voltage of the SRAM memory cell) is stored in the capacitor 3915 within the SRAM cell. The latch formed by inverters 3911 and 3912 can store a value of "0" or "1" (=output of inverter 3912), where "0" means zero charge and "1" means the effective weight Q charge of SRAM memory cell 3901. When the output of inverter 3912 is "0", which means ground (0V), capacitor 3915 is charged to ground through transistor 3916, and therefore Q=0 (representing the weight of "0"). When the output of inverter 3912 is "1", for example =Vdds, capacitor 3915 is charged to Vdds through transistor 3916, and therefore Q=C×Vdds (representing the weight of "1"). When transistor 3916 is off (ENSB="0"), transistor 3917 is on (input IN0="1"), and transistor 3918 is on (ENS="1"), the stored charge is transferred to bit line BL0. In the case of the weight of "1", when input IN0="1" (meaning transistor 3917 is on), the charge Q (=C×Vdss) will be transferred to bit line BL0.

[0124] The weight is stored in the SRAM memory cell 3901 through a write operation. During the write operation, the word line WL0 is asserted, which turns on NMOS transistors 3913 and 3914. By driving BLS0B high and BLS0 low, "1" is stored in the latch, and by driving BLS0 high and BLS0B low, "0" is stored in the latch.

[0125] During the inference or read operation of the digital CIM engine, an input is applied to the input line IN0 and ENSB is asserted. The SRAM memory cell 3901 performs multiplication of the input on IN0 with the stored weight. If IN0 is "1", the NMOS transistor 3917 turns on, and if WLN0 is "0", the NMOS transistor 3917 turns off.

[0126] If the stored weight is "1" and the input INx on the input line is "1", then NMOS transistor 3916 is off and transistors 3917 and 3918 are on, so bit line BL0 will receive the charge from capacitor 3915. If the stored weight is "0", or if the input on input line INx0 is "0", then bit line BL0 will receive a charge of 0 and will not contain any charge component originating from SRAM memory cell 3801.

[0127] SRAM memory cells 3902, 3903, and 3904, as well as other SRAM memory cells in the digital CIM engine, operate in the same manner as SRAM memory cell 3901.

[0128] The bit lines of the digital CIM engine, such as BL0 and BL1, sum the charges of all SRAM memory cells connected to them. BL0 contains the sum of all charges output by all SRAM memory cells in column 0, BL1 contains the sum of all charges output by all SRAM memory cells in column 1, and so on. This summed charge can be converted into digital output bits by an ADC circuit as shown in Figures 44 and 46 below.

[0129] Figure 40 shows a portion of another exemplary digital CIM engine 4000. The portion of the digital CIM engine 4000 comprises a subarray of CIM digital cells, each CIM digital cell storing a 1-bit weight w. In this example, subarrays 4010-11 and 4010-12 are shown in detail. In the horizontal direction, the digital CIM engine 4000 comprises m subarrays (e.g., subarrays 4010-11, 4010-12, ..., 4010-1m in row 1). In the vertical direction, the digital CIM engine 4000 comprises n subarrays (e.g., subarrays 4010-11, ..., 4010-n1 in column 1).

[0130] Here, we will explain using subarray 4010-11 as an example. The considerations for subarray 4010-11 apply similarly to other subarrays. Subarray 4010-11 comprises an array of CIM digital cells, such as CIM digital cell 4001, arranged in rows and columns. In this example, subarray 4010-11 contains four rows and four columns of CIM digital cells, but it should be understood that subarray 4010-11 and other subarrays can each contain any number of rows and columns according to the same principle considered here, such as an 8x8 array accommodating 8-bit inputs and 8-bit weights (meaning that 1 bit is stored in each of the 8 CIM digital cells, and together they store an 8-bit weight), which instead produces a 16-bit output (because multiplying an 8-bit input by an 8-bit weight produces a 16-bit output). In this example, subarray 4010-11 implements a 4-bit input multiplied by 4-bit weights, with output DOUT[7:0] = IN[3:0] × W[3:0], where each row of the four CIM digital cells stores four weights W[3:0], and the four rows store the same weights W[3:0]. The MUX block is used to enable output from each subarray 4010x to the main output bus DOUTx.

[0131] The digital CIM engine 4000 receives inputs from multiple rows. In this example, subarray 4010-11 receives inputs IN[0], IN[1], IN[2], and IN[3] on its four rows. The 4-bit inputs are multiplied by a 4-bit weight W[3:0] stored in each row. Each digital cell, such as digital cell 4001, receives an input on its port I1, multiplies that input by a 1-bit weight value (W) stored in the digital cell, and adds to the resulting product any data received on its port I2 from a digital cell located in the row above it, and any carry bits received on its port CI from an adjacent digital cell located to its right in the same row. In the example shown, the leftmost column (Col3) represents the most significant bit of the weight, the column to its right (Col2) represents the next most significant bit of the weight, the next column to its right (Col1) represents the next most significant bit of the weight, and the last column (Col0) represents the least significant bit of the weight.

[0132] Each CIM digital cell, such as CIM digital cell 4001, includes a memory device such as an SRAM cell, latch, or register for storing weights W. Each digital cell, such as CIM digital cell 4001, also includes digital multiplication and addition logic. Inputs are received digitally by each row of digital devices in the I1 port of each CIM digital cell. The inputs received at port I1 are multiplied by the weights stored in the SRAM of the CIM digital cell, and the results are then added column by column and output. The output (O) of a particular CIM digital cell is provided as an input (I2) to the CIM digital cell located below that particular CIM digital cell in the same column, and the carry output (CO) from a particular CIM digital cell is provided as a carry input (CI) to the CIM digital cell located to its left in the same row, because that cell represents higher bits than that particular CIM digital cell.

[0133] Multiplexer block 4020-11 is used to enable output from subarray 4010-11 to the main output bus DOUTx in response to the enable signal EN0. Other subarrays have similar multiplexer blocks.

[0134] Figures 41A, 41B, and 41C show exemplary components that can be used within each CIM digital cell in Figure 40, such as CIM digital cell 4001.

[0135] Referring to Figure 41A, the multiplication logic cell 4101 receives two inputs I1 and I2 and outputs their product O according to the truth table shown in Table 9. Table 9: Truth table for multiplication logic cell 4101

[0136] [Table 9]

[0137] Referring to Figure 41B, the 2-bit adder logic cell 4102 receives inputs I1 and I2, as well as the carry input CI, and generates output O and carry output CO according to the truth table shown in Table 10. Table 10: Truth table for 2-bit adder logic cell 4102

[0138] [Table 10]

[0139] Referring to Figure 41C, the digital CIM cell 4103 stores the weight W in the SRAM cell 4104. The digital CIM cell 4103 uses the multiplication logic cell 4101 to multiply the received input I2 by W, and uses the 2-bit adder logic cell 4102 to add the resulting product P to the received inputs I1 and CI to generate outputs O and CO. In this way, each digital CIM cell 4103 performs a 1-bit multiplication operation (W × I2), adds the result to the received inputs (I1 and CI), and performs a vector × matrix multiplication operation using the stored digital value W.

[0140] Figure 42 shows a portion of another exemplary digital CIM engine 4200. The portion of the digital CIM engine 4200 comprises an array of blocks, each block comprising an array of multipliers and a shift and adder tree. In this example, blocks 4210-11, 4210-12, 4210-21, and 4210-22 are shown in detail. In the horizontal direction, the digital CIM engine 4200 comprises m blocks (blocks 4210-11, 4210-12, ..., 4212-1m, etc. in row 1). In the vertical direction, the digital CIM engine 4200 comprises n blocks (blocks 4210-11, 4210-21, ..., 4210-n1, etc. in column 1).

[0141] Here, we will explain using block 4210-11 as an example. The considerations for block 4210-11 apply similarly to the other blocks. Block 4210-11 comprises an array of multipliers, such as multiplier 4201, arranged in rows and columns. In this example, block 4210-11 has a 4x4 multiplier configuration, but it should be understood that block 4210-11 and all other blocks can instead have any number of rows and columns, such as 8x8 to accommodate 8-bit inputs and 8-bit weights producing a 16-bit output, according to the same principles considered here.

[0142] The digital CIM engine 4200 receives inputs in multiple rows. In this example, block 4210-11 receives inputs IN[0], IN[1], IN[2], and IN[3] on its four rows. Each multiplier, such as multiplier 4201, receives an input, multiplies the input by a 1-bit weight (W) stored in the multiplier, and outputs the product. The product is provided to the shift and adder tree 4202, which adds the product and performs shift operations as needed to reflect the fact that each row (IN[0], IN[1], IN[2], and IN[3]) represents a different digit in the binary input (IN[3:0]). That is, IN[0] is 2 0 IN[1] represents 2 1 IN[2] represents 2 2 IN[3] represents 2 3 This represents the multiplexer block 4203, which is used to enable output from each block, such as blocks 4210-4211, into the main output bus DOUTx in response to the enable signal EN0. Other blocks also have similar multiplexer blocks.

[0143] Figure 43 shows a shift and adder tree 4300, which is an example of an embodiment of the shift and adder tree 4202 used in Figure 42. Each multiplier, such as multiplier 4201 within a block such as blocks 4210-11, receives a 1-bit input, multiplies it by a 1-bit weight, and outputs a 1-bit value provided to the shift and adder tree 4202. For each row, the shift and adder tree 4300 receives four 1-bit values ​​and treats them as a single 4-bit value arranged in the order corresponding to columns D3, D2, D1, and D0, respectively. The 4-bit value for row 0 (receiving input IN[0]) is X4-0, the 4-bit value for row 1 (receiving input IN[1]) is X4-1, the 4-bit value for row 2 (receiving input IN[2]) is X4-2, and the 4-bit value for row 3 (receiving input IN[3]) is X4-3.

[0144] Shift and adder 4301 first adds X4-0 to X4-1 (shifting the digit of X4-1 one place to the left due to the fact that row 1 represents the value of the input digit to the left of row 0; for example, if X4-1 is 1010, the shifted version will be 10100) to produce a 6-bit value. Shift and adder 4302 adds its 6-bit value to the shifted version of X4-2 (X4-2 is shifted two places) to produce a 7-bit value. Shift and adder 4303 then adds its 7-bit value to X4-3 (X4-3 is shifted three places) to produce an 8-bit value representing the sum of the products received from the block's multiplier.

[0145] Figure 44 shows a shift and adder tree 4400, which is an example of an embodiment of the shift and adder tree 4202 used in Figure 42. Each multiplier, such as multiplier 4201 within a block such as blocks 4210-11, receives a 1-bit input, multiplies it by a 1-bit weight, and outputs a 1-bit value provided to the shift and adder tree 4202. For each row, the shift and adder tree 4400 receives four 1-bit values ​​and treats them as a single 4-bit value arranged in the order corresponding to columns D3, D2, D1, and D0, respectively. The 4-bit value for row 0 (receiving input IN[0]) is X4-0, the 4-bit value for row 1 (receiving input IN[1]) is X4-1, the 4-bit value for row 2 (receiving input IN[2]) is X4-2, and the 4-bit value for row 3 (receiving input IN[3]) is X4-3.

[0146] The shift and adder 4401 first adds X4-0 to X4-1 (shifting the digit of X4-1 one place to the left due to the fact that row 1 represents the value of the input digit to the left of row 0; for example, if X4-1 is 1010, the shifted version will be 10100) to produce a 6-bit value X6. The shift and adder 4302 then adds the shifted version of X4-2 (X4-2 is shifted two places) to the shifted version of X4-3 (X4-3 is shifted three places) to produce a 7-bit value X7. The shift and adder 4403 then adds its X6 and X7 together (without shifting) to produce an 8-bit value X8 representing the sum of the products received from the block's multiplier.

[0147] Another application of the digital CIM array is for floating-point numbers, where the first array is used for the exponent and the second array for the mantissa (fractional part), and appropriate realignment and recombination of the array outputs are performed to reconstruct the final floating-point number.

[0148] Figure 45 shows a portion of the dynamic weight engine 4500. The dynamic weight engine 4500 comprises CIM dynamic weight cells 4501, 4502, 4503, and 4504 arranged in rows and columns.

[0149] CIM dynamic weight cell 4501 represents CIM dynamic weight cells 4502, 4503, and 4504, as well as other CIM memory cells in the dynamic weight engine, and its operation is described here. CIM dynamic weight cell 4501 comprises NMOS transistors 4511, 4512, 4514, and 4515, and capacitor 4513. CIM dynamic weight cell 4501 can store weights that can be dynamically changed by input modifications. CIM dynamic weight cell 4501 is selected when WL0 and WBL0 are asserted. When WL0 is asserted, NMOS transistors 4511 and 4514 are turned on. When WBL0 is asserted, NMOS transistor 4512 is turned on. The voltage W representing the weight applied by the CIM dynamic weight cell 4501 is applied to WWL0 and transferred to the gate of the NMOS transistor 4515, and stored by capacitor 4513 coupled between the gate of the NMOS transistor 4515 and SL0, which is the source line of row 0. The NMOS transistor 4515 draws current from the bit line BL0, and the drawn current is a function of the voltage W.

[0150] CIM dynamic weight cells 4502, 4503, 4504, and other CIM dynamic weight cells within the dynamic weight engine operate in the same manner as CIM dynamic weight cell 4501.

[0151] The bit lines of the CIM dynamic weight engines, such as BL0 and BL1, sum the currents drawn in by all the CIM dynamic weight cells connected to them. This means that BL0 contains the sum of all currents drawn in by all the CIM dynamic weight cells in column 0, BL1 contains the sum of all currents drawn in by all the CIM dynamic 8 cells in column 1, and so on. This current can be converted into digital output bits by an ADC circuit, such as those shown in Figures 47 and 49 below.

[0152] Figure 46 shows a portion of the dynamic weight engine 4600. The dynamic weight engine 4600 comprises CIM dynamic weight cells 4601, 4602, 4603, and 4604 arranged in rows and columns.

[0153] CIM dynamic weight cell 4601 represents CIM dynamic weight cells 4602, 4603, and 4604, as well as other CIM dynamic weight cells in the dynamic weight engine, and its operation is described here. CIM dynamic weight cell 4601 comprises NMOS transistors 4611, 4612, 4613, 4615, and 4616, and capacitor 4614. CIM dynamic weight cell 4601 can store weights that can be dynamically changed by input modifications. CIM dynamic weight cell 4601 is selected when WL0 and WBL are asserted. When WL0 is asserted, NMOS transistors 4611 and 4615 are turned on. When WBL is asserted, NMOS transistor 4613 is turned on. The voltage W representing the weight applied by the CIM dynamic weight cell 4601 is applied to WWL0 and transferred to the gate of the NMOS transistor 4616, and stored by capacitor 4614 coupled between the gate of the NMOS transistor 4616 and SL0, which is the source line of row 0. The NMOS transistor 4616 draws current from the bit line BL0, and the drawn current is a function of the voltage W.

[0154] CIM dynamic weight cells 4602, 4603, 4604, and other CIM dynamic weight cells within the dynamic weight engine operate in the same way as CIM dynamic weight cell 4601.

[0155] The bit lines of the CIM dynamic weight engines, such as BL0 and BL1, sum the currents drawn in by all the CIM dynamic weight cells connected to them. BL0 will contain the sum of all currents drawn in by all the CIM dynamic weight cells in column 0, and so on. This means that BL1 will contain the sum of all currents drawn in by all the CIM dynamic 8 cells in column 1, and so on. This current can be converted into digital output bits by an ADC circuit, such as those shown in Figures 47 and 49 below.

[0156] Figure 47 shows an exemplary integrating ADC 4700 used to convert the charge stored in a portion of the cells of the digital CIM engine 3900 in Figure 39 into digital pulses or digital output bits. The integrating ADC 4700 converts the analog output charge in the neuron output block (charge stored in capacitor 4702CINT) into digital pulses whose width is proportional to the magnitude of the analog output current in the neuron output block. Capacitor 4702 represents all capacitors from selected CIM volatile SRAM memory cells that are summed up (connected in parallel through a pass transistor) in Figure 39. The ADC 4700 comprises a reference current 4707, an operational amplifier 4701, a comparator 4704, an AND gate 4740, and a counter 4720. The charges of the individual capacitors in the CIM volatile SRAM memory cells are summed up and then reconfigured to form an integrating capacitor 4702 across operational amplifier 4701. The reference current 4707 discharges the total amount of charge stored in the integrating capacitor 4702, and the counter 4720 generates pulses until the discharge is complete. As shown in Figure 48, the pulses represent digital output bits.

[0157] Figure 48 shows the analog CIM engine in Figure 37, the digital CIM engine 3800 in Figure 38, the dynamic weight engine 4500 in Figure 45, and the integrating ADC 4800 used to convert current received from one or more columns in the dynamic weight engine 4600 in Figure 46 into digital pulses or digital output bits.

[0158] The ADC4800 has a current of I NEU This is converted into a digital pulse EC whose width changes in proportion to the magnitude of the current. The integrator, comprising an integrating operational amplifier 4801 and an integrating capacitor 4802, is oriented with respect to a reference current IREF provided by the current source 4807. NEU Integrate 4806.

[0159] Optionally, the current source 4807 has a temperature coefficient of 0, or the neuron current I NEU It can be equipped with a bandgap filter having a temperature coefficient that tracks the temperature. NEU The temperature coefficient for tracking can be obtained from a lookup table (not shown) containing values ​​determined during the testing phase.

[0160] During the initialization phase, switch 4808 is closed. Then, the inputs to Vout 4803 and the negative terminal of op-amp 4801 will be equal to VREF. Subsequently, switch 4808 is opened and switch S2 is closed, while switch S1 remains open, and a constant reference current IREF 4807 is up-integrated for a certain period tref. During a certain period tref, Vout rises, and its slope reflects the value of the constant reference current IREF 4807. Subsequently, switch S2 is opened and switch S1 is closed, and for a period tmeas, the neuron current I NEU 4806 is down-integrated over the period tmeas (during which Vout decreases), where tmeas is the time for down-integrating Vout to VREF, as indicated by the change in the output of comparator 4804.

[0161] The output of the EC4805 will be high when VOUT > VREFV, and low otherwise. Therefore, the EC4805 generates a pulse whose width reflects the period tmeas, and tmeas is the current I NEU It is proportional to 4806. Therefore, the output neuron current I NEUThe 4806 is converted to a digital pulse EC4805, and the width of the digital pulse EC4805 is the output neuron current I NEU It changes in proportion to the size of 4806.

[0162] current I NEU The formula for 4806 is = tmeas / tref × IREF. For example, for a desired 10-bit output bit resolution, tref is equal to 1024 clock cycles. The period tmeas is I NEU Depending on the values ​​of 4806 and Iref, the neuron current I varies from a period equal to 0 clock cycles to 1024 clock cycles. NEU 4806 affects charging speed and tilt.

[0163] Optionally, the output pulse EC4805 can be converted into a series of pulses of uniform period for transmission to the next block of circuitry, such as the input block of the CIM engine. At the start of period tmeas, the output EC4805 is input to the AND gate 4840 using the reference clock 4841. The output will become a pulse sequence 4842 (the pulse frequency in pulse sequence 4842 is the same as the frequency of clock 4841) for the period VOUT > VREF. The number of pulses is proportional to the period tmeas, and the period tmeas is proportional to the current I NEU It is proportional to 4806.

[0164] Optionally, pulse sequence 4843 can be input to counter 4820, which counts the number of pulses in pulse sequence 4842 and the neuron current I NEU This will produce a count value 4821, which is a digital count of the number of pulses in pulse sequence 4842, directly proportional to 4806. The count value 4821 contains a set of digital bits. In another example, the integrating ADC 4800 will produce a neuron current I NEU 4806 can be converted into pulses, and the pulse width is the neuron current I NEUIt is inversely proportional to the magnitude of the 4806. This inversion can be done digitally or analogously and can be converted into a series of pulses or digital bits for output to a subsequent circuit.

[0165] Figure 49A shows an exemplary output circuit 4900 capable of converting array current into digital output bits. The output circuit 4900 comprises a current-to-voltage converter (ITV) 4901 and an analog-to-digital converter (ADC) 4902. The ITV 4901 converts the array current into a voltage, which is then digitized by the ADC 4902. The ADC 4902 may be a successive approximation (SAR) ADC.

[0166] Figure 49B shows an exemplary output circuit 4950, comprising an ITV4951 that receives a differential input and generates a differential output, and an ADC4952 that receives a differential input from the differential output of the ITV4951 and generates a single-ended digital output. Examples of implementations of current-to-voltage converters and analog-to-digital converters are described in U.S. Patent Application No. 17 / 521,772, which is incorporated herein by reference.

[0167] Other examples of analog and digital CIM engines, though not limited to them, may utilize NAND memory, resistive RAM (ReRAM), magnetic RAM (MRAM), or dynamic RAM (DRAM).

[0168] It should be noted that, as used herein, the terms “over” and “on” both encompass “directly” (no intermediate material, element, or gap is located between them) and “indirectly to” (intermediate material, element, or gap is located between them). Similarly, the term “adjacent” includes “directly adjacent” (no intermediate material, element, or gap is located between them) and “indirectly adjacent” (intermediate material, element, or gap is located between them); “attached” includes “directly attached” (no intermediate material, element, or gap is located between them) and “indirectly attached to” (intermediate material, element, or gap is located between them); and “electrically coupled” includes “directly electrically coupled” (no intermediate material or element electrically connecting the elements together between them) and “indirectly electrically coupled to” (intermediate material or element electrically connecting the elements together between them). For example, forming an element "on top of a substrate" may include forming the element directly on the substrate without any intermediate materials / elements between them, and forming the element indirectly on the substrate with one or more intermediate materials / elements between them.

Claims

1. It is a system, An analog memory-based computation engine for performing calculations in the first layer of a neural network, A system comprising: a digital memory computing engine for performing operations in a second layer of the neural network, which is different from the first layer.

2. The system according to claim 1, further comprising a system bus coupled to the analog memory computing engine and the digital memory computing engine.

3. The system according to claim 1, wherein the analog memory computing engine comprises a plurality of non-volatile memory cells arranged in rows and columns.

4. The system according to claim 3, wherein the non-volatile memory cell is a stacked gate flash memory cell.

5. The system according to claim 3, wherein the non-volatile memory cell is a split-gate flash memory cell.

6. The system according to claim 1, wherein the digital memory computing engine comprises a plurality of static random access memory (SRAM) cells arranged in rows and columns.

7. The system according to claim 1, wherein the digital memory computing engine comprises a plurality of CIM digital cells arranged in rows and columns.

8. The system according to claim 7, wherein each of the plurality of CIM digital cells comprises a multiplication logic cell and a 2-bit adder logic cell.

9. The system according to claim 7, wherein the digital memory calculation engine comprises a shift and adder tree coupled to the plurality of CIM digital cells.

10. It is a system, An analog memory-based computation engine for performing calculations in the first layer of a neural network, A digital memory-based computation engine for performing calculations in the second layer of the neural network, The neural network comprises a dynamic weight engine for performing calculations in the third layer of the neural network, A system in which the first layer, the second layer, and the third layer are different layers in the neural network.

11. The system according to claim 10, comprising a system bus coupled to the analog memory-based calculation engine, the digital memory-based calculation engine, and the dynamic weight engine.

12. The system according to claim 10, wherein the analog memory computing engine comprises a plurality of non-volatile memory cells arranged in rows and columns.

13. The system according to claim 12, wherein the non-volatile memory cell is a stacked gate flash memory cell.

14. The system according to claim 12, wherein the non-volatile memory cell is a split-gate flash memory cell.

15. The system according to claim 10, wherein the digital memory computing engine comprises a plurality of static random access memory (SRAM) cells arranged in rows and columns.

16. The system according to claim 10, wherein the digital memory computing engine comprises a plurality of CIM digital cells.

17. The system according to claim 16, wherein each of the plurality of CIM digital cells comprises a multiplication logic cell and a 2-bit adder logic cell.

18. The system according to claim 16, wherein the digital memory calculation engine comprises a shift and adder tree coupled to the plurality of CIM digital cells.

19. It is a method, The steps include: using a digital memory computing engine to perform a vector × matrix multiplication operation in the first layer of the neural network; A method comprising the step of performing a vector × matrix multiplication operation in a second layer of the neural network, different from the first layer, using an analog memory-based computation engine.

20. The method according to claim 19, wherein the analog memory computing engine comprises a plurality of non-volatile memory cells arranged in rows and columns.

21. It is a method, The steps include: using a digital memory computing engine to perform a vector × matrix multiplication operation in the first layer of the neural network; The steps include: using an analog memory-based computation engine to perform a vector × matrix multiplication operation in the second layer of the neural network; The process includes the step of performing a vector × matrix multiplication operation in the third layer of the neural network using a dynamic weight engine, A method wherein the first layer, the second layer, and the third layer are different layers in the neural network.

22. The method according to claim 21, wherein the analog memory computing engine comprises a plurality of non-volatile memory cells arranged in rows and columns.

23. It is a method, The steps include: performing a vector × matrix multiplication operation in the first layer of a neural network using one of the following: an analog memory-based computation engine, a digital memory-based computation engine, and a dynamic weight engine; A method comprising the step of performing a vector × matrix multiplication operation in a second layer of a neural network using another of the analog memory computing engine, the digital memory computing engine, and the dynamic weight engine.

24. It is a method, A method comprising the step of storing weights received from an analog memory-based computation engine in one or more of the following: a digital memory-based computation engine, a digital computation engine, and a dynamic weight engine.

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