Device for precise timestamping of the start of Ethernet frames

Abstract

Systems, devices, products, and methods for precise timestamping of Ethernet frames are described. In some implementations, a device may include a network interface circuit element and a logic circuit element configured to execute an instruction (500) which causes the logic circuit element to determine a first delay introduced by a physical coding sublayer circuit element in a first time (502), adjust a first timestamp associated with and transmitted with a first transmission based on the first delay (504), determine a second delay introduced by a physical coding sublayer circuit element in a second time, which is different from the first delay (502), adjust a second timestamp associated with and transmitted with a second transmission based on the second delay (506) (504).

Description

Technical Field

[0001] This description generally relates to network communication, and more particularly to an apparatus for precise timestamping of the start of an Ethernet frame.

Background Art

[0002] Networked devices often rely on precise time synchronization among multiple devices to facilitate synchronization of the timing of actions. For example, some systems utilize a master clock to synchronize clocks among multiple slave devices. Some such examples communicate the master clock time using messaging, and the slave devices can synchronize their clocks to the master clock time.

Brief Description of the Drawings

[0003] [Figure 1] It is a block diagram of an exemplary environment where a slave device synchronizes time with a master time server.

[0004] [Figure 2] It illustrates exemplary messaging for time synchronization, including adjustment of timestamps to account for variable delays.

[0005] [Figure 3A] It is a block diagram of an exemplary transmission component of the master time server of FIG. 1. [Figure 3B] It is a block diagram of an exemplary receiving component of the slave device of FIG. 1.

[0006] [Figure 4] It is a block diagram of an exemplary implementation of an Ethernet physical layer (PHY) including an egress tracking circuit and an ingress tracking circuit.

[0007] [Figure 5]This is a flowchart illustrating exemplary machine-readable instructions and / or exemplary operations that may be executed, instantiated, and / or performed by programmable circuit elements to implement the egress time correction circuit elements and / or ingress time correction circuit elements of Figure 1 and / or Figure 3. [Figure 7] This is a flowchart illustrating exemplary machine-readable instructions and / or exemplary operations that may be executed, instantiated, and / or performed by programmable circuit elements to implement the egress time correction circuit elements and / or ingress time correction circuit elements of Figure 1 and / or Figure 3. [Figure 8] This is a flowchart illustrating exemplary machine-readable instructions and / or exemplary operations that may be executed, instantiated, and / or performed by programmable circuit elements to implement the egress time correction circuit elements and / or ingress time correction circuit elements of Figure 1 and / or Figure 3. [Figure 12] This is a flowchart illustrating exemplary machine-readable instructions and / or exemplary operations that may be executed, instantiated, and / or performed by programmable circuit elements to implement the egress time correction circuit elements and / or ingress time correction circuit elements of Figure 1 and / or Figure 3. [Figure 14] This is a flowchart illustrating exemplary machine-readable instructions and / or exemplary operations that may be executed, instantiated, and / or performed by programmable circuit elements to implement the egress time correction circuit elements and / or ingress time correction circuit elements of Figure 1 and / or Figure 3.

[0008] [Figure 6A] This is a block diagram of an example implementation of the Physical Coding Sublayer (PCS). [Figure 6B] This is a block diagram of an example implementation of the Physical Coding Sublayer (PCS).

[0009] [Figure 9] The various variable delays introduced by the physical coding sublayer during time synchronization are illustrated. [Figure 10]The various variable delays introduced by the physical coding sublayer during time synchronization are illustrated. [Figure 11] The various variable delays introduced by the physical coding sublayer during time synchronization are illustrated. [Figure 13] The various variable delays introduced by the physical coding sublayer during time synchronization are illustrated.

[0010] [Figure 15] This is a block diagram of an exemplary processing platform including programmable circuit elements structured to execute, instantiate, and / or implement the machine-readable instructions of Figures 5, 7, 8, 12, and 14, and / or perform the operations of Figures 5, 7, 8, 12, and 14, in order to implement the egress time correction circuit elements 108, 124, 312, 404 of Figures 1, 3, and / or Figure 4, and / or the ingress time correction circuit elements 112, 120, 330, 412 of Figures 1, 3, and / or Figure 4.

[0011] [Figure 16] Figure 15 is a block diagram illustrating the implementation of an example programmable circuit element.

[0012] [Figure 17] Figure 15 is a block diagram of another example implementation of a programmable circuit element.

[0013] [Figure 18]Software, instructions, and / or firmware (e.g., corresponding to the machine-readable instructions of FIGS. 5, 7, 8, 12, and 14) are distributed to client devices associated with end users and / or consumers (e.g., for license, sale, and / or use), to client devices associated with retailers (e.g., for sale, resale, license, and / or sublicense), and / or to client devices associated with original equipment manufacturers (OEMs) of counterparty trademark products (e.g., for inclusion in products to be distributed to retailers and / or other end users such as direct purchasing customers), in an exemplary software / firmware / instructions distribution platform (e.g., one or more servers).

[0014] Generally, the same reference numbers are used throughout the drawings and the accompanying written description to refer to the same or similar parts.

Best Mode for Carrying Out the Invention

[0015] In a system that uses time synchronization, a master time server sends a message with a timestamp, and the timestamp enables a slave device to determine an adjustment to the slave device's clock while eliminating communication latency. Such an approach can succeed when the communication latency is consistent. However, when the latency in the communication process is variable, such an approach cannot determine an accurate synchronization time. For example, after a timestamp is embedded in a message, the time required to encode such a message and / or the time required to decode the message may be of variable length. In such an example, the slave device cannot determine an accurate adjustment to its clock due to such variability.

[0016] The methods and apparatuses described herein facilitate precise time synchronization by adjusting time values (e.g., timestamps, clock times, time serial numbers, etc.) associated with messages such as time synchronization messages to account for variable delays. For example, the delay associated with encoding time during message transmission can be predicted, and the timestamp inserted into the message can be adjusted to compensate for the predicted delay. In other examples, the delay associated with decoding the message can be predicted, and the timestamp can be adjusted accordingly. By adjusting the timestamp to account for variable encoding and / or decoding delays, the clock of the slave device can be more accurately adjusted to synchronize more closely with the master time server.

[0017] FIG. 1 is a block diagram of an exemplary environment 100 that includes a master time server 104 and a slave device 116 that can communicate via a network 114. The master time server 104 includes a transmission circuit element 106 that includes an egress time correction circuit element 108 and a reception circuit element 110 that includes an ingress time correction circuit element 112. The network 114 communicatively couples the master time server 104 to the slave device 116. The slave device 116 includes a reception circuit element 118 that includes an ingress time correction circuit element 120 and a transmission circuit element 122 that includes an egress time correction circuit element 124. The master time server 104 is connected to the network 114 via the transmission circuit element and the reception circuit element 110. The slave device 116 is coupled to the network 114 (and thus to the master time server 104 via the network 114) via the reception circuit element 118 and the transmission circuit element 122.

[0018] The master time server 104 provides messaging to facilitate time synchronization between one or more slave devices, such as the slave device 116. The master time server 104 can be any type of computing device, such as a server, client, in-vehicle controller, or Internet of Things device. To facilitate time synchronization, the master time server 104 includes a transmitting circuit element 106 for sending time synchronization messages (e.g., synchronization and delay response messages) and a receiving circuit element 110 for receiving time synchronization messages (e.g., delay request messages). The master time server 104 may support time synchronization based on messaging described in any version of the Institute of Electrical and Electronics Engineers (IEEE) 1588 – Standard for a Precision Clock Synchronization Protocol for Networked Measurement and Control Systems.

[0019] In one example, the slave device 116 in Figure 1 is a controller in an automotive control system. Alternatively, the slave device 116 could be any other type of device that is required to synchronize one or more clocks with the master time server 104.

[0020] In one example, the transmitting circuit elements 106 and 122, and the receiving circuit elements 110 and 118, constitute an Ethernet PHY, each including a physical coding sublayer that performs coding for messages to be transmitted and decoding for received messages, respectively. The physical coding sublayer, and / or any other components that perform coding and / or decoding, may introduce errors that vary over time and / or per message. For example, a first delay may be associated with the transmission of a first message, and a second delay, different from the first, may be associated with the transmission of a second message. Therefore, when time synchronization is performed without considering the variability of such coding and decoding delays, the adjustment of the clock of the slave device 116 may result in clock timing that is not synchronized with the master time server 104. Accordingly, the transmitting circuit element 106 and the transmitting circuit element 122 each include an egress time correction (ETC) circuit element 108 and an egress time correction (ETC) circuit element 124, respectively, and the receiving circuit element 110 and the receiving circuit element 118 each include an ingress time correction (ITC) circuit element 112 and an ingress time correction circuit element 120.

[0021] Time correction circuit elements 108, 112, 120, and 124 monitor and / or detect the state of the physical coding sublayer (or other encoder / decoder) to determine the delay that will result from the encoding or decoding of the message. For example, time correction circuit elements 108, 112, 120, and 124 include latency tracking circuit elements for tracking the state of the physical coding sublayer and latency correction circuit elements for adjusting the generated timestamp to account for the latency resulting from encoding or decoding. The state of the physical coding sublayer may include the timing and / or phase of one or more clock signals of the physical coding sublayer, the state of the communication path and / or multiplexer of the physical coding sublayer, the communication state of blocks in a communication frame, and so on.

[0022] Network 114, in one example, connects the master time server 104 to the slave device 116 via the Ethernet protocol. Network 114 can also connect any number of other devices. Furthermore, network 114 can utilize any other type of network protocol supported by the master time server 104 and the slave device 116. Network 114 can be implemented by network circuit elements for connecting multiple devices, such as switches, hubs, routers, and gateways. Alternatively, network 114 may be a cable (e.g., an Ethernet cable) connecting the master time server 104 to the slave device 116.

[0023] Figure 2 illustrates an illustrative message diagram 200 showing the operation of the device in Figure 1. According to Figure 2, the master time server 104 sends a synchronization message 202 to the slave device 116 via the transmitting circuit element 106, and the slave device 116 receives the synchronization message 202 via the receiving circuit element 118. The slave device 116 determines a timestamp t2 as the time after the message has been received and decoded. The ingress time correction circuit element 120 determines an adjusted time t2', which is a timestamp t2 adjusted to compensate for the variable delay introduced by decoding the synchronization message 202.

[0024] The egress time correction circuit element 108 adjusts the timestamp t1, which is the timestamp assigned to the synchronization message 202, to compensate for the variable delay in encoding that occurs after the timestamp t1 is determined. The adjusted timestamp t1' is sent to the slave device 116 via the follow-up message 204. The timestamp t1' may also or alternatively be included in the synchronization message 202.

[0025] Next, the slave device 116 sends a delay request message 206 to the master time server 104. The egress time correction circuit element 124 determines an adjusted timestamp t3' based on the timestamp t3 determined before the transmitting circuit element 122 encodes the delay request message 206, in order to compensate for the variable delay caused by encoding. The master time server 104 determines an adjusted timestamp t4' based on the timestamp t4 determined after the receiving circuit element 112 decodes the delay request message 206, in order to compensate for the variable delay introduced by decoding. The master time server 104 sends a delay response message 208 to the slave device 116 in order to send the adjusted timestamp t4' to the slave device 116.

[0026] Next, the ingress time correction circuit element 120 utilizes the determined adjusted timestamp to determine the clock adjustment for the clock of the slave device 116. According to such examples, the clock adjustment is performed as follows: As determined in TIFF2026511572000002.tif9128, and assuming that the transmission latency between the master time server and the slave time server is fixed, the transmission delay is eliminated by this formula, and therefore the resulting value is the time difference between the clock of the master time server 104 and the clock of the slave device 116. Accordingly, the ingress time correction circuit element 120 adjusts the clock timing to eliminate this difference and synchronize the clocks.

[0027] Figure 3A is a block diagram of an illustrative implementation of the transmitting circuit element 106 of the master time server 104 in Figure 1, and Figure 3B is a block diagram of an illustrative implementation of the receiving circuit element 118 of the slave device 116 in Figure 1. Although the transmitting circuit element 106 is shown for illustrative purposes, the illustrated block may also implement the transmitting circuit element 122 of the slave device 116. Similarly, although the receiving circuit element 118 is shown in Figure 3B, the corresponding block may also implement the receiving circuit element 110 of the master time server 104.

[0028] The transmitting circuit element 106 includes an ingress-side media access control (MAC) interface 302, a timestamp assignment circuit element 304, a clock 306, an egress-side physical coding sublayer (PCS) circuit element 308, a physical media attachment 310, and an egress time correction circuit element 312 which includes an egress latency tracking circuit element (ELTC) 314 and an egress latency correction circuit element (ELCC) 316.

[0029] The ingress-side MAC interface 302 receives data for transmission (e.g., time-synchronized messages) from a computing circuit element that generates and / or relays such data. The ingress-side MAC interface 302 is connected to a timestamping circuit element 304. The timestamping circuit element 304 is connected to a clock 306, an egress-side PCS 308, and an ELCC 316. The egress-side PCS 308 is connected to a physical media connector 310 and an ELTC 314. The physical media connector 310 is connected to a slave device 116 (e.g., via a network, cable, etc.).

[0030] When data is received by the ingress-side MAC interface 302, the timestamping circuit element 304 determines the current timestamp from the clock 306. The ELTC314 of the egress time correction circuit element 312 determines the state of the egress-side PCS308, determines the estimated coding delay based on the state, and provides the estimated coding delay to the ELCC316. The various states that can be detected are described in relation to Figures 6A to 14.

[0031] The ELCC316 receives the current timestamp from the timestamping circuit element 304 and adjusts the timestamp to compensate for the estimated coding delay. For example, the ELCC316 adds a delay to the timestamp to determine an adjusted timestamp that is expected to offset the variable portion of the delay introduced by the coding process. The ELCC316 may also add a known constant delay to the timestamp to compensate for a known transmission delay when the delay is constant and known. The ELCC316 provides the adjusted timestamp to the timestamping unit 304 to include the adjusted timestamp in the transmission (e.g., insert the timestamp into a time-synchronized message) (e.g., instead of the original current timestamp).

[0032] The egress-side PCS308 encodes the data, and the physical media connection unit 310 transmits the encoded data to the slave device 116.

[0033] The receiving circuit element 118 includes a physical medium connection unit 318, an ingress-side PCS 320, a timestamp assignment unit 324, a clock 326, an egress-side MAC interface 328, and an ingress time correction circuit element 330 which includes an ingress latency tracking circuit element (ILTC) 332 and an ingress latency correction circuit element (ILCC) 334.

[0034] The physical media connection unit 318 receives data from the physical media (for example, the physical media connecting the slave device 116 to the master time server 104). The physical media connection unit 318 is connected to the ingress-side PCS 320. The ingress-side PCS 320 is connected to the time stamping unit 324 and the ILTC 332. The time stamping unit 324 is connected to the clock 326, the egress-side MAC interface 328, and the ILCC 334. The egress-side MAC interface 328 provides the decoded received data to other components of the slave device 116.

[0035] When data is received by the physical media connection unit 318, the physical media connection unit 318 provides the data to the ingress PCS 320. The ingress PCS decodes the received data (e.g., a time-synchronized message) and provides the decoded message to the timestamping unit 324. The ILTC 332 determines the status information of the ingress PCS 320 and uses this status information to determine the expected variable delay for the decoding process. The ILCC 334 receives the current timestamp for the reception time from the clock 326 via the timestamping unit 324 and adjusts the time based on the variable latency determined by the ILTC 332. The ILCC 334 provides the adjusted timestamp to the timestamping unit 324. The timestamping unit 324 provides the decoded received data, along with the received adjusted timestamp, to the egress MAC interface 328.

[0036] Figure 4 is a block diagram of an exemplary Ethernet PHY 400. The Ethernet PHY 400 includes a transmit PCS 402, which includes an egress time correction circuit element 404 comprising an ELTC 406 and an ELCC 408. The PHY 400 also includes a receive PCS 410, which includes an ingress time correction circuit element 412 comprising an ILCC 414 and an ILTC 416.

[0037] The Ethernet PHY 400 may implement a transmit circuit element 106 and a receive circuit element 110, and / or a receive circuit element 118 and a transmit circuit element 122. The Ethernet PHY 400 may implement the transmit circuit element 106 and / or the receive circuit element 118 shown in Figures 3A and 3B. In one example, ELTC 406 is implemented by ELTC 314, and ELCC 408 is implemented by ELCC 316. In this example, the egress time correction circuit element 404 is implemented by the egress time correction circuit element 312 in Figure 3A, and / or the ingress time correction circuit element 412 is implemented by the ingress time correction circuit element 330 in Figure 3B. Also in this example, ILCC 414 is implemented by ILCC 334, and ILTC 416 is implemented by ILTC 332.

[0038] Following these examples, the ELTC406 is implemented within the transmitting PCS402 and connected to the ELCC408, which is implemented as a separate circuit element from the ELTC406. Similarly, the ILTC416 is implemented within the receiving PCS410 and connected to the ILCC414, which is implemented as a separate circuit element from the ILTC416. Alternatively, any other combination of components within the PCS and / or components separate from the PCS may be used.

[0039] The egress time correction circuit elements 108, 124, 312, 404, and / or the ingress time correction circuit elements 112, 120, 330, 412 of Figures 1, 3, and / or Figure 4 can be instantiated by a programmable circuit element such as a central processing unit (CPU) that executes a first instruction (e.g., creating instances to exist for any length of time, instances to materialize, instances to implement, etc.). The egress time correction circuit elements 108, 124, 312, 404, and / or the ingress time correction circuit elements 112, 120, 330, 412 can be instantiated by (1) application-specific integrated circuits (ASICs) and / or (2) field-programmable gate arrays (FPGAs) that are structured and / or configured in response to the execution of a second instruction to perform an operation corresponding to a first instruction (e.g., creating instances to exist for any length of time, instances to materialize, instances to implement, etc.). Therefore, some or all of the circuit elements in Figures 1, 3, and / or 4 may be instantiated at the same time or at different times. Some or all of the circuit elements in Figures 1, 3, and / or 4 may be instantiated in one or more threads that run concurrently and / or sequentially on hardware, for example.

[0040] Furthermore, some or all of the circuit elements in Figures 1, 3, and / or 4 may be implemented by microprocessor circuit elements that execute instructions and / or FPGA circuit elements that perform operations, in order to implement one or more virtual machines and / or containers. As used herein, the phrase "a logic circuit element is configured to execute instructions, which cause the logic circuit element to perform an action" and its equivalents mean that a logic circuit element can read instructions and execute instructions to perform an action (e.g., a processor executing machine-readable instructions), and / or that a logic circuit element can be configured with instructions (e.g., instructions used to program embedded devices, instructions used to implement ASICs, instructions used to configure FPGAs, etc.).

[0041] The egress time correction circuit elements 108, 124, 312, and 404 in Figures 1, 3, and / or 4 are instantiated by programmable circuit elements that execute egress time correction commands and / or are configured to perform operations such as those represented by the flowcharts in Figures 5, 7, 8, 12, and 14.

[0042] The egress time correction circuit elements 108, 124, 312, and 404 in Figures 1, 3, and / or 4 include means for correcting timestamps to adjust for variable delays in encoding. The means for correction can be implemented by the egress time correction circuit elements 108, 124, 312, and 404 in Figures 1, 3, and / or 4. The egress time correction circuit elements 108, 124, 312, and 404 in Figures 1, 3, and / or 4 can be instantiated by programmable circuit elements, such as the programmable circuit element 1512 in Figure 15. For example, the egress time correction circuit elements 108, 124, 312, and 404 in Figures 1, 3, and / or 4 can be instantiated by the microprocessor 1600 in Figure 16, which executes machine-executable instructions, such as those implemented in Figures 5, 7, 8, 12, and 14.

[0043] The exemplary Ethernet PHY 400 also includes a medium-independent interface 420 (e.g., a reduced gigabit medium-independent interface) for connecting the Ethernet PHY 400 to a computing device (e.g., via an interface) in a communicative manner. The medium-independent interface 420 is also connected to the exemplary transmit PCS 402 (for transmitting communications from the transmit PCS 402 to the network) and to the exemplary receive PCS 410 (for receiving communications from the network by the receive PCS 402). The medium-independent interface 420 is further connected to a set of medium-independent registers 422 for storing various control settings, parameters, and management values.

[0044] The exemplary Ethernet PHY 400 includes a PHY control unit 424, which is connected to a medium-independent register 422, a transmit PCS 402, a receive PCS 404, a physical medium connection (PMA) transmit block 426, and a PMA receive block 428. The PHY control unit 424 commands the operation of the connected blocks and controls the operation of the Ethernet PHY 400. The PMA transmit block 426 and the PMA receive block 428 are connected to a hybrid block 434 to couple the Ethernet PHY with incoming signals related to network transmissions from the transmit / receive data line (TRD). The exemplary Ethernet PHY 400 includes an embedded self-test circuit (BIST) 430 for performing a self-test of the Ethernet PHY 400. The exemplary Ethernet PHY 400 includes an exemplary cable diagnostic block 432 coupled to the incoming TRD for performing a diagnostic of the network cable coupled to the exemplary Ethernet PHY 400. The example Ethernet PHY400 also includes an LED driver 436 for operating an output light-emitting diode (LED) (e.g., a status LED).

[0045] The egress time correction circuit elements 108, 124, 312, and 404 in Figures 1, 3, and / or 4 may be instantiated by hardware logic circuit elements, which may be implemented by an ASIC, XPU, or FPGA circuit element 1700 in Figure 17, configured and / or structured to perform operations corresponding to machine-readable instructions. The egress time correction circuit elements 108, 124, 312, and 404 in Figures 1, 3, and / or 4 may be instantiated by any other combination of hardware, software, and / or firmware. For example, the egress time correction circuit elements 108, 124, 312, and 404 in Figures 1, 3, and / or 4 may be implemented by at least one or more hardware circuits (e.g., processor circuit elements, discrete analog circuit elements and / or discrete digital circuit elements and / or integrated analog circuit elements and / or integrated digital circuit elements, FPGAs, ASICs, XPUs, comparators, operational amplifiers (op-amps), logic circuits, etc.) configured and / or structured to execute some or all of the machine-readable instructions and / or to perform some or all of the operations corresponding to the machine-readable instructions without executing software or firmware, but other structures are equally suitable.

[0046] Means for correction include means for egress latency tracking and egress latency correction. The ingress time correction circuit elements 112, 120, 330, 412 in Figures 1, 3, and / or 4 are instantiated by programmable circuit elements that execute egress time correction instructions and / or are configured to perform operations such as those represented by the flowcharts in Figures 5, 7, 8, 12, and 14. The ingress time correction circuit elements 112, 120, 330, 412 in Figures 1, 3, and / or 4 include means for correcting timestamps to adjust for variable delays in decoding. Means for correction may be implemented by the ingress time correction circuit elements 112, 120, 330, 412 in Figures 1, 3, and / or 4.

[0047] The ingress time correction circuit elements 112, 120, 330, and 412 in Figures 1, 3, and / or 4 may be instantiated by programmable circuit elements such as the programmable circuit element 1512 in Figure 15. For example, the ingress time correction circuit elements 112, 120, 330, and 412 in Figures 1, 3, and / or 4 may be instantiated by the microprocessor 1600 in Figure 16, which executes machine-executable instructions, such as those implemented by at least Figures 5, 7, 8, 12, and 14. The ingress time correction circuit elements 112, 120, 330, and 412 in Figures 1, 3, and / or 4 may be instantiated by hardware logic circuit elements, which may be implemented by an ASIC, XPU, or FPGA circuit element 1700 in Figure 17, which is configured and / or structured to perform operations corresponding to machine-readable instructions. The ingress time correction circuit elements 112, 120, 330, and 412 in Figures 1, 3, and / or 4 can be instantiated by any other combination of hardware, software, and / or firmware. The ingress time correction circuit elements 112, 120, 330, and 412 in Figures 1, 3, and / or 4 can be implemented by at least one or more hardware circuits (e.g., processor circuit elements, discrete analog circuit elements and / or discrete digital circuit elements and / or integrated analog circuit elements and / or integrated digital circuit elements, FPGAs, ASICs, XPUs, comparators, operational amplifiers (op-amps), logic circuits, etc.) configured and / or structured to execute some or all of the machine-readable instructions and / or to perform some or all of the operations corresponding to the machine-readable instructions without executing software or firmware, but other structures are equally suitable.

[0048] Means for correction include means for ingress latency tracking and ingress latency correction.

[0049] Exemplary methods for implementing the egress time correction circuit elements 108, 124, 312, 404 and / or the ingress time correction circuit elements 112, 120, 330, 412 of Figures 1, 3, and / or 4 are illustrated in Figures 1, 3, and / or 4, but one or more of the elements, processes, and / or devices illustrated in Figures 1, 3, and / or 4 may be combined, divided, rearranged, omitted, deleted, and / or implemented in any other manner. Furthermore, the egress time correction circuit element 108, the ingress time correction circuit element 112, the ingress time correction circuit element 120, and / or the egress time correction circuit element 124, the ELTC314, ELCC316, ILTC332, and / or ILCC334 in Figure 3, the ELTC406, ELCC408, ILCC414, and / or ILTC416 in Figure 4, and / or more generally, the Ethernet PHY400 in Figure 4 may be implemented by hardware alone or by hardware in combination with software and / or firmware.

[0050] Therefore, for example, any of the egress time correction circuit elements 108, ingress time correction circuit elements 112, ingress time correction circuit elements 120, and / or egress time correction circuit elements 124, ELTC314, ELCC316, ILTC332, and / or ILCC334 in Figure 3, ELTC406, ELCC408, ILCC414, and / or ILTC416 in Figure 4, and / or more generally, any of the Ethernet PHY400 in Figure 4 can be implemented by programmable circuit elements combined with machine-readable instructions (e.g., firmware or software), processor circuit elements, analog circuits, digital circuits, logic circuits, programmable processors, programmable microcontrollers, graphics processing units (GPUs), digital signal processors (DSPs), ASICs, programmable logic devices (PLDs), and / or field-programmable logic devices (FPLDs) such as FPGAs. Furthermore, the egress time correction circuit elements 108, 124, 312, 404 in Figures 1, 3, and / or 4, and / or the ingress time correction circuit elements 112, 120, 330, 412 in Figures 1, 3, and / or 4, may include, in addition to or instead of, those illustrated in Figures 1, 3, and / or 4, and / or may include two or more of any or all of the illustrated elements, processes, and devices.

[0051] Figures 5, 7, 8, 12, and 14 show flowcharts representing exemplary machine-readable instructions that can be executed by programmable circuit elements to implement and / or instantiate the egress time correction circuit elements 108, 124, 312, 404 and / or the ingress time correction circuit elements 112, 120, 330, 412 of Figures 1, 3, and / or 4, and / or flowcharts representing exemplary operations that can be performed by programmable circuit elements to implement and / or instantiate the egress time correction circuit elements 108, 124, 312, 404 and / or the ingress time correction circuit elements 112, 120, 330, 412 of Figures 1, 3, and / or 4. A machine-readable instruction may be one or more executable programs, or part of one or more executable programs, to be executed by a programmable circuit element, such as the programmable circuit element 1512 shown in the processor platform 1500 described below in relation to Figure 15, and / or one or more functions, or part of functions, to be performed by a programmable circuit element (e.g., FPGA) described below in relation to Figures 16 and / or 17. A machine-readable instruction causes an action, a task, etc., to be performed and / or carried out in an automated manner in the real world. As used herein, “automated” means without human intervention.

[0052] A program may be embodied in instructions (e.g., software and / or firmware) stored in one or more non-temporary computer-readable media and / or machine-readable storage media, such as cache memory, magnetic storage devices or magnetic storage disks (e.g., floppy disks, hard disk drives (HDDs), etc.), optical storage devices or optical storage disks (e.g., Blu-ray discs, compact discs (CDs), digital multipurpose discs (DVDs), etc.), RAID (Redundant Arrays of Independent Disks), registers, ROM, solid-state drives (SSDs), SSD memory, non-volatile memory (e.g., electrically erasable programmable read-only memory (EEPROM), flash memory, etc.), volatile memory (e.g., any type of random access memory (RAM), etc.), and / or any other storage device or storage disk. Instructions in non-temporary computer-readable media and / or machine-readable media may be programmed and / or executed by programmable circuit elements located within one or more hardware devices, although the entire program and / or parts thereof may, alternatively, be executed and / or instantiated by one or more hardware devices other than programmable circuit elements, and / or embodied in dedicated hardware. Machine-readable instructions may be distributed across multiple hardware devices and / or executed by two or more hardware devices (e.g., server and client hardware devices). For example, client hardware devices may be implemented by endpoint client hardware devices (e.g., hardware devices associated with human and / or machine users), or by intermediate client hardware device gateways (e.g., a radio access network (RAN)) that facilitate communication between the server and endpoint client hardware devices. Similarly, non-temporary computer-readable storage media may include one or more media.

[0053] Furthermore, the program will be described with reference to the flowcharts illustrated in Figures 5, 7, 8, 12, and 14, but many other methods may be used as alternatives to implement the egress time correction circuit elements 108, 124, 312, 404 and / or the ingress time correction circuit elements 112, 120, 330, 412 of Figures 1, 3, and / or 4. The execution order of the blocks in the flowchart may be changed, and / or some of the blocks described may be modified, deleted, or combined. Any or all of the blocks in the flowchart may be implemented by one or more hardware circuits (e.g., processor circuit elements, discrete analog circuit elements and / or discrete digital circuit elements and / or integrated analog circuit elements and / or integrated digital circuit elements, FPGAs, ASICs, comparators, operational amplifiers (op-amps), logic circuits, etc.) that are structured to perform the corresponding operations without running software or firmware. Programmable circuit elements may be distributed across different network locations and / or local to one or more hardware devices (e.g., single-core processors (e.g., single-core CPUs), multi-core processors (e.g., multi-core CPUs, XPUs, etc.)). For example, programmable circuit elements may be CPUs and / or FPGAs located in the same package (e.g., the same integrated circuit (IC) package or two or more separate enclosures), one or more processors in a single machine, multiple processors distributed across multiple servers in a server rack, multiple processors distributed across one or more server racks, and / or any combination thereof.

[0054] The machine-readable instructions described herein may be stored in one or more of the following formats: compressed format, encrypted format, fragmented format, compiled format, executable format, packaged format, etc. Machine-readable instructions as described herein may be stored as data (e.g., computer-readable data, machine-readable data, one or more bits (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), bitstreams (e.g., computer-readable bitstreams, machine-readable bitstreams, etc.)) or data structures (e.g., as part of instructions, code, code representations, etc.) which can be used to create, manufacture, and / or generate machine-executable instructions. For example, machine-readable instructions may be stored in fragmented form on one or more storage devices, disks, and / or computing devices (e.g., servers) located in the same or different locations (e.g., in the cloud, on edge devices, etc.) within a network or a collection of networks.

[0055] Machine-readable instructions may require one or more of the following actions to be installed, modified, adapted, updated, combined, supplemented, configured, decrypted, restored, decompressed, delivered, reallocated, or compiled, so that they can be directly read, interpreted, and / or executed by computing devices and / or other machines. For example, machine-readable instructions may be stored as multiple parts, each individually compressed, encrypted, and / or stored on a separate computing device, which, when decrypted, decompressed, and / or combined, form a set of computer-executable instructions and / or machine-executable instructions that implement one or more functions and / or operations, which together may form a program such as those described herein.

[0056] In another example, machine-readable instructions are stored in a state that can be read by programmable circuit elements, but additional libraries (e.g., dynamic link libraries (DLLs)), software development kits (SDKs), application programming interfaces (APIs), etc., are required to execute such machine-readable instructions on a particular computing device or other device. In yet another example, machine-readable instructions require configuration (e.g., settings are stored, data is entered, network addresses are recorded, etc.) before such machine-readable instructions and / or corresponding programs can be executed in whole or in part. Therefore, machine-readable media, computer-readable media, and / or machine-readable media, as used herein, may include instructions and / or programs regardless of the specific format or state of machine-readable instructions and / or programs.

[0057] The machine-readable instructions described herein can be expressed in any past, present, or future instruction language, scripting language, programming language, etc. Machine-readable instructions can be expressed using any of the following languages: C, C++, Java, C#, Perl, Python, JavaScript, hypertext markup language (HTML), structured query language (SQL), Swift, etc.

[0058] As described above, the operations in Figures 5, 7, 8, 12, and 14 can be implemented using executable instructions (e.g., computer-readable instructions and / or machine-readable instructions) stored in one or more non-temporary computer-readable media and / or machine-readable media. As used herein, the terms non-temporary computer-readable media, non-temporary computer-readable storage media, non-temporary machine-readable media, and / or non-temporary machine-readable storage media are explicitly defined to include any type of computer-readable storage device and / or computer-readable storage disk, and to exclude propagating signals and transmitting media. Examples of such non-temporary computer-readable media, non-temporary computer-readable storage media, non-temporary machine-readable media, and / or non-temporary machine-readable storage media include optical storage devices, magnetic storage devices, HDDs, flash memory, read-only memory (ROM), CDs, DVDs, caches, any type of RAM, registers, and / or any other storage devices or storage disks on which information is stored for any duration (e.g., over a long period, permanently, for short instances, for temporary buffering of information, and / or for caching).

[0059] Figure 5 is a flowchart representing exemplary machine-readable instructions and / or exemplary operations 500, which are executed, instantiated, and / or performed by programmable circuit elements to adjust timestamps based on the state of physical coding sublayer circuit elements (e.g., egress PCS308, ingress PCS320, transmit PCS402, and / or receive PCS410). The machine-readable instructions and / or operations 500 in Figure 5 begin in block 502, in which ELTC314, ILTC332, ELTC406, and / or ILTC416 determine delays (e.g., variable coding delays and / or variable decoding delays) based on the state of PCS circuit elements (e.g., encoder circuit elements, decoder circuit elements, etc.). For example, as illustrated in Figures 6A to 14, such states are the state of one or more clock signals (e.g., the relative state of two different clock signals), a specific path through the PCS (e.g., a path through a multiplexer), a specific block index of a transmit frame, and so on.

[0060] Next, ELCC316, ILCC334, ELCC408, and / or ILCC414 adjust the timestamp value to compensate for the determined delay (e.g., by adding the delay time to the timestamp or subtracting the delay from the timestamp) (block 504). Then, ELCC316, ILCC334, ELCC408, and / or ILCC414 output such adjusted timestamps (e.g., to egress PCS308, ingress PCS320, transmit PCS402, and / or receive PCS410, respectively) for association with the transmitted or received data (block 506). For example, the adjusted timestamp compensates for the variable portion of the PCS delay that might interfere with the precise timestamping process. The corrected timestamp can be used as part of a clock adjustment process to cause clock adjustment of a slave device (e.g., slave device 116) to synchronize the slave device's clock with the master time server's clock (e.g., master time server 104).

[0061] Figure 5 illustrates a single flow through determining delays and adjusting timestamps, a process that may be repeated for each message to be transmitted. Adjustments associated with two different messages may be determined based on a variable delay that changes between at least some of those messages. As in these examples, the delay is determined as each message is to be transmitted. Alternatively, a first delay and adjustment may be determined for a first set of messages, symbols, blocks, frames, etc., and then a second delay and adjustment may be determined for a second set of messages, symbols, blocks, frames, etc. In an example of multiple executions of the instruction in Figure 5 to consider multiple transmissions (e.g., a first transmission and a second transmission), ELTC314, ILTC332, ELTC406, and / or ILTC416 determine a first delay (e.g., a variable coding delay and / or a variable decoding delay) introduced by PCS402 in a first time. ELTC314, ILTC332, ELTC406, and / or ILTC416 adjust a first timestamp associated with a first transmission based on a first delay. In such an example, the first timestamp is transmitted with the first transmission. Then, ELTC316, ILCC334, ELCC408, and / or ILCC414 adjust a first timestamp associated with a first transmission based on a first delay, and the first timestamp is transmitted with the first transmission. Subsequently, ELTC314, ILTC332, ELTC406, and / or ILTC416 determine a second delay introduced by PCS402 in a second time, the second delay being different from the first delay (for example, because the state of PCS402 in the first time is different from the state of PCS in the second time). Next, ELCC316, ILCC334, ELCC408, and / or ILCC414 adjust the second timestamp associated with the second transmission based on the second delay, and the second timestamp is transmitted together with the second transmission.

[0062] For example, the adjusted timestamp is then used for transmission, so that the receiver of such transmission will receive a timestamp that does not include the variable delay (e.g., includes only the transmission delay). For example, as illustrated in Figure 2, after the slave device 116 receives the delay response 208, the slave device 116 has a set of timestamps adjusted (e.g., adjusted by the master time server 104 and the slave device 116) to offset the variable delay introduced in the transmission by various components (e.g., by components of the PCS). Thus, the slave device 116 can use such adjusted timestamps to determine the amount of time required to adjust its local clock to synchronize it with the clock of the master time server 104. The amount of time required to adjust the clock can be calculated as the difference between the first timestamp and the second timestamp corresponding to the time. In particular, as described in relation to Figure 2, the slave device 116, Based on multiple timestamps, such as TIFF2026511572000003.tif9128, the amount of time needed to adjust the clock can be calculated.

[0063] Figure 6A is a block diagram of an exemplary transmitting PCS602, and Figure 6B is a block diagram of an exemplary receiving PCS614. PCS602 and PCS614 are illustrated to facilitate the explanation of certain components that may cause variable delays during operation (e.g., rather than static delays, consistent delays, stable delays, etc.).

[0064] The transmitting PCS602 includes a 4-bit to 3-bit (4B3B) converter 604, a sidestream scrambler 606, a 3-bit to 3-value (3B2T) converter, a two-dimensional to one-dimensional (2D-1d) converter 610, and an ELTC612. The 4B3B converter 604 receives 4-bit data and outputs 3-bit data which will be adjusted by the sidestream scrambler 606. The adjusted 3-bit data adjusted by the sidestream scrambler 606 is input to the 3B2T608. The output of the 3B2T608 is connected to the 2D-1D converter 610, which outputs encoded data for transmission. The ELTC612 monitors the state of the PCS602 during operation. Although not shown in Figure 6, the ELTC612 is connected to the ELCC to perform timestamp adjustment. The ELTC612 may be implemented by the ELTC314 in Figure 3A and / or the ELTC406 in Figure 4.

[0065] In these examples, the 4B3B604 introduces a delay that varies between 10 nanoseconds and 30 nanoseconds, as illustrated in Figure 9. Therefore, the ELTC612 monitors the state of the 4B3B converter 604 to determine the specific delay present during data transmission. In this example, components of the PCS602 other than the 4B3B converter 604 are not described further because they do not have variable delays. However, the techniques described can similarly be used to account for latencies caused by or otherwise associated with other components of the PCS602.

[0066] The PCS614 includes a 3-bit to 4-bit (3B4B) converter, a sidestream descrambler 618, a 3-value to 3-bit (2T3B) converter 620, a one-dimensional to two-dimensional (1D-2D) converter 622, and an ILTC624. The 1D-2D converter 622 receives incoming symbol data and outputs the converted two-dimensional data to the 2T3B620, the 2T3B converter outputs 3-bit data to be descrambled by the sidestream descrambler 618, and the 3-bit data is converted from 3 bits to 4 bits by the 3B4B616. The ILTC624 monitors the state of the PCS614 during operation. Although not shown in Figure 6, the ILTC624 is connected to an ILCC to perform timestamp adjustment. The ILTC624 may be implemented by the ILTC332 in Figure 3B and / or the ILTC416 in Figure 4.

[0067] In these examples, the 3B4B616 introduces a delay that varies between 10 nanoseconds and 40 nanoseconds, as illustrated in Figure 10. The 1D-2D622 introduces a delay that varies between 0 nanoseconds and 15 nanoseconds (for example, the amount of time associated with delaying the transmission of one symbol). Therefore, the ILTC624 monitors the states of the 3B4B converter 616 and the 1D-2D622 to determine the specific delay present when receiving data. Components of the PCS614 other than the 3B4B converter 616 and the 1D-2D converter 622 do not have variable delays and are therefore not described further. However, the techniques described can similarly be used to account for latencies caused by or otherwise associated with other components of the PCS614.

[0068] Figure 7 is a flowchart illustrating an example implementation of block 502 for detecting a clock signal that causes variable delay in the PCS. For example, bit-level conversion circuit elements convert a first bit level (e.g., 2-bit, 3-bit, 4-bit, etc.) transmission / communication to a different bit level in 4B3B604 (e.g., first bit-level conversion) and / or 3B4B616 (e.g., second bit-level conversion), etc. ELTC314 and / or ILTC332 detect the edge of the first clock signal (block 702) and the second edge of the second clock signal (block 704). For example, the bit-level converter has a base clock signal (e.g., a 100MHz clock signal), which is used to generate a first clock signal (e.g., 25MHz) and a second clock signal (e.g., 33MHz). In such examples, the ELTC314 and / or ILTC332 access the first and second clock signals to determine the phase alignment of those clock signals relative to each other.

[0069] ELTC314 and / or ILTC332 determine the delay based on the difference (block 706). Following these examples, ELTC314 and / or ILTC332 determine the delay as the difference between the rising edge of the first clock signal and the next rising edge of the second clock signal. For example, if the rising edges of the first and second clock signals occur simultaneously, the rising edge of the second clock signal is not considered the next rising edge. The difference between rising edges can be determined by observing the current state of the clock signals. Another method for determining the difference is to track the historical state of the clock signals (for example, since clock signals are synchronous and deterministic, the future difference between rising edges can be determined based on previous alignment of rising edges).

[0070] After the operation shown in Figure 7, control returns to block 504 in Figure 5, based on the delay determined in Figure 8.

[0071] Figure 8 is a flowchart of another illustrative implementation of block 502 for detecting a clock signal causing a variable delay in the PCS, for example in 4B3B604 and / or 3B4B616. ELTC314 and / or ILTC332 determine the alignment of the first clock signal to the base clock signal (block 802) and the alignment of the second clock signal to the base clock signal (block 804). Then, ELTC314 and / or ILTC332 determine the delay based on the difference between the clock signal alignments. For example, ELTC314 and / or ILTC332 determine the phase of the first clock signal and the phase of the second clock signal and determine the delay based on what the state of the clock signal will be during the transmission of data to which a timestamp will be added (block 806).

[0072] After the operation in Figure 8, control returns to block 504 in Figure 5 to adjust the timestamp value based on the delay determined in Figure 8.

[0073] Figure 9 illustrates several clock signals 900 used to drive the operation of the bit-level converter. The example clock signals include a 100 MHz base clock signal 902, a 25 MHz first clock signal 904 derived from the rising edge of the base clock signal 902, and a 33 MHz second clock signal 906 derived from the rising edge of the base clock signal 902. For example, the 4B3B converter 604 effectively converts a 25 MHz 4-bit incoming signal to a 33 MHz 3-bit outgoing signal by using the first clock signal 904 to read the next 4 bits of data and the second clock signal 906 to output the next 3 bits of data. Because the clock signals operate at different frequencies, the rising edges of those clock signals driving the operation are not aligned. The signal passing through the converter is delayed by the amount of time elapsed between the rising edge of the first clock signal 904 and the rising edge of the second clock signal 906. Therefore, by analyzing the clock signal as shown in Figure 7 and / or Figure 8, the delay introduced by the converter can be determined / predicted, and such delay can be compensated for by adjusting the timestamp (for example, by incrementing the timestamp over the amount of time introduced by the delay so that the delay is offset), as shown in Figure 5.

[0074] As illustrated by the clock signal 900 in Figure 9 of 4B3B604, in the first example, the relative positions of the edges of the 25MHz clock signal and the 33MHz clock signal indicate that the delay between the rising edge of the 25MHz clock signal and the next (temporal) rising edge of the 33MHz clock signal can be 30 nanoseconds, 20 nanoseconds, and / or 10 nanoseconds, depending on the relative timing. Similarly, by knowing the phases of the 25MHz and 33MHz clock signals according to the process in Figure 8, the future alignment between the clock signals, and therefore the variable delay in future time, can be determined. As illustrated by Figure 9, the clock signals operating at 25MHz and 33MHz have a phase difference of 10 nanoseconds, constantly changing their relative alignment, although such alignment differences are deterministically always one of three different values ​​(e.g., 30 nanoseconds, 20 nanoseconds, or 10 nanoseconds). Clock signals utilizing other frequencies may encounter different alignment differences, as well as different numbers of alignment differences. The rising edge and / or phase of the signals can be determined by ELTC314 and / or ILTC332, which monitor the state of the 100MHz clock signal from which the other clock signals are derived. In such an example, the predictable nature of the clock signals generated from the 100MHz clock signal makes it possible to determine the state of the other clock signals at a given time. For example, as shown in Figure 9, if the rising edge of the first clock signal 904 occurs simultaneously with the rising edge of the second clock signal 906 at a given time, then it can be predicted that the second clock signal 906 will have its rising edge 20 nanoseconds after the next rising edge of the first clock signal 904.

[0075] Referring to Figure 10, the clock signal 1000 of 3B4B616 is illustrated. The same principle of recognizing the edges and / or phase of the clock signal 1000 can be used to determine the delay, and as illustrated, the actual delay will vary, and the delay may be 10 nanoseconds, 20 nanoseconds, 30 nanoseconds, or 40 nanoseconds. For example, the clock signal 1000 includes a base clock signal 1002 of 100 MHz, a first clock signal 1004 of 33 MHz, and a second clock signal 1006 of 25 MHz. Since the first clock signal 1004 is associated with capturing an input value (e.g., 3-bit data at 33 MHz), the delay of the associated converter (e.g., 3B4B converter 616) is the difference between the rising edge of the first clock signal 1004 and the next (temporarily) rising edge of the second clock signal 1006.

[0076] Referring to Figure 11, different types of delays are introduced by the message flow 1100. The illustrated message flow 1100 facilitates the conversion of a 1-bit signal to a 2-bit signal (for example, in the 1D-2D converter 622). Flow 1100 introduces a variable delay, rather than a delay due to the difference between the input clock and the output clock. This is because some symbols 1102 proceed to a first path 1104 with a variable delay of 0, and some symbols proceed to a second path 1106 that introduces a delay of 15 nanoseconds. These particular paths are selected by the control of the multiplexer 1110. In other words, the first path 1104 and the second path 1106 are used by the multiplexer 1110 to selectively control whether or not a delay is introduced (provided by the flop 1108) to control the matching of the 2-bit signals output by the multiplexer 1110. In the example in Figure 11, some symbol sequences require correction, so a flop 1108 or another type of delay is provided along a second path 1106 via the multiplexer 1110 to force realignment. For example, a 15-nanosecond delay aligns symbol A0, which is initially not aligned with symbol B0, with symbol B0. Such symbol sequences, and whether or not correction needs to be applied, can be determined by attempting to descramble the resulting signal and determining whether the descramble was successful (e.g., by a sidestream descrambler 618). If the sidestream descrambler 618 determines that the descramble was unsuccessful because the corresponding symbols (e.g., A0 and B0) are not aligned in a single cycle, the sidestream descrambler 618 controls the multiplexer 1110 to select the second path 1106 to correct such misalignment. The variable delay introduced by the converter can be determined by detecting the state of the multiplexer 1110 and / or the signals controlling the multiplexer 1110. In this example, the variable delay is 0 nanoseconds when the first path 1104 is selected, and 15 nanoseconds when the second path 1106 is selected.

[0077] Figure 12 is a flowchart illustrating an exemplary implementation of block 502, or the detection of delays resulting from the selection of various symbol transmission paths that may have variable delays.

[0078] ELTC314 and / or ILTC332 determine the path a set of symbols will take through the multiplexer by examining the current symbol sequence (block 1202). ELTC314 and / or ILTC332 may detect the state of the multiplexer 1110 and / or signals controlling the multiplexer 1110 (e.g., from the sidestream descrambler 618) to determine which path is selected. For example, ELTC314 and / or ILTC332 may determine that the symbol sequence allows symbols to take a delay-free path, and / or that the symbol sequence needs to be corrected, and therefore symbols will take a delay-inclusive path.

[0079] If ELTC314 and / or ILTC332 determine that a first path without delay is selected (block 1202), ELTC314 and / or ILTC332 determine that the variable delay is zero (block 1204). If ELTC314 and / or ILTC332 determine that a second path including delay is selected (block 1202), ELTC314 and / or ILTC332 determine that the variable delay is the path delay (e.g., 15 nanoseconds) (block 1206). After ELTC314 and / or ILTC332 have determined the delay, ELTC314 and / or ILTC332 output the delay that will be used to adjust the timestamp value to offset the delay (e.g., when control returns to block 504) (block 1208).

[0080] Figure 13 illustrates yet another type of variable delay that may occur during encoding and / or decoding. The input symbol 1302 and output symbol 1304 in Figure 13 illustrate the input and output of an exemplary Reed-Solomon (RS) forward error correction (FEC) process. Such a process may be employed by PCS's Reed-Solomon error correction circuit elements. RS FEC may be implemented by PCS's error correction circuit elements, such as error correction encoder circuit elements and error correction decoder circuit elements. The 1000BaseT1 standard uses RS encoding for FEC, using a block size of 406 symbols and 44 parity symbols. Such an encoding process introduces a variable delay. As illustrated in Figure 13, the delay of the first symbol 0 (from input 1302 to output 1304) is the time from the first time 1306 to the second time 1308 (e.g., several N cycles). However, block coding in such encoders results in a slight decrease in the delay of each symbol until the delay for the last symbol in a frame is 44 cycles less than the delay for the first symbol (for example, the last symbol 405 has a delay of N-44 cycles).

[0081] Alternatively, other methods may utilize a different number of symbols. This nature of block coding results in variable latency for each symbol, from the input to the RS encoder to the output of the RS encoder and decoder. For example, the latency of each symbol within a frame gradually decreases, with the last symbol in the frame having 44 cycles (or the number of parity symbols used) less latency than the first symbol. In other words, latency or delay is based on the relative position of the symbols to be transmitted with respect to the beginning of the frame.

[0082] Figure 14 is a flowchart illustrating an implementation of block 502 in Figure 5 for determining the delay associated with the encoding and / or decoding illustrated in Figure 13. ELTC314 and / or ILTC332 detect the position of the Start of Packet in the frame (e.g., the difference between time 1306 and time 1308) as the number of cycles from the start of the frame (e.g., N cycles) (block 1402). ELTC314 and / or ILTC332 then detect the index of the symbol to be transmitted at the time when the timestamp adjustment will be determined (block 1404). ELTC314 and / or ILTC332 then determine the delay based on the difference between the position and index of the symbol to be transmitted (block 1406). Therefore, since the ELTC314 and / or ILTC332 can determine the position of the symbols to be transmitted, the ELTC314 and / or ILTC332 can determine the delay based on the initial delay from the start of input symbol 1302 to the start of output symbol 1304 and a specific symbol index. For example, the delay varies from A) a delay equal to the number of cycles between the encoder / decoder input and the start of the output frame to B) a delay for the last symbol in the frame equal to that number of cycles minus 44 cycles.

[0083] Figure 15 is a block diagram of an exemplary programmable circuit element platform 1500, structured to execute and / or instantiate machine-readable instructions and / or operations of Figures 5, 7, 8, 12, and 14 in order to implement the egress time correction circuit elements 108, 124, 312, 404 and / or the ingress time correction circuit elements 112, 120, 330, 412 of Figures 1, 3, and / or 4. The programmable circuit element platform 1500 may be, for example, a server, a personal computer, a workstation, a self-learning machine (e.g., a neural network), a mobile device (e.g., a mobile phone, a smartphone, a tablet such as iPad®), a personal digital assistant (PDA), an internet device, a DVD player, a CD player, a digital video recorder, a Blu-ray player, a game console, a personal video recorder, a set-top box, a headset (e.g., an augmented reality (AR) headset, a virtual reality (VR) headset, etc.), or other wearable devices, or any other type of computing device and / or electronic device.

[0084] The programmable circuit element platform 1500 in this example includes a programmable circuit element 1512. The programmable circuit element 1512 in this example is hardware. For example, the programmable circuit element 1512 can be implemented by one or more integrated circuits, logic circuits, FPGAs, microprocessors, CPUs, GPUs, DSPs, and / or microcontrollers from any desired family or manufacturer. The programmable circuit element 1512 can be implemented by one or more semiconductor-based (e.g., silicon-based) devices. In this example, the programmable circuit element 1512 implements, for example, ELTC314, ELCC316, ILTC332, and ILCC334.

[0085] In such examples, the programmable circuit element 1512 includes local memory 1513 (e.g., cache, registers, etc.). The programmable circuit element 1512 in such examples communicates with main memories 1514, 1516, which include volatile memory 1514 and non-volatile memory 1516, via a bus 1518. The volatile memory 1514 may be implemented by synchronous dynamic random access memory (SDRAM), dynamic random access memory (DRAM), RAMBUS® dynamic random access memory (RDRAM®), and / or any other type of RAM device. The non-volatile memory 1516 may be implemented by flash memory, and / or any other desired type of memory device. Access to the main memories 1514, 1516 in such examples is controlled by a memory controller 1517. The memory controller 1517 may be implemented by one or more integrated circuits, logic circuits, microcontrollers from any desired family or manufacturer, or any other type of circuit element for managing the flow of data to and from the main memories 1514, 1516.

[0086] Such programmable circuit element platforms 1500 also include interface circuit elements 1520. Interface circuit elements 1520 can be implemented by hardware of any type of interface standard, such as Ethernet interfaces, Universal Serial Bus (USB) interfaces, Bluetooth® interfaces, Near Field Communication (NFC) interfaces, Peripheral Component Interconnect (PCI) interfaces, and / or Peripheral Component Interconnect Express (PCIe) interfaces. Following these examples, the interface circuit element 1520 implements network interface circuit elements such as the network interface circuit element of the master time server 104, the network interface circuit element of the transmit circuit element 106, the network interface circuit element of the egress time correction circuit element 108, the network interface circuit element of the receive circuit element 110, the network interface circuit element of the ingress time correction circuit element 112, the network interface circuit element of the slave device 116, the network interface circuit element of the receive circuit element 118, the network interface circuit element of the ingress time correction circuit element 120, the network interface circuit element of the transmit circuit element 122, and / or the network interface circuit element of the egress time correction circuit element 124.

[0087] In these examples, one or more input devices 1522 are connected to the interface circuit element 1520. The input devices 1522 allow a user (e.g., a human user, a machine user, etc.) to input data and / or commands to the programmable circuit element 1512. The input devices 1522 can be implemented, for example, by audio sensors, microphones, cameras (still cameras or video cameras), keyboards, buttons, mice, touchscreens, trackpads, trackballs, isopoint devices, and / or speech recognition systems.

[0088] One or more output devices 1524 are also connected to the interface circuit element 1520 of such examples. The output devices 1524 can be implemented, for example, by display devices (e.g., light-emitting diodes (LEDs), organic light-emitting diodes (OLEDs), liquid crystal displays (LCDs), cathode ray tube (CRT) displays, in-place switching (IPS) displays, touchscreens, etc.), haptic output devices, printers, and / or speakers. The interface circuit element 1520 of such examples includes graphics driver cards, graphics driver chips, and / or graphics processor circuit elements such as GPUs.

[0089] The interface circuit elements 1520 in such examples also include communication devices such as transmitters, receivers, transceivers, modems, residential gateways, wireless access points, and / or network interfaces for facilitating the exchange of data with external machines (e.g., any type of computing device) via the network 1526. Such communication may be via, for example, Ethernet connections, digital subscriber line (DSL) connections, telephone line connections, coaxial cable systems, satellite systems, beyond-line-of-sight wireless systems, within-line-of-sight wireless systems, cellular systems, optical connections, and the like.

[0090] Such programmable circuit element platforms 1500 also include one or more mass storage disks or devices 1528 for storing firmware, software, and / or data. Examples of such mass storage disks or devices 1528 include solid-state storage disks or devices such as magnetic storage devices (e.g., floppy disks, drives, HDDs, etc.), optical storage devices (e.g., Blu-ray discs, CDs, DVDs, etc.), RAID systems, and / or flash memory devices and / or SSDs.

[0091] The machine-readable instruction 1532, which can be implemented by the machine-readable instructions in Figures 5, 7, 8, 12, and 14, may be stored in a mass storage device 1528, in volatile memory 1514, in non-volatile memory 1516, and / or in at least one non-temporary computer-readable storage medium such as a removable CD or DVD.

[0092] Figure 16 is a block diagram of an illustrative implementation of the programmable circuit element 1512 of Figure 15. In this example, the programmable circuit element 1512 of Figure 15 is implemented by a microprocessor 1600. The microprocessor 1600 may be a general-purpose microprocessor (e.g., a general-purpose microprocessor circuit element). The microprocessor 1600 executes some or all of the machine-readable instructions in the flowcharts of Figures 5, 7, 8, 12, and 14 to effectively instantiate the circuit element of Figure 15 as a logic circuit to perform the operations corresponding to those machine-readable instructions. In some such examples, the circuit elements of Figure 1 and / or Figures 3A and 3B are instantiated by the hardware circuit of the microprocessor 1600 in combination with machine-readable instructions. The microprocessor 1600 may be implemented by a multi-core hardware circuit element such as a CPU, DSP, GPU, or XPU. Such multicore hardware circuit elements may include any number of cores 1602 (e.g., one core), but the microprocessor 1600 in this example is a multicore semiconductor device containing N cores. The cores 1602 of the microprocessor 1600 may operate independently or cooperate to execute machine-readable instructions. Firmware programs, embedded software programs, or machine code corresponding to software programs may be executed by one of the cores 1602, or by multiple cores 1602, simultaneously or at different times. The firmware programs, embedded software programs, or machine code corresponding to software programs may be divided into threads and executed in parallel by two or more of the cores 1602. Such software programs may correspond to some or all of the machine-readable instructions and / or operations represented by the flowcharts in Figures 5, 7, 8, 12, and 14.

[0093] The core 1602 may communicate via a first bus 1604. The first bus 1604 may be implemented by a communication bus for performing communication associated with one (or more) of the cores 1602. The first bus 1604 may be implemented by at least one of the following: an inter-integrated circuit (I2C) bus, a serial peripheral interface (SPI) bus, a PCI bus, or a PCIe bus. The first bus 1604 may be implemented by any other type of computing bus or electrical bus. The core 1602 may receive data, instructions, and / or signals from one or more external devices via an interface circuit element 1606. The core 1602 may output data, instructions, and / or signals to one or more external devices via the interface circuit element 1606. In this example, core 1602 includes local memory 1620 (e.g., an L1 cache which can be divided into a Level 1 (L1) data cache and an L1 instruction cache), while microprocessor 1600 also includes shared memory 1610 (e.g., Level 2 (L2 cache)) which can be shared by cores for high-speed access to data and / or instructions. Data and / or instructions can be transferred (e.g., shared) by writing to and / or reading from shared memory 1610. The local memory 1620 and shared memory 1610 of each core 1602 may be part of a storage device hierarchy which includes multiple levels of cache memory and main memory (e.g., main memories 1514, 1516 in Figure 15). Higher levels of memory in the hierarchy may have shorter access times and smaller storage capacities than lower levels of memory. Changes at various levels of the cache hierarchy are managed (e.g., coordinated) by a cache coherency policy.

[0094] Each core 1602 may be referred to as a CPU, DSP, GPU, or any other type of hardware circuit element. Each core 1602 includes a control unit circuit element 1614, an arithmetic logic (AL) circuit element (sometimes referred to as an ALU) 1616, several registers 1618, local memory 1620, and a second bus 1622. Other structures may also exist. For example, each core 1602 may include a vector unit circuit element, a single instruction multiple data (SIMD) unit circuit element, a load / store unit (LSU) circuit element, a branch / jump unit circuit element, a floating-point unit (FPU) circuit element, and so on. The control unit circuit element 1614 includes semiconductor-based circuitry structured to control (e.g., coordinate) data movement within the corresponding core 1602. The AL circuit element 1616 includes semiconductor-based circuitry structured to perform one or more mathematical and / or logical operations on data within the corresponding core 1602. In some examples, the AL circuit element 1616 performs integer-based arithmetic. In other examples, the AL circuit element 1616 also performs floating-point arithmetic. In yet another example, the AL circuit element 1616 may include a first AL circuit element that performs integer-based arithmetic and a second AL circuit element that performs floating-point arithmetic. The AL circuit element 1616 may be referred to as an arithmetic logic unit (ALU).

[0095] Register 1618 is a semiconductor-based structure for storing data and / or instructions, such as the results of one or more operations performed by the AL circuit element 1616 of the corresponding core 1602. Register 1618 may include vector registers, SIMD registers, general-purpose registers, flag registers, segment registers, machine-specific registers, instruction pointer registers, control registers, debug registers, memory management registers, machine check registers, etc. Register 1618 may be arranged in a bank structure, as shown in Figure 16. Alternatively, register 1618 may be organized in any other arrangement, format, or structure, such as being distributed across the entire core 1602 to reduce access time. The second bus 1622 may be implemented by at least one of the I2C bus, SPI bus, PCI bus, or PCIe bus.

[0096] Each core 1602, and / or more generally, the microprocessor 1600, may include additional and / or alternative structures to the structures shown and described above. For example, one or more clock circuits, one or more power supplies, one or more power gates, one or more cache home agents (CHAs), one or more convergence / common mesh stops (CMS), one or more shifters (e.g., barrel shifters), and / or other circuit elements may be present. The microprocessor 1600 is a semiconductor device manufactured to include many transistors interconnected to implement the above structures in one or more integrated circuits (ICs) contained within one or more packages.

[0097] The microprocessor 1600 may include and / or cooperate with one or more accelerators (e.g., acceleration circuit elements, hardware accelerators, etc.). In some examples, the accelerator is implemented by logic circuit elements to perform a particular task faster and / or more efficiently than could be done by a general-purpose processor. Examples of accelerators include ASICs and FPGAs, such as those described herein. GPUs, DSPs, and / or other programmable devices may also be accelerators. The accelerator may be mounted directly on the microprocessor 1600, may reside in the same chip package as the microprocessor 1600, and / or may reside in one or more separate packages from the microprocessor 1600.

[0098] Figure 17 is a block diagram of another example implementation of the programmable circuit element 1512 of Figure 15. The programmable circuit element 1512 is implemented by an FPGA circuit element 1700. The FPGA circuit element 1700 can be implemented by an FPGA. The FPGA circuit element 1700 can be used to perform operations that can be performed in other ways by the microprocessor 1600 of Figure 16 by executing the corresponding machine-readable instructions. However, once configured, the FPGA circuit element 1700 can instantiate the operations and / or functions corresponding to the machine-readable instructions in hardware and therefore can perform such operations / functions faster than can often be performed by a general-purpose microprocessor that runs the corresponding software.

[0099] More specifically, in contrast to the microprocessor 1600 in Figure 16 (which is a general-purpose device whose interconnects and logic circuit elements are fixed at the time of manufacture, although it can be programmed to execute some or all of the machine-readable instructions represented by the flowcharts in Figures 5, 7, 8, 12, and 14), the FPGA circuit element 1700 in Figure 17 includes interconnects and logic circuit elements that can be configured, structured, programmed, and / or interconnected in different ways after manufacture to instantiate some or all of the operations / functions corresponding to the machine-readable instructions represented by the flowcharts in Figures 5, 7, 8, 12, and 14. In particular, the FPGA circuit element 1700 can be thought of as an array of logic gates, interconnects, and switches. The switches can be programmed to change how the logic gates are interconnected by the interconnects, thereby effectively forming one or more dedicated logic circuits (unless the FPGA circuit element 1700 is reprogrammed, and until it is reprogrammed). The configured logic circuits enable logic gates to cooperate in various ways to perform various operations on data received by input circuit elements. Such operations may correspond to some or all of the instructions (e.g., software and / or firmware) represented by the flowcharts in Figures 5, 7, 8, 12, and 14. Therefore, FPGA circuit elements 1700 can be configured and / or structured to effectively instantiate some or all of the operations / functions corresponding to the machine-readable instructions in the flowcharts of Figures 5, 7, 8, 12, and 14 as dedicated logic circuits, and to perform the operations / functions corresponding to such software instructions in a dedicated manner similar to that of an ASIC. Therefore, FPGA circuit elements 1700 can perform the operations / functions corresponding to some or all of the machine-readable instructions in Figures 5, 7, 8, 12, and 14 faster than a general-purpose microprocessor could perform the same operations / functions.

[0100] In Figure 17, the FPGA circuit element 1700 is configured and / or structured in response to being programmed (and / or reprogrammed one or more times) based on a binary file. The binary file may be compiled and / or generated based on instructions in a hardware description language (HDL), such as Lucid, a very high-speed integrated circuit (VHSIC) hardware description language (VHDL), or Verilog. For example, a user (e.g., a human user, a machine user, etc.) may write code or a program in HDL that corresponds to one or more operations / functions, and such code / programs may be translated into a lower-level language as needed, and such code / programs (e.g., code / programs in a lower-level language) may be converted into a binary file (e.g., by a compiler, a software application, etc.). The FPGA circuit element 1700 in Figure 17 may access and / or load such a binary file in order to configure and / or structure the FPGA circuit element 1700 in Figure 17 to perform one or more operations / functions. The binary file may be implemented by a bitstream (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), data (e.g., computer-readable data, machine-readable data, etc.), and / or machine-readable instructions accessible to the FPGA circuit element 1700 in Figure 17, so as to cause the configuration and / or structuring of the FPGA circuit element 1700 or a part thereof in Figure 17.

[0101] Binary files are output from a uniform software platform used to program FPGAs, compiled, generated, modified, and / or otherwise. The uniform software platform can translate a first instruction (e.g., code or program) corresponding to one or more operations / functions in a higher-level language (e.g., C, C++, Python, etc.) into a second instruction corresponding to one or more operations / functions in HDL. In some such examples, binary files are output from the uniform software platform based on the second instruction, compiled, generated, and / or otherwise. The FPGA circuit element 1700 in Figure 17 may access and / or load a binary file to configure and / or structure the FPGA circuit element 1700 in Figure 17 to perform one or more operations / functions. The binary file may be implemented by a bitstream (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), data (e.g., computer-readable data, machine-readable data, etc.), and / or machine-readable instructions accessible to the FPGA circuit element 1700 in Figure 17, so as to cause the configuration and / or structuring of the FPGA circuit element 1700 or a part thereof in Figure 17.

[0102] The FPGA circuit element 1700 in Figure 17 includes an input / output (I / O) circuit element 1702 for acquiring and / or outputting data to and from the component circuit element 1704 and / or external hardware 1706. For example, the component circuit element 1704 is implemented by an interface circuit element, which acquires a binary file that can be implemented by bitstreams, data, and / or machine-readable instructions to constitute the FPGA circuit element 1700 or a part thereof. In some such examples, the component circuit element 1704 acquires the binary file from a user, a machine (e.g., an artificial intelligence / machine learning (AI / ML) model implementing an artificial intelligence / machine learning (AI / ML) model to generate the binary file), a hardware circuit element (e.g., a programmable circuit element or a dedicated circuit element), and / or any combination thereof. The external hardware 1706 may be implemented by an external hardware circuit element. The external hardware 1706 may be implemented by the microprocessor 1600 in Figure 16.

[0103] The FPGA circuit element 1700 also includes an array of logic gate circuit elements 1708, a plurality of configurable interconnects 1710, and a storage circuit element 1712. The logic gate circuit elements 1708 and the configurable interconnects 1710 are configurable to instantiate one or more operations / functions and / or other desired operations that can correspond to at least some of the machine-readable instructions in Figures 5, 7, 8, 12, and 14. The logic gate circuit elements 1708 shown in Figure 17 are manufactured in blocks or groups. Each block includes a semiconductor-based electrical structure that can be configured into a logic circuit. The electrical structure includes logic gates (e.g., AND gates, OR gates, NOR gates, etc.) that provide basic building blocks for the logic circuit. Electrically controllable switches (e.g., transistors) are present in each of the logic gate circuit elements 1708 to enable the configuration of the electrical structure and / or logic gates to form a circuit for performing a desired operation / function. The logic gate circuit element 1708 may include other electrical structures such as lookup tables (LUTs), registers (e.g., flip-flops or latches), and multiplexers.

[0104] Such configurable interconnections 1710 include conductive paths, traces, vias, etc., which may include electrically controllable switches (e.g., transistors) whose state can be changed by programming (e.g., using an HDL instruction language) to activate or deactivate one or more connections between one or more logic gate circuit elements 1708 in order to program a desired logic circuit.

[0105] In such examples, the storage circuit element 1712 is structured to store one or more results of operations performed by the corresponding logic gate. The storage circuit element 1712 may be implemented by registers or the like. In such examples, the storage circuit element 1712 is distributed among the logic gate circuit elements 1708 to facilitate access and improve execution speed.

[0106] The FPGA circuit element 1700 in Figure 17 also includes a dedicated operating circuit element 1714. In this example, the dedicated operating circuit element 1714 includes a special-purpose circuit element 1716 that is called upon to implement commonly used functions, avoiding the need to program such functions in the field. Examples of such special-purpose circuit elements 1716 include a memory (e.g., DRAM) controller circuit element, a PCIe controller circuit element, a clock circuit element, a transceiver circuit element, memory, and a multiply-accumulate circuit element. Other types of special-purpose circuit elements may also exist. The FPGA circuit element 1700 may also include a general-purpose programmable circuit element 1718, such as a CPU 1720 and / or a DSP 1722. Other general-purpose programmable circuit elements 1718, such as a GPU or XPU, may also exist that can be programmed to perform other operations.

[0107] Figures 16 and 17 illustrate two illustrative implementations of the programmable circuit element 1512 of Figure 15, but many other methods can be conceived. For example, the FPGA circuit element includes an onboard CPU, such as one or more of the CPUs 1720 in Figure 17. Therefore, the programmable circuit element 1512 of Figure 15 can also be implemented by combining at least the microprocessor 1600 of Figure 16 and the FPGA circuit element 1700 of Figure 17. In some examples of such hybrids, one or more cores 1602 in Figure 16 execute a first portion of machine-readable instructions represented by the flowcharts in Figures 5, 7, 8, 12, and 14 to perform a first operation / function; FPGA circuit elements 1700 in Figure 17 are configured and / or structured to perform a second operation / function corresponding to a second portion of machine-readable instructions represented by the flowcharts in Figures 5, 7, 8, 12, and 14; and / or the ASIC is configured and / or structured to perform a third operation / function corresponding to a third portion of machine-readable instructions represented by the flowcharts in Figures 5, 7, 8, 12, and 14.

[0108] Therefore, some or all of the circuit elements in Figure 1 and / or Figures 3A and 3B may be instantiated at the same time or at different times. The same and / or different parts of the microprocessor 1600 in Figure 16 may be programmed to execute some of the machine-readable instructions at the same time and / or at different times. The same and / or different parts of the FPGA circuit element 1700 in Figure 17 may be configured and / or structured to perform operations / functions corresponding to some of the machine-readable instructions at the same time and / or at different times.

[0109] Some or all of the circuit elements in Figure 1 and / or Figures 3A and 3B may be instantiated, for example, in one or more threads that run concurrently and / or sequentially. The microprocessor 1600 in Figure 16 may execute machine-readable instructions in one or more threads that run concurrently and / or sequentially. The FPGA circuit elements 1700 in Figure 17 may be configured and / or structured to perform operations / functions concurrently and / or sequentially. Furthermore, some or all of the circuit elements in Figure 1 and / or Figures 3A and 3B may be implemented in one or more virtual machines and / or containers that run on the microprocessor 1600 in Figure 16.

[0110] The programmable circuit element 1512 in Figure 15 may reside in one or more packages. For example, the microprocessor 1600 in Figure 16 and / or the FPGA circuit element 1700 in Figure 17 may reside in one or more packages. An XPU can be implemented by the programmable circuit element 1512 in Figure 15, which may reside in one or more packages. The XPU may include a CPU in one package (e.g., the microprocessor 1600 in Figure 16, the CPU 1720 in Figure 17, etc.), a DSP in another package (e.g., the DSP 1722 in Figure 17), a GPU in yet another package, and an FPGA in yet another package (e.g., the FPGA circuit element 1700 in Figure 17).

[0111] Figure 18 illustrates a block diagram of an exemplary software distribution platform 1805 for distributing software, such as the machine-readable instruction 1532 in Figure 15, to other hardware devices (e.g., hardware devices owned and / or operated by a third party separate from the owner and / or operator of the software distribution platform). The software distribution platform 1805 may be implemented by any computer server, data facility, cloud service, etc., capable of storing software and transmitting software to other computing devices. The third party may be a customer of the entity that owns and / or operates the software distribution platform 1805. The entity that owns and / or operates the software distribution platform 1805 may be the developer, seller, and / or licensor of the software, such as the machine-readable instruction 1532 in Figure 15. The third party may be a consumer, user, retailer, OEM, etc., who purchases and / or licenses the software for use and / or resale and / or sublicensing. In such examples, the software distribution platform 1805 includes one or more servers and one or more storage devices. The storage device stores machine-readable instructions 1532 that can correspond to the machine-readable instructions in Figures 5, 7, 8, 12, and 14 as described above. One or more servers of the software distribution platform 1805 communicate with an exemplary network 1810 that can correspond to the Internet and / or any one or more of the networks described above. One or more servers transmit the software to the requesting party as part of a commercial transaction, upon request. Payment for the delivery, sale, and / or license of the software may be handled by one or more servers of the software distribution platform and / or by a third-party payment entity. The servers enable purchasers and / or licensors to download machine-readable instructions 1532 from the software distribution platform 1805.Software that can correspond to the machine-readable instructions in Figures 5, 7, 8, 12, and 14 may be downloaded to the programmable circuit element platform 1500, which executes the machine-readable instructions 1532 to implement the egress time correction circuit element or ingress time correction circuit element function. One or more servers of the software distribution platform 1805 periodically provide, transmit, and / or enforce updates to the software (e.g., the machine-readable instructions 1532 in Figure 15) to ensure that improvements, patches, updates, etc., are delivered and applied to the software on end-user devices. Although referred to as "software" above, the "software" delivered may instead be firmware.

[0112] From the above, it will be understood that the described systems, devices, products, and methods facilitate improvements in the precise timestamping of network communications. The systems, devices, products, and methods described improve the efficiency of using computing devices by determining, predicting, and / or estimating variable delays resulting from encoding and / or decoding, and adjusting timestamps to offset such variable delays. By eliminating variable delays, consistent clock adjustment measurements can be determined and used to adjust the clock of a slave device to synchronize its clock with the clock of a master time server or other device. Thus, the systems, devices, products, and methods described are intended to address one or more improvements in the operation of computers or other electronic and / or mechanical devices.

[0113] Exemplary methods, apparatus, systems, and products for precise timestamping of Ethernet frames are described herein. Further examples, and combinations of such examples, are given below.

[0114] Example 1 is a device including a network interface circuit element and a logic circuit element configured to execute an instruction, wherein the instruction causes the logic circuit element to determine a first delay introduced by a physical coding sublayer circuit element at a first time, to adjust a first timestamp associated with and transmitted with a first transmission based on the first delay, and to determine a second delay introduced by the physical coding sublayer circuit element at a second time, which is different from the first delay, to adjust a second timestamp associated with and transmitted with a second transmission based on the second delay.

[0115] Example 2 is the same device as in Example 1, and includes a device in which an instruction causes a logic circuit element to determine a first delay at the start of transmission of a first signal and a second delay at the start of transmission of a second signal.

[0116] Example 3 is the device of Example 1, which includes a device in which an instruction causes a logic circuit element to insert a first timestamp into a time-synchronized message.

[0117] Example 4 is the apparatus of Example 1, which includes an apparatus in which an instruction causes a logic circuit element to determine a first delay based on the state of a physical coding sublayer circuit element.

[0118] Example 5 is the apparatus of Example 4, wherein the state of the physical coding sublayer circuit element includes matching of a first clock signal and a second clock signal.

[0119] Example 6 is the apparatus of Example 5, which includes an instruction that causes a logic circuit element to determine a first delay based on the difference between the first edge of a first clock signal and the second edge of a second clock signal.

[0120] Example 7 is the apparatus of Example 6, which includes an instruction that causes a logic circuit element to determine a first delay based on the difference between the first rising edge of a first clock signal and the second rising edge of a second clock signal.

[0121] Example 8 is the apparatus of Example 1, wherein the physical coding sublayer circuit element includes an encoder circuit element, and the instruction causes the logic circuit element to determine a first delay of the encoder circuit element.

[0122] Example 9 is the apparatus of Example 8, which includes an apparatus in which the encoder circuit element is an error correction circuit element.

[0123] Example 10 is the apparatus of Example 9, which includes an encoder circuit element that is a Reed-Solomon error correction circuit element.

[0124] Example 11 is the device of Example 9, which includes a device in which an instruction causes a logic circuit element to determine a first delay based on the relative position of the start of a packet within a frame of an encoder circuit element.

[0125] Example 12 is the apparatus of Example 9, which includes a first delay associated with a first frame of data, and an instruction causes a logic circuit element to determine a second delay for a second frame of data as a number of fewer cycles than the first delay.

[0126] Example 13 is a device comprising a network interface circuit element, a clock circuit element, and a logic circuit element configured to execute an instruction, wherein the instruction causes the logic circuit element to determine a first delay introduced by a physical coding sublayer circuit element at a first time, to adjust a first timestamp associated with a first received time-synchronization message, to determine a second delay introduced by a physical coding sublayer circuit element at a second time, to adjust a second timestamp associated with a second received time-synchronization message which is associated with the first received time-synchronization message, and to adjust the time value of the clock circuit element based on the difference between the first timestamp and the second timestamp. 13 is the device of Example 12, wherein the logic circuit element further adjusts the time value based on a third timestamp and a fourth timestamp.

[0127] Example 14 is the apparatus of Example 13, which includes an apparatus in which an instruction causes a logic circuit element to determine a first delay based on the state of a physical coding sublayer circuit element.

[0128] Example 15 is the apparatus of Example 13, which includes an instruction that causes a logic circuit element to determine a first delay based on a first variable delay of a first bit-level conversion.

[0129] Example 16 is the apparatus of Example 15, which includes an instruction that causes a logic circuit element to determine a first delay based on a second variable delay of a second bit-level conversion.

[0130] Example 17 is the apparatus of Example 13, which includes an instruction that causes a logic circuit element to determine a first delay based on a variable delay of the error correction process.

[0131] Example 18 includes a method that includes adjusting a first timestamp based on a first delay of a first physical coding sublayer associated with receiving a first time-synchronization message, adjusting a second timestamp based on a second delay of a second physical coding sublayer associated with sending a second time-synchronization message, and adjusting a clock time based on at least the first timestamp and the second timestamp.

[0132] Example 19 includes the method of Example 18, further comprising sending a second time synchronization message to a time server.

[0133] Example 20 includes the method of Example 18, further comprising inserting a second timestamp into a second time synchronization message.

[0134] Please note that this application claims priority to Indian Provisional Patent Application No. 202341020859, filed on 24 March 2023, which is incorporated herein by reference in its entirety. [Patent Document 1] Indian provisional patent application number 202341020859

[0135] In this specification, descriptors such as “first,” “second,” and “third” are used to identify multiple elements or components that may be referred to individually. Unless otherwise specified, such descriptors do not imply any order, physical sequence, placement within a list, or temporal sequence, but are merely used as markers to refer to multiple elements or components individually in order to facilitate understanding of the examples described. The descriptor “first” may be used to refer to an element in a “mode for carrying out the invention,” but the same element may also be referred to in the claims along with different descriptors such as “second” or “third.” In such cases, such descriptors are merely used to facilitate referencing multiple elements or components.

[0136] In the specification and claims, the terms “includes” and “have,” and variations thereof, are inclusive, as is the term “inclusive,” unless otherwise stated. Unless otherwise stated, “about,” “approximately,” or “substantially” preceding a value means plus or minus 10 percent of the stated value. In another example, “about,” “approximately,” or “substantially” preceding a value means plus or minus 5 percent of the stated value. In another example, “about,” “approximately,” or “substantially” preceding a value means plus or minus 1 percent of the stated value.

[0137] The terms “to connect,” “connected,” and “coupled,” and variations thereof, may include connections, communications, or signaling paths that enable a functional relationship consistent with this description. For example, if device A generates a signal to control device B to perform a certain action, in the first example, device A is connected to device B, or in the second example, if the intervening component C does not substantially alter the functional relationship between device A and device B, device A is connected to device B via the intervening component C, and therefore device B is controlled by device A via the control signal generated by device A. The terms “to connect,” “connected,” and variations thereof, and variations thereof, may include indirect or direct electrical or mechanical connections.

[0138] A device "configured" to perform a certain task or function may be configured (e.g., programmed and / or wired) by the manufacturer at the time of manufacture to perform such function, and / or may be configurable (or reconfigurable) by the user after manufacture to perform such function and / or other additional or alternative functions. Such configuration may be via the device's firmware and / or software programming, via the construction and / or layout of the device's hardware components and interconnections, or a combination thereof.

[0139] In the drawings, not all are shown separately, but the components or elements of the illustrated systems and circuits have one or more conductors or terminations that allow signals to enter into and / or exit from such components or elements. Conductors or terminations (or parts thereof) may be referred to herein as pins, pads, terminals (including, for example, input terminals, output terminals, reference terminals, and ground terminals), inputs, outputs, nodes, and interconnects.

[0140] As used herein, “terminals” of a component, device, system, circuit, integrated circuit, or other electronic or semiconductor component generally refers to conductors such as wires, traces, pins, pads, or other connectors or interconnects that enable a component, device, system, etc. to be electrically and / or mechanically connected to another component, device, system, etc. For example, terminals may be used to receive or provide analog or digital electrical signals (or simply signals), or to electrically connect to a common reference or ground reference. Thus, an input terminal or input is used to receive a signal from another component, device, system, etc. An output terminal or output is used to provide a signal to another component, device, system, etc. Other terminals may be used to connect to a common reference, ground reference, or voltage reference, for example, a reference terminal or ground terminal. Terminals of an IC or PCB may also be referred to as pins (longitudinal conductors) or pads (planar conductors). A node refers to a point of connection or interconnection of two or more terminals. An illustrative number of terminals and nodes may be shown. However, depending on the topology of a particular circuit or system, there may be more or fewer terminals and nodes. However, in some cases, "terminals," "nodes," "interconnectors," "pads," and "pins" can be used interchangeably.

[0141] As used herein, “programmable circuit element” is defined to include (1) one or more special-purpose electrical circuits (e.g., application-specific circuits (ASICs)) that are structured to perform a particular operation and include one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors), and / or (2) one or more general-purpose semiconductor-based electrical circuits that are programmable with instructions to perform a particular function and / or operation and include one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of programmable circuit elements include programmable microprocessors such as central processing units (CPUs) that can execute a first instruction to perform one or more operations and / or functions; field-programmable gate arrays (FPGAs) that can be programmed with a second instruction to cause configuration and / or structuring of an FPGA in order to instantiate one or more operations and / or functions corresponding to a first instruction; graphics processor units (GPUs) that can execute a first instruction to perform one or more operations and / or functions; digital signal processors (DSPs), XPUs, network processing units (NPUs) that can execute a first instruction to perform one or more operations and / or functions; and / or integrated circuits such as microcontrollers and / or application-specific integrated circuits (ASICs). A certain XPU may be implemented by a heterogeneous computing system that includes multiple types of programmable circuit elements (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more NPUs, one or more DSPs, and / or any combination thereof) and orchestration techniques (e.g., application programming interfaces (APIs)) that can assign computing tasks to any of the multiple types of programmable circuit elements that are suitable and available to perform such computing tasks.

[0142] As used herein, an integrated circuit / circuit element is defined as one or more semiconductor packages containing one or more circuit elements, such as transistors, capacitors, inductors, resistors, current paths, and diodes. An integrated circuit may be implemented as one or more of the following: an ASIC, FPGA, chip, microchip, programmable circuit element, semiconductor substrate combining multiple circuit elements, or system-on-a-chip (SoC).

[0143] As used herein, the terms “non-transient computer-readable storage device” and “non-transient machine-readable storage device” are defined to include any physical (mechanical, magnetic, and / or electrical) hardware for holding information over a period of time, but exclude propagating signals and transmitting media. Examples of non-transient computer-readable storage devices and / or non-transient machine-readable storage devices include any type of random-access memory, any type of read-only memory, solid-state memory, flash memory, optical disks, magnetic disks, disk drives, and / or RAID (redundant arrays of independent disks) systems. As used herein, the term “device” refers to a physical structure, such as mechanical and / or electrical equipment, hardware, and / or circuit elements, which may or may not be composed of computer-readable instructions, machine-readable instructions, etc., and / or are manufactured to execute computer-readable instructions, machine-readable instructions, etc., or are not manufactured to execute them.

[0144] The term "includes" (and all its forms and tenses) is used herein as an open-ended term. Therefore, whenever a claim employs any form of "includes" (e.g., include, encompass, equip, have, etc.) as a preamble or within the description of any claim, additional elements, terms, etc., may exist without departing from the scope of the corresponding claim or description. Where used herein, the phrase "at least" is open-ended, for example, when used as a transitional term in the preamble of a claim, just as the terms "encompass" and "include" are open-ended. The term "and / or" refers to any combination or subset of A, B, and C, such as (1) A only, (2) B only, (3) C only, (4) A and B, (5) A and C, (6) B and C, or (7) A, B, and C, when used in the form of A, B, and / or C, for example. When used herein in the context of describing a structure, component, item, object, and / or thing, the phrase "at least one of A and B" refers to an implementation that includes any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, when used herein in the context of describing a structure, component, item, object, and / or thing, the phrase "at least one of A or B" refers to an implementation that includes any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. When used herein in the context of describing the implementation or execution of a process, instruction, action, activity, and / or step, the phrase "at least one of A and B" refers to an implementation that includes any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.Similarly, as used herein in the context of describing the implementation or execution of a process, instruction, action, activity, and / or step, the phrase “at least one of A or B” means an implementation that includes (1) at least one A, (2) at least one B, or (3) any of at least one A and at least one B.

[0145] Where used herein, singular references (e.g., “a certain,” “first,” “second,” etc.) do not exclude the plural. Where used herein, the term “a certain object” refers to one or more of those objects. The terms “a certain,” “one or more,” and “at least one” are interchangeable herein. Furthermore, although listed individually, multiple means, elements, or actions may be implemented, for example, by the same entity or object. Also, individual features may appear in different examples or claims, but these features may be combined in some cases, and their appearance in different examples or claims does not mean that the combination of features is not feasible and / or advantageous.

[0146] Modifications to the described examples are permitted within the scope of the claims, and other examples are also permitted.

Claims

1. It is a device, Network interface circuit elements, A logic circuit element configured to execute instructions, Includes, The instruction is given to the logic circuit element, In the first time period, a first delay is determined by the physical coding sublayer circuit element. A first timestamp is associated with and transmitted together with the first transmission based on the first delay, and is adjusted. A second delay is introduced by the physical coding sublayer circuit element in the second time period, which is different from the first delay, and the second delay is determined accordingly. Associated with the second transmission based on the second delay, and transmitted together with the second transmission, to adjust the second timestamp, Device.

2. The apparatus according to claim 1, wherein the instruction causes the logic circuit element to determine a first delay at the start of transmission of a first signal and to determine a second delay at the start of transmission of a second signal.

3. The apparatus according to claim 1, wherein the instruction causes the logic circuit element to insert the first timestamp into the time-synchronized message.

4. The apparatus according to claim 1, wherein the instruction causes the logic circuit element to determine the first delay based on the state of the physical coding sublayer circuit element.

5. The apparatus according to claim 4, wherein the state of the physical coding sublayer circuit element includes matching of a first clock signal and a second clock signal.

6. The apparatus according to claim 5, wherein the instruction causes the logic circuit element to determine the first delay based on the difference between the first edge of the first clock signal and the second edge of the second clock signal.

7. The apparatus according to claim 6, wherein the instruction causes the logic circuit element to determine the first delay based on the difference between the first rising edge of the first clock signal and the second rising edge of the second clock signal.

8. The apparatus according to claim 1, wherein the physical coding sublayer circuit element includes an encoder circuit element, and the instruction causes the logic circuit element to determine the first delay of the encoder circuit element.

9. The apparatus according to claim 8, wherein the encoder circuit element is an error correction circuit element.

10. The apparatus according to claim 9, wherein the encoder circuit element is a Reed-Solomon error correction circuit element.

11. The apparatus according to claim 9, wherein the instruction causes the logic circuit element to determine the first delay based on the relative position of the start of a packet within the frame of the encoder circuit element.

12. The apparatus according to claim 9, wherein the first delay is associated with a first frame of data, and the instruction causes the logic circuit element to determine the second delay for a second frame of data as a number of fewer cycles than the first delay.

13. It is a device, Network interface circuit elements, Clock circuit elements, A logic circuit element configured to execute instructions, Includes, The instruction is given to the logic circuit element, In the first time period, a first delay is determined by the physical coding sublayer circuit element. Adjust the first timestamp associated with the first received time-synchronized message, In the second time period, the second delay introduced by the physical coding sublayer circuit element is determined. Adjust the second timestamp associated with the second received time-synchronized message associated with the first received time-synchronized message, Based on the difference between the first timestamp and the second timestamp, the time value of the clock circuit element is adjusted. Device.

14. The apparatus according to claim 13, wherein the instruction causes the logic circuit element to determine the first delay based on the state of the physical coding sublayer circuit element.

15. The apparatus according to claim 13, wherein the instruction causes the logic circuit element to determine the first delay based on the first variable delay of the first bit-level conversion.

16. The apparatus according to claim 15, wherein the instruction causes the logic circuit element to determine the first delay based on the second variable delay of the second bit-level conversion.

17. The apparatus according to claim 13, wherein the instruction causes the logic circuit element to determine the first delay based on the variable delay of the error correction process.

18. It is a method, Adjusting a first timestamp based on a first delay of a first physical coding sublayer associated with receiving a first time-synchronized message, Adjusting the second timestamp based on the second delay of the second physical coding sublayer associated with the transmission of the second time-synchronized message, Adjusting the clock time based at least the first timestamp and the second timestamp, Methods that include...

19. A method according to claim 18, further comprising transmitting the second time synchronization message to a time server.

20. A method according to claim 18, further comprising inserting the second timestamp into the second time synchronization message.

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