High-speed selective carry-propagation adder

Abstract

The high-speed selective carry propagation adder circuit consists of a full adder that performs selective carry propagation in the critical path, rather than the conventional carry propagation method that limits operating speed. Instead of propagating the carry and using it for summation, it is proposed to propagate a selective carry in the critical path and use it for summation. As a result, the number of transistors required for the full adder cell is reduced, and high-speed operation and low power consumption are achieved by reducing parasitic resistance and capacitance. Furthermore, the proposed circuit design reduces the number of transistors required for a 1-bit full adder cell to 14 for static CMOS logic, 10 for transmission gate type, and 8 for pass transistor type. In addition, the proposed adder circuit provides a versatile and efficient solution for multi-bit adders in various logic schemes and is expected to have applications in various fields.

Description

[Technical Field]

[0001] This invention generally relates to the addition of two N-bit binary numbers. More specifically, this invention relates to a high-speed selective carry-propagation adder. [Background technology]

[0002] In modern digital systems such as microprocessors, image and video processing, and digital signal processing devices (DSPs), one of the most basic and important arithmetic functions is the addition of two N-bit binary numbers.

[0003] Binary addition, performed using a full adder, is a fundamental operation in digital systems, and full adders are essential components in arithmetic operations such as subtraction, multiplication, and division. Similar to the central processing unit (CPU), full adders are essential components of multiply-accumulate (MAC) units and are widely used in digital signal processing, neural networks, and in-memory computing applications.

[0004] The efficiency and speed of a full adder directly impact the performance of the entire digital system. Therefore, the performance of a digital computing system largely depends on how quickly the adder processes data, as this determines the minimum clock cycle time.

[0005] This speed improvement benefits applications such as real-time processing, data-intensive computing, and high-performance computing. Furthermore, faster binary arithmetic contributes to energy efficiency by reducing computation time, resulting in lower power consumption and extended battery life for mobile devices.

[0006] Despite advancements in adder architecture at the system level, such as carry skip, carry save, and carry lookahead adders, the conventional Miller adder remains the most widely used standard adder cell.

[0007] Conventional binary adders, such as Miller adders, inherit the advantages of static CMOS logic, including rail-to-rail swing and high noise immunity. Alternate full adders using different logic modes have also been proposed, but each logic mode has its own advantages and disadvantages, which affect applications. The delay of ripple adders employing these logic modes is limited by the carry propagation method, which belongs to the critical path. Such full adder circuits are called conventional full adder circuits (TFACs). They have limitations such as long carry propagation delay, a large number of transistors, high power consumption, and lack of flexibility.

[0008] Conventional full adder designs aim for a compact and efficient implementation of Boolean functions. Prior art has proposed numerous full adder designs in the categories of static CMOS, dynamic CMOS, pseudo-NMOS, transmission gate, and pass transistor logic. However, a drawback of these designs is their dependence on specific logic modes, making them inefficient for other modes.

[0009] The Miller-designed full adder (MDFA), also known as the Miller adder, is the most widely used conventional adder circuit in CMOS logic. As shown in Figure 1, the PMOS stack in the Miller-designed full adder is a perfect mirror image of the NMOS stack, but requires up to 24 transistors. One of the main drawbacks of this design is that the increased number of transistors increases parasitic resistance and capacitance, resulting in reduced signal integrity and slower operating speed. Another drawback is increased power consumption, which limits the application of these circuits to low-power computing systems.

[0010] As shown in Figure 2, a two-stage arithmetic approach known as the Full Adder using Generate and Propagate (FAGP) allows for an alternative full adder design requiring only 18 transistors. The speed of the adder circuit depends on both the number and size of transistors, which are factors that determine the input capacitance. Despite the reduction in the number of transistors, the performance is inferior to MDFA because the carry propagation mechanism is slow due to the large size of the PMOS stack used for sum calculation. Furthermore, a major reason why the Full Adder using Generate and Propagate (FAGP) design is disadvantageous is that the sum is a redundant Boolean variable G i and P i The key point is that it is calculated using a full adder. A carry generator (G i ) and carry propagation (P i ) cannot be done simultaneously. [Overview of the project] [Problems that the invention aims to solve]

[0011] The objective of the present invention is to provide a high-speed selective carry-propagation adder circuit that achieves faster performance, improved overall efficiency, and application to various logic modes.

[0012] Another object of the present invention is to provide a circuit that can reduce the number of transistors required for a full adder cell and minimize the propagation delay of the critical path.

[0013] Another objective of the present invention is to provide a circuit that is compatible with other logic designs such as static CMOS, dynamic logic, transmission gates, and pass transistors, thereby increasing design versatility and providing a circuit suitable for a wide range of applications.

[0014] Another object of the present invention is to provide a circuit that can efficiently add multiple bits without signal degradation in the critical path, resulting in improved robustness and increased operating speed.

[0015] Another object of the present invention is to provide a circuit that reduces parasitic resistance and parasitic capacitance within the circuit, resulting in improved performance and increased operating speed.

[0016] Another object of the present invention is to provide a circuit that improves the logical effort of full adder design and thereby improves the operating speed of the circuit. [Means for solving the problem]

[0017] This summary describes embodiments related to full adder circuits, including those in CMOS logic, transmission logic, and pass transistor logic. This summary does not identify the essential features of the claimed invention, nor is it intended to be used to determine or limit the scope of the claimed invention.

[0018] In a preferred embodiment, the present invention provides a selective carry full adder circuit in static CMOS logic, the circuit having first (V1) and second (V2) power terminals to which an operating voltage is applied, a selective carry output generation circuit configured to receive a first input signal, a second input signal and a third input signal and generate a first output signal, and a sum bit generation circuit connected to the selective carry output generation circuit and configured to receive an output signal from the selective carry output generation circuit, a first input signal, a second input signal and a third input signal and generate a second output signal, the selective carry output generation circuit including a first pull-up network and a first pull-down network, the first pull-down network having a selective carry input (M i ) and the signal generated from the pre-adder (G i-1 Two parallel-connected NMOS transistors configured to receive a propagating carry signal (P iand an NMOS transistor serially connected to two transistors configured to receive a ground voltage supply. The first pull-up network is complementary logic of the first pull-down network, and the generated first output signal is a selection carry output signal (number 1). Here, the sum bit generation circuit includes a second pull-up network and a second pull-down network. The second pull-down network includes a selection carry input (M i ), a generated carry (G i-1 ) from the previous adder, and a propagation carry signal (P i ), and three NMOS transistors connected in parallel configured to receive the signal, and an NMOS transistor serially connected to three transistors configured to receive the selection carry output signal (number 1) from the selection carry generation circuit and a ground voltage supply. The second pull-up network is complementary logic of the second pull-down network, and the generated second output signal is the sum of the inputs (number 2).

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[0019] In another preferred embodiment, the present invention provides a selective digit carry propagation full adder circuit in transmission gate logic, the circuit having a selection carry output generation circuit and a sum generation circuit. The carry output generation circuit has a selection carry input (number 4) that passes through a first NMOS transistor by a generated input (number 3) from the previous adder to generate a first non-inverted output. The first output passes through a first NOT gate (U1) to generate a second inverted output. The second output passes through a second NMOS transistor by a propagation carry input (P i ) to generate a third output, and the third output passes through a second NOT gate (U2) to provide a selection carry output (number 1). The sum generation circuit has three inputs, namely, a carry propagation signal input (P i ), the first non-inverted output from the selection carry output generation circuit, and an inverter and a sum (S) from the selection carry output generation circuiti It has a second output to a transmission gate that generates ).

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[0020] In another preferred embodiment, the present invention provides a selective carry-propagating full adder circuit in pass transistor logic, the circuit comprising a selective carry output generation circuit and a sum generation circuit. The carry output generation circuit includes a selective carry input (Equation 4) that passes through a first NMOS transistor via a generated input (Equation 3) from the preceding adder to generate a first non-inverting output, the first output passing through a first NOT gate (U1) to generate a second inverting output, and the second output passing through a propagating carry input (P i The signal passes through a second NMOS transistor to generate a third output, which then passes through a second NOT gate (U2) to provide a selected carry output (Equation 1). The sum generation circuit has three inputs, namely, a carry-propagation signal input at the gates of the NMOS and PMOS pass transistors (P i ), including a first non-inverting output and a second inverting output that is supplied from a selective carry output generation circuit to a pass transistor to generate a sum (Si).

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[0021] In another preferred embodiment, the present invention provides a method for adding 3 bits using a selective carry-lookahead full adder circuit, the method comprising the steps of: (901) performing a first NAND operation on first and second input terminals adapted to receive a first carry input (C0) and a first propagation (P0) to generate a first output as an inverted selective carry input signal (Equation 5); and performing a first AND operation on first and second input terminals adapted to receive a first output inverted selective carry input (Equation 5) and a first inverted generated carry (Equation 6) to a first OR operation Steps include: generating an output that gives a number (902); performing a first OR operation on first and second input terminals adapted to receive the output from the first AND operation and an inverted second propagation (number 7), and generating a second output as an inverted selected carry input signal (number 8) (903); and performing a second AND operation on first, second and third input terminals adapted to receive the first output inverted selected carry input signal (number 5), an inverted first generated carry (number 6), and an inverted second generated carry (number 9), and generating an output that gives a first input signal to the second OR operation ( 904) and a step (905) of performing a third AND operation on first and second input terminals adapted to receive an inverted second propagation (Equation 7) and an inverted second generated carry (Equation 9), thereby generating an output that provides a second input signal to the second OR operation, and a step (906) of performing a second OR operation on first, second and third input terminals adapted to receive the output from the second AND operation, the output from the third AND operation, and an inverted third propagation (Equation 10), thereby generating a third output as an inverted selected carry input signal (Equation 11), and the output from the first NAND operation (Equation 5), the inverted Steps (907) include: performing a fourth AND operation on first, second, third, and fourth input terminals adapted to receive a first generated carry (equation 6), an inverted second generated carry (equation 9), and an inverted third generated carry (equation 12), thereby generating an output that provides a first input signal to the third OR operation; and performing a fifth AND operation on first, second, and third input terminals adapted to receive an inverted second propagation (equation 7), an inverted second generated carry (equation 9), and an inverted third generated carry (equation 12), thereby generating an output that provides a second input signal to the third OR operation.The process includes: (909) performing a sixth AND operation on first and second input terminals adapted to receive a third inverted propagation (Equation 10) and an inverted third generated carry (Equation 12), and generating an output that provides a third input signal to the third OR operation; (910) performing a third OR operation on first, second, third, and fourth input terminals adapted to receive the output from the fourth AND operation, the output from the fifth AND operation, the output from the sixth AND operation, and the fourth inverted propagation (Equation 13), and generating a fourth output as an inverted selected carry input signal (Equation 14); and (911) performing a second NAND operation on first and second input terminals adapted to receive the output from the third OR operation and the fourth inverted generated carry signal (Equation 15), and generating a carry output signal (C4).

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[0022] Other aspects and advantages of the present invention will become apparent from the following description in conjunction with the accompanying drawings that illustrate the principles of the present invention.

[0023] The accompanying drawings constitute part of the detailed description and are used to aid in a further understanding of the present invention. These accompanying drawings illustrate embodiments of the present invention used to illustrate the principles of the present invention. The embodiments are shown illustratively in the accompanying drawings and are not limited thereto. In the drawings, the same reference numerals indicate similar components. In this invention, the phrase "one embodiment" or "one embodiment" does not necessarily refer to the same embodiment, but means at least one embodiment. [Brief explanation of the drawing]

[0024] [Figure 1] Figure 1 is a schematic diagram showing a conventional Miller-designed full adder (MDFA) cell. [Figure 2] Figure 2 is a schematic diagram showing a full adder (FAGP) using the conventional generation and propagation method. [Figure 3A] Figure 3A is a block diagram of a high-speed selective carry-propagation full adder (SCPFA). [Figure 3B] Figure 3B is a schematic diagram showing a high-speed selective carry-propagation full adder (FA_EVEN block). [Figure 4] Figure 4 is a schematic diagram showing a multibit adder / subtractor using a selective carry-propagation adder. [Figure 5] Figure 5 is a schematic diagram showing a high-speed selective carry-propagation full adder (FA_ODD block). [Figure 6] Figure 6 is a schematic diagram showing a high-speed selective carry-propagation adder (transmission gate logic method). [Figure 7] Figure 7 is a schematic diagram showing a high-speed selective carry-propagation adder (pass transistor logic type). [Figure 8] Figure 8 is a schematic diagram showing a conventional carry-lookahead adder. [Figure 9A] Figure 9A is a schematic diagram of a selective carry-ahead adder. [Figure 9B] Figure 9B shows the 2-bit addition method in a selective carry lookahead adder. [Modes for carrying out the invention]

[0025] A more complete understanding of the present invention and its embodiments can be obtained by referring to the following description and accompanying drawings.

[0026] The detailed description below, in relation to the accompanying drawings, is intended to describe various embodiments of the present invention and is not intended to represent the only possible embodiments in which the present invention can be carried out. Each embodiment described herein is provided merely as an example or illustration of the present invention and should not necessarily be construed as being preferable or advantageous to other embodiments. The detailed description includes certain details for the purpose of making the present invention fully understandable. However, those skilled in the art will understand that the present invention can be carried out without these specific details.

[0027] In this specification, the term “comprising” means, but not limited to, “including,” and should be interpreted in the manner commonly used in a patent context. The use of broader terms such as “comprising,” “including,” and “having” should be understood as supporting narrower terms such as “consisting of,” “essentially consisting of,” and “substantially constituted.”

[0028] Expressions such as "in one embodiment," "according to one embodiment," and "in several embodiments" generally mean that a particular function, structure, or feature following such expression may be included in at least one embodiment of the Disclosure (importantly, these expressions do not necessarily refer to the same embodiment) and may be included in multiple embodiments of the Disclosure.

[0029] In this specification, the terms “example” or “exemplary” mean “functioning as an example, case, or illustration.” No embodiment described as “exemplary” in this specification should be construed as preferable or advantageous to any other embodiment.

[0030] The approximate expressions used throughout this specification and the claims may be applied to modify any quantitative expressions that may vary within an acceptable range without altering the underlying function. Therefore, values ​​modified by terms such as “less than” or “approximately” are not limited to the specified exact value. In some cases, the approximate expression may correspond to the precision of the instrument used to measure the value.

[0031] This invention proposes a high-speed selective carry full adder circuit for improving the performance of digital systems such as microprocessors and digital signal processors. The invention proposes improving performance, power consumption, and applicability to various logic designs by using selective carry propagation in the critical path instead of conventional carry propagation methods. By propagating selective carry and using it in sum calculations, the number of transistors is reduced, making the system faster and more energy-efficient. The proposed circuit is highly versatile and adaptable to various logic modes, making it suitable for a wide range of applications.

[0032] Figure 1 shows a conventional full adder circuit (100) consisting of a carry output generation circuit (101) and a sum generation circuit (102) based on prior art. The carry output generation circuit receives the first input signal (A i ), second input signal (B i ), 3rd input signal (C i It is configured to generate a first output signal (equation 16) based on ).

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[0033] The sum bit generation circuit (102) is connected to the carry output generation circuit (101), and receives the first output (number 16) from the carry output generation circuit, and the first input signal (A i ), second input signal (B i ), 3rd input signal (C i ) and the sum of the second output signals (S) based on the first output signal (Equation 16) i This generates the second output signal, which is the output sum bit of the full adder circuit.

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[0034] The circuit shown in Figure 1 is a Miller-designed full adder (MDFA) circuit (100), which comprises multiple pull-up and pull-down networks, and each pair of pull-up and pull-down networks is structurally symmetrical.

[0035] The carry output generation circuit (101) may include subunits in the form of a first pull-up network subunit (101a) and a first pull-down network subunit (101b). The pull-up subunit (101a) controls input A i and B i The signal is received by a parallel-connected PMOS transistor, and input C i Enter A i and B i It is configured to receive the signal through a PMOS transistor connected in series with it. Input A i and B i Two more PMOS transistors are present in series and are arranged in parallel with the remaining inputs. The pull-down subunit (101b) is complementary (and mirrored) to the pull-up subunit, and both subunits generate an output signal (equation 16), which becomes the input to the sum bit generation circuit (102).

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[0036] The sum bit generation circuit (102) may include subunits in the form of a second pull-up network subunit (102a) and a second pull-down network subunit (102b). The pull-up subunit (102a) is a parallel PMOS transistor connected in series with a PMOS transistor that receives the input signal (equation 16) to input A i B i , C i It is configured to receive input A. i B i , C i Three more PMOS transistors are connected in series and in parallel with the remaining inputs to subunit (102a). The pull-down subunit (102b) is complementary (and mirrored) to the pull-up subunit, and both subunits generate the output sum (number 2) for the adder.

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[0037] In the full adder disclosed in Figure 1, the relationship between the input and output is expressed by logic Boolean expressions (1) and (2). These expressions are given by two binary inputs A i B i , and carry input C i It is used in digital systems to calculate additions.

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[0038] These formulas are the sum of the total adder (S i ) and carry output (C i+1 This defines the calculation of the sum (S). Carry propagation is a critical path in multibit adders, causing a large delay in the overall calculation. As a result, the sum (S iThe calculation of ) can tolerate some delay, so the carry output (C i+1 The ) signal can be used to calculate the sum. This approach can reduce the number of transistors in the circuit. Sum (S) in a full adder. i ) is evaluated using equation (3).

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[0039] The Boolean expressions given by equations (2) and (3) are used to implement the Miller-designed full adder (MDFA) shown in Figure 1.

[0040] Figure 2, following another example of prior art, shows a full adder using a generation and propagation scheme (FAGP) requiring 18 transistors, but this is not an optimized design for a full adder cell. This circuit includes a carry output generation circuit (201) and a sum generation circuit (202). The carry output generation circuit takes the first input signal (G i ), second input signal (P i ), and the third input signal (C i It is configured to generate a first output signal (equation 16) based on ).

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[0041] The summing circuit disclosed in Figure 2 comprises multiple pull-up networks and pull-down networks, and each pair of pull-up and pull-down networks is structurally complementary to one another.

[0042] The carry output generation circuit (201) may include subunits in the form of a first pull-up network subunit (201a) and a first pull-down network subunit (201b). The pull-up subunit (201a) is connected to input C i and input P i The signal is received by a parallel PMOS transistor, and the input G i Input C i and input P iIt is configured to receive the signal through a PMOS transistor connected in series. The pull-down subunit (201b) is complementary to the pull-up subunit, and both subunits generate an output signal (equation 16), which becomes the input to the sum bit generation circuit (202).

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[0043] The sum bit generation circuit (202) may include subunits in the form of a second pull-up network subunit (202a) and a second pull-down network subunit (202b). The pull-up subunit (202a) receives the input signal (number 16). Furthermore, the input G i and input C i Two PMOS transistors are arranged in parallel and connected in series to the remaining inputs to subunit (202a). The pull-down subunit (202b) is complementary to the pull-up subunit, and both subunits generate the output sum (equation 2) for the adder.

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[0044] FAGP can be implemented using 18 transistors per bit and can be achieved through a two-step arithmetic approach.

[0045] In the first stage of the adder, the generation term (G) for each bit is defined by equations (4) and (5). i ) and propagation term (P i ) calculate.

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[0046] P i This is called "carry propagation". i This is because when it is high, the carry input propagates to the carry output. i When is high, the bit being added generates a carry output, so this variable is known as the "carry generator". In the second stage, the carry generator term (G) of each bit is calculated. i ) and carry propagation term (P i ) combine and use equations (6) and (7) to sum (S i ) and carry output (C i+1 ) generates.

[0047] The sum in equation (3) (S i By using the same method as the evaluation of ), the sum (S i ) is G i , P i , C i It is expressed using (6) and (7). The implementation of a full adder using Boolean expressions is called a full adder with generation and propagation (FAGP).

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[0048] This invention proposes a Selective Carry-Propagation Full Adder (SCPFA) circuit aimed at improving the speed and efficiency of multi-bit adders. Unlike conventional full adder designs specialized for specific logic modes, the proposed design can be easily integrated into various computing systems and adapted to diverse logic modes. This flexibility enables seamless integration into various digital architectures and facilitates efficient binary addition across different platforms.

[0049] The following sections discuss in detail implementation examples of full adder circuits in various logic configurations, making their implementation clear to those skilled in the art.

[0050] Full adder using static CMOS logic According to a first embodiment of the present invention, Figure 3A shows a block diagram of a static CMOS full adder circuit (300). This circuit comprises a plurality of pull-up networks and pull-down networks, where each pair of pull-up and pull-down networks has a complementary structure. The circuit mainly consists of two units: a selective carry output generation circuit (301) and a sum bit generation circuit (302). The selective carry output generation unit includes a first pull-up circuit (301a) and a first pull-down circuit (301b) connected to each other, and is configured to generate a first intermediate output selective carry output bit (Number 1). The sum bit generation unit includes a second pull-up circuit (302a) and a second pull-down circuit (302b) connected to each other, and is configured to receive an intermediate output (Number 1) from the selective carry output generation circuit as one of its inputs and generate a sum (Number 2) as an output.

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[0051] According to another embodiment of the present invention, Figure 3B is a schematic diagram showing the high-speed carry propagation adder shown in Figure 3A. The circuit shown in Figure 3A can be divided into two subcircuits: a selective carry output generation circuit (301) and a sum bit generation circuit (302). Operating voltage (V dd There are two power supply terminals V1 and V2 to which the first input signal (P) is applied. The selective carry output generation circuit receives the first input signal (P) i ), second input signal (G i-1 ), and the third input signal (M i It is configured to receive the selected carry input (M) and generate a first output signal (Equation 1). The selected carry output generation circuit is further divided into a pair of first pull-up and first pull-down networks. The first pull-down network receives the selected carry input (M) and is configured to generate a first output signal (Equation 1). i ) and the generated signal (G) from the pre-adder. i-1 Two NMOS transistors are connected in parallel to receive the propagated signal (P). i ) and an NMOS transistor configured to receive a ground voltage supply. The first pull-up network is the complementary logic of the first pull-down network and consists of two PMOS transistors connected in series and one PMOS transistor placed between the first power supply terminal V1 and the first output signal (Equation 1) and connected in parallel with the two transistors.

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[0052] The sum bit generation circuit is connected to a selective carry output generation circuit and is configured to receive the output signal (Equation 1), the first input signal (Pi), the second input signal (Gi-1), and the third input signal (Mi) from the selective carry output generation circuit and generate a second output signal (Equation 2). The sum bit generation circuit is further divided into a pair of second pull-up and second pull-down networks. Here, the second pull-down network receives the selective carry input (M i ), the signal generated from the pre-adder (G i-1 ), and the propagated signal (Pi It is composed of three NMOS transistors connected in parallel and configured to receive i , and further includes one NMOS transistor connected in series to the three transistors and configured to receive the selection carry output signal (Equation 1) from the selection carry generation circuit and the ground voltage supply. The second pull-up network is the complementary logic of the second pull-down network, and is composed of three PMOS transistors connected in series between the second power supply terminal V2 and the second output signal (Equation 2), and one PMOS transistor arranged in parallel with these three transistors.

Equation

Equation

[0053] Carry propagation forms the critical path of a multi-bit adder that limits the operating speed. As shown in Equation (6) above, a conventional full adder cell either generates a carry (G i ) or propagates an input carry (C i P i ) to the next stage. Equation (6) is reproduced here for reference.

Equation

[0054] Instead of propagating the carry output (C i+1 ) for use in the sum calculation, this specification proposes selectively propagating only the carry propagation (C i P i ) bits in the critical path and using this for the sum calculation.

[0055] For this purpose, a variable "M" representing the carry propagation (C i P i ) is defined as follows.

Equation

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[0056] The implementation of a full adder using the Boolean expressions given by equations (11) and (12) requires 14 transistors in a static CMOS implementation, as shown in Figures 3A and 3B. The full adder design according to this embodiment employs fewer transistors for a comparable size, resulting in improved operating speed due to lower parasitic resistance and capacitance. In the proposed design, an independent Boolean variable G i-1 and P i By using this method to calculate the sum, the number of transistors used is reduced.

[0057] Therefore, the carry output (C i+1 Instead of propagating the ) bits and using them in the sum calculation, selectively propagating only the carry-propagated (CiPi) bits in the critical path and using them in the sum calculation reduces the number of transistors used in the logic implementation and improves the efficiency of the sum calculation.

[0058] Logical effort is a widely used technique for calculating the delay of digital logic circuits. Since logical effort measures the relative ability of a gate to supply current to a fixed input capacitance, a smaller logical effort indicates a faster circuit. The logical effort of a carry signal is a suitable performance metric for comparing different full adder designs. Table 1 shows a performance comparison of different full adder designs using logical effort. The FAGP circuit has fewer transistors than the MDFA, but its logical effort is 18.55% higher due to its large PMOS stack. The proposed SCPFA adder design uses only 14 transistors and reduces the logical effort by 33.33% compared to the MDFA.

[0059] [Table 1]

[0060] Trade-offs between characteristics such as delay, area, and energy dissipation are available in different digital logic schemes. The advantage of static CMOS is its robustness to voltage scaling and transistor sizing, achieved through linear (ratio-less) circuits, enabling reliable operation even at low voltages. Dynamic CMOS circuits allow for high-speed operation due to their lower transistor count, but overall power consumption tends to be higher, including the power required for the clock tree. Due to their lower transistor count, pseudo-NMOS, transmission gate, and pass-transistor logic often result in area reduction. Each logic design style has its advantages and disadvantages, offering choices based on constraints and requirements.

[0061] The proposed selective carry propagation full adder scheme can be implemented using, but is not limited to, other logic designs such as dynamic CMOS logic, pseudo-NMOS, transmission gates, and pass transistor logic. Architectural-level optimizations such as carry skipping and carry preservation are also applicable to the proposed design.

[0062] The proposed application examples of the full adder design are shown below. The proposed SCPFA cell shown in FIGS. 3A and 3B generates an inverted sum and an output (Mout). Therefore, in a multi-bit adder design, it is required to add an inverter to the output of the full adder. Since the inverter becomes the critical path, it is necessary to eliminate it for high speed.

[0063] According to still other embodiments of the present invention, FIG. 4 shows a multi-bit select carry propagate adder and subtractor using SCPFA cells. Here, the necessity of an inverter in the critical path is eliminated by cascading the output of the full adder block (denoted as FA_EVEN in the circuit diagram shown in FIG. 3B) with an inverted full adder block (denoted as FA_ODD in the circuit diagram shown in FIG. 5). The GP_GEN_ODD block generates (Equation 31) and G i and the GP_GEN_EVEN block generates P i and (Equation 32). Here, P and G represent propagate and generate, respectively, and are defined by Equations (4) and (5). [Equation] [Equation]

[0064] Although a 4-bit adder / subtractor design is shown, it can be extended to any number of bits. Subtraction is realized using the two's complement method, and the same hardware can be used for both addition and subtraction by adding the two's complement of the subtrahend to the minuend. In the two's complement method, when subtracting one number from another, all bits of the minuend are inverted and then 1 is added to the least significant bit (LSB) (using a signal). The multi-bit design we propose utilizes the select carry propagate adder method based on the Boolean expressions shown in Equations (11) and (12) and can also be implemented in other logic designs such as dynamic logic, pseudo-NMOS, transmission gates, and pass transistors.

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[0065] According to yet another embodiment of the present invention, Figure 5 shows an inverting selective carry propagation full adder circuit (500). This circuit can be divided into two subcircuits: a selective carry output generation circuit (501) and a sum bit generation circuit (502). There are two power supply terminals V1 and V2 to which the operating voltage is applied. The selective carry output generation circuit (501) receives a first input signal (Equation 31), a second input signal (Equation 3), and a third input signal (Equation 4), and generates a first output signal (M i+1 The selective carry output generation circuit (501) is configured to generate a first pull-up (501a) and a first pull-down network (501b). The first pull-down network consists of two series-connected NMOS transistors configured to receive the selective carry input (Equation 4) and the carry generation signal (Equation 3) from the preceding adder, and an NMOS transistor connected in parallel to the two transistors and configured to receive the propagated signal (Equation 31) and the ground voltage supply. The first pull-up network (501a) is the complementary logic of the first pull-down network and consists of two PMOS transistors connected in parallel, and further consists of a first power supply terminal V1 and a first output signal (M i+1 It is positioned between the two transistors and includes one PMOS transistor connected in series with the two transistors.

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[0066] The sum bit generation circuit (502) is connected to the selective carry output generation circuit (501), and the output signal (M) from the selective carry output generation circuit is connected. i+1), receives the first input signal (Equation 31), the second input signal (Equation 3), and the third input signal (Equation 4), and outputs the second output signal (S i The sum bit generation circuit is further divided into a pair of second pull-up circuits (502a) and second pull-down circuits (502b). The second pull-down network consists of three series-connected NMOS transistors configured to receive a selective carry input (Equation 4), a generated carry from the preceding adder (Equation 3), and a propagating signal (Equation 31), and three transistors connected in parallel to the three transistors, which receive a selective carry output signal (M) from the selective carry output generation circuit. i+1 It has one NMOS transistor configured to receive the second power supply terminal V2 and the second output signal (S). The second pull-up network is a complementary logic circuit to the second pull-down network and has three parallel-connected PMOS transistors and three transistors connected in series with the second power supply terminal V2 and the second output signal (S). i It has one PMOS transistor located between ) and ).

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[0067] Full adder using transmission gate and pass transistor logic The transmission gate and pass transistor logic designs described later are complex, and multiple designs may be required for the same logic generation. Transmission gate and pass transistor logic schemes can cause signal degradation and increase the noise sensitivity of logic circuits, potentially affecting accuracy and reliability.

[0068] Logic circuits can be implemented using various transmission gate and pass transistor logic configurations.

[0069] According to another embodiment of the present invention, Figure 6 shows a full adder (600) using transmission gate and pass transistor logic with 10 transistors. The disclosed circuit comprises a selective carry output generation circuit (601) and a sum generation circuit (602). The carry output generation circuit has a selective carry input (Equation 4) that passes through a first NMOS transistor (601a) via a carry generation input (Equation 3) from the preceding adder, generating a first non-inverting output. A NOT operation is performed on this to generate a second inverting output. The second output is then passed through a propagated input (P i The signal passes through the second NMOS transistor (601b) and generates a third output. A NOT operation is performed on this third output to derive the selected carry output (Equation 1). The sum generation circuit (602) has three inputs, namely the propagated signal input (P) given to the inverter and the transmission gate. i ), has a first output from a selective carry output generation circuit and a second output from a selective carry output generation circuit, and sums (S i ) generates.

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[0070] To design the full adder cell using a transmission gate and pass transistor logic scheme, modified Boolean expressions such as those given in equations (13) and (14) were used. Using equations (11) and (12), the following equation is obtained:

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[0071] Full adder using pass transistor logic According to yet another embodiment of the present invention, Figure 7 shows a pass-transistor logic full adder (700) that uses only pass-transistor logic and requires only eight transistors. The disclosed circuit comprises a select-carry output generation circuit (701) and a carry generation circuit (702). The carry output generation circuit has a select-carry input (Equation 4), which passes through a first NMOS transistor (701a) via a generated carry input (Equation 3) from the preceding adder to generate a first non-inverting output. A NOT operation is performed on this first non-inverting output to generate a second inverting output. The second output is then passed through a propagated input (P i The signal passes through a second NMOS transistor (701c) to generate a third output. A NOT operation is performed on this third output to derive the selected carry output (Equation 1). The sum generation circuit has three inputs, namely the gates of the NMOS and PMOS pass transistors, to which the propagated signal input (P i It has an input that supplies (S), a first non-inverting output and a second inverting output to a pass transistor, and the sum (S i ) generates.

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[0072] To design a full adder cell using a transmission gate and pass transistor logic scheme, the modified Boolean expressions shown in equations (13) and (14) were used. Using equations (11) and (12), the following equation is obtained:

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[0073] A key advantage of this design (Figures 6 and 7) is that multi-bit addition can be achieved simply by cascading all adder cells, eliminating the need for an inversion step. The main problem with transmission gate and pass transistor logic design is threshold voltage loss, which can prevent the proper operation of multi-bit adders due to voltage drops. The proposed transmission gate and pass transistor logic design reduces output threshold voltage loss by using an output inverter as a voltage level recovery circuit in the critical path. The inverter in the critical path properly isolates the input and output while ensuring the necessary drive strength for the next stage.

[0074] Selective carry-forward adder A Carry Look Ahead Adder (CLA) uses carry look-ahead logic to calculate the carry input for each bit directly from the input. Compared to conventional ripple carry adders, CLAs require more components to implement one stage of a multi-bit adder.

[0075] Following the example of prior art, Figure 8 shows a conventional carry-lookahead adder, demonstrating that the number of components required for the circuit increases as the number of calculation stages increases. The carry-lookahead adder circuit has significantly shorter delays than the conventional ripple-carry adder circuit. However, the number of components increases even more dramatically as the number of stages increases, resulting in a CLA architecture of up to 4-bit blocks.

[0076] Two 4-bit binary numbers A and B need to be added, represented as A3A2A1A0 and B3B2B1B0 respectively, with the external carry input indicated by C0. The sum of this addition, S3S2S1S0, can be calculated by a full adder. Thus, it is expressed as (number 36), where C3, C2, and C1 are the carry outputs of the preceding bits. In the carry-lookahead adder circuit shown in Figure 8, the input P i and G i The carry output bits C4, C3, C2, and C1 are directly estimated using this method, and these do not depend on the carry value of the preceding stage.

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[0077] According to another embodiment of the present invention, Figure 9A shows a selective carry-lookahead adder circuit. This circuit comprises first and second NAND gates, first, second, third, fourth, fifth, and sixth AND gates, and first, second, and third OR gates. The first NAND gate has first and second input terminals adapted to receive a first carry input (C0) and a first propagation (P0), and generates a first output as an inverted selective carry input signal (Equation 5). The first AND gate has first and second input terminals adapted to receive a first output inverted selective carry input (Equation 5) and a first inverted generated carry (Equation 6), and generates an output that provides a first input signal to the first OR gate. The first OR gate has first and second input terminals adapted to receive the output from the first AND gate and an inverted second propagation (Equation 7), and generates a second output as an inverted selective carry input signal (Equation 8). The second AND gate has first, second, and third input terminals adapted to receive a first output inverted selective carry input (Equation 5), an inverted first generated carry (Equation 6), and an inverted second generated carry (Equation 9), and generates an output that provides the first input signal to the second OR gate. The third AND gate has first and second input terminals adapted to receive an inverted second propagation (Equation 7) and an inverted second generated carry (Equation 9), and generates an output that provides the second input signal to the second OR gate. The second OR gate has first, second, and third input terminals adapted to receive the output from the second AND gate, the output from the third AND gate, and an inverted third propagation (Equation 10), and generates a third output as an inverted selective carry input signal (Equation 11). The fourth AND gate has first, second, third, and fourth input terminals adapted to receive the output from the first NAND gate (Equation 5), an inverted first generated carry (Equation 6), an inverted second generated carry (Equation 9), and an inverted third generated carry (Equation 12), and generates an output that provides the first input signal to the third OR gate. The fifth AND gate is adapted to receive an inverted second propagated (Equation 7), an inverted second generated carry (Equation 9), and an inverted third generated carry (Equation 12), and generates an output that provides the second input signal to the third OR gate.The sixth AND gate has first and second input terminals adapted to receive a third inverted propagation (Equation 10) and an inverted third generated carry (Equation 12), and generates an output that provides a third input signal to the third OR gate. The third OR gate has first, second, third, and fourth input terminals adapted to receive the output from the fourth AND gate, the output from the fifth AND gate, the output from the sixth AND gate, and a fourth inverted propagation (Equation 13), and generates a fourth output as an inverted selected carry input signal (Equation 14). The second NAND gate has first and second input terminals adapted to receive the output from the third OR gate and a fourth inverted generated carry signal (Equation 15), and generates a carry output signal (C4).

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[0078] According to another embodiment of the present invention, Figure 9B shows a method for generating a sum using a selective carry-ahead adder circuit.

[0079] In step 901, the system performs a first NAND operation on the first and second input terminals, which are adapted to receive a first carry input (C0) and a first propagation (P0), to generate a first output as an inverted selected carry input signal (M1).

[0080] In step 902, the system performs a first AND operation on the first and second input terminals, which are adapted to receive a first output inverting selective carry input (M1) and a first inverting generating carry (G0), to generate an output that provides a first input signal to the first OR operation.

[0081] In step 903, the system performs a first OR operation on the first and second input terminals, which have been adapted to receive the output from the first AND operation and an inverted second propagation (P1), to generate a second output as an inverted selected carry input signal (M2).

[0082] In step 904, the system performs a second AND operation on the first, second, and third input terminals, which are adapted to receive a first output inverted selective carry input (M1), an inverted first generated carry (G0), and an inverted second generated carry (G1), to generate an output that provides a first input signal to the second OR operation.

[0083] In step 905, the system performs a third AND operation on the first and second input terminals, which have been adapted to receive an inverted second propagation (P1) and an inverted second generated carry (G1), generating an output that provides a second input signal to the second OR operation.

[0084] In step 906, the system performs a second OR operation on the first, second, and third input terminals, which are adapted to receive the output from the second AND operation, the output from the third AND operation, and an inverted third propagation (P2), thereby generating a third output as an inverted selected carry input signal (M3).

[0085] In step 907, the system performs a fourth AND operation on the first, second, third, and fourth input terminals, which are adapted to receive the output from the first NAND operation (M1), an inverted first generated carry (G0), an inverted second generated carry (G1), and an inverted third generated carry (G2), thereby generating an output that provides the first input signal to the third OR operation.

[0086] In step 908, the system performs a fifth AND operation on the first, second, and third input terminals, which are adapted to receive an inverted second propagated (P1), an inverted second generated carry (G1), and an inverted third generated carry (G2), generating an output that provides a second input signal to the third OR operation.

[0087] In step 909, the system performs a sixth AND operation on the first and second input terminals, which are adapted to receive a third inverted propagation (P2) and an inverted third generated carry (G2), to generate an output that provides a third input signal for the third OR operation.

[0088] In step 910, the system performs a third OR operation on the first, second, third, and fourth input terminals, which have been adapted to receive the output of the fourth AND operation, the output of the fifth AND operation, the output of the sixth AND operation, and the fourth inverted propagation (P3), thereby generating a fourth output as an inverted selected carry input signal (M4).

[0089] In step 911, the system performs a second NAND operation on the first and second input terminals, which have been adapted to receive the output from the third OR operation and the fourth inverted generated carry signal (G3), thereby generating a carry output signal (C4).

[0090] Using equation (13), select carry M i The formula used for estimation is as follows:

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[0091] Equation (18) also confirms that the generation of the selective carry output (equation 14) can be achieved with far fewer transistors than the generation of C4 in conventional CLA circuits. The sum can be calculated using equation (12), which further significantly reduces the number of transistors compared to conventional CLA circuits. Due to these two reductions in the number of transistors, the proposed selective carry-lookahead adder significantly reduces the hardware required for a parallel binary adder.

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[0092] Various embodiments of the present invention highlight the potential of the proposed selective carry propagation full adder circuit to overcome the limitations of conventional full adder designs. Significant reductions in propagation delay, energy consumption, and transistor count demonstrate the effectiveness of the selective carry propagation adder method. The performance improvements of the proposed circuit can impact various digital systems, potentially improving the speed and efficiency of microprocessors, digital signal processors, and multipliers (MACs). Reduced power consumption enables applications in energy-efficient computing systems, contributing to sustainability and lower operating costs. Furthermore, efficient transistor utilization and reduced chip area requirements allow for more compact and cost-effective integrated circuit designs.

[0093] As used herein, the terms “or” and “and / or” are interpreted comprehensively, meaning any one or any combination thereof. Thus, “A, B or C” or “A, B and / or C” may mean any of A, B, C, A and B, A and C, B and C, or A, B and C. An exception to this definition arises only if the combination of elements, functions, steps, or actions is in any way inherently mutually exclusive.

[0094] Any combination of the above features and functionalities may be used according to one or more embodiments. In the above-described specification, embodiments are described with reference to numerous specific details, which may differ from implementation to implementation. Therefore, the specification and drawings should be understood in an illustrative rather than restrictive sense. The sole and exclusive indication of the scope of the invention, and what the applicant intends to be the scope of the invention, is indicated only by the literal and equivalent scope in its particular form, as defined by the claims of this application (including any subsequent amendments).

Claims

1. A selection carry propagation full adder circuit (300) in static CMOS logic, The first (V) to which the operating voltage is applied. １ ) and the second (V ２ ) Power terminal and, First input signal (M ｉ ), second input signal (P ｉ ) and the third input signal (G ｉ－１ A selective carry output generation circuit (301) is configured to receive a signal and generate a first output signal (Equation 1), Connected to the selected carry output generation circuit, the output signal (Equation 1) from the selected carry output generation circuit, the first input signal (M ｉ ), the second input signal (Pi), and the third input signal (G ｉ－１ A sum bit generation circuit (302) is configured to receive the signal and generate a second output signal (number 2), Equipped with, The selected carry output generation circuit (301) includes a first pull-up network (301a) and a first pull-down network (301b). The first pull-down network (301b) receives a selective carry input (M ｉ ), and generation (G ｉ－１ ) from the adder in the previous stage, and includes two NMOS transistors connected in parallel and configured to receive the signals, and an NMOS transistor connected in series to the two transistors and configured to receive a propagation signal (P ｉ ) and a ground voltage supply. The first pull-up network is the complementary logic of the first pull-down network, The generated first output signal is a selected carry output signal (Equation 1), The sum bit generation circuit (302) includes a second pull-up network (302a) and a second pull-down network (302b). The second pulldown network (302b) has a selected carry input (M ｉ ), generated carry from the preceding adder (G ｉ－１ ), and propagated signal (P ｉ It includes three parallel-connected NMOS transistors configured to receive the selected carry output signal (Equation 1) and the ground voltage supply from the selected carry generation circuit, and an NMOS transistor connected in series with the three transistors and configured to receive the selected carry output signal (Equation 1) and the ground voltage supply from the selected carry generation circuit. The second pull-up network (302a) is the complementary logic of the second pull-down network, The generated second output signal is the sum of the inputs (Equation 2). A selective carry-propagation full adder circuit characterized by the following: [Math 1] [Math 2]

2. The first pull-up network (301a) consists of two PMOS transistors connected in series and the first power supply terminal V １ The selective carry propagation full adder circuit according to claim 1, further comprising a PMOS transistor positioned between the two transistors and the first output signal and connected in parallel with the two transistors.

3. The second pull-up network (302a) consists of three PMOS transistors connected in series and the second power supply terminal V ２ The selective carry propagation full adder circuit according to claim 1, further comprising a PMOS transistor positioned between the three transistors and the second output signal and connected in parallel with the three transistors.

4. A selection carry propagation full adder circuit (600) in transmission gate logic, Selective carry output generation circuit (601), Sum generation circuit (602) and Equipped with, The aforementioned carry output generation circuit is: The generated carry input (Equation 3) from the preceding adder passes through the first NMOS transistor (601a) and includes a selectable carry input (Equation 4) that generates the first output. The first output passes through the first NOT gate (601b) to generate the second output. The second output is the propagation input (P ｉ ) passes through the second NMOS transistor (601c) to generate the third output, The third output passes through the second NOT gate (601d) and provides a selected carry output (Equation 1), The sum generation circuit (602) receives a propagated signal input (P) which is input to the inverter and the transmission gate. ｉ It has three inputs, including the first output from the selective carry output generation circuit and the second output from the selective carry output generation circuit, and the sum (S ｉ ) generates A selective carry-propagation full adder circuit characterized by the following: [Math 3] [Math 4] [Math 1]

5. A selectable carry propagation full adder circuit (700) in pass transistor logic, Selective carry output generation circuit (701), Sum generation circuit (702) and Equipped with, The aforementioned selective carry output generation circuit (701) is, The generated carry input (Equation 3) from the preceding adder passes through the first NMOS transistor (701a) and generates the first non-inverting output, including a selective carry input (Equation 4), The first output passes through the first NOT gate (701b) to generate a second inverted output. The second output is the propagation input (P ｉ ) passes through the second NMOS transistor (701c) to generate the third output, The third output passes through the second NOT gate (701d) and provides a selected carry output (Equation 1), The sum generation circuit receives a propagated signal input (P) which is input to the NMOS and PMOS pass transistors. ｉ It has three inputs, including a first non-inverting output and a second inverting output, and the sum (S ｉ ) generates A selective carry propagation full adder circuit (700) characterized by the following: [Math 3] [Math 4] [Math 1]

6. A method for 3-bit addition using a select-carry-lookahead full adder circuit (900), First carry input (C ０ ) and first propagation (P ０ The process (901) involves performing a first NAND operation on first and second input terminals adapted to receive ) and generating a first output as an inverted selected carry input signal (Equation 5), The process (902) involves performing a first AND operation on first and second input terminals adapted to receive the first output inverting select carry input (Equation 5) and the first inverting generating carry (Equation 6), and generating an output that provides a first input signal to the first OR operation. The process (903) involves performing a first OR operation on first and second input terminals adapted to receive the output from the first AND operation and the inverted second propagation (Equation 7), thereby generating a second output as an inverted selected carry input signal (Equation 8), Step (904) of performing a second AND operation on first, second, and third input terminals adapted to receive the first output inverted selective carry input (Equation 5), the inverted first generated carry (Equation 6), and the inverted second generated carry (Equation 9), and generating an output that provides a first input signal to the second OR operation, The process (905) involves performing a third AND operation on the first and second input terminals adapted to receive the inverted second propagation (Equation 7) and the inverted second generated carry (Equation 9), and generating an output that provides a second input signal to the second OR operation. The process (906) involves performing a second OR operation on the first, second, and third input terminals adapted to receive the output from the second AND operation, the output from the third AND operation, and an inverted third propagation (Equation 10), thereby generating a third output as an inverted selected carry input signal (Equation 11), A step (907) of performing a fourth AND operation on first, second, third, and fourth input terminals adapted to receive the output (Equation 5) from the first NAND operation, the inverted first generated carry (Equation 6), the inverted second generated carry (Equation 9), and the inverted third generated carry (Equation 12) from the first NAND operation, and generating an output that provides a first input signal to the third OR operation, Step (908) of performing a fifth AND operation on first, second, and third input terminals adapted to receive the inverted second propagation (Equation 7), the inverted second generated carry (Equation 9), and the inverted third generated carry (Equation 12), and generating an output that provides a second input signal to the third OR operation, A step (909) of performing a sixth AND operation on first and second input terminals adapted to receive the third inverted propagation (Equation 10) and the inverted third generated carry (Equation 12), and generating an output that provides a third input signal to the third OR operation, The process (910) involves performing a third OR operation on the first, second, third, and fourth input terminals adapted to receive the output of the fourth AND operation, the output of the fifth AND operation, the output of the sixth AND operation, and the fourth inverted propagation (Equation 13), thereby generating a fourth output as an inverted selected carry input signal (Equation 14), A second NAND operation is performed on the first and second input terminals, which are adapted to receive the output of the third OR operation and the fourth inverted generated carry signal (Equation 15), and the carry output signal (C ４ The process of generating (911) A method for providing this. [Math 5] [Math 6] [Number 7] [Number 8] [Number 9] [Number 10] [Math 11] [Math 12] [Number 13] [Number 14] [Number 15]

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