Enhanced Memory Training

Abstract

The data processing system includes a data processor having a memory controller and memory. The memory is coupled to the memory controller and is for reading and writing data synchronously with respect to a clock signal. The memory includes a sensor circuit that outputs measured values ​​in response to a control signal without using a clock signal.

Description

Technical Field

[0001] The present disclosure generally relates to data processing systems, and more particularly to data processing systems having memory chips that require parameters to be trained for operation.

Background Art

[0002] Modern dynamic random access memories such as double data rate (DDR) dynamic random access memories include large arrays of very small dynamic random access memory cells that store charge on very small capacitors. During a memory access, the rows of a DDR DRAM are first "activated" by reading the contents of the memory cells into a row buffer. Once the contents are transferred to the row buffer, they can be read and written very quickly, e.g., at speeds of several gigahertz (GHz). If access to another row is desired, the contents of the selected row are rewritten to the memory array with any new data that may have been changed.

Brief Description of the Drawings

[0003] [Figure 1] A block diagram of a data processing system according to some embodiments. [Figure 2] A block diagram of a memory for use in the data processing system of FIG. 1 according to some embodiments. [Figure 3] A flowchart useful for understanding the operation of the data processing system of FIG. 1 according to some embodiments. [Figure 4] A timing diagram showing a synchronous temperature readout sequence according to the prior art. [Figure 5] A timing diagram showing an asynchronous temperature readout sequence according to some embodiments. [Figure 6]This is a block diagram of a mode register file system that can be used as part of the mode register of the memory in Figure 1, according to several embodiments. [Modes for carrying out the invention]

[0004] In the following description, the use of the same reference numeral in different drawings indicates similar or identical items. Unless otherwise specified, the word “coupled” and its associated verb forms include both direct and indirect electrical connections by means known in the art, and unless otherwise specified, any mention of direct connection also means alternative embodiments using a preferred form of indirect electrical connection.

[0005] The data processing system includes a data processor having a memory controller and memory. The memory is coupled to the memory controller and is for reading and writing data synchronously with respect to a clock signal. The memory includes a sensor circuit that outputs measured values ​​in response to a control signal without using a clock signal.

[0006] The memory includes a control logic circuit, a memory array, an access circuit, and a sensor circuit. The control logic circuit has a first input for receiving a clock signal, a second input for receiving a command signal, and an output for providing a control signal according to a predetermined state of the second input. The access circuit accesses data in the memory array in response to a command received at the second input, synchronous with the clock signal. The sensor circuit outputs a measured value in response to the activation of the control signal. The control logic circuit (210) activates the control signal according to a predetermined state of the second input without using the clock signal.

[0007] The method involves determining whether the memory enters low-power mode. The memory is put into low-power mode, which involves stopping the supply of an external clock to the memory. A wake-up event is detected. Measurements are detected using a sensor circuit. A set of cold-boot parameters for operating the memory according to the measurements is adjusted to form the current parameters. The memory operates using the current parameters.

[0008] Figure 1 is a block diagram of a data processing system 100 in several embodiments. The data processing system 100 generally includes a data processor in the form of a graphics processing unit (GPU) 110, a host central processing unit (CPU) 120, double data rate (DDR) memory 130, and graphics DDR (GDDR) memory 140.

[0009] The GPU 110 is a discrete graphics processor with very high performance for optimized graphics processing, rendering, and display, but requires high memory bandwidth to perform these tasks. The GPU 110 generally includes a set of command processors 111, graphics single instruction multiple data (SIMD) cores 112, a set of caches 113, a memory controller 114, a DDR physical interface circuit (DDR PHY) 115, and a GDDR PHY 116. Although a GPU is shown in this embodiment, the GPU 110 could be any of various data processing elements, such as a machine learning parallel accelerator processor.

[0010] The command processor 111 is used to interpret high-level graphics instructions, such as those specified in the OpenGL programming language. The command processor 111 has bidirectional connections to the memory controller 114 for receiving high-level graphics instructions such as OpenGL instructions, bidirectional connections to the cache 113, and bidirectional connections to the graphics SIMD core 112. Upon receiving high-level instructions, the command processor uses the cache 113 as temporary storage to issue low-level instructions for rendering, geometric processing, shading, and rasterizing data such as frame data. In response to graphics instructions, the graphics SIMD core 112 executes the low-level instructions on large datasets in a highly parallel manner. The command processor 111 and the cache 113 are used for temporary storage of input data and output (e.g., rendered and rasterized) data. The cache 113 also has bidirectional connections to the graphics SIMD core 112 and bidirectional connections to the memory controller 114.

[0011] The memory controller 114 has a first upstream bidirectional port connected to the command processor 111, a second upstream bidirectional port connected to the cache 113, a first downstream bidirectional port to the DDR PHY 115, and a second downstream bidirectional port to the GDDR PHY 116. As used herein, an "upstream" port is on the side of the circuit facing the data processor and away from memory, and a "downstream" port is in the direction away from the data processor and towards memory. The memory controller 114 controls the timing and ordering of data transfers between the DDR memory 130 and the GDDR memory 140. The DDR and GDDR memories have asymmetric access, meaning that access to open pages in memory is faster than access to closed pages. The memory controller 114 stores memory access commands and processes them in no particular order for efficiency, for example, by prioritizing access to open pages while adhering to specific quality of service objectives.

[0012] The DDR PHY 115 has an upstream bidirectional port connected to a first downstream port of the memory controller 114 and a downstream port bidirectionally connected to the DDR memory 130. The DDR PHY 115 satisfies all specified timing parameters of the version of the DDR memory 130, such as DDR version 5 (DDR5), and performs timing calibration operations as instructed by the memory controller 114. Similarly, the GDDR PHY 116 has an upstream port connected to a second downstream port of the memory controller 114 and a downstream port bidirectionally connected to the GDDR memory 140. The GDDR PHY 116 satisfies all specified timing parameters of the version of the GDDR memory 140 and performs timing calibration operations as instructed by the memory controller 114. The GDDR memory 140 includes a sensor circuit 141 that indicates the values ​​of parameters affecting the operation of the memory, which can be read by the memory controller 114.

[0013] During operation, the data processing system 100 can be used as a graphics card or accelerator for high-bandwidth graphics processing required for graphics applications. The host CPU 120, which runs the operating system or application program, sends graphics processing commands to the GPU 110 through the DDR memory 130, which acts as integrated memory for the GPU 110 and the host CPU 120. It can send commands to the GPU interface, for example, as OpenGL commands or through any other host CPU. OpenGL is a cross-language, cross-platform application programming interface for rendering 2D and 3D vector graphics. The host CPU 120 interacts with the GPU 110 using the application programming interface (API) to provide hardware-accelerated rendering.

[0014] The data processing system 100 uses two types of memory. The first type of memory is DDR memory 130, which is accessible by both the GPU 110 and the host CPU 120. As part of the high performance of the graphics SIMD core 112, the GPU 110 uses high-speed graphics double data rate (GDDR) memory.

[0015] Because the operation is extremely fast compared to the signal propagation time between the memory controller and the host processor, certain electrical parameters are "trained." For example, during a write cycle, the timing of the rise of the write clock signal relative to the data signal from the data processor must be trained so that the data signal arrives at the DRAM chip with appropriate setup and hold times relative to the write clock signal. In modern DDR DRAM, with numerous electrical parameters that must be trained, the training operation consumes a considerable amount of time.

[0016] To conserve power under various processing conditions, DRAM can be placed into various operating power states defined by different operating frequencies, resulting in reduced power consumption by the DRAM during periods of relatively low processing activity. However, the time required to retrain all the electrical parameters that must be changed for each new power state can be disruptive to system operation and may cause stalls that harm the user experience. Therefore, some systems train parameters for all possible power states when the system is started up before normal operation. However, as the system heats up due to the operation of the memory chip itself, the parameters change, making it difficult to provide accurate trained values ​​for all power states without lengthy retraining operations.

[0017] Figure 2 is a block diagram of a memory 200 for use in the data processing system 100 of Figure 1, according to several embodiments. The memory 200 in the integrated circuit DRAM generally includes a control logic circuit 210, an address register 220, a row address circuit 230, a bank control logic circuit 240, a row address latch and decoder block 250, a memory array 260, a column access circuit 270, a data input / output circuit 280, and a sensor circuit 290.

[0018] The control logic circuit 210 has inputs for receiving true and complementary clock signals labeled "CK_t" and "CK_c", respectively, a command and address input for receiving a set of command and address signals labeled "CA", and various outputs not shown in Figure 2. The control logic circuit 210 includes a command decoder 211 and a mode register block 212. The command decoder 211 has inputs for receiving the CA signal in synchronization with the CK_t and CK_c signals, and outputs for providing a set of control signals for executing the received command. The mode register block 212 includes a set of various mode registers having programmable values ​​that control the operation of memory 200, and outputs for providing various mode register settings to other circuits in the control logic circuit 210.

[0019] The address register 220 has a command and address input for receiving command and address signals, a clock input (not shown in Figure 2) for receiving CK_t and CK_c signals, and an output for providing latched addresses to various circuit blocks in memory 200.

[0020] The row address circuit 230 includes a refresh counter 231 and a row address multiplexer 232 labeled "MUX". The refresh counter 231 has an output for providing a refresh address and an output for providing a part of the refresh address. The row address multiplexer 232 has an input connected to the output of the refresh counter 231 and an output for the row address.

[0021] The bank control circuit 240 has a first input connected to the second output of the refresh counter 231, a second input connected to the control logic circuit 210, a third input connected to the output of the address register 220, and an output for providing a set of decoded bank selection signals.

[0022] The row address latch and decoder block 250 includes a set of row latches and decoders for each bank. Each row address latch and decoder has an input connected to the output of the row address multiplexer 232, a second input connected to the output of the bank control logic circuit 240, and an output for providing a set of decoded row selection signals.

[0023] The memory array 260 includes a set of memory banks. In the example of DDR5, the memory array 260 includes a set of 32 memory banks. However, in other embodiments, different types of memory and different numbers of memory banks may be used. Each memory bank has a memory array and a sense amplifier circuit. As shown in FIG. 2, an exemplary memory bank forming bank 0 includes a memory array 261 and a sense amplifier 262. The memory array 261 includes a set of rows intersecting a set of columns where memory cells are located at the intersections of rows and columns. Each row receives the corresponding row address from the set of row addresses, and when activated, the row outputs a set of data values to the sense amplifier 262 or, when precharged, receives a set of data values to be rewritten to the memory cells along the selected row.

[0024] The column access circuit 270 includes a column address counter / latch 271, a column decoder 272, and an input / output (I / O) gating circuit 273. The column address counter / latch 271 has an input connected to the output of the address register 220 to receive a column address, and an output for providing the current column address. The column decoder 272 includes a set of column decoders for each bank, and has an input connected to the output of the column address counter / latch 271, a control input for receiving the decoded bank selection signal, and an output for providing a set of column selection signals. The I / O gating circuit 273 has a set of gating circuits for each bank, each having an output for providing read data and an input for receiving write data.

[0025] The data input / output circuit 280 includes a data output register 281 and a data input register 282. The data output register 282 has a data input connected to the data output of the I / O gating circuit for each bank and an output connected to a set of data I / O terminals generally labeled "DQ". The data input register 281 has an input connected to the data I / O terminal and an output connected to the input of the I / O gating circuit for each bank.

[0026] Memory 200 can be, for example, DDR version 5 (DDR5) memory or an extension of graphics DDR version 6 (GDDR6) memory. DDR5 memory has 32 banks, as well as certain features common to conventional DDR memory and certain unique features. The command decoder 211 has been modified from known DDR and GDDR memory to decode a new command known as the "sleep end" signal. The decoder outputs a control signal, i.e., the sleep end signal, in response to receiving a specific combination of CA signals.

[0027] The sensor circuit 290 includes a sensor 291 and a self-timing sequencer circuit 292. The sensor 291 has an input for receiving a control signal and an output for providing a digital signal representing the detected value to the DQ signal line. The self-timing sequencer circuit 292 has an input connected to the output of the command decoder 211 for receiving a control signal and an output connected to the control input of the sensor 291. In the illustrated embodiment, the sensor circuit is a temperature sensor and is labeled "T" which outputs a multibit digital signal representing temperature. In this example, the sensor circuit may be implemented using a resistor whose resistance is proportional to temperature, a voltage amplifier which measures the voltage across the resistor, and an analog-to-digital converter which provides a digital signal having a value corresponding to the magnitude of the voltage. In other embodiments, the sensor 291 has a reference voltage "V REF The sensor 291 may be a voltage sensor that outputs a signal representing a voltage that affects the operation of memory 200, such as the power supply voltage. In yet another embodiment, the sensor 291 may be a frequency sensor that outputs a digital signal representing the frequencies of the CK_t and CK_c signals. In any of these examples, the parameters are parameters that change over time and may affect the training values.

[0028] The self-timing sequencer circuit 292 is a circuit that, in response to the activation of a control signal, causes a temperature sensor to measure the temperature and outputs it on the DQ signal.

[0029] By providing the sensor circuit 290 to asynchronously measure temperature, the temperature of the memory 200 can be measured while the memory is in a low-power self-refresh mode during a memory device power state change. When the power manager measures the temperature, it can adjust the values ​​of the cold boot parameters in accordance with the temperature change without performing full training (known as "warm boot" training). In this way, the power manager 151 can change the memory device power state while updating the training values ​​based on the current temperature with lower latency.

[0030] Figure 3 is a flowchart of a method 300 for operating the data processing system 100 of Figure 1, according to several embodiments. Method 300 begins with system startup 310.

[0031] In the action box 320, the system BIOS 150 controls the memory controller 114 and DDR PHY 115 to perform cold boot training. Cold boot training determines the “cold boot” (default) values ​​of several system parameters in each of the supported set of memory power states. A memory power state is defined by frequency and the corresponding voltage sufficient for the memory to operate safely at that frequency. Cold boot training determines the parameter values ​​for each supported memory device power state and therefore requires a relatively large amount of time. This is “cold” boot training in the sense that the data processing system 100, in particular the memory die, can operate near ambient temperature, i.e., before any significant integrated circuit or system heating occurs that could affect the parameter values. More generally, this is cold boot training in the sense that the data processing system 100 has not yet acquired any specific knowledge of the DRAM and therefore cold boot training can be performed at any valid operating temperature. The data processing system 100 may store approximate parameter values ​​in non-volatile memory as a starting point, but during cold boot training, it acquires additional knowledge of the actual parameter values ​​under the system conditions under which it is performed.

[0032] Cold boot training can be applied to any type of memory, including the extended features described below. In one example, the GDDR memory 140 in Figure 1 is implemented as an extended version of GDDR6 memory. In this example, the parameters to be trained include the delay from command / address to CK, the delay from write clock (WCK) to CK, the read training (read from DQ to WCK), the write training (write from DQS to DQ) delay, the data reference voltage offset (VREFD), and the command and address reference voltage offset (VREFC). In another example, the DDR memory 130 in Figure 1 is implemented as an extended version of low-power DDR4 (LPDDR4) memory. In this example, the parameters to be trained include the write leveling delay, the read delay from DQS to DQ, the write delay from DQS to DQ, and the data reference voltage (V REF (DQ)) Voltage, as well as command and address reference voltage (V REF (CA)) is included. In yet another example, the DDR memory 130 in Figure 1 is implemented with an extended version DDR version 5 (DDR5) memory. In this example, the parameters to be trained are read DQ preamble delay, command and address (CA) to CK delay, chip select (CS) to CK delay, write DQ to CK delay (write leveling delay), data reference voltage (VrefDQ) voltage, command and address V REF This includes (VrefDQ), chip-selection reference voltage (VrefCS), and DQ decision feedback equalizer (DFE) parameters. The techniques described herein will clearly apply to these examples and any similar memory.

[0033] In the action box 330, the trained values ​​are stored as a specific "context". According to some embodiments, the context is defined by a set of mode registers in memory and a set of training registers in the PHY, which are active only when the memory is in a context corresponding to a memory device power state. In the example shown in Figure 3, the first context, or "context 1", includes a set of mode registers in memory and a set of training registers in the PHY, which establish parameters for a specific memory device power state. Thus, after the BIOS performs cold boot training, the BIOS stores the trained values ​​in the mode registers for context 1 and causes the PHY to store the trained values ​​in the training registers for context 1.

[0034] The flow then proceeds to subflow 340, which includes action box 341 and decision box 342. In action box 341, the power manager instructs the memory controller and PHY to operate the memory in context 1. In decision box 342, the power manager decides whether to change the memory power state. If not, the flow returns to action box 341, and the power manager instructs the memory controller and PHY to operate the memory in context 1; if, it decides to change the state, the flow proceeds to subflow 350.

[0035] Subflow 350 includes an action box 351 and a decision box 352. In the action box 351, the power manager puts the memory into self-refresh mode. While the memory is in self-refresh mode, the power manager changes the clock frequency to a frequency defined for the desired memory power state. In the decision box 352, the power manager waits for a wake-up event, such as a determination that enough time has elapsed for the memory clock signal to stabilize at its new frequency. The power manager returns to the decision box 352 until this wake-up event occurs. When this occurs, the memory controller issues a sleep-end command to the DRAM.

[0036] After the wake-up event occurs, the flow proceeds to action box 360. In action box 360, the power manager causes memory to output a parameter, in this example, a temperature measurement. As shown in Figure 2, memory is enhanced to provide asynchronous on-die temperature measurement in response to sleep-end commands sent to memory by the power manager. In action box 360, the memory controller reads the temperature value and passes it to the power manager.

[0037] In the action box 370, the power manager adjusts the cold boot training parameters for the selected power state according to the measured temperature that would have risen above the ambient temperature due to the operation of the memory that heats the die. The parameters in context 2 can be adjusted to take the actual operating temperature into account. The power manager can easily make these adjustments in the firmware running on the CPU core.

[0038] In the action box 380, the power manager activates the currently stable memory clock and, before initiating normal memory read and write operations, executes a mode register set command to adjust the training value of the context 2 register and activate the context 2 parameter in the PHY. In some embodiments, the power manager stores the cold boot value of each memory device power state in system memory and uses the context 1 and context 2 registers to alternate between two or more memory device power states at the actual measured temperature. For example, context 1 may initially store the D0 or highest frequency memory device power state at cold boot, and then be adjusted during operation by adjusting the cold boot parameter stored in context 1 according to the difference between the actual temperature and the cold boot temperature. Since the power manager holds the cold boot temperature values ​​in system memory, these values ​​can be adjusted later if the temperature changes further.

[0039] In action box 390, the power manager issues a mode register set command to switch the context to context 2, and then issues a self-refresh termination command to allow the memory to resume normal read and write operations using temperature-controlled cold boot (default) parameters for the new device power state. At this point, the flow returns to action box 341.

[0040] Figure 4 is a timing diagram 400 showing a synchronous temperature readout sequence according to prior art. In timing diagram 400, the horizontal axis represents time in picoseconds (ps), and the vertical axis represents the amplitude of various signals in volts. Timing diagram 400 shows three target waveforms and different target times that satisfy different timing specifications.

[0041] Waveform 410 shows a differential memory clock signal having a true component labeled "CK_t" and a complementary component labeled "CK_c", collectively referred to as the CK signal. Timing diagram 400 shows the rising edge of CK_t, which includes times T0 and T1, interrupted by an indeterminate time period, followed by times Ta0 and Ta1, interrupted by another indeterminate time period, followed by times Tb0, Tb1, Tb2, and Tc0, interrupted by the six clock periods shown, followed by times Tc6 and Tc7, interrupted by yet another indeterminate time period, followed by time Td0. Waveform 420 shows command and address (CA) signal groups of various encoded commands superimposed on the waveform. Waveform 430 shows the data signal group DQ[7:0].

[0042] Timing diagram 400 shows exemplary signal timing for GDDR6 memory. In GDDR6 memory, each command is encoded using two parts of the CA signal over two consecutive CK half-cycles. At time T0, the memory receives the full bank precharge command "PREab" to put the memory into a bank idle state, followed by no-operation (NOP) on the CA pin. The next command is then filled at time T0. RP It cannot issue a row precharge delay labeled "". At time Ta0, the memory receives a full bank refresh command labeled "REFab". Only NOP commands are issued at time Tb0 when the memory returns to a bank idle state. KO It can be issued until a delay labeled " has elapsed. At time Tb0, the memory receives a mode register set command labeled "MRS" to mode register 3, where bits 7 and 6 are equal to "10" in binary. This command is a "DRAM information" command that initiates the temperature read operation. The temperature read is issued at Tc0 with "t WRIDONIt is valid after a time labeled "(max)" has occurred. At time Tc0, the memory outputs a binary temperature readout on the DQ[7:0] signal line. The binary temperature readout is valid until time Tc7. At time Tc7, the memory receives a mode register set command to mode register 3, where bits 7 and 6 are equal to "00" in binary, and resets the DRAM information command to "off". Then, at time Td0, the memory can receive an activation command (ACT) which puts the memory into a bank active state and subsequently enables the memory to receive read and write commands.

[0043] The GDDR6 temperature read command is a synchronous command that requires the presence of the CK signal. Training updates require the memory to be in self-refresh mode while the CK signal is unstable and during power state changes; therefore, the CK signal cannot be used to read the temperature synchronously.

[0044] Figure 5 is a timing diagram 500 showing an asynchronous temperature readout sequence according to several embodiments. In the timing diagram 500, the horizontal axis represents time in picoseconds (ps), and the vertical axis represents the amplitude of various signals in volts. The timing diagram 500 shows four target signal groups.

[0045] Waveform 510 shows a differential memory clock signal having a true component CK_t and a complementary component labeled CK_c, where CK_t and CK_c are collectively referred to as the CK signal. Waveform 520 shows a group of CA signals encoding various commands superimposed on the waveform. Waveform 530 shows the sleep termination command. Waveform 540 shows a group of DQ[7:0] signals.

[0046] As shown in timing diagram 500, the CK signal is removed, the CK_t signal is driven continuously low, and the CK_c signal is driven continuously high. The CA signal is ignored until the data processor 110 encodes the sleep end command. Upon receiving the sleep end command, the command decoder 211 outputs an active-high sleep end signal, shown as waveform 530. The rising edge of the sleep end signal causes the memory 200 to output a temperature signal, shown as a binary temperature readout in timing diagram 500. Although the operation is asynchronous, there are two timings that the memory controller PHY can use to capture the binary temperature readout. The first is a time period labeled "t1", which is the time from encoding the sleep end command to outputting the binary temperature readout. The second is a time period labeled "t2", which represents the amount of time the binary temperature readout remains on the DQ[7:0] pin. Thus, although asynchronous, the host memory controller and PHY use the t1 and t2 parameters to determine when to capture the binary temperature readout.

[0047] Figure 6 is a block diagram of a mode register file system 600 that can be used as part of the mode registers of the memory in Figure 1, according to several embodiments. The mode register file system 600 includes a set of non-training-related mode registers 610, a set of mode registers 620 associated with context 1, and a second mode register 630 associated with context 2.

[0048] The non-training-related mode registers 610 include mode registers independent of the context and memory device power state. The non-training-related mode registers include representative registers 611, 612, and 613. Register 613 includes a field 614 of one or more bits labeled "Context Selection," which is used by the power manager 151 to select the current context of memory. Mode registers 620 are associated with context 1 and include representative registers 621, 622, and 623. Mode registers 630 are associated with context 2 and include representative registers 631, 632, and 633.

[0049] For example, if field 614 has a binary value of "0", field 614 selects context 1 register to control the value of the trained parameter, and if field 614 has a binary value of "1", field 614 selects context 2 register to control the value of the trained parameter. In this way, the memory controller can program one set of registers based on a measurement, such as the current temperature, while the memory is still running with the other context. Context switching can then be achieved using a single-mode register set command instead of writing the registers one at a time, which increases the latency of changing the memory device power state.

[0050] In other embodiments, the context selection bit can be used to select from three or more contexts, but the usefulness of more than two contexts is significantly reduced. Furthermore, various parameters can be associated with specific contexts, which differ between different memory types.

[0051] While specific embodiments have been described, various modifications to these embodiments will be apparent to those skilled in the art. For example, while temperature was used as a parameter, other parameters such as power supply voltage and the actual frequencies of the command and address oscillators can be used to adjust the training parameters. As described above, this technology can be used to enhance existing GDDR, DDR, LPDDR memory, and other types of memory such as high-bandwidth memory (HBM), as well as other existing and future memory types. The actual training parameters affected by the measurements will vary based on the memory type. Furthermore, the number of contexts that can be defined to adjust the default parameters to the current parameters may vary in other embodiments. The signals used by the memory device to asynchronously output the measurements may also vary in other embodiments.

[0052] Therefore, the attached claims are intended to cover all modifications of the disclosed embodiments that fall within the scope of the disclosed embodiments.

Claims

1. A data processing system, A data processor having a memory controller, The memory controller is coupled to a memory for reading and writing data in synchronization with a clock signal, The memory includes a sensor circuit that outputs a measured value in accordance with a control signal without using the clock signal. Data processing system.

2. The aforementioned sensor circuit is Sensors and, The system includes a self-timing sequencer circuit that acquires the measured value from the sensor and activates the sensor in accordance with the control signal in order to output the measured value to at least one external terminal of the memory, The data processing system according to claim 1.

3. The sensor includes a temperature sensor, and the measured value is the temperature of the memory. The data processing system of claim 2.

4. The sensor includes a voltage sensor, and the measured value is the power supply voltage of the memory. The data processing system of claim 2.

5. The sensor includes a clock sensor, and the measured value is a characteristic of the clock signal. The data processing system of claim 2.

6. The memory's at least one external terminal includes a plurality of data input / output terminals. The data processing system of claim 2.

7. The data processor puts the memory into a low-power state in response to a change in the operating point of the memory. The data processor, in response to initiating the termination of the low-power state, The control signal, which is the sleep termination signal, is activated. Read the measured value, Adjust at least one parameter value according to the measured value to generate at least one adjusted parameter value. The at least one adjusted parameter value is programmed into one or more mode registers of the memory, The memory is returned from the low-power state to the normal operating state. The data processing system according to claim 1.

8. The data processor adjusts at least one parameter value according to the measurement value, based on the difference between the measurement value and the previous measurement value. The data processing system according to claim 1.

9. It is memory, A control logic circuit having a first input for receiving a clock signal, a second input for receiving a command signal, and an output for providing a control signal according to a predetermined state of the second input, Memory array and, An access circuit that accesses data in the memory array in response to a command received at the second input in synchronization with the clock signal, The system includes a sensor circuit that outputs a measured value in response to the activation of the aforementioned control signal, The control logic circuit activates the control signal according to the predetermined state of the second input without using the clock signal. Memory.

10. The aforementioned sensor circuit is Sensors and, The system includes a self-timing sequencer circuit that acquires the measured value from the sensor and activates the sensor in accordance with the control signal in order to output the measured value to at least one external terminal of the memory, The memory according to claim 9.

11. The sensor includes a temperature sensor, and the measured value is the temperature of the memory. The memory according to claim 10.

12. The sensor includes a voltage sensor, and the measured value is the power supply voltage of the memory. The memory according to claim 10.

13. The sensor includes a clock sensor, and the measured value is a characteristic of the clock signal. The memory according to claim 10.

14. The memory's at least one external terminal includes a plurality of data input / output terminals. The memory according to claim 10.

15. The control logic circuit puts the memory into a low-power state in response to a low-power state entry command. The control logic circuit continues to respond to the predetermined state of the second input without using the clock signal while the memory is in the low-power state, and provides the control signal which is the sleep termination signal. The control logic circuit terminates the memory from the low-power state in response to the low-power state termination command. The memory according to claim 9.

16. A first set of mode registers that store multiple training values ​​with the first parameter value, A second set of mode registers corresponding to the first set of mode registers, The memory comprises a register having a field for storing at least one bit indicating which of the first set of mode registers or the second set of mode registers the memory uses in its operation. The memory according to claim 9.

17. It is a method, The process involves determining whether the memory will switch to low-power mode, The memory is put into the low-power mode, which includes stopping the supply of an external clock to the memory. Detecting wake-up events and Detecting measured values ​​using a sensor circuit, Adjusting the set of cold boot parameters for operating the memory according to the measured values ​​to form the current parameters, This includes operating the memory using the current parameters, method.

18. The set of cold boot parameters is determined in accordance with the system startup, This includes, before determining whether the memory transitions to the low-power mode, initializing the memory using the cold boot parameters, The method according to claim 17.

19. The aforementioned adjustments are, The difference between the measured value and the cold boot measured value corresponding to the cold boot parameter is determined. This includes adjusting the cold boot parameters based on the difference between the measured value and the cold boot measured value. The method of claim 18.

20. The cold boot parameters are stored in a first set of mode registers that form a first context. This includes storing the current parameters in a second set of mode registers that correspond to a first set of mode registers and form a second context, The aforementioned operation is, Selecting the second context, This includes operating the memory using the current parameters, The method according to claim 19.

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