Memory device and method for forming a memory device

Abstract

This book describes memory devices and methods for manufacturing memory devices. A memory device includes a bit-wire metal stack on a surface that includes a matrix of conductive bit-wire contacts (e.g., polysilicon) and insulating dielectric islands (e.g., silicon nitride (SiN)). The bit-wire metal stack includes one or more of titanium (Ti), tungsten (W), tungsten nitride (WN), tungsten silicide (WSi2), or tungsten silicon nitride (WSiN). A memory device includes a bit-wire metal layer (e.g., tungsten (W)) on the upper surface of the insulating dielectric islands and on the bit-wire metal stack.

Description

Technical Field

[0001]

[0001] Embodiments of the present disclosure relate to the field of electronic devices, as well as methods and apparatuses for manufacturing electronic devices. More specifically, embodiments of the present disclosure provide a memory device and a method for forming a memory device with reduced thickness of a bit line metal stack and bit line capacitance.

Background Art

[0002]

[0002] Electronic devices (e.g., personal computers, workstations, computer servers, mainframes, and other computer-related devices such as printers, scanners, and hard disk drives) use memory devices that provide sufficient data storage capacity while resulting in low power consumption. Random access memory cells have two main types, dynamic and static, which are well suited for use in electronic devices. Dynamic random access memory (DRAM) is programmable to store a voltage representing one of two binary values, but requires periodic reprogramming, i.e., "refresh," to maintain this voltage for more than a very short period of time. Static random access memory (SRAM) is so named because it does not require periodic refresh.

[0003]

[0003] A DRAM memory circuit is manufactured on a single semiconductor wafer by replicating millions of identical circuit elements known as DRAM cells. Each DRAM cell is an addressable location capable of storing 1 bit (binary digit) of data. In its most common form, a DRAM cell consists of two circuit elements, a field effect transistor (FET) and a capacitor.

[0004]

[0004] The manufacture of DRAM cells includes the manufacture of transistors, capacitors, and connections to the bit lines and word lines. DRAM manufacturing is a highly competitive business. There is constant pressure to reduce the size of individual cells and increase the density of memory cells in order to pack more memory onto a single memory chip, especially at densities above 256 megabits. Constraints on reducing cell size include the fact that both active and passive word lines pass through the cell, the size of the cell capacitor, and the compatibility between array elements and non-array elements.

[0005]

[0005] Bit line capacitance is an important parameter for DRAM cells, and low bit line capacitance is desirable. The bit line metal stack consists of metal and a barrier metal stack. The thickness of the barrier metal stack accounts for 20% to 30% of the thickness of the bit line metal stack, and the overall thickness of the bit line metal stack determines the bit line capacitance. Typically, a thin bit line metal stack provides low bit line capacitance. However, reducing the thickness of the metal usually increases the line resistance, especially when the bit line limit dimension (CD) is aggressively reduced.

[0006]

[0006] Therefore, in the art there is a need for memory devices and methods for forming memory devices that reduce the thickness of the bit line metal stack and the bit line capacitance without increasing the line resistance. [Overview of the Initiative]

[0007]

[0007] One or more embodiments of the present disclosure relate to a method for forming a memory device. The method includes depositing a bit wire metal stack on a surface including a matrix of conductive bit wire contacts and insulating dielectric islands, etching a portion of the bit wire metal stack to expose the upper surface of the insulating dielectric islands, and depositing a bit wire metal layer on the exposed upper surface of the insulating dielectric islands and on the bit wire metal stack to form a plurality of bit wires.

[0008]

[0008] Further embodiments of the present disclosure relate to a method for forming a memory device. The method includes selectively depositing a bit-wire metal stack onto a surface including a matrix of conductive bit-wire contacts and an insulating dielectric island. The bit-wire metal stack is selectively deposited on the conductive bit-wire contacts relative to the insulating dielectric island. The method further includes depositing bit-wire metal layers on the upper surface of the insulating dielectric island and on the bit-wire metal stack to form a plurality of bit wires.

[0009]

[0009] Additional embodiments of the present disclosure relate to memory devices. In one or more embodiments, the memory device includes a bit wire metal stack on a surface including a matrix of conductive bit wire contacts and insulating dielectric islands. In some embodiments, the bit wire metal stack comprises one or more of titanium (Ti), tungsten (W), tungsten nitride (WN), tungsten silicide (WSi2), or tungsten silicon nitride (WSiN), and has a thickness in the range of about 50 Å to about 100 Å. The memory device further includes a bit wire metal layer on the upper surface of the insulating dielectric islands and on the bit wire metal stack. In some embodiments, the bit wire metal layer comprises tungsten (W) and has a thickness in the range of about 150 Å to about 250 Å.

[0010]

[0010] To enable a detailed understanding of the above-described features of this disclosure, a more specific description of this disclosure, which has been briefly summarized above, can be obtained by referring to embodiments. Some of these embodiments are illustrated in the accompanying drawings. However, it should be noted that since this disclosure may also permit other equally valid embodiments, the accompanying drawings illustrate only typical embodiments of this disclosure and should therefore not be considered to limit the scope of this disclosure. Embodiments described herein are illustrated as examples and are not limited to those in the accompanying drawings, and similar reference numerals in the drawings indicate similar elements. [Brief explanation of the drawing]

[0011] [Figure 1A]

[0011] A process flow diagram of a method for forming a memory device according to one or more embodiments is shown. [Figure 1B]

[0012] A process flow diagram of a method for forming a memory device according to one or more embodiments is shown. [Figure 2A]

[0013] A top view of a memory device according to one or more embodiments is shown. [Figure 2B]

[0014] Figure 2A shows a cross-sectional view of the memory device along line A-A'. [Figure 3A]

[0015] A top view of a memory device according to one or more embodiments is shown. [Figure 3B]

[0016] Figure 3A shows a cross-sectional view of the memory device along line A-A'. [Figure 4A]

[0017] A top view of a memory device according to one or more embodiments is shown. [Figure 4B]

[0018] Figure 4A shows a cross-sectional view of the memory device along line A-A'. [Figure 5A]

[0019] A top view of a memory device according to one or more embodiments is shown. [Figure 5B]

[0020] Figure 5A shows a cross-sectional view of the memory device along line A-A'. [Figure 6A]

[0021] A top view of a memory device according to one or more embodiments is shown. [Figure 6B]

[0022] Figure 6A shows a cross-sectional view of the memory device along line A-A'. [Figure 6C]

[0023] Figure 6A shows a cross-sectional view of the memory device along line B-B'. [Figure 6D]

[0024] Figure 6A shows a cross-sectional view of the memory device along the line C-C'. [Figure 7A]

[0025] Figure showing a top view of a memory device according to one or more embodiments. [Figure 7B]

[0026] Figure showing a cross-sectional view of the memory device of FIG. 7A along line A-A'. [Figure 8A]

[0027] Figure showing a top view of a memory device according to one or more embodiments. [Figure 8B]

[0028] Figure showing a cross-sectional view of the memory device of FIG. 8A along line A-A'. [Figure 9A]

[0029] Figure showing a top view of a memory device according to one or more embodiments. [Figure 9B]

[0030] Figure showing a cross-sectional view of the memory device of FIG. 9A along line A-A'. [Figure 10A]

[0031] Figure showing a top view of a memory device according to one or more embodiments. [Figure 10B]

[0032] Figure showing a cross-sectional view of the memory device of FIG. 10A along line A-A'. [Figure 10C]

[0033] Figure showing a cross-sectional view of the memory device of FIG. 10A along line B-B'. [Figure 10D]

[0034] Figure showing a cross-sectional view of the memory device of FIG. 10A along line C-C. [Figure 11] Figure showing a cluster tool according to one or more embodiments.

Embodiments for Carrying Out the Invention

[0012]

[0036] Before describing some exemplary embodiments of the present disclosure, it should be understood that the present disclosure is not limited to the details of the configurations or process steps presented in the following description. The present disclosure is capable of other embodiments and can be practiced or carried out in various ways.

[0013]

[0037] As used in this document and the attached claims, terms such as “precursor,” “reactant,” and “reactive gas” are interchangeable and refer to any gas species that can react with the substrate surface.

[0014]

[0038] As used herein, “atomic layer deposition” or “periodic deposition” refers to the sequential exposure of two or more reactive compounds to a substrate surface in order to deposit a layer of material. Terms such as “reactive compound,” “reactive gas,” “reactive species,” “precursor,” and “process gas” as used herein and in the attached claims are interchangeable and refer to substances having species capable of reacting with the substrate surface or the material on the substrate surface in surface reactions (e.g., chemiadsorption, oxidation, reduction). The substrate or a portion of the substrate is exposed to the precursor (or reactive gas) sequentially or substantially sequentially. As used throughout this specification, “substantially sequentially” means that, with some overlap, the majority of the precursor exposure period does not overlap with exposure to the co-reagent.

[0015]

[0039] The term "over" as used in this book does not suggest the physical orientation of one surface over the other, but rather the relationship between the thermodynamic or mechanical properties of the chemical reaction of one surface and the other. For example, selectively depositing a bit wire metal stack on a conductive bit wire contact on an insulating dielectric island means that the bit wire metal stack is deposited on the conductive bit wire contact, and little to no bit wire metal stack is deposited on the insulating dielectric island. Alternatively, forming a bit wire metal stack on a conductive bit wire contact means that it is thermodynamically or kinetically advantageous compared to forming a bit wire metal stack on an insulating dielectric island.

[0016]

[0040] The term "relative" can also be used to describe the relationship between the thermodynamic or dynamic properties of the chemical reaction of one surface to that of another. In this respect, the terms "over" and "relative" are interchangeable unless otherwise indicated in the context. For example, selectively depositing a bit wire metal stack on a conductive bit wire contact with respect to an insulating dielectric island means that the bit wire metal stack is deposited on the conductive bit wire contact, and little or no bit wire metal stack is deposited on the insulating dielectric island. Alternatively, forming a bit wire metal stack on a conductive bit wire contact means that it is thermodynamically or kinetically advantageous compared to forming a bit wire metal stack on an insulating dielectric island.

[0017]

[0041] In the following description, numerous details, such as specific materials, chemical properties, and element dimensions, are provided to enable a detailed understanding of one or more embodiments of the present invention. However, it will be apparent to those skilled in the art that these one or more embodiments of the present invention can be practiced without these specific details. In other examples, semiconductor manufacturing processes, techniques, materials, equipment, etc., are not described in excessive detail to avoid unnecessarily ambiguity. Those skilled in the art will be able to implement appropriate functionality without conducting unnecessary experiments by using the descriptions contained herein.

[0018]

[0042] While certain exemplary embodiments of this disclosure are described and shown in the accompanying drawings, such embodiments are merely illustrative and not limiting to this disclosure. Those skilled in the art can imagine variations, so it should be understood that this disclosure is not limited to the specific structures and arrangements shown and described.

[0019]

[0043] In one or more embodiments, metal deposition and other processes may be carried out in an isolated environment (e.g., a cluster process tool). Accordingly, some embodiments of this disclosure provide an integrated tool system comprising relevant process modules for implementing the methods described herein.

[0020]

[0044] Embodiments of the present disclosure advantageously provide a memory device, as well as a method for forming a memory device that reduces the thickness of the bit wire metal stack and the bit wire capacitance without increasing the line resistance.

[0021]

[0045] As described herein, a bit-line metal stack includes a metal and a barrier metal stack. Embodiments of this disclosure involve removing a portion of the bit-line metal stack (e.g., a barrier metal stack) from an insulating dielectric island beneath the bit-line metal layer, thereby reducing the thickness of the bit-line metal stack on the insulating dielectric island. The portion of the bit-line metal stack on the insulating dielectric island is called a "through bit line." The total length of the "through bit line" is approximately half the length of the bit line. The through bit line does not form conductive bit line contacts because it has no conductive path for accessing the transistor. The metal has low resistance and can be deposited directly on the insulating dielectric island to grow its grain size. Therefore, a barrier metal stack is not considered necessary on top of the insulating dielectric island. Consequently, since the overall thickness of the bit-line metal stack defines the bit-line capacitance, in the memory devices described herein (e.g., memory devices 100, 200), the thickness of the bit-line metal stack and the bit-line capacitance are reduced without reducing the thickness of the metal, and as a result, the line resistance does not increase.

[0022]

[0046] Embodiments of this disclosure advantageously provide a method for adjusting bit-line capacitance and resistance. Advantageously, by providing the bit-line metal stack described herein, reduced bit-line capacitance is obtained while the thickness of the bit-line metal remains the same and the bit-line resistance does not increase significantly.

[0023]

[0047] Figure 1A shows a process flow diagram of method 10 for forming a memory device. Figure 1B shows a process flow diagram of method 50 for forming a memory device. Those skilled in the art will recognize that the methods described herein may include any or all of the illustrated processes.

[0024]

[0048] Referring to Figure 1A, Method 10 includes depositing a bit wire metal stack on a surface including a matrix of conductive bit wire contacts and insulating dielectric islands (Step 12), etching a portion of the bit wire metal stack to expose the upper surface of the insulating dielectric island (Step 14), depositing a bit wire metal layer on the exposed upper surface of the insulating dielectric island and on the bit wire metal stack to form a plurality of bit wires (Step 16), optionally depositing a hard mask on the bit wire metal layer (Step 18), and optionally etching a portion of the bit wire metal layer (Step 20).

[0025]

[0049] Manufacturing a DRAM cell (e.g., memory device 100) involves manufacturing transistors, capacitors, and connections to bit lines and word lines. In Figures 2A to 6D, the memory device 100 includes a source, a drain, and an active region 115 that forms the channel of the DRAM cell. The array transistor is a switch that connects the storage node capacitor to the bit line. The word line (WL) 135 is the gate of the array transistor. In some embodiments, the WL 135 includes a first conductive material and a second conductive material on the first conductive material. In some embodiments, and without intending to be bound by theory, the WL (e.g., WL 135) including the first conductive material and the second conductive material on the first conductive material is a double work function word line that reduces the leakage current of the access transistor.

[0026]

[0050] A shallow trench isolation (STI) 110 isolates one active array transistor from an adjacent active array transistor. The STI 110 prevents adjacent active array transistors from short-circuiting each other. Conductive bit-line contacts 130 are the source / drain of the array transistors connected to the bit lines. The active region 115 beneath the insulating dielectric island 120 is the source / drain of the array transistors connected to the storage node capacitor. The conductive bit-line contacts 130 are formed between the insulating dielectric islands 120. In detail, embodiments of the present disclosure provide a memory device and a method for forming a memory device with reduced bit-line metal stack thickness and bit-line capacitance.

[0027]

[0051] Figures 2A to 6D show a portion of the memory device 100 according to the process flow diagram shown for method 10 in Figure 1A. Figures 2A and 2B show an initial or first memory device 100 according to one or more embodiments of the present disclosure. Figure 2A shows a top view of the memory device 100. Figure 2B shows a cross-sectional view of the memory device 100 of Figure 2A along line A-A'.

[0028]

[0052] Figure 2B shows a memory device 100 that includes a plurality of word lines (WLs) 135 comprising a first conductive material 135A and a second conductive material 135B on the first conductive material 135A. In some embodiments, and without intending to be bound by theory, the WLs 135 comprising the first conductive material 135A and the second conductive material 135B on the first conductive material 135A are double work function word lines that reduce the leakage current of the access transistor. In some embodiments, the first conductive material 135A comprises tungsten (W). In some embodiments, the second conductive material 135B comprises polysilicon. The memory device 100 includes a plurality of shallow trench isolations (STIs) 110, each STI 110 isolating one active array transistor from an adjacent active array transistor. The STIs 110 prevent adjacent active array transistors from short-circuiting each other. Each of the STIs 110 is isolated by a gate oxide material 112. The gate oxide material 112 can be any suitable gate oxide material known to those skilled in the art. The WL 135 is isolated from the STI 110 by the gate oxide material 112. In some embodiments, the gate oxide material isolates each active region 115. Conductive bit line contacts 130 are the source / drain of the array transistor connected to the bit line. Multiple insulating dielectric islands 120 are formed on the upper surface of the gate oxide material 112, isolating each of the STI 110. The active regions 115 below the insulating dielectric islands 120 are the source / drain of the array transistor connected to the storage node capacitor. Conductive bit line contacts 130 are formed between the insulating dielectric islands 120 above the active regions 115. The insulating dielectric islands 120 have an upper surface 122. Conductive bit line contacts 130 have an upper surface 132.

[0029]

[0053] STI110 may include any suitable insulating dielectric material. In some embodiments, STI110 includes one or more silicon oxide (SiOx) or silicon nitride (SiN).

[0030]

[0054] The active region 115 may include any suitable semiconductor material. In some embodiments, the active region 115 includes one or more of crystalline silicon, single-crystal silicon, polycrystalline silicon, germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), or indium gallium zinc oxide (IGZO).

[0031]

[0055] The insulating dielectric island 120 may contain any suitable dielectric material. In some embodiments, the insulating dielectric island 120 contains one or more of silicon oxide (SiOx), silicon nitride (SiN), aluminum oxide (AlOx), hafnium oxide (HfOx), polysilocarb (SiOC), and silicon carbonitride (SiCN). In some embodiments, the insulating dielectric island 120 contains silicon nitride (SiN).

[0032]

[0056] The conductive bit wire contact 130 may include any suitable conductive material. In some embodiments, the conductive bit wire contact 130 includes one or more of the following: polysilicon, conductive doped polycrystalline silicon germanium, conductive doped polycrystalline germanium, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), cobalt (Co), or ruthenium (Ru), or alloys thereof. In some embodiments, the conductive bit wire contact 130 includes polysilicon.

[0033]

[0057] In one or more embodiments not shown, Method 10 includes recessing a portion of the conductive bit wire contact 130 such that the height of the conductive bit wire contact 130 is lower than the height of the insulating dielectric island 120 before the bit wire metal stack 140 is deposited in step 12. In one or more embodiments not shown, Method 10 includes recessing the upper surface 132 of the conductive bit wire contact 130 such that the height of the conductive bit wire contact 130 is lower than the height of the insulating dielectric island 120 before the bit wire metal stack 140 is deposited in step 12. In some embodiments, the conductive bit wire contact 130 has a height lower than the height of the insulating dielectric island 120 before the bit wire metal stack 140 is deposited in step 12, so that recessing is not necessary.

[0034]

[0058] Figures 3A and 3B illustrate step 12 of method 10 (depositing a bit wire metal stack 140 onto a surface containing a matrix of conductive bit wire contacts 130 and insulating dielectric islands 120). Figure 3A shows a top view of the memory device 100, and Figure 3B shows a cross-sectional view of the memory device 100 of Figure 3A along line A-A'.

[0035]

[0059] In some embodiments, depositing the bit wire metal stack 140 in step 12 of method 10 includes a vapor deposition method. In some embodiments, the vapor deposition method includes a physical vapor deposition (PVD) process or a variation thereof. In one or more embodiments, the bit wire metal stack 140 is deposited by physical vapor deposition (PVD).

[0036]

[0060] In one or more embodiments, the bit wire metal stack 140 includes a metal and a barrier metal stack. In one or more embodiments, the bit wire metal stack 140 includes one or more of titanium (Ti), tungsten (W), tungsten nitride (WN), tungsten silicide (WSi2), or tungsten silicon nitride (WSiN). In some embodiments, the bit wire metal stack 140 includes a barrier metal stack containing one or more of titanium (Ti), tungsten nitride (WN), tungsten silicide (WSi2), or tungsten silicon nitride (WSiN).

[0037]

[0061] In one or more embodiments, the bit wire metal stack 140 has a first thickness before etching, ranging from about 50 Å to about 100 Å. In one or more embodiments, the first thickness of the bit wire metal stack 140 is measured in the Z direction from the upper surface 132 of the conductive bit wire contact 130 to the upper surface 142 of the bit wire metal stack 140.

[0038]

[0062] In one or more embodiments, the bit wire metal stack 140 has a second thickness before etching, ranging from about 50 Å to about 100 Å. In one or more embodiments, the second thickness of the bit wire metal stack 140 is measured in the Z direction from the top surface of the insulating dielectric island to the top surface 142 of the bit wire metal stack 140.

[0039]

[0063] Figures 4A and 4B illustrate step 14 of method 10 (etching a portion of the bit wire metal stack 140 to expose the upper surface 122 of the insulating dielectric island 120). In some embodiments, step 14 involves etching a portion of the bit wire metal stack 140 to expose the upper surface 122 of the insulating dielectric island 120, thereby forming the exposed insulating dielectric island 120. Figure 4A shows a top view of the memory device 100, and Figure 4B shows a cross-sectional view of the memory device 100 of Figure 4A along the line A-A'.

[0040]

[0064] In one or more embodiments, the first thickness of the bit wire metal stack 140 remains the same after etching. In one or more embodiments, the second thickness of the bit wire metal stack 140 decreases after etching. In some embodiments, the thickness of the bit wire metal stack 140 on the upper surface 122 of the insulating dielectric island 120 (e.g., the second thickness) is 10 Å or less, 5 Å or less, 2 Å or less, 1 Å or less, 0.5 Å or less, or 0.1 Å or less. In some embodiments, the bit wire metal stack 140 is absent or negligible on the upper surface 122 of the insulating dielectric island. As used herein, the term “negligible” means that the bit wire metal stack 140 accounts for less than about 5% (including less than about 4%, less than about 3%, less than about 2%, less than about 1%, or less than about 0.5%) of the configuration of the upper surface 122 of the insulating dielectric island.

[0041]

[0065] The etching in step 14 may be any suitable etching or patterning process. In some embodiments, the etching in step 14 includes a planarization process (e.g., a chemical mechanical polishing (CMP) process or an etch-back process).

[0042]

[0066] Figures 5A and 5B show step 16 of method 10 (depositing a bit wire metal layer 150 on the upper surface 122 of the exposed insulating dielectric island 120 and on the bit wire metal stack 140 to form multiple bit wires). Figure 5A shows a top view of the memory device 100, and Figure 5B shows a cross-sectional view of the memory device 100 of Figure 5A along line A-A'.

[0043]

[0067] In some embodiments, the bit wire metal layer 150 contains one or more of tungsten (W), molybdenum (Mo), tantalum (Ta), ruthenium (Ru), niobium (Nb), osmium (Os), zirconium (Zr), iridium (Ir), or rhenium (Re). In some embodiments, the bit wire metal layer 150 contains tungsten (W).

[0044]

[0068] In some embodiments, the multiple bit lines and conductive bit line contacts 130 self-align. In some embodiments, the multiple bit lines and conductive bit line contacts 130 self-align as a result of a single dry etching process.

[0045]

[0069] Figures 6A to 6D show optional steps 18 and 20 of Method 10 (depositing a hard mask 160 on the bit wire metal layer 150 (step 18), and etching a portion of the bit wire metal layer 150 (step 20)). Figure 6A shows a top view of the memory device 100. Figure 6B shows a cross-sectional view of the memory device 100 of Figure 6A along line A-A'. Figure 6C shows a cross-sectional view of the memory device 100 of Figure 6A along line B-B'. Figure 6D shows a cross-sectional view of the memory device 100 of Figure 6A along line C-C'.

[0046]

[0070] The hard mask 160 prevents damage and deformation of the bit wire metal layer 150. In addition, the hard mask 160 can act as an etching mask in relation to conventional lithography techniques to prevent removal of the bit wire metal layer 150 during etching.

[0047]

[0071] The hard mask 160 may contain any suitable dielectric material. In some embodiments, the hard mask 160 contains one or more of silicon oxide (SiOx), silicon nitride (SiN), aluminum oxide (AlOx), hafnium oxide (HfOx), polysilocarb (SiOC), and silicon carbonitride (SiCN). In some embodiments, the hard mask 160 contains silicon nitride (SiN).

[0048]

[0072] The hard mask 160 can be deposited on the bit wire metal layer 150 by any suitable deposition process. In some embodiments, the hard mask 160 is deposited on the bit wire metal layer 150 by chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). In some embodiments, the hard mask 160 is deposited on the bit wire metal layer 150. The hard mask 160 can have any suitable thickness. In some embodiments, the hard mask 160 has a thickness in the range of about 800 Å to about 1200 Å.

[0049]

[0073] The etching in step 20 may include the same process as the etching in step 14. The etching in step 20 may be any suitable etching or patterning process. In some embodiments, the etching in step 20 includes a planarization process (e.g., a chemical mechanical polishing (CMP) process or an etch-back process).

[0050]

[0074] In some embodiments, the memory device 100 includes a bit wire metal stack 140 on a surface including a matrix of conductive bit wire contacts 130 and insulating dielectric islands 120. In some embodiments, the bit wire metal stack 140 includes one or more of titanium (Ti), tungsten (W), tungsten nitride (WN), tungsten silicide (WSi2), or tungsten silicon nitride (WSiN), and has a thickness in the range of about 50 Å to about 100 Å. The memory device 100 further includes a bit wire metal layer 150 on the upper surface 122 of the insulating dielectric islands 120 and on the bit wire metal stack 140. In some embodiments, the bit wire metal layer 150 includes tungsten (W) and has a thickness in the range of about 150 Å to about 250 Å. In some embodiments, the memory device 100 includes a hard mask 160 on the bit wire metal layer 150. In some embodiments, the hard mask 160 has a thickness in the range of about 800 Å to about 1200 Å.

[0051]

[0075] Referring to Figure 1B, Method 50 includes selectively depositing a bit wire metal stack on a surface including a matrix of conductive bit wire contacts and an insulating dielectric island, wherein the bit wire metal stack is selectively deposited on the conductive bit wire contacts relative to the insulating dielectric island (Step 52); depositing a bit wire metal layer on the upper surface of the insulating dielectric island and on the bit wire metal stack to form a plurality of bit wires (Step 54); optionally depositing a hard mask on the bit wire metal layer (Step 56); and optionally etching a portion of the bit wire metal layer (Step 58).

[0052]

[0076] Figures 7A to 10D show portions of the memory device 200 according to the process flow diagram shown for method 50 in Figure 1B. Figures 7A and 7B show the initial or first memory device 200 according to one or more embodiments of the present disclosure. Similar reference numerals used herein indicate similar elements. For example, the active area 115 of memory device 100 corresponds to the active area 215 of memory device 200 unless specifically indicated otherwise in the context.

[0053]

[0077] Figure 7B shows a cross-sectional view of the memory device 200 shown in Figure 7A along the line A-A'. The memory device 200 shown in Figure 7B has the same characteristics as the memory device 100 shown in Figure 2A.

[0054]

[0078] Figures 8A and 8B show step 52 of method 50 (selectively depositing a bit wire metal stack 240 on the conductive bit wire contact 230 onto the insulating dielectric island 220). Figure 8A shows a top view of the memory device 200, and Figure 8B shows a cross-sectional view of the memory device 200 of Figure 8A along line A-A'.

[0055]

[0079] In some embodiments, selectively depositing the bit wire metal stack 240 on the conductive bit wire contact 230 relative to the insulating dielectric island 220 in step 52 means that the bit wire metal stack 240 is deposited on the conductive bit wire contact 230, and little to no bit wire metal stack 240 is deposited on the insulating dielectric island 220. Alternatively, forming the bit wire metal stack 240 on the conductive bit wire contact 230 means that it is thermodynamically or kinetically advantageous compared to forming the bit wire metal stack 240 on the insulating dielectric island 220.

[0056]

[0080] In one or more embodiments, selective deposition of a bit wire metal stack 240 on a conductive bit wire contact 230 relative to an insulating dielectric island 220 is highly conformal. As used in this document, a “highly conformal” layer refers to a layer whose thickness is nearly uniform throughout (for example, on each upper surface 232 of the conductive bit wire contact 230). Highly conformal layers have thickness differences of approximately 5%, 2%, 1%, or less than 0.5%.

[0057]

[0081] Figures 9A and 9B show step 54 of method 50 (depositing a bit wire metal layer 250 on the upper surface 222 of the exposed insulating dielectric island 220 and on the bit wire metal stack 240 to form multiple bit wires). Figure 9A shows a top view of the memory device 200, and Figure 9B shows a cross-sectional view of the memory device 200 of Figure 9A along line A-A'. The bit wire metal layer 250 may have the same properties as the bit wire metal layer 150 and may be deposited by the same process as step 16 of method 10.

[0058]

[0082] Figures 10A to 10D show optional steps 56 and 58 of method 50 (depositing a hard mask 260 on the bit wire metal layer 250 (step 56), and etching a portion of the bit wire metal layer 250 (step 58)). Figure 10A shows a top view of the memory device 200. Figure 10B shows a cross-sectional view of the memory device 200 of Figure 10A along line A-A'. Figure 10C shows a cross-sectional view of the memory device 200 of Figure 10A along line B-B'. Figure 10D shows a cross-sectional view of the memory device 200 of Figure 10A along line C-C'.

[0059]

[0083] In some embodiments, the memory device 200 includes a bit wire metal stack 240 on a surface including a matrix of conductive bit wire contacts 230 and insulating dielectric islands 220. In some embodiments, the bit wire metal stack 240 includes one or more of titanium (Ti), tungsten (W), tungsten nitride (WN), tungsten silicide (WSi2), or tungsten silicon nitride (WSiN), and has a thickness in the range of about 50 Å to about 100 Å. The memory device 200 further includes a bit wire metal layer 250 on the upper surface 222 of the insulating dielectric islands 220 and on the bit wire metal stack 240. In some embodiments, the bit wire metal layer 250 includes tungsten (W) and has a thickness in the range of about 150 Å to about 250 Å. In some embodiments, the memory device 200 includes a hard mask 260 on the bit wire metal layer 250. In some embodiments, the hard mask 260 has a thickness in the range of about 800 Å to about 1200 Å.

[0060]

[0084] Additional embodiments of this disclosure, as shown in Figure 11, relate to a cluster tool 900 for forming the memory devices and methods described.

[0061]

[0085] The cluster tool 900 includes at least one central transfer station 921, 931 having multiple sides. Robots 925, 935 are positioned within the central transfer stations 921, 931 and are configured to move robot blades and wafers to each of the multiple sides.

[0062]

[0086] The cluster tool 900 comprises several processing chambers 902, 904, 906, 908, 910, 912, 914, 916, and 918, also called process stations, connected to a central transfer station. The various processing chambers provide separate processing areas isolated from adjacent process stations. The processing chambers may be, but are not limited to, any suitable chambers including pre-clean chambers, buffer chambers, transfer spaces, wafer orientation / degassing chambers, cryogenic cooling chambers, deposition chambers, annealing chambers, etching chambers, selective oxidation chambers, oxide layer thinning chambers, or word line deposition chambers. The specific arrangement of process chambers and components may vary depending on the cluster tool and should not be considered as limiting the scope of this disclosure.

[0063]

[0087] In the embodiment shown in Figure 11, the factory interface 950 is connected to the front of the cluster tool 900. The factory interface 950 includes a loading chamber 954 and an unloading chamber 956 on the front 951 of the factory interface 950. The loading chamber 954 is shown on the left and the unloading chamber 956 is shown on the right, but those skilled in the art will understand that this is merely representative of one possible configuration.

[0064]

[0088] The size and shape of the loading chamber 954 and the unloading chamber 956 may vary, for example, depending on the substrate being processed by the cluster tool 900. In the shown embodiment, the loading chamber 954 and the unloading chamber 956 are sized to hold a wafer cassette containing multiple wafers arranged in the cassette.

[0065]

[0089] Robot 952 is located within the factory interface 950 and can move between the loading chamber 954 and the unloading chamber 956. Robot 952 can transfer wafers from a cassette in the loading chamber 954 to the load lock chamber 960 via the factory interface 950. Robot 952 can also transfer wafers from the load lock chamber 962 to a cassette in the unloading chamber 956 via the factory interface 950. As will be understood by those skilled in the art, the factory interface 950 may have multiple robots 952. For example, the factory interface 950 may have a first robot that transfers wafers between the loading chamber 954 and the load lock chamber 960, and a second robot that transfers wafers between the load lock 962 and the unloading chamber 956.

[0066]

[0090] The cluster tool 900 shown has a first section 920 and a second section 930. The first section 920 is connected to the factory interface 950 via load lock chambers 960, 962. The first section 920 includes a first transfer chamber 921 with at least one robot 925 located therein. The robot 925 is also called a robotic wafer transport mechanism. The first transfer chamber 921 is centrally located relative to the load lock chambers 960, 962, process chambers 902, 904, 916, 918, and buffer chambers 922, 924. In some embodiments, the robot 925 is a multi-arm robot capable of independently moving multiple wafers at once. In some embodiments, the first transfer chamber 921 includes multiple robotic wafer transport mechanisms. The robot 925 within the first transfer chamber 921 is configured to move wafers between chambers around the first transfer chamber 921. Each wafer is transported on a wafer transport blade located at the distal end of the first robotic mechanism.

[0067]

[0091] After processing the wafer in the first section 920, the wafer can be moved to the second section 930 via a pass-through chamber. For example, chambers 922, 924 may be unidirectional or bidirectional pass-through chambers. Pass-through chambers 922, 924 can be used, for example, to cool the wafer to a low temperature before processing in the second section 930, or to allow cooling or post-processing of the wafer before returning it to the first section 920.

[0068]

[0092] The system controller 990 communicates with the first robot 925, the second robot 935, the first set of processing chambers 902, 904, 916, 918, and the second set of processing chambers 906, 908, 910, 912, 914. The system controller 990 can be any suitable component capable of controlling the processing chambers and robots. For example, the system controller 990 may be a computer including a central processing unit, memory, appropriate circuitry, and storage.

[0069]

[0093] The process may generally be stored as a software routine in the memory of the system controller 990, and when executed by the processor, it causes the process chamber to execute the process of the disclosure. The software routine may also be stored and / or executed by a second processor (not shown) located remotely from the hardware controlled by the processor. Some or all of the methods of the disclosure can also be performed in hardware. Thus, the process may be implemented in software and executed using a computer system in hardware (e.g., application-specific integrated circuits or other types of hardware implementations), or in a combination of software and hardware. When executed by the processor, the software routine transforms a general-purpose computer into a dedicated computer (controller) that controls the chamber operation so that the process can be executed.

[0070]

[0094] In one or more embodiments, the processing tool comprises: a central transfer station equipped with a robot configured to move wafers; a plurality of process stations, each process station connected to the central transfer station and providing a processing area separated from the processing areas of adjacent process stations, and including deposition chambers (e.g., physical vapor deposition (PVD) chambers and / or atomic layer deposition (ALD) chambers); and controllers connected to the central transfer station and the plurality of process stations, configured to activate the robot to move wafers between process stations and to control the processes occurring at each of the process stations.

[0071]

[0095] One or more embodiments provide a non-temporary computer-readable medium containing instructions, which, when executed by a controller of a processing chamber, cause the processing chamber to perform the steps of Method 10. Further embodiments provide a non-temporary computer-readable medium containing instructions, which, when executed by a controller of a processing chamber, cause the processing chamber to perform the steps of Method 50.

[0072]

[0096] In the context of describing the materials and methods discussed in this book (particularly in the context of the claims below), the use of “a” and “an,” “the,” and similar referents should be interpreted as encompassing both singular and plural, unless otherwise indicated in this book or unless the context clearly contradicts this interpretation. Enumerations of numerical ranges in this book are merely intended as abbreviations to refer individually to each specific value within that range, unless otherwise indicated in this book, and each specific value is incorporated in this book as if it were individually listed. All methods described in this book may be performed in any appropriate order, unless otherwise indicated in this book or unless the context clearly contradicts this interpretation. Any and all examples or exemplary language provided in this book (e.g., “such as”) are merely intended to better describe the materials and methods and do not limit their scope unless otherwise specified in the claims. Nothing in this document should be interpreted as indicating that any element not specified in the claims is essential for carrying out the disclosed materials and methods.

[0073]

[0097] Throughout this publication, any reference to “one embodiment,” “a particular embodiment,” “one or more embodiments,” or “embodiments” means that any particular feature, structure, material, or property described in relation to an embodiment is included in at least one embodiment of this disclosure. Therefore, any other instances of phrases such as “in one or more embodiments,” “a particular embodiment,” “in one embodiment,” or “in an embodiment” throughout this publication do not necessarily refer to the same embodiment of this disclosure. Furthermore, any particular feature, structure, material, or property may be combined in any suitable manner in one or more embodiments.

[0074]

[0098] While the disclosures in this book are described with reference to specific embodiments, it should be understood that these embodiments are merely illustrative of the principles and applications of the disclosure. Those skilled in the art will see that various modifications and variations can be made to the methods and apparatus of the disclosure without departing from the spirit and scope of the disclosure. Therefore, the disclosure is intended to include modifications and variations that fall within the scope of the appended claims and their equivalents.

Claims

1. A method for forming a memory device, Depositing a bit wire metal stack on a surface containing a matrix of conductive bit wire contacts and insulating dielectric islands, Etching a portion of the bit wire metal stack to expose the upper surface of the insulating dielectric island, and A plurality of bit wires are formed by depositing a bit wire metal layer on the upper surface of the exposed insulating dielectric island and on the bit wire metal stack. Methods that include...

2. The method according to claim 1, wherein the bit wire metal stack is deposited by physical vapor deposition (PVD).

3. The aforementioned bit wire metal stack is made of titanium (Ti), tungsten (W), tungsten nitride (WN), and tungsten silicide (WSi). ２ The method according to claim 1, comprising one or more of the following: ), or a tungsten silicon nitride film (WSinN).

4. The method according to claim 1, wherein the conductive bit wire contact includes polysilicon.

5. The method according to claim 1, wherein the insulating dielectric island comprises one or more oxides and nitrides.

6. The method according to claim 5, wherein the insulating dielectric island comprises silicon nitride (SiN).

7. The method according to claim 1, further comprising recessing a portion of the conductive bit wire contact such that the conductive bit wire contact has a height lower than the height of the insulating dielectric island prior to the deposition of the bit wire metal stack.

8. The method according to claim 1, wherein the bit wire metal layer comprises one or more of tungsten (W), molybdenum (Mo), tantalum (Ta), ruthenium (Ru), niobium (Nb), osmium (Os), zirconium (Zr), iridium (Ir), or rhenium (Re).

9. The method according to claim 8, further comprising etching a portion of the bit wire metal layer.

10. The method according to claim 1, wherein the plurality of bit lines and the conductive bit line contacts are self-aligning.

11. A method for forming a memory device, A method for selectively depositing bit wire metal stacks on a surface including a matrix of conductive bit wire contacts and insulating dielectric islands, wherein the bit wire metal stacks are selectively deposited on the conductive bit wire contacts relative to the insulating dielectric islands, and Multiple bit lines are formed by depositing a bit line metal layer on the upper surface of the insulating dielectric island and on the bit line metal stack. Methods that include...

12. The method according to claim 11, further comprising recessing a portion of the conductive bit wire contact such that the conductive bit wire contact has a height lower than the height of the insulating dielectric island prior to the selective deposition of the bit wire metal stack.

13. The aforementioned bit wire metal stack is made of titanium (Ti), tungsten (W), tungsten nitride (WN), and tungsten silicide (WSi). ２ The method according to claim 11, comprising one or more of the following: ), or a tungsten silicon nitride film (WSinN).

14. The method according to claim 11, wherein the conductive bit wire contact includes polysilicon.

15. The method according to claim 11, wherein the insulating dielectric island comprises silicon nitride (SiN).

16. The method according to claim 11, wherein the bit wire metal layer comprises one or more of tungsten (W), molybdenum (Mo), tantalum (Ta), ruthenium (Ru), niobium (Nb), osmium (Os), zirconium (Zr), iridium (Ir), or rhenium (Re).

17. The method according to claim 11, further comprising etching a portion of the bit wire metal layer.

18. A memory device, A bit wire metal stack on a surface comprising a matrix of conductive bit wire contacts and insulating dielectric islands, wherein the materials are titanium (Ti), tungsten (W), tungsten nitride (WN), and tungsten silicide (WSi). ２ A bit wire metal stack comprising one or more of the following: ), or a tungsten silicon nitride film (WSinN), having a thickness in the range of approximately 50 Å to approximately 100 Å, and The upper surface of the insulating dielectric island and the bit wire metal layer on the bit wire metal stack, comprising tungsten (W) and having a thickness in the range of about 150 Å to about 250 Å, A memory device that includes this.

19. The memory device according to claim 18, wherein the conductive bit wire contact includes polysilicon.

20. The memory device according to claim 18, wherein the insulating dielectric island contains silicon nitride (SiN).

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