Formation of Storage Node Contacts (SNCs) for Three-Dimensional Dynamic Random Access Memory (DRAM)

Abstract

The embodiments herein relate to three-dimensional (3D) dynamic random access memory (DRAM) and corresponding methods. In one embodiment, a multilayer semiconductor structure is provided, the multilayer semiconductor structure comprising a plurality of unit stacks formed on a substrate. Each unit stack has a semiconductor layer, a first dielectric layer, a first gate electrode, and a second dielectric layer of a capacitor portion. A lateral recess of the capacitor portion opens to a first opening through the unit stack. The method comprises conformally depositing a doped silicon layer on the lateral edge of a semiconductor layer within the lateral recess, and then performing a thermal annealing process after forming a doped silicon layer on a second lateral edge. The method further comprises forming a capacitor in which the lateral recess is located, the capacitor in contact with the doped silicon layer on the second lateral edge of the semiconductor layer.

Description

Technical Field

[0001]

[0001] The embodiments described herein generally relate to the field of semiconductor processing, and more specifically, to three-dimensional (3D) dynamic random access memory (DRAM), and methods of forming storage node contacts (SNC) junctions for 3D DRAM.

Background Art

[0002] Description of Related Art

[0002] Advances in technology in semiconductor processing have pushed integrated circuits to the physical limits of Moore's Law. These advances have brought about new paradigms for devices and structures in integrated circuits. For example, various three-dimensional (3D) designs have been developed for DRAM. However, such 3D devices can pose new challenges for processing and manufacturing.

Summary of the Invention

[0003]

[0003] Embodiments of the present disclosure include methods for semiconductor processing. A multilayer semiconductor structure is provided. The multilayer semiconductor structure includes a plurality of unit stacks formed on a substrate, each unit stack having a transistor portion and a capacitor portion laterally adjacent to the transistor portion. The transistor portion has a semiconductor layer, a first dielectric layer formed on the semiconductor layer, and a first gate electrode formed on the first dielectric layer. The first gate electrode penetrates a row of memory cells of a memory device, and the first gate electrode forms a gate structure having the semiconductor layer. The first lateral end of the semiconductor layer is doped and coupled to a bit line node of the memory device. The second lateral end of the semiconductor layer is on the opposite side of the first lateral end, and the second lateral end is adjacent to a lateral recess formed in the second dielectric layer of the capacitor portion. The doped silicon layer is conformally deposited in the lateral recess including the second lateral end of the semiconductor layer. An optional thermal annealing process is performed after the doped silicon layer is formed at the second lateral end. A capacitor is formed within a capacitor region where a lateral recess is located, and the capacitor contacts the doped silicon layer at the second lateral end of the semiconductor layer.

[0004]

[0004] Embodiments of the present disclosure also include other methods for semiconductor processing. The method comprises providing a multilayer semiconductor structure, the multilayer semiconductor structure comprising a plurality of unit stacks formed on a substrate. Each unit stack comprises a semiconductor layer having a first lateral end and a second lateral end, a first dielectric layer formed on the semiconductor layer, a first gate electrode formed on the first dielectric layer, and a second dielectric layer for a capacitor portion. A lateral recess is defined by a second dielectric layer at the top and bottom and a second lateral end of the semiconductor layer on the first side. The lateral recess opens to a first opening that penetrates the unit stack of the multilayer semiconductor structure on the second side. The method further comprises conformally depositing a doped silicon layer on the second lateral end of the semiconductor layer within the lateral recess. The method further comprises performing an optional thermal annealing process after forming the doped silicon layer on the second lateral end. The method further includes forming a capacitor having a lateral recess, the capacitor in contact with a doped silicon layer at a second lateral end of a semiconductor layer.

[0005]

[0005] Embodiments of the present disclosure also include other methods for semiconductor processing. The method includes forming a multilayer semiconductor structure comprising a plurality of unit stacks formed on a substrate. Each unit stack comprises a semiconductor layer, a first dielectric layer formed on the semiconductor layer, and a second dielectric layer for the capacitor portion of the multilayer semiconductor structure, wherein the semiconductor layer has a first lateral end and a second lateral end opposite the first rear end. The method further includes forming a first opening through the unit stack. The method further includes pulling back the second dielectric layer from the first opening to form a lateral recess that exposes the second lateral end of the semiconductor layer. The method further includes conformally depositing a doped silicon layer in the lateral recess, which includes a vertical portion on the second lateral end and a lateral portion connected to the vertical portion. The method further includes forming a third dielectric layer on the doped silicon layer in the lateral recess. The method further includes pulling back the third dielectric layer to expose the vertical portion of the doped silicon layer. The method further includes pulling back the vertical and transverse portions of the doped silicon layer. The method further includes removing (e.g., completely removing) a sacrificial third dielectric layer. The method further includes performing an optional thermal annealing process after conformally depositing the doped silicon layer, or after depositing the third dielectric layer, or after pulling back the doped silicon layer, or after completely removing the sacrificial third dielectric layer.

[0006]

[0006] To enable a detailed understanding of the above-described features of the Disclosure, a more specific description of the Disclosure, which has been briefly summarized above, can be obtained by referring to the Examples. Some of these Examples are illustrated in the accompanying Drawings. However, it should be noted that the accompanying Drawings show only a few Examples, and therefore should not be considered to limit the scope of the Disclosure, as the Disclosure may also allow for other equally valid Examples. [Brief explanation of the drawing]

[0007] [Figure 1] This is a schematic circuit diagram of a dynamic random access memory (DRAM) cell according to some embodiments of the present disclosure. [Figure 2] This is a perspective view of a mirrored DRAM pair according to some embodiments of the present disclosure. [Figure 3] This is a perspective view of a mirrored DRAM pair according to some embodiments of the present disclosure. [Figure 4] This is a cross-sectional view of an intermediate structure in a method for forming a memory device such as a 3D DRAM cell, according to some embodiments of the present disclosure. [Figure 5] This is a cross-sectional view of an intermediate structure in a method for forming a memory device such as a 3D DRAM cell, according to some embodiments of the present disclosure. [Figure 6] This is a cross-sectional view of an intermediate structure in a method for forming a memory device such as a 3D DRAM cell, according to some embodiments of the present disclosure. [Figure 7] This is a cross-sectional view of an intermediate structure in a method for forming a memory device such as a 3D DRAM cell, according to some embodiments of the present disclosure. [Figure 8] This is a cross-sectional view of an intermediate structure in a method for forming a memory device such as a 3D DRAM cell, according to some embodiments of the present disclosure. [Figure 9] This is a cross-sectional view of an intermediate structure in a method for forming a memory device such as a 3D DRAM cell, according to some embodiments of the present disclosure. [Figure 10] This is a cross-sectional view of an intermediate structure in a method for forming a memory device such as a 3D DRAM cell, according to some embodiments of the present disclosure. [Figure 11] This is a flowchart of a semiconductor processing method according to one or more embodiments. [Figure 12] This is a flowchart of a semiconductor processing method according to one or more embodiments. [Figure 13] This is a flowchart of a semiconductor processing method according to one or more embodiments. [Modes for carrying out the invention]

[0008]

[0012] To facilitate understanding, the same reference numbers are used to indicate identical elements common to the diagrams, where possible.

[0009]

[0013] The embodiments described herein generally relate to the field of semiconductor processing, and more specifically to memory devices including three-dimensional (3D) dynamic random access memory (DRAM), and methods for semiconductor processing, including forming storage node contact (SNC) junctions for memory devices such as 3D DRAM. According to various examples, a multilayer semiconductor structure is formed on a substrate. The multilayer semiconductor structure comprises a plurality of unit stacks (e.g., up to 100 or more unit stacks), each unit stack comprising a layer selected from a group of different materials, and the structure of the unit stacks is repeated vertically (e.g., each unit stack is a transposition or vertical mirror of an adjacent unit stack), and each unit stack comprises one or more semiconductor layers. The unit stacks are used to form memory devices such as 3D DRAM devices. Specifically, the multilayer semiconductor structure is used to form a vertically stacked memory device having a laterally arranged capacitor structure (e.g., a capacitor portion) from the transistors (e.g., transistor portions) of the unit stacks. The formation of a unit stack memory device involves doping a semiconductor layer laterally positioned within a concave cavity below the opening of the film stack, which is formed by pulling back the semiconductor layer within the unit stack. The doped silicon layer is conformally deposited within the concave cavity, including portions of the semiconductor layer exposed to the concave cavity (e.g., vertical portions of the semiconductor layer). In one embodiment, the doped silicon layer is a doped amorphous silicon layer. In another embodiment, the doped silicon layer is a doped polycrystalline layer. Optionally, an undoped silicon layer may be deposited before the doped silicon layer. Then, an optional thermal annealing process (e.g., a rapid heat treatment process) is performed on the stacked semiconductor structure. Thus, dopants from the doped silicon layer (e.g., phosphorus, arsenic) may be injected into the semiconductor layer and / or the optional undoped silicon layer by the thermal annealing process to form source or drain regions.The drain or source region within the semiconductor layer may already be formed on the opposite side of the formed source or drain region. A capacitor is then formed within the concave cavity of the capacitor region, and the deposited doped silicon layer forms part of the contact between the transistor and the capacitor.

[0010]

[0014] The semiconductor processing described herein, including the formation of a multilayer semiconductor structure, ensures dopant injection at locations that cannot be directly seen during the formation of memory devices such as 3D DRAM devices having concave cavities during formation. In addition, the semiconductor processing described herein can provide a desired doping level within a lateral recess during the formation of a memory device, for example, in a high aspect ratio lateral recess where the width of the recess exceeds the vertical height of the recess.

[0011]

[0015] Furthermore, various numbers of vertically stacked memory devices can be achieved without adding different materials, and capacitors of different sizes (e.g., with different capacitance values) can be implemented in accordance with the disclosure herein while maintaining the same or substantially similar set of processing steps. Various embodiments herein can also realize single or double-gate transistors for 3D DRAM.

[0012]

[0016] Various different embodiments are described below. Multiple features of different embodiments may be described together in a process flow or system, but multiple features may be implemented separately or individually and / or in different process flows or different systems. Furthermore, various process flows are described as being executed in a specific order, but other embodiments may execute the process flow in a different order and / or with more or fewer operations. In addition, source and drain nodes, as well as source and drain regions, are described in various examples, but such descriptions may more generally relate to source / drain nodes or source / drain regions. Furthermore, n-type transistors are described in some embodiments, but more generally, any type of transistor (e.g., p-type transistors) can be implemented.

[0013]

[0017] Figure 1 is a schematic circuit diagram of a dynamic random access memory (DRAM) cell 100 according to several embodiments of the present disclosure. The DRAM cell 100 includes an n-type transistor 2 and a capacitor 4. The first node 6 of the n-type transistor 2 (e.g., the drain node) is electrically connected to the bit line (BL) node 8. The second node 10 of the n-type transistor 2 (e.g., the source node) is electrically connected to the first terminal of the capacitor 4, and the second terminal of the capacitor 4 (opposite to the first terminal) is electrically connected to the power node (e.g., the ground node). The gate node 12 of the n-type transistor 2 is electrically connected to the word line (WL) node 14.

[0014]

[0018] FIG. 2 is a perspective view of a mirrored DRAM pair 200 according to some embodiments of the present disclosure. FIG. 2 shows two DRAM cells mirrored along a vertical axis, which may be referred to herein as a mirrored DRAM pair 200 for convenience. As will be described later, a plurality of mirrored DRAM pairs (e.g., two pairs, three pairs, etc.) can be vertically stacked in a DRAM structure. To avoid the figure's aspect becoming unnecessarily unclear, one DRAM cell of the mirrored DRAM pair is labeled with a reference number, and those skilled in the art will easily understand the mirrored components of the other DRAM cells of the mirrored DRAM pair.

[0015]

[0019] The DRAM cell includes an n-type transistor 22 (corresponding to, for example, n-type transistor 2) and a capacitor 24 (corresponding to, for example, capacitor 4). The n-type transistor 22 includes a semiconductor layer 26 that forms the active region of the n-type transistor 22. In one or more embodiments, the semiconductor layer 26 is p-type doped, for example, lightly p-type doped (e.g., less than about 1 atom per 100 million atoms). In other embodiments, the semiconductor layer 26 is not doped. A first region 28 (corresponding to, for example, first node 6) and a second region 30 (corresponding to, for example, second node 10) are disposed within the semiconductor layer 26 and have a channel region between the first region 28 and the second region 30 within the semiconductor layer 26. In one or more embodiments, the first region 28 is a drain region, the first node 6 is a drain node, the second region 30 is a source region, and the second node 10 is a source node in certain situations (e.g., when programming the cell with one charge). In other situations (e.g., when programming the cell with zero charge), the first region 28 is a source region, the first node 6 is a source node, the second region 30 is a drain region, and the second node 10 is a drain node. The first region 28 and the second region 30 are n-type doped in this embodiment. A gate dielectric layer, a first dielectric layer 32, is disposed on the semiconductor layer 26 (e.g., on the upper surface of the semiconductor layer 26), and a gate electrode 34 (corresponding to, for example, gate node 12) is disposed on the first dielectric layer 32.

[0016]

[0020] The capacitor 24 includes an outer plate 36 (e.g., corresponding to the first terminal of the capacitor 4), a capacitor dielectric layer 38, and an inner plate 40 (e.g., corresponding to the second terminal of the capacitor 4). The outer plate 36 is a conductive material such as metal or a metal-containing material. The outer plate 36 generally has a shape such as a single-cap cylinder, a single-cap rectangular prism, etc. The outer plate 36 generally extends laterally from the n-type transistor 22 and has a capped end that contacts the second region 30 of the n-type transistor 22 to electrically connect the second region 30 to the capacitor 24. The end of the outer plate 36 on the opposite side of the n-type transistor 22 is open. The capacitor dielectric layer 38 is a dielectric material conformally disposed along the inner surface of the outer plate 36. The dielectric material of the capacitor dielectric layer 38 can be a high-k dielectric material (e.g., having a k value greater than 4.0). The inner plate 40 is a conductive material such as metal or a metal-containing material, is disposed on the capacitor dielectric layer 38, and fills the remaining inner portion of the outer plate 36.

[0017]

[0021] The bit line contact 42 (e.g., corresponding to the BL node 8) is disposed to contact the first region 28 of the n-type transistor 22 laterally. The bit line contact 42 extends vertically, and the vertical axis along which the mirrored DRAM pairs are mirrored extends along the bit line contact 42. The power supply contact 44 (e.g., a ground contact) is disposed to contact the inner plate 40 of the capacitor 24 laterally.

[0018]

[0022] Figure 3 is a perspective view of a mirrored DRAM pair 300 according to some embodiments of the present disclosure. In one or more embodiments, the 3D DRAM cell in Figure 3 is similar to the 3D DRAM cell in Figure 2, and for brevity, a general description is omitted. The DRAM cell includes an n-type transistor 52 (e.g., corresponding to n-type transistor 2) and a capacitor 24 (e.g., corresponding to capacitor 4). The n-type transistor 52 includes a semiconductor material 54 that forms the active region of the n-type transistor 52. The semiconductor material 54 may generally be, for example, undoped or lowly p-type doped. A drain region 56 (e.g., corresponding to a first node 6) and a source region 58 (e.g., corresponding to a second node 10) are located within the semiconductor material 54, with a channel region between the drain region 56 and the source region 58 within the semiconductor material 54. In this embodiment, the drain region 56 and the source region 58 are n-type doped. The upper gate dielectric layer 60 is located on the semiconductor material 54 (for example, on the upper surface of the semiconductor material 54), and the bottom gate dielectric layer 62 is located on the semiconductor material 54 on the opposite side of the upper gate dielectric layer 60 (for example, on the bottom surface of the semiconductor material 54). The upper gate electrode 64 (for example, corresponding to the gate node 12) is located on the upper gate dielectric layer 60 (for example, on top), and the bottom gate electrode 66 (for example, corresponding to the gate node 12) is located on the bottom gate dielectric layer 62 (for example, on bottom).

[0019]

[0023] The capped end of the outer plate 36 (for example, corresponding to the first terminal of the capacitor 4) contacts the source region 58 of the n-type transistor 52, electrically connecting the source region 58 to the capacitor 24. The bit line contact 42 (for example, corresponding to BL node 8) is positioned to make lateral contact with the drain region 56 of the n-type transistor 52.

[0020]

[0024] Figures 4 to 9 are cross-sectional views of intermediate structures in a method for forming memory devices such as 3D DRAM cells according to some embodiments of the present disclosure. Memory devices formed according to the first method of Figures 4 to 9 may be substantially similar to those shown in Figure 3 or a portion thereof. The stacked semiconductor structures shown in Figures 4 to 9 are for illustrative purposes only. It should be understood that the semiconductor structures and corresponding materials may vary based on the process integration flow.

[0021]

[0025] Referring to Figure 4, a stacked semiconductor structure 400 according to several embodiments of the present disclosure is shown. In one or more embodiments, the stacked semiconductor structure 400 is a partially formed memory device, such as one or more 3D DRAM cells of a set of 3D DRAM cells in a 3D DRAM device. A full set of 3D DRAM cells may include many additional cells stacked perpendicular to the z direction (e.g., more than 5, up to 100 or more cells) and may be formed on a substrate forming planes in the x and y directions, which are not shown for clarity. The stacked semiconductor structure 400 includes at least a portion of the memory device.

[0022]

[0026] In one or more embodiments, the multilayer semiconductor structure 400 is a partially formed memory device. The multilayer semiconductor structure 400 includes an n-type transistor 22 and a capacitor 24 being formed. In one or more embodiments, the capacitor 24 is the capacitor portion of the unit stack 80. In one or more embodiments, the n-type transistor 22 may be a transistor or may be referred to as a transistor and is the transistor portion of the unit stack 80. In one or more embodiments, the n-type transistor 22 may be a p-type transistor.

[0023]

[0027] The transistor 22 portion of the multilayer semiconductor structure 400 includes a semiconductor layer 26, a first dielectric layer 32, a gate electrode 34, and a dielectric layer 46. As can be seen in the multilayer semiconductor structure 400, a complete unit stack 80 is shown along with portions of two unit stacks. Although described with reference to a single-gate type structure (see, for example, Figure 2), a multilayer semiconductor structure 400 having two gates is shown (see, for example, Figure 3). In one or more embodiments, the steps described herein can be applied to a single-gate type structure. In some embodiments, the steps described herein can be applied to a two-gate type structure. In other embodiments, the steps described herein can be applied to a gate-all-around (GAA) structure (e.g., a four-gate type structure). In yet another embodiment, the steps described herein can be applied to a combination of these structures or to a memory device utilizing other structures. In one or more embodiments, repeating the unit stack 80 of the film stack makes it possible to form additional layers of a memory device including 3D DRAM cells. Furthermore, by using one example of a unit stack within a film layer, it becomes possible to form one layer of a 3D DRAM cell.

[0024]

[0028] The gate electrode 34 is connected to the gate node of the transistor 22, and the gate electrode 34 may also be referred to herein as the gate node. The gate electrode 34 is formed on a first dielectric layer 32 formed on a semiconductor layer 26. The first dielectric layer 32 may also be called a gate dielectric or gate oxide, and may be any suitable high dielectric constant (high dielectric constant dielectric) material of a thickness suitable for a field-effect transistor device. The gate electrode 34 can be deposited by any suitable deposition process, such as conformal deposition such as ALD.

[0025]

[0029] In some embodiments, the semiconductor layer 26 is silicon (e.g., undoped or p-doped to a low degree, single crystal, amorphous, or polycrystalline) or InGaZnO. The semiconductor layer 26 can be deposited by any suitable deposition technique, such as epitaxial deposition. In one or more embodiments, the semiconductor layer 26 is formed by depositing a stack of silicon and silicon-germanium layers (e.g., alternating layers formed by epitaxial deposition), where the silicon-germanium layer is sacrificial and removed, leaving the crystalline silicon layer.

[0026]

[0030] In some embodiments, the first dielectric layer 32 is silicon oxide, silicon oxynitride, or another suitable dielectric material (such as a high dielectric constant dielectric). In one or more embodiments, the first dielectric layer 32 can be deposited by any suitable deposition process, such as conformal deposition processes, such as atomic layer deposition (ALD). In one or more embodiments, the first dielectric layer 32 is an oxide formed by an oxidation process (for example, by oxidizing the exposed surface of the semiconductor layer 26).

[0027]

[0031] In some embodiments, the gate electrode 34 is any suitable conductive material such as a metal (e.g., tungsten or molybdenum), a metal composite (e.g., titanium nitride), or polysilicon (n-type or p-type doped). In one or more embodiments, the gate electrode 34 can be deposited by any suitable deposition process such as conformal deposition such as ALD. Although the multilayer semiconductor structure 400 is not shown, one or more gate barrier / tuning layers can be optionally formed on the first dielectric layer 32 prior to the formation of the gate electrode 34, for example, using a conformal deposition process such as ALD.

[0028]

[0032] In some embodiments, the dielectric layer 46 is another suitable dielectric material such as silicon dioxide, silicon nitride, a low-dielectric-constant or high-dielectric-constant dielectric material, or a combination of several materials. In one or more embodiments, the dielectric layer 46 can be deposited by any suitable deposition process, such as a conformal deposition process such as atomic layer deposition (ALD).

[0029]

[0033] In one or more embodiments, the transistor 22 further includes dielectric fillers 50 and dielectric fillers 51 (which may be called gate electrode fillers). In some embodiments, dielectric fillers 50, dielectric fillers 51, or both are made of the same material as a portion of the dielectric layer 46, or are formed as a portion of the dielectric layer 46. Dielectric fillers 50 and dielectric fillers 51 can be deposited by any suitable deposition technique, such as conformal deposition processes such as ALD or chemical vapor deposition (CVD), or fluid deposition processes such as fluid CVD (FCVD).

[0030]

[0034] The bit line node 42 is a contact along the vertical axis (z-direction). In one or more embodiments, the bit line node 42 is along the vertical axis (z-direction) in which the DRAM pair is mirrored.

[0031]

[0035] The capacitor 24 portion of the multilayer semiconductor structure 400 includes a second dielectric layer 72. A single unit stack 80 may include two portions of the second dielectric layer 72. In one or more embodiments, prior to the multilayer semiconductor structure 400, a stack of materials includes a first set of dielectric layers (including the second dielectric layer 72) and semiconductor layers (including semiconductor layer 26). The semiconductor layers (including semiconductor layer 26) can be pulled back laterally to expose a second lateral edge 70 of the semiconductor layer 26. On the other hand, the first lateral edge 69 of the semiconductor layer 26 opposite the second lateral edge 70 is coupled to a bit line node 42. The pullback process may be any suitable isotropic etching that selectively etches the semiconductor layers (including semiconductor layer 26) to leave the first set of dielectric layers (including the second dielectric layer 72) and form a lateral recess 71.

[0032]

[0036] In one or more embodiments, a first set of dielectric layers (including a second dielectric layer 72) is etched to reduce the thickness of each dielectric layer, for example, after a pullback process that selectively etches the semiconductor layers, to obtain a desired or suitable size.

[0033]

[0037] In one or more embodiments, a second set of one or more sacrificial layers can be deposited between the dielectric layer and the semiconductor layer. In some embodiments, the second set of one or more sacrificial layers may be a different dielectric from the first set of dielectric layers. The second set of one or more sacrificial layers can then be selectively etched (for example, before or after selectively etching the semiconductor layer) to remove these sacrificial layers.

[0034]

[0038] Referring to Figure 5, a multilayer semiconductor structure 500 according to several embodiments of the present disclosure is shown. In one or more embodiments, the multilayer semiconductor structure 500 after the deposition of a doped silicon layer 74 is shown.

[0035]

[0039] The doped silicon layer 74 can be deposited by any suitable deposition process, such as conformal deposition processes like ALD or CVD. The doped silicon layer 74 may be a doped amorphous, polysilicon, or polycrystalline silicon layer. In one or more embodiments, an undoped silicon layer 75 may be optionally deposited prior to the deposition of the doped silicon layer 74. The undoped silicon layer 75 can be deposited by any suitable deposition process, such as conformal deposition processes like ALD or CVD. In one or more embodiments, the undoped silicon layer 75 may be an undoped amorphous silicon layer or a polycrystalline silicon layer.

[0036]

[0040] In one or more embodiments, the doped silicon layer 74 has a thickness between 3 nanometers and 50 nanometers (e.g., average thickness). In some embodiments, the doped silicon layer 74 has a thickness of about 5 nanometers (e.g., average thickness) on the portion of the doped silicon layer 74 that contacts the second lateral edge 70 of the semiconductor layer 26, for example. In embodiments in which an undoped silicon layer 75 is also deposited, the combined thickness of the undoped silicon layer 75 and the doped silicon layer 74 is 50 nanometers or less.

[0037]

[0041] In one or more embodiments, the doped silicon layer 74 is doped with phosphorus. In one or more embodiments, the doped silicon layer 74 is doped with arsenic. In other embodiments, the doped silicon layer 74 is doped with any suitable n-type dopant, for example, antimony. In other embodiments, the doped silicon layer 74 is doped with any suitable p-type dopant, for example, boron, gallium, or indium. In one or more embodiments, the doped silicon layer 74 is doped with approximately 1 × 10¹⁶ particles per cubic centimeter. 21 It is doped with atoms (e.g., phosphorus or arsenic). In one or more embodiments, the doped silicon layer 74 has a density of about 5 × 10¹⁶ per cubic centimeter. 20 Approximately 2 x 10¹⁶ atoms 21 It is doped with atoms. In some embodiments, about 2 × 10¹ 21 Atomic superatomic energy is used.

[0038]

[0042] In one or more embodiments, a native oxide pre-cleaning process may be performed on the multilayer semiconductor structure 400 before the formation of the doped silicon layer 74, as shown in the multilayer semiconductor structure 500.

[0039]

[0043] Referring to Figure 6, a multilayer semiconductor structure 600 according to several embodiments of the present disclosure is shown. In one or more embodiments, the multilayer semiconductor structure 600 is shown after the deposition of a third dielectric layer 76, which may be any suitable sacrificial material. In one or more embodiments, the third dielectric layer 76 is silicon nitride. In one or more embodiments, the third dielectric layer 76 is aluminum oxide. In other embodiments, the third dielectric layer 76 may be SiON, SiCN, SiOCN, SiOC, SiGe, carbon, aluminum oxide, silicon, titanium nitride, Mo, or tungsten. The third dielectric layer 76 may be deposited by any suitable deposition process, such as conformal deposition processes such as ALD or CVD.

[0040]

[0044] Referring to Figure 7, a multilayer semiconductor structure 700 according to several embodiments of the present disclosure is shown. In one or more embodiments, the multilayer semiconductor structure 700 is shown after etching the third dielectric layer 76 to expose the doped silicon layer 74. In one or more embodiments, the third dielectric layer 76 is etched isotropically to vertically separate the third dielectric layer 76 and expose the sidewalls of the doped silicon layer 74.

[0041]

[0045] Referring to Figure 8, a multilayer semiconductor structure 800 according to several embodiments of the present disclosure is shown. In one or more embodiments, the multilayer semiconductor structure 700 is shown such that, following the pullback of the lateral portion of the doped silicon layer 74, the vertical portion 78 of the doped silicon layer 74 remains on the second lateral edge 70 of the semiconductor layer 26. In one or more embodiments, if any undoped silicon layer 75 is deposited, the lateral portion of the undoped silicon layer 75 is also pulled back, and the vertical portion 79 of the undoped silicon layer 75 also remains on the second lateral edge 70 of the semiconductor layer 26. The pullback process can be any suitable etching process that selectively etches the undoped silicon layer 75 (if deposited) and the doped silicon layer 74. For example, the etching process may use an ion screen to enhance selectivity during etching, which is primarily radical-based.

[0042]

[0046] Referring to Figure 9, a multilayer semiconductor structure 900 according to several embodiments of the present disclosure is shown. In one or more embodiments, the multilayer semiconductor structure 900 after the removal of the third dielectric layer 76 is shown. The removal (or pullback) of the third dielectric layer 76 can be any suitable isotropic etching that selectively etches the third dielectric layer 76. For example, if the third dielectric layer 76 is silicon nitride, a thermal phosphoric acid etching process may be used to pull back the third dielectric layer 76. Other isotropic etching processes may be used for silicon nitride or when the third dielectric layer 76 is formed of a different dielectric material.

[0043]

[0047] Referring to Figure 10, a multilayer semiconductor structure 1000 according to several embodiments of the present disclosure is shown. In one or more embodiments, the multilayer semiconductor structure 1000 is shown after dopant injection from the vertical portion 78 of a doped silicon layer 74 to the vertical portion 79 of any underlying undoped silicon layer 75 (if deposited) and / or semiconductor layer 26 to generate a doped region, a second region 30 by performing a thermal annealing process. By using thermal annealing, the dopant (e.g., an n-type dopant such as phosphorus, arsenic, or antimony, or a p-type dopant such as boron, gallium, or indium) can diffuse and form a deeper gradient profile as a low-doped drain (LDD), thereby reducing gate-induced drain leakage in the transistor 22. In other embodiments, injection during thermal annealing can be skipped if a steep junction is desired depending on the device requirements. In yet another embodiment, different thermal annealing may be performed to activate the dopant in the silicon layer.

[0044]

[0048] In one or more embodiments, performing a thermal annealing process includes performing a rapid heat treatment procedure. In one or more embodiments, performing a thermal annealing process includes applying heat to the multilayer semiconductor structure 900 for a time between less than one second and about 30 minutes over a time between 600°C and 1100°C. According to one or more embodiments, a rapid heat treatment procedure is used which has a higher temperature, e.g., a temperature higher than 600°C, a temperature lower than 1100°C, or both, applied to the doped silicon layer 74 on the second lateral edge 70 of the semiconductor layer 26. According to one or more embodiments, a rapid heat treatment procedure is used which has a lower temperature, e.g., a temperature lower than 600°C and a temperature of 1100°C or less, applied to the doped silicon layer 74 on the second lateral edge 70 of the semiconductor layer 26. According to one or more embodiments, the rapid heat treatment procedure is performed over a time between less than one second and 30 minutes.

[0045]

[0049] Figure 11 is a flow chart of a semiconductor processing method 1100 according to some embodiments of the present disclosure. In one or more embodiments, method 1100 includes one or more steps of a memory device manufacturing process, for example, the manufacture of a 3D DRAM. In one or more embodiments, method 1100 includes one or more steps described herein, for example, with reference to one or more of Figures 1 to 10.

[0046]

[0050] Step 1105 of Method 1100 includes providing a multilayer semiconductor structure comprising a plurality of unit stacks formed on a substrate, each unit stack 80 comprising a transistor 22 portion and a capacitor 24 portion laterally adjacent to the transistor 22 portion. In one or more embodiments, the transistor 22 portion comprises a semiconductor layer 26, a first dielectric layer 32 formed on the semiconductor layer 26, and a gate electrode 34 formed on the first dielectric layer 32. The gate electrode 34 extends through a row of memory cells in the memory device and forms a gate structure having the semiconductor layer 26. A first lateral end 69 of the semiconductor layer 26 is doped and connected to a bit line node 42 of the memory device. A second lateral end 70 of the semiconductor layer 26 is on the opposite side of the first lateral end 69. The second lateral end is adjacent to a lateral recess 71 formed in the second dielectric layer 72 of the capacitor 24 portion.

[0047]

[0051] Step 1107 of Method 1100 includes conformally depositing an undoped silicon layer 75 on a second lateral end 70 of the semiconductor layer 26 in a lateral recess 71. In one or more embodiments, step 1107 is optional.

[0048]

[0052] Step 1110 of Method 1100 includes conformally depositing a doped silicon layer 74. The doped silicon layer 74 is deposited in a lateral recess 71. If an undoped silicon layer 75 is deposited, the doped silicon layer 74 is deposited on top of the undoped silicon layer 75. If an undoped silicon layer 75 is not deposited, the doped silicon layer 74 is deposited on the second lateral edge 70 of the semiconductor layer 26.

[0049]

[0053] Step 1115 of Method 1100 includes performing a thermal annealing treatment after depositing the doped silicon layer 74. In one or more embodiments, step 1115 is optional.

[0050]

[0054] Step 1120 of Method 1100 includes forming the capacitor 24 in the portion of the capacitor 24 where the lateral recess 71 is located, the capacitor 24 in contact with a doped silicon layer 74 on a second lateral end 70 of the semiconductor layer 26 (or any undoped silicon layer 75).

[0051]

[0055] In one or more embodiments, method 1100 includes forming a third dielectric layer 76 on a doped silicon layer 74 in a lateral recess 71, the doped silicon layer 74 including a vertical portion 78 on a second lateral end 70 and a lateral portion coupled with the vertical portion 78. The lateral portion of the doped silicon layer is pulled back, and the third dielectric layer 76 is pulled back to expose the vertical portion 78 of the doped silicon layer 74. In one or more embodiments, pulling back the vertical portion 78 and the lateral portion of the doped silicon layer includes removing the portion of the doped silicon layer 74 between the third dielectric layer 76 and the second dielectric layer 72. In one or more embodiments, the third dielectric layer 76 includes silicon nitride, aluminum oxide, or a combination of both silicon nitride and aluminum oxide. In one or more embodiments, if any undoped silicon layer 75 is deposited, the pullback process also includes removing the portion of the undoped silicon layer 75 between the third dielectric layer 76 and the second dielectric layer 72, leaving the vertical portion 79 of the undoped silicon layer 75.

[0052]

[0056] In one or more embodiments, performing a thermal annealing process includes performing a rapid heat treatment procedure after forming a doped silicon layer 74 on the second transverse end 70. In one or more embodiments, performing a thermal annealing process includes applying heat to the multilayer semiconductor structure for a time ranging from less than 1 second to about 30 minutes at a temperature of at least 600°C to 1100°C or less. According to one or more embodiments, the rapid heat treatment procedure is used to apply a higher or lower temperature, for example, a temperature higher than 1100°C or a temperature lower than 600°C, to the doped silicon layer 74 on the second transverse end 70 of the semiconductor layer 26 (or any undoped silicon layer 75).

[0053]

[0057] In one or more embodiments, the doped silicon layer 74 has a thickness between 3 nanometers and 50 nanometers (e.g., average thickness). In some embodiments, the doped silicon layer 74 has a thickness of about 5 nanometers (e.g., average thickness) on the portion of the doped silicon layer 74 that contacts the second lateral edge 70 of the semiconductor layer 26, for example. In embodiments in which an undoped silicon layer 75 is also deposited, the combined thickness of the undoped silicon layer 75 and the doped silicon layer 74 is 50 nanometers or less.

[0054]

[0058] In one or more embodiments, the doped silicon layer 74 is doped with phosphorus. In one or more embodiments, the doped silicon layer 74 is doped with arsenic. In other embodiments, the doped silicon layer 74 is doped with any suitable n-type dopant, for example, antimony. In other embodiments, the doped silicon layer 74 is doped with any suitable p-type dopant, for example, boron, gallium, or indium. In one or more embodiments, the doped silicon layer 74 has a density of at least 1 × 10¹⁶ per cubic centimeter. 20 It is doped with an atom (for example, phosphorus or arsenic).

[0055]

[0059] Figure 12 is a flow chart of semiconductor processing method 1200 according to one or more embodiments. In one or more embodiments, method 1200 includes one or more steps of a memory device manufacturing process, for example, the manufacture of a 3D DRAM. In one or more embodiments, method 1200 includes one or more steps described herein, for example, with reference to one or more of Figures 1 to 11.

[0056]

[0060] Step 1205 of Method 1200 includes providing a multilayer semiconductor structure comprising a plurality of unit stacks formed on a substrate. Each unit stack 80 of the plurality of unit stacks includes a semiconductor layer 26 having a first lateral end 69 and a second lateral end 70. A first dielectric layer 32 of the unit stack 80 is formed on the semiconductor layer 26. A gate electrode 34 of the unit stack 80 is formed on the first dielectric layer 32. The unit stack 80 also includes a second dielectric layer 72 for the portion of the capacitor 24. A lateral recess 71 is defined by the upper and bottom second dielectric layers 72 and the second lateral end 70 of the semiconductor layer 26 on the first side. On the second side, the lateral recess 71 opens to a first opening that penetrates the unit stack 80 of the multilayer semiconductor structure.

[0057]

[0061] Step 1207 of Method 1200 includes conformally depositing an undoped silicon layer 75 on a second lateral end 70 of the semiconductor layer 26 in a lateral recess 71. In one or more embodiments, step 1107 is optional.

[0058]

[0062] Step 1210 of Method 1200 includes conformally depositing a doped silicon layer 74. The doped silicon layer 74 is deposited in a lateral recess 71. If an undoped silicon layer 75 is deposited, the doped silicon layer 74 is deposited on top of the undoped silicon layer 75. If an undoped silicon layer 75 is not deposited, the doped silicon layer 74 is deposited on the second lateral edge 70 of the semiconductor layer 26.

[0059]

[0063] Step 1215 of Method 1200 includes performing a thermal annealing process after forming a doped silicon layer on the second lateral end. In one or more embodiments, step 1215 is optional.

[0060]

[0064] Step 1220 of Method 1200 includes forming a capacitor 24 in which a lateral recess 71 is located, the capacitor 24 in contact with a doped silicon layer 74 on a second lateral end 70 of a semiconductor layer 26.

[0061]

[0065] Figure 13 is a flow chart of semiconductor processing method 1300 according to one or more embodiments. In one or more embodiments, method 1300 includes one or more steps of a memory device manufacturing process, for example, the manufacture of a 3D DRAM. In one or more embodiments, method 1300 includes one or more steps described herein, for example, with reference to one or more of Figures 1 to 12.

[0062]

[0066] Step 1305 of Method 1300 includes forming a multilayer semiconductor structure comprising a plurality of unit stacks formed on a substrate, each unit stack 80 comprising a semiconductor layer 26, a first dielectric layer 32 formed on the semiconductor layer 26, and a second dielectric layer 72 of the capacitor 24 portion of the multilayer semiconductor structure. The semiconductor layer 26 has a first lateral end 69 and a second lateral end 70 opposite the first lateral end 69.

[0063]

[0067] Step 1310 of Method 1300 includes forming a first opening through the unit stack 80.

[0064]

[0068] Step 1315 of Method 1300 includes forming a lateral recess 71 from the first opening to expose a second lateral end 70 of the semiconductor layer 26.

[0065]

[0069] Step 1317 of Method 1300 includes conformally depositing an undoped silicon layer 75 on a second lateral end 70 of the semiconductor layer 26 in a lateral recess 71. In one or more embodiments, step 1317 is optional.

[0066]

[0070] Step 1320 of Method 1300 includes conformally depositing a doped silicon layer 74 in a lateral recess 71. The doped silicon layer includes a vertical portion 78 (or a vertical portion 79 of an undoped silicon layer 75) on a second lateral end 70 and a lateral portion connected to the vertical portion 78.

[0067]

[0071] Step 1325 of Method 1300 includes forming a third dielectric layer 76 on the doped silicon layer 74 within the lateral recess 71.

[0068]

[0072] Step 1330 of Method 1300 includes pulling back the third dielectric layer 76 to expose the vertical portion 78 of the doped silicon layer 74.

[0069]

[0073] Step 1335 of Method 1300 includes pulling back the vertical portion 78 and the lateral portion of the doped silicon layer 74 (and any undoped silicon layer 75, if deposited).

[0070]

[0074] Step 1340 of Method 1300 includes removing the third dielectric layer 76 as a sacrificial layer.

[0071]

[0075] Step 1345 of Method 1300 includes performing a thermal annealing process after conformally depositing a doped silicon layer 74, depositing a third dielectric layer 76, or pulling back the doped silicon layer 74, or completely removing the sacrificial third dielectric layer 76.

[0072]

[0076] It is conceivable that various subjects disclosed herein may be combined. For example, one or more aspects, features, components, and / or characteristics of DRAM cell 100, mirrored DRAM pairs 200-300, stacked semiconductor structures 400-1000, and / or methods 1100-1300 may be combined. Furthermore, it is assumed that various subjects disclosed herein may include some or all of the aforementioned advantages.

[0073]

[0077] The foregoing applies to embodiments of the present disclosure, but other embodiments and further embodiments of the present disclosure can be devised without departing from the basic scope of the present disclosure. The present disclosure also assumes that one or more aspects of the embodiments described herein may be replaced by one or more of the other aspects described herein. The scope of the present disclosure is defined by the following claims.

Claims

1. A method for semiconductor processing, The present invention provides a multilayer semiconductor structure comprising a plurality of unit stacks formed on a substrate, wherein each unit stack comprises a transistor portion and a capacitor portion laterally adjacent to the transistor portion, the transistor portion comprises a semiconductor layer, a first dielectric layer formed on the semiconductor layer, and a first gate electrode formed on the first dielectric layer, the first gate electrode penetrates a row of memory cells of a memory device to form a gate structure having the semiconductor layer, the first lateral end of the semiconductor layer is doped and coupled to a bit line node of the memory device, the second lateral end of the semiconductor layer is on the opposite side of the first lateral end, and the second lateral end is adjacent to a lateral recess formed in the second dielectric layer of the capacitor portion. Conformally depositing a silicon layer doped on the second lateral end of the semiconductor layer within the aforementioned lateral recess, After forming the doped silicon layer on the second lateral end, an arbitrary thermal annealing process is performed, A capacitor is formed within the capacitor portion where the lateral recess is located, wherein the capacitor is in contact with the doped silicon layer on the second lateral end of the semiconductor layer. Methods that include...

2. A third dielectric layer is formed on the doped silicon layer within the lateral recess, wherein the doped silicon layer forms a third dielectric layer including a vertical portion on the second lateral end and a lateral portion coupled to the vertical portion. Pulling back the vertical and lateral portions of the doped silicon layer, To expose the vertical portion of the doped silicon layer, the third dielectric layer is pulled back, The method according to claim 1, including the method described in claim 1.

3. The method according to claim 2, wherein the third dielectric layer comprises silicon nitride, aluminum oxide, or a combination thereof.

4. The method according to claim 2, wherein pulling back the vertical and lateral portions of the doped silicon layer includes removing a portion of the doped silicon layer between the third dielectric layer and the second dielectric layer.

5. The method according to claim 1, wherein performing the thermal annealing process includes performing a rapid heat treatment procedure after forming the doped silicon layer on the second lateral end.

6. The method according to claim 1, wherein performing the thermal annealing treatment includes applying heating to the multilayer semiconductor structure at least 600°C and 1100°C or less for a period of less than 1 second and 30 minutes.

7. The method according to claim 1, wherein the doped silicon layer has an average thickness between 3 nanometers and 50 nanometers.

8. The method according to claim 1, wherein the doped silicon layer comprises polysilicon doped with phosphorus, arsenic, or a combination thereof.

9. The doped silicon layer has at least 1 × 10 per cubic centimeter ２０ The method according to claim 8, comprising polysilicon having a doping concentration containing phosphorus atoms.

10. A method for semiconductor processing, The present invention provides a multilayer semiconductor structure comprising a plurality of unit stacks formed on a substrate, wherein each unit stack comprises a semiconductor layer having a first lateral end and a second lateral end, a first dielectric layer formed on the semiconductor layer, a first gate electrode formed on the first dielectric layer, and a second dielectric layer for a capacitor portion, wherein a lateral recess is defined by the upper and bottom second dielectric layers and the second lateral end of the semiconductor layer on the first side surface, and the lateral recess opens to a first opening that penetrates the unit stack of the multilayer semiconductor structure on the second side surface. Conformally depositing a silicon layer doped on the second lateral end of the semiconductor layer within the aforementioned lateral recess, After forming the doped silicon layer on the second lateral end, a thermal annealing process is performed. A capacitor having the aforementioned lateral recess, wherein the capacitor is formed in contact with the doped silicon layer on the second lateral end of the semiconductor layer, Methods that include...

11. The method involves forming a third dielectric layer on the doped silicon layer within the lateral recess, wherein the doped silicon layer forms a third dielectric layer that includes a vertical portion on the second lateral end and a lateral portion coupled to the vertical portion. Pulling back the vertical and lateral portions of the doped silicon layer, To expose the vertical portion of the doped silicon layer, the third dielectric layer is pulled back, The method according to claim 10, including the method described in claim 10.

12. The method according to claim 11, wherein the third dielectric layer comprises silicon nitride, aluminum oxide, or a combination thereof.

13. The method according to claim 11, wherein pulling back the vertical and lateral portions of the doped silicon layer includes removing a portion of the doped silicon layer between the third dielectric layer and the second dielectric layer.

14. The method according to claim 10, wherein performing the thermal annealing process includes performing a rapid heat treatment procedure after forming the doped silicon layer on the second lateral end.

15. The method according to claim 10, wherein performing the thermal annealing treatment includes applying heating to the multilayer semiconductor structure at least 600°C and 1100°C or less for a period of less than 1 second and 30 minutes.

16. The method according to claim 10, wherein the doped silicon layer comprises polysilicon doped with phosphorus, arsenic, or a combination thereof.

17. A method for semiconductor processing, The present invention relates to forming a multilayer semiconductor structure comprising a plurality of unit stacks formed on a substrate, wherein each unit stack includes a semiconductor layer, a first dielectric layer formed on the semiconductor layer, and a second dielectric layer of the capacitor portion of the multilayer semiconductor structure, and the semiconductor layer has a first lateral end and a second lateral end opposite to the first lateral end, thereby forming a multilayer semiconductor structure. To form a first opening that penetrates the unit stack, In order to expose the second lateral end of the semiconductor layer, a lateral recess is formed from the first opening, Conformally depositing a doped silicon layer within the lateral recess, which includes the vertical portion on the second lateral end and the lateral portion connected to the vertical portion, A third dielectric layer is formed on the doped silicon layer within the lateral recess, To expose the vertical portion of the doped silicon layer, the third dielectric layer is pulled back, The third dielectric layer described above is removed as a sacrificial layer, Pulling back the vertical and lateral portions of the doped silicon layer, After conformally depositing the doped silicon layer, after depositing the third dielectric layer, or after pulling back the doped silicon layer, or after completely removing the third dielectric layer, a thermal annealing process is performed. Methods that include...

18. The method according to claim 17, further comprising forming a capacitor in which the lateral recess is disposed, wherein the capacitor is in contact with the doped silicon layer on the second lateral end of the semiconductor layer.

19. The method according to claim 17, further comprising performing a rapid heat treatment procedure after forming the doped silicon layer on the second lateral end.

20. The doped silicon layer has an average thickness of at least 3 nanometers and no more than 20 nanometers, and has at least 1 × 10¹⁶ layers per cubic centimeter. ２０ The method according to claim 17, comprising polysilicon having a doping concentration containing phosphorus atoms.

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